Datasheet CXPI Transceiver for Automotive BD41001FJ-C General Description Key Specifications BD41001FJ-C can reduce EMI (Electromagnetic Emission) noise of AM frequency band in comparison with BD41000AFJ-C. BD41001FJ-C is a transceiver for the CXPI (Clock Extension Peripheral Interface) communication. Switching between Master/Slave Mode can be done using the external pin (the MS pin). Low power consumption during standby (non-communication) using Power Saving function. Arbitration function stops transmitter output upon the detection of BUS data collision. Also Fail-safe function stops transmitter output upon the detection of under voltage or temperature abnormality. Power Supply Voltage: +7 V to +18 V Absolute Maximum Rating of BAT: -0.3 V to +40 V Absolute Maximum Rating of BUS: -27 V to +40 V Power OFF Mode Current: 3 A (Typ) Operating Temperature Range: -40 C to +125 C Package W(Typ) x D(Typ) x H(Max) SOP-J8 4.90 mm x 6.00 mm x 1.65 mm Features AEC-Q100 Qualified(Note 1) CXPI Standards Qualified Transmission Speed Range from 18.8 kbps to 20 kbps Master/Slave Switching Function Microcontroller Interface Corresponds to 3.3 V/5.0 V Built-in Terminator (30 k(Typ)) Power Saving Function Data Arbitration Function Built-in Under Voltage Lockout (UVLO) Function Built-in Thermal Shutdown (TSD) Function Low Electro Magnetic Interference (EMI) High Electro Magnetic Susceptibility (EMS) High Electro Static Discharge (ESD) Robustness SOP-J8 (Note 1) Grade 1 Applications Automotive Networks Typical Application Circuit CXPI BUS Master node VECU Regulator 10k 2.7k VDD MS(8) INT RXD RXD(1) Micro TXD Controller TXD(4) CLK CLK(3) (Note 2) BAT(7) 100nF BD41001FJ-C 1k BUS(6) NSLP(2) I/O GND 1nF GND(5) Slave node Regulator 2.7k VDD MS(8) INT RXD RXD(1) Micro TXD Controller TXD(4) CLK CLK(3) (Note 2) 10k 2.7k (Note 3) BAT(7) 100nF BD41001FJ-C BUS(6) NSLP(2) I/O GND GND(5) 220pF (Note 2) INT: Interrupt, RXD: UART RXD, TXD: UART TXD, CLK: Clock, I/O: General Purpose I/O (Note 3) While using slave, it is no problem that the CLK pin is opened in the case of non-using the CLK output. Figure 1. Typical Application Circuit Consider the actual application design confirming the following linked document before applying this product. Application Note Product structure : Silicon monolithic integrated circuit www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 14 * 001 This product has no designed protection against radioactive rays 1/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Pin Configuration (TOP VIEW) RXD 1 8 MS NSLP 2 7 BAT CLK 3 6 BUS TXD 4 5 GND Figure 2. Pin Configuration Pin Description Table 1. Pin Description Pin No. Pin Name Function 1 RXD 2 NSLP 3 CLK Clock signal input/output pin (Master setting: Input, Slave setting: Output) 4 TXD Transmission data input pin 5 GND Ground 6 BUS CXPI BUS pin 7 BAT Power supply pin 8 MS Master/Slave switching pin ("H": Master, "L": Slave) Received data output pin Power saving control input pin ("H": Change to "Codec Mode", "L": Change to "Power OFF Mode") Block Diagram 7 BAT 6 BUS 5 GND BAT MS Thermal Shutdown (TSD) 8 Under Voltage Lockout (UVLO) Power on Reset (POR) Regulator To each block LOGIC RXD Low Pass Filter 1 Decoder Wakeup Timer Slope Control TXD 4 Arbiter Encoder Dominant Timeout Counter (DTC) Controller NSLP 2 CLK 3 Slope Timer Timing Generator Oscillator Figure 3. Block Diagram www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 2/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Description of Blocks State Transition Diagram BD41001FJ-C has "Power OFF Mode", "Through Mode", "RX Through Mode" other than "CODEC Mode" for power saving control. Each mode is controlled by the NSLP, BUS, and TXD pins. Non-power Supply When VBAT<VPOR is established in all modes, It shifts to Non-power supply state VBATVPOR Power OFF Mode RXD output Hi-Z(H) fixed CLK output (slave) Hi-Z(H) fixed BUS output Hi-Z(H) fixed BUS terminator Weak pull-up BUS Wakeup pulse detect(Note 4) TXD Wakeup input detect(Note 5) NSLP=L RX Through Mode RXD output NSLP=H CODEC Mode Output is reversed at every BUS signal rising edge RXD output NSLP=H Through Mode Decode BUS signal, and output it NSLP=H RXD output Output BUS signal by through CLK output (slave) BUS clock output CLK output (slave) BUS clock output CLK output (slave) Hi-Z(H) fixed BUS output Hi-Z(H) fixed BUS output Code TXD signal, and output it. BUS output Output TXD signal by through BUS terminator 30 k(Typ) pull-up BUS terminator 30 k(Typ) pull-up BUS terminator 30 k(Typ) pull-up (Note 4) Refer to the Wakeup pulse detection LO time of the electrical characteristics. (Note 5) Refer to the Wakeup input detection time (TXD) of the electrical characteristics. Figure 4. State Transition Diagram While using master, the CLK pin becomes input pin, and uses to input BUS clock in "CODEC Mode". Power OFF Mode "Power OFF Mode" reduces power consumption by not supplying powers to any circuits other than necessary ones for "Wakeup pulse detection (the BUS pin)" and "Wakeup input detection (the TXD pin)". When the TXD pin is "H", Wakeup input is detected, and then changes to "Through Mode". If shift to "Power OFF Mode", set the TXD pin to "L" and then set the NSLP pin to "L". "Through Mode" and "RX Through Mode" cannot change to "Power OFF Mode" directly. Change it via "CODEC Mode" by setting the NSLP pin to "H". Through Mode "Through Mode" does not process Coding/Decoding. It only drives signals from the TXD pin to the BUS pin and from the BUS pin to the RXD pin directly. When sending Wakeup pulse, change to "Through Mode" with the TXD pin as "H". RX Through Mode "RX Through Mode" reverses the RXD pin output at each rising edge of the BUS pin. When detecting Wakeup pulse in "Power OFF Mode", monitor the change of the RXD pin CODEC Mode "CODEC Mode" is the mode of CXPI communication. NSLP should be "H" for the chip to enter "CODEC Mode". The RXD output changes synchronized with the falling edge of the CLK pin when in the Master setting, and with the falling edge of the BUS pin when in the Slave setting. The BUS output is delayed for 2.00.5 Tbit from the TXD input, and the RXD output is delayed for 1.00.5 Tbit from the BUS input. For about the jitter of the clock signal supplying the CLK pin when in the Master setting, input the signal satisfies the CXPI standard (1.0 %) considering the jitters occurs in the BD41001FJ-C (0.2 %). www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 3/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Description of Blocks - continued Sequence Diagram Show the examples of the BD41001FJ-C control sequence which corresponding to the mode management of CXPI standard, "Sleep Mode", "Standby Mode" and "Normal Mode".(Refer to the CXPI standard for specifications about the detail of mode management.) 1. The Sequence from "Normal Mode" to "Sleep Mode" When changing to "Sleep Mode", the NSLP pin should be switched from "H" to "L", and then turn the IC to "Power OFF Mode". The TXD pin has built-in pull-down resistor in case of a fail-safe. Fix the TXD pin to "L" before BD41001FJ-C enters "Power OFF Mode" to prevent extra currents from MCU side while "Sleep Mode". Fix the CLK pin to "L" just like the TXD pin, because the pull-down resister of the CLK pin is active in the case of Master setting. Master Node Micro Controller (MCU) Slave Node BD41001FJ-C Micro Controller (MCU) BD41001FJ-C Sleep condition establish TXD (Sleep flame) Sleep flame transmit Sleep flame transmit (with coding) Sleep flame transmit (with coding) Sleep flame(Note 6) RXD (Sleep flame) RXD (Sleep flame) Sleep flame detect Sleep flame detect Normal Mode Normal Mode CODEC Mode CODEC Mode CLK ("L" fixed) CLK output stop BUS clock supply stop TXD ("L" output) TXD output control TXD ("L" output) TXD output control NSLP ("L" fixed) Power OFF indicate NSLP ("L" output) Power OFF indicate Sleep Mode Power OFF Mode Power OFF Mode Sleep Mode (Note 6) Refer to sleep flame shown in the JASO D015-3 standard. Figure 5. The Sequence from "Normal Mode" to "Sleep Mode" Master Node Operating mode CODEC Mode Power OFF Mode NSLP T XD Sleep flame transmit CLK RXD Sleep flame receive Tclock_stop_m BUS (Note 7) Sleep flame (Note 7) Refer to Tclock_stop_m shown in the JASO D015-3 standard. Figure 6. The Timing Chart from "Normal Mode" to "Sleep Mode" (Master) www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 4/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C 1. The Sequence from "Normal Mode" to "Sleep Mode" - continued Slave Node Operating mode CODEC Mode Power OFF Mode NSLP TXD RXD Sleep flame receive BUS Tsleep_s (Note 8) Sleep flame (Note 8) Refer to Tsleep_s shown in the JASO D015-3 standard. Figure 7. The Timing Chart from "Normal Mode" to "Sleep Mode" (Slave) 2. The Sequence from "Sleep Mode" to "Normal Mode" (Master Node Trigger) To wakeup the node by an internal factor, switch the IC to "CODEC Mode" by setting the NSLP pin to "H". The TXD pin should be "H" within 30 s before changing from "Power OFF Mode" to "CODEC Mode" in order to prevent abnormal the BUS output or the RXD output. In the case of slave node, BD41001FJ-C reverses RXD output at every rising edge of the BUS signal after receiving the BUS clock. When start wakeup detecting at the RXD first falling edge, start micro controller initializing operation. To establish wakeup pulse, check if the RXD pin is "H" after initializing operation or detect RXD rising edge. To change from "Standby Mode" to "Sleep Mode" because the slave node cannot receive the second rising pulse within the specified time, return to "Power OFF Mode" with the NSLP pin as "L" again after the change to "CODEC Mode" with the NSLP pin as "H". Master Node Slave Node Micro Controller (MCU) BD41001FJ-C Micro Controller (MCU) BD41001FJ-C Sleep Mode Wakeup factor CLK (Output start) CLK output start Power OFF Mode Power OFF Mode Sleep Mode Standby Mode T XD ("H" output) T XD output control NSLP ("H" output) Power OFF reset CLK transmit (with coding) BUS clock supply start Wakeup pulse receive (First rising edge) RXD ("L" output) Normal Mode CODEC Mode Wakeup detect Initializing operation Wakeup pulse receive (Second rising edge) RXD ("H" output) RX Through Mode After that, Output rev ers e by every BUS signal pull up edge Wakeup decision Standby Mode TXD ("H" output) TXD output control NSLP ("H" output) Power OFF control CODEC Mode Normal Mode Figure 8. The Sequence from "Sleep Mode" to "Normal Mode" (Master Node Trigger) www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 5/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C 2. The Sequence from "Sleep Mode" to "Normal Mode" (Master Node Trigger) - continued Master Node Operating mode Power OFF Mode CODEC Mode Within 30s NSLP TXD CLK RXD BUS Figure 9. The Timing Chart from "Sleep Mode" to "Normal Mode" (Master Node Trigger, Master) Slave Node Operating mode Power OFF Mode RX Through Mode CODEC Mode Within 30s NSLP TXD CLK RXD BUS Wakeup pulse (Clock signal) Figure 10. The Timing Chart from "Sleep Mode" to "Normal Mode" (Master Node Trigger, Slave) www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 6/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Sequence Diagram - continued 3. The Sequence from "Sleep Mode" to "Normal Mode" (Slave Node Trigger) When waking up the slave node by an internal factor, shift to "Through Mode" by setting the TXD pin to "H" and then send wakeup pulse. After receiving the wakeup pulse in the Master Node, the RXD output reverses at every rising edge of the BUS signal. Master node should establish wakeup pulse at the RXD first falling edge. To change from "Standby Mode" to "Sleep Mode", in case the master node cannot receive BUS clock within the specified time, return to "Power OFF Mode" with the NSLP pin as "L" again after the change to "CODEC Mode" with the NSLP pin as "H". Master Node Slave Node Micro Controller (MCU) BD41001FJ-C MicroController (MCU) BD41001FJ-C Sleep Mode Wakeup factor Power OFF Mode T XD ("H" output) Sleep Mode Wakeup BD41001FJ-C Power OFF Mode TXD (Wakeup pulse) Wakeup pulse transmit Wakeup pulse transmit (without coding) Wakeup pulse receive Wakeup decision TXD output control when it exceeds tTXD_WAKEUP Wakeup pulse RXD ("L" output) After that, Output reverse at every BUS signal rising edge Standby Mode CLK (Output start) CLK output start RX Through Mode Standby Mode In the case of it cannot receive clock within the role time, Wakeup pulse retransmit T hrough Mode T XD ("H" output) T XD output control NSLP ("H" output) Power OFF control Clock transmit (with coding) Clock receive Normal Mode BUS clock supply start RXD(Clock signal) CODEC Mode Clock signal detect Through output NSLP ("H" output) Power OFF control CODEC Mode Normal Mode Figure 11. The Sequence from "Sleep Mode" to "Normal Mode" (Slave Node Trigger) Master Node Operation mode Power OFF Mode Rx Through Mode NSLP CODEC Mode Within 30s TXD CLK RXD BUS ( 10) Tclock_start_m Note Ttx_wakeup(Note 9) (Note 9) Refer to Ttx_wakeup shown in the JASO D015-3 standard. (Note 10) Refer to Tclock_start_m shown in the JASO D015-3 standard. Figure 12. The Timing Chart from "Sleep Mode" to "Normal Mode" (Slave Node Trigger, Master) www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 7/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C 3. The Sequence from "Sleep Mode" to "Normal Mode" (Slave Node Trigger) - continued Slave Node Operation mode Power OFF Mode T hrough Mode CODEC Mode Wakeup pulse NSLP TTXD _w akeup (Note 12) Ttx_w akeup_space T XD Ttx_w akeup (Note 11) Ttx_w akeup (Note 11) CLK RXD BUS (Note 11) Refer to Ttx_wakeup shown in the JASO D015-3 standard. (Note 12) Refer to Ttx_wakeup_space shown in the JASO D015-3 standard. Figure 13. The Timing Chart from "Sleep Mode" to "Normal Mode" (Slave Node Trigger, Slave) Transmission and Reception Starting Effective Time after Shift to CODEC Mode After changing to "CODEC Mode" by setting the NSLP pin to "H", BD41001FJ-C detect the clock period and then learn the LO width of logic value1. To secure the learning time of the LO width of logic value1, start to transmit and receive data after the time equal to 16 Tbit clocks at least. (After setting the NSLP pin to "H", 6 Tbit (maximum) clocks are necessary to output clock signal to the BUS signal input or the CLK signal input.) Master state Prohibit Transmit and Receive Transmit and Receive possible Master CLK Master NSLP Max 6Tbit 16Tbit BUS Slave RXD Slave NSLP 16Tbit Max 6Tbit Slave CLK Slave state Power OFF RX Th rou g h Transmit and Receive possible Prohibit Transmit and Receive Figure 14. The Actual Time of Transmission and Reception after "CODEC Mode" Changing www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 8/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Arbitration Function To carry out collision resolution functions that defined by CXPI specification, both micro controller and BD41001FJ-C share functions. Basically, BD41001FJ-C arbitrates the bit data in the UART flame and micro controller arbitrates the byte data between the UART flames. 1. In case of collision is happened by transmitting from other node at the same time In the case of collision (arbitration defeat) is happened by transmitting from other node at the same time, it stops the transmission of remaining UART flame data after the collision from micro controller side. It is necessary to have the interval of 1 Tbit or more (BUS baud rate period) to transmit again after arbitration defeat. Set the wait time in consideration of the frequency deviation of the baud rate clock in micro controller side and BUS side and the delay at UART circuit in micro controller side. When arbitration defeat is detected, 1 Tbit or more interval is needed at next transmition TXD Start Bit 1 0 1 0 1 1 1 0 Stop Bit Start Bit 0 1 0 1 1 1 1 0 0 1 1 1 Stop Bit Arbitration defeat 2.00.5Tbit delay BUS 0 0 1 1 0 0 0 1 1 1 0 0 0 1 1 1.00.5Tbit delay Start Bit RXD Transmit prohibit signal (Internal signal) 1 Start Bit 0 While transmit prohibit signal is set "H", BUS output is stopped BUS output is stopped Arbitration defeat (TXDRXD) BUS output can generate When arbitration defeat is detected, remainig UART output data is stopped Figure 15. Arbitration Function (When the Collision is detected after Data Transmission) 2. In case of collision is detected by receiving from other node before transmission is started. After BD41001FJ-C detects transmission of other node on BUS, BD41001FJ-C stops to transmit data for 10 Tbit period not to destroy other node transmission. If the TXD signal is inputted to BD41001FJ-C while stopping to transmit data, BD41001FJ-C stops to transmit data for further 10 Tbit period of the transmit data. When arbitration defeat is detected, more than 1 Tbit interval is needed at next transmition TXD Start Bit 1 0 1 0 1 0 1 0 Stop Bit Start Bit 0 1 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 Stop Bit 0 1 2.00.5Tbit delay BUS 1 1 1 1 1 1 0 1.00.5Tbit delay Start Bit RXD Transmit prohibit signal (Internal signal) While transmit prohibit signal is set "H", BUS output is stopped Receive detect BUS output is stopped When the receive data is detected BUS output is stopped for 10 Tbit period. and then, while stopping BUS output, if TXD signal is inputted, BUS output is stopped for further 10 Tbit period BUS output can generate Figure 16. Arbitration Function (When receive data is detected before transmission) www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 9/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Arbitration Function - continued 3. In case of arbitration function failure is happened because micro controller outputs transmission data to BD41001FJ-C at the out of range of BD41001FJ-C arbitration function. The BUS output is delayed for 2.5 Tbit(Maximum) from the TXD input and the RXD output is delayed for 1.5 Tbit(Maximum) from BUS input. When micro controller outputs transmission data to BD41001FJ-C at the timing that shown in Figure 17, CXPI frame of other node is destroyed because BD41001FJ-C outputs PID just after receive PID. Micro controller should stop transmission while receiving UART flame. Figure 17 shows the example in case of 2.0 Tbit delay from the TXD input to the BUS output and 1.0 Tbit delay from the BUS input to the RXD output. Since the transmission delay is 2.0 0.5 Tbit, there is a timing that the data transmitted to the TXD is transmitted to the BUS before the stopbit detection (Max imum 2.5 Tbit) on the micro controller side (The time to stop TXD after detecting s topbit depends on the proc es s ing on the micro controller side) Range of stopping transmission by detecting receive data from other node (ex plained operation in prev ious page) Start Bit TXD BUS 1 0 1 0 1 2.0 0.5Tbit delay PID transmission from other node 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 Stop Bit 1 0 1 0 CXPI frame of other node is destroyed because irregular own node PID is outputted 0 0 1 0 Start Bit 0 1 1.0 0.5Tbit delay Start Bit RXD Transmit prohibit signal (Internal signal) While transmit prohibit signal is set "H", BUS output is stopped BUS output is stopped Receive detect BUS output can generate When the receive data is detected BUS output is stopped for 10 Tbit period. Figure 17. Arbitration Function (When micro controller detects receive data with stopbit) In case of supporting event trigger method of CXPI standard, not to destroy CXPI flame, micro controller should detect startbit of UART receive flame before transmitting PID, and then stop transmission of PID. Fail-safe Function BD41001FJ-C has built in fail-safe mode such as DTC (TXD Dominant Abnormal Detection Circuit), TSD (Abnormal Thermal Detection Circuit) and UVLO/POR (Under Voltage Lockout Circuit/Power ON Reset Circuit). The operations of each abnormal situation are as follows; Table 2. Fail-safe Functions Fail-safe Function State Transition DTC abnormality No change BUS Output CODEC Mode: Logical value1 output(Note 13) Through Mode: Hi-Z(H) fixed RXD Output CLK Output (While using slave) BUS signal output Hi-Z(H) fixed TSD abnormality No change Hi-Z(H) fixed Hi-Z(H) fixed Hi-Z(H) fixed UVLO abnormality No change Hi-Z(H) fixed Hi-Z(H) fixed Hi-Z(H) fixed POR abnormality Power OFF Mode Hi-Z(H) fixed Hi-Z(H) fixed Hi-Z(H) fixed (Note 13) In the case of TXD fixed L, Logical value0 is outputted only in first 10bit. Logical value1 is outputted before DTC abnormality is detected. When "L" time of the TXD pin is more than tDTC, DTC (Dominant Timeout Counter) detects abnormality, and then it stops output. It can return to normal status with the TXD pin as "H" When the junction temperature exceeds TTSD, TSD (Thermal Shutdown) circuit detects abnormality, and then it stops output. It can return to normal status when the temperature drops TTSD_HYS. Operations of UVLO (Under Voltage Lockout) and POR (Power ON Reset) are as follows; When supply voltage is VUVLO or less, UVLO abnormality is detected, and then the BUS, the RXD and the CLK outputs (only slave) are fixed Hi-Z(H). When power supply When power supply is VUVLO or more, transceiver restarts output. When supply voltage drops below VPOR, POR abnormality is detected, and then it changes to "Power OFF Mode", and reset status. www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 10/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Fail-safe Function - continued Absolute maximum rating 0V 5V BAT voltage Mode POR Activ ation range 6.7V 7V UVLO Activation range Operating guarantee range UVLO detection state Power OFF 40V 18V Normal operation Figure 18. Internal Status and Mode by Supply Voltage Absolute Maximum Ratings Table 3. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Voltage Input/Output Voltage Junction Max Temperature Storage Temperature Electro Static Discharge (HBM)(Note 14) Symbol Rating Unit VBAT -0.3 to +40.0 V VMS -0.3 to +40.0 VNSLP ,VTXD -0.3 to +7.0 VRXD -0.3 to +7.0 VBUS -27.0 to +40.0 VCLK -0.3 to +7.0 V V V Tjmax +150 C Tstg -55 to +150 C VESD 4000 V (Note 14) JEDEC qualified. Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the absolute maximum ratings. Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, design a PCB boards with thermal resistance taken into consideration by increasing board size and copper area so as not to exceed the maximum junction temperature rating. www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 11/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Thermal Resistance(Note 15) Table 4. Thermal Resistance Parameter Thermal Resistance (Typ) Symbol Unit 1s(Note 17) 2s2p(Note 18) JA 149.3 76.9 C/W JT 18 11 C/W SOP-J8 Junction to Ambient Junction to Top Characterization Parameter(Note 16) (Note 15) Based on JESD51-2A(Still-Air) (Note 16) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface of the component package. (Note 17) Using a PCB board based on JESD51-3(Table 5). (Note 18) Using a PCB board based on JESD51-7(Table 6). Table 5. 1 Layer Board Layer Number of Measurement Board Single Material Board Size FR-4 114.3mm x 76.2mm x 1.57mmt Top Copper Pattern Thickness Footprints and Traces 70m Table 6. 4 Layers Board Layer Number of Measurement Board 4 Layers Material Board Size FR-4 114.3mm x 76.2mm x 1.6mmt Top 2 Internal Layers Bottom Copper Pattern Thickness Copper Pattern Thickness Copper Pattern Thickness Footprints and Traces 70m 74.2mm x 74.2mm 35m 74.2mm x 74.2mm 70m Recommended Operating Conditions Table 7. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage VBAT 7.0 12.0 18.0 V Operating Temperature Topr -40 +25 +125 C www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 12/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Electrical Characteristics (Unless Otherwise Specified Ta=-40C to +125C, VBAT=7V to 18V) Table 8. Electrical Characteristics (1) Parameter Symbol Min Typ Max Unit Conditions Supply Current 1 IBAT_SLP - 3 10 A Supply Current 2 IBAT_NOR - 3 10 mA H Level Input Voltage VIHMCU_IN 2.0 - - V L Level Input Voltage VILMCU_IN - - 0.8 V Input H Current IIHMCU_IN 6.0 14.0 40.0 A Input L Current IILMCU_IN -5.0 0.0 +5.0 A Wakeup Input Detection Time (TXD) tTXD_WAKEUP 30 100 150 s H Width DDUTYCLK 48 50 95 % Duty Rule of H Width BAT After NSLP shifts from H to L NSLP=H, MS=H, CLK=20kHz (Duty=50%) TXD=10kHz (Duty=50%) TXD, NLSP, CLK (When Input) Input Clock Duty (CLK) Input Voltage=5V MS H Level Input Voltage VIHMS_IN VBAT-1.0 - - V L Level Input Voltage VILMS_IN - - VBAT-3.0 V Input H Current IIHMS_IN -5.0 - +5.0 A Input Voltage= VBAT=18V Input L Current IILMS_IN -5.0 - +5.0 A In Power OFF Mode RXD, CLK (When Output) Output ON Current IOLMCU_OUT 1.3 3.5 - mA Output Pin=0.4V Output OFF Current IOHMCU_OUT -5.0 0.0 +5.0 A Output Pin=5V VBUS_RES VBAT x 0.9 - - V RL=500 VBUS_DOM_1 - - 1.2 V VBAT=7V, RL=500 VBUS_DOM_2 0.6 - - V VBAT=7V, RL=1k VBUS_DOM_3 - - 2.0 V VBAT=18V, RL=500 VBUS_DOM_4 0.8 - - V VBAT=18V, RL=1k H Level Leakage Current IIHBUS -5.0 0.0 +5.0 A When Recessive Output VBAT=VBUS=18V Pull-up Resister Short-circuit Output Current RBUS 20 30 50 k VBAT=12V IOCPBUS 40 - 200 mA VBAT=VBUS=18V, RL=0 IOLBUS -1 - - mA VBAT=12V, VBUS=0V ILBUS - - 20 A VBAT=8V, VBUS=18V ILBUS_NO_GND -1 - +1 mA GND=VBAT=12V, VBUS=0V to 18V Leakage Current when NO_BAT ILBUS_NO_BAT - 100 A VBAT=0V, VBUS=0V to 18V Input H Threshold Voltage VIHBUS_REC VBAT x 0.556 - V BUS (DC Characteristics) Recessive Output Voltage (Note 19) Dominant Output Voltage 1 (Note 19) Dominant Output Voltage 2 (Note 19) Dominant Output Voltage 3 (Note 19) Dominant Output Voltage 4 (Note 19) (Note 19) L Current at Receiver Operating Input Leakage Current at Receiver Operating Leakage Current when NO_GND Input L Threshold Voltage - VILBUS_DOM - - Input Threshold Voltage (Typical) VTHCBUS VBAT x 0.475 VBAT x 0.5 Input Hysteresis Voltage VHYSBUS - - VBAT x 0.423 VBAT x 0.525 VBAT x 0.133 V V V (Note 19) RL is pull-up resistor that is connected between BAT and BUS terminal outside. www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 13/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Electrical Characteristics - continued Table 9. Electrical Characteristics (2) Parameter BUS (AC Characteristics) LO Level Time 1 of Logical Value "1"(Note 20) LO Level Time 2 of Logical Value "1" HI Detection Time of Receiving Difference of LO Level Time between Logical Value "1" and Logical Value "0" Delay Time from the LO Level Detection to Logical Value "0" Output Symbol Min Typ Max Unit Conditions tTX_1_LO_REC - - 0.39Tbit +0.6 - tH_REC=70% tTX_1_LO_DOM 0.11 - - Tbit tH_DOM=30% tTX_0_HI 0.06 - - Tbit tH_REC=55.6% tTX_DIF 0.06 - - Tbit tTX_DIF= tTX_0_LO tTX_1_LO tTX_0_PD - - 0.11 Tbit tH_DOM=30% - - Tbit tH_REC=70% - - Tbit tH_DOM=30% - 0.16 Tbit tH_DOM=30% Ratio for the Recessive Voltage (V_REC_1) when logical value is 1 LO Time 1 of Logical Value "0" tTX_0_LO_REC LO Time 2 of Logical Value "0" tTX_0_LO_DOM BUS Pull-down Time tTX_1_DOM_M tTX_1_LO_REC + 0.06 tTX_1_LO_DOM + 0.06 - Recessive Voltage of Logical Value "0" V_REC_0 93 - - % Wakeup Pulse Detection LO Time for Master Setting tRX_WAKEUP_MASTER 30 100 150 s tH_DOM=42.3% Wakeup Pulse Detection LO Time for Slave Setting tRX_WAKEUP_SLAVE 0.5 3 5 s tH_DOM=42.3% TTSD 150 - 200 C TTSD_HYS - 14 - C VUVLO 5.0 - 6.7 V VPOR - - 5.0 V tDTC 9 13 22 ms TSD TSD Detection Temperature (Note 21) TSD Hysteresis Temperature (Note 21) UVLO UVLO Detection Voltage POR POR Detection Voltage DTC Dominant Time-out Time (Note 20) is a fixed number when BUS (1s 5s) (Note 21) It is a design guarantee parameter, and is not production tested. Tbit tTX_1_LO_REC V_REC_1 BUS Wave Logical Value "1" tTX_1_LO_DOM tH_REC (Note 22) tH_DOM (Note 22) tTX_DIF tTX_0_LO_REC V_REC_0 BUS Wave Logical Value "0" tTX_0_HI tTX_0_LO_DOM tH_REC (Note 22) tH_DOM (Note 22) tTX_1_DOM_M (Note 22) These parameters are shown as the ratio of VBAT. Figure 19. BUS Waves of Logical Value 1, 0 www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 14/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Application Example Slave node (Applicable secondary clock master option) CXPI BUS VECU Regulator 2.7k VDD 2.7k(Note 24) RXD RXD(1) Micro TXD Controller TXD(4) CLK CLK(3) (Note 23) I/O I/O GND 10k MS(8) INT BAT(7) 100nF BD41001FJ-C BUS(6) NSLP(2) GND(5) 220pF (Note 23) INT: Interrupt, RXD: UART RXD, TXD: UART TXD, CLK: Clock, I/O: General Purpose I/O (Note 24) While using slave, it is no problem that the CLK pin is opened in the case of non-using the CLK output. Figure 20. Application Example of Secondary Clock Master Option www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 15/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C I/O Equivalence Circuits Type Equivalence Circuit A Type Equivalence Circuit B Output pin: RXD Input pin: NSLP, TXD BAT C D BUS 1/2 x BAT Input/output pin: CLK CXPI BUS Input/output pin: BUS E Input pin: MS www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 16/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Operational Notes 1. Reverse Connection of Power Supply Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the IC's power supply pins. 2. Power Supply Lines Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. Ground Voltage Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4. Ground Wiring Pattern When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. Also ensure that the ground traces of external components do not cause variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance. 5. Recommended Operating Conditions The function and operation of the IC are guaranteed within the range specified by the recommended operating conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical characteristics. 6. Inrush Current When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 7. Operation Under Strong Electromagnetic Field Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction. 8. Testing on Application Boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC's power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. 9. Inter-pin Short and Mounting Errors Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. 10. Unused Input Pins Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power supply or ground line. www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 17/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Operational Notes - continued 11. Regarding the Input Pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a parasitic diode or transistor. For example (refer to figure below): When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided. Resistor Transistor (NPN) Pin A Pin B C E Pin A N P+ P N N P+ N Pin B B Parasitic Elements N P+ N P N P+ B N C E Parasitic Elements P Substrate P Substrate GND GND Parasitic Elements Parasitic Elements GND GND N Region close-by Figure 21. Example of Monolithic IC Structure 12. Ceramic Capacitor When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with temperature and the decrease in nominal capacitance due to DC bias and others. 13. Area of Safe Operation (ASO) Operate the IC such that the output voltage, output current, and the maximum junction temperature rating are all within the Area of Safe Operation (ASO). 14. Thermal Shutdown Circuit (TSD) This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be within the IC's maximum junction temperature rating. If however the rating is exceeded for a continued period, the junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj falls below the TSD threshold, the circuits are automatically restored to normal operation. Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat damage. www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 18/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Ordering Information B D 4 1 0 0 1 Part Number F J Package FJ: SOP-J8 C - E 2 Product Rank C: for Automotive Packaging and forming specification E2: Embossed tape and reel Marking Diagram SOP-J8(TOP VIEW) Part Number Marking 4 1 0 0 1 LOT Number Pin 1 Mark www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 19/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Physical Dimension and Packing Information Package Name www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 SOP-J8 20/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 BD41001FJ-C Revision History Date Revision 16.Mar.2018 001 26.Mar.2019 002 Changes New Release P1 Added the ApplicationNote information P9 1. In case of collision is happened by transmitting from other node at the same time Added a caution about the time to validate the transmit after an arbitration defeat occurred. www.rohm.com (c) 2018 ROHM Co., Ltd. All rights reserved. TSZ22111 * 15 * 001 21/21 TSZ02201-0E2E0H600200-1-2 26.Mar.2019 Rev.002 Notice Precaution on using ROHM Products 1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property ("Specific Applications"), please consult with the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM's Products for Specific Applications. (Note1) Medical Equipment Classification of the Specific Applications JAPAN USA EU CHINA CLASS CLASSb CLASS CLASS CLASS CLASS 2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. The following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM's Products under any special or extraordinary environments or conditions. If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] Sealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used. However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. The Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8. Confirm that operation temperature is within the specified range described in the product specification. 9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / Circuit board design 1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification Notice-PAA-E (c) 2015 ROHM Co., Ltd. All rights reserved. Rev.004 Precautions Regarding Application Examples and External Circuits 1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for Storage / Transportation 1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2 [b] the temperature or humidity exceeds those recommended by ROHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label A two-dimensional barcode printed on ROHM Products label is for ROHM's internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign Trade act Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export. 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Provided, however, that ROHM will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the Products, subject to the terms and conditions herein. Other Precaution 1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. The proper names of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties. Notice-PAA-E (c) 2015 ROHM Co., Ltd. All rights reserved. Rev.004 Datasheet General Precaution 1. Before you use our Products, you are requested to carefully read this document and fully understand its contents. ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any ROHM's Products against warning, caution or note contained in this document. 2. All information contained in this document is current as of the issuing date and subject to change without any prior notice. Before purchasing or using ROHM's Products, please confirm the latest information with a ROHM sales representative. 3. The information contained in this document is provided on an "as is" basis and ROHM does not warrant that all information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccuracy or errors of or concerning such information. Notice - WE (c) 2015 ROHM Co., Ltd. All rights reserved. Rev.001