1 GSPS Quadrature Digital Upconverter with 18-Bit I/Q Data Path and 14-Bit DAC AD9957 Data Sheet FEATURES GENERAL DESCRIPTION 1 GSPS internal clock speed (up to 400 MHz analog output) Integrated 1 GSPS 14-bit DAC 250 MSPS input data rate Phase noise -125 dBc/Hz (400 MHz carrier @ 1 kHz offset) Excellent dynamic performance >80 dB narrow-band SFDR 8 programmable profiles for shift keying Sin(x)/(x) correction (inverse sinc filter) Reference clock multiplier Internal oscillator for a single crystal operation Software and hardware controlled power-down Integrated RAM Phase modulation capability Multichip synchronization Easy interface to Blackfin SPORT Interpolation factors from 4x to 252x Interpolation DAC mode Gain control DAC Internal divider allows references up to 2 GHz 1.8 V and 3.3 V power supplies 100-lead TQFP_EP package The AD9957 functions as a universal I/Q modulator and agile upconverter for communications systems where cost, size, power consumption, and dynamic performance are critical. The AD9957 integrates a high speed, direct digital synthesizer (DDS), a high performance, high speed, 14-bit digital-to-analog converter (DAC), clock multiplier circuitry, digital filters, and other DSP functions onto a single chip. It provides baseband upconversion for data transmission in a wired or wireless communications system. APPLICATIONS The user interface to the control functions includes a serial port easily configured to interface to the SPORT of the Blackfin(R) DSP and profile pins to enable fast and easy shift keying of any signal parameter (phase, frequency, or amplitude). The AD9957 is the third offering in a family of quadrature digital upconverters (QDUCs) that includes the AD9857 and AD9856. It offers performance gains in operating speed, power consumption, and spectral performance. Unlike its predecessors, it supports a 16-bit serial input mode for I/Q baseband data. The device can alternatively be programmed to operate either as a single tone, sinusoidal source or as an interpolating DAC. The reference clock input circuitry includes a crystal oscillator, a high speed, divide-by-two input, and a low noise PLL for multiplication of the reference clock frequency. HFC data, telephony, and video modems Wireless base station transmissions Broadband communications transmissions Internet telephony FUNCTIONAL BLOCK DIAGRAM I I/Q DATA FORMAT AND INTERPOLATE 14-BIT DAC DATA FOR XMIT Q NCO TIMING AND CONTROL AD9957 USER INTERFACE REFERENCE CLOCK INPUT 06384-001 REFERENCE CLOCK INPUT CIRCUITRY Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007-2012 Analog Devices, Inc. All rights reserved. AD9957 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RAM Control .................................................................................. 27 Applications ....................................................................................... 1 RAM Overview ........................................................................... 27 General Description ......................................................................... 1 RAM Segment Registers ............................................................ 27 Functional Block Diagram .............................................................. 1 RAM State Machine ................................................................... 27 Revision History ............................................................................... 4 RAM Trigger (RT) Pin ............................................................... 27 Specifications..................................................................................... 5 Load/Retrieve RAM Operation ................................................ 28 Electrical Specifications ............................................................... 5 RAM Playback Operation ......................................................... 28 Absolute Maximum Ratings............................................................ 8 Overview of RAM Playback Modes......................................... 29 ESD Caution .................................................................................. 8 RAM Ramp-Up Mode ........................................................... 29 Pin Configuration and Function Descriptions ............................. 9 RAM Bidirectional Ramp Mode .......................................... 30 Typical Performance Characteristics ........................................... 12 RAM Continuous Bidirectional Ramp Mode .................... 32 Modes of Operation ....................................................................... 16 RAM Continuous Recirculate Mode ................................... 33 Overview...................................................................................... 16 Clock Input (REF_CLK) ................................................................ 34 Quadrature Modulation Mode ................................................. 17 REFCLK Overview..................................................................... 34 BlackFin Interface (BFI) Mode ................................................. 18 Crystal Driven REF_CLK ......................................................... 34 Interpolating DAC Mode .......................................................... 19 Direct Driven REF_CLK ........................................................... 34 Single Tone Mode ....................................................................... 20 Phase-Locked Loop (PLL) Multiplier ...................................... 35 Signal Processing ............................................................................ 21 PLL Charge Pump ...................................................................... 36 Parallel Data Clock (PDCLK) ................................................... 21 External PLL Loop Filter Components ................................... 36 Transmit Enable Pin (TxEnable) .............................................. 21 PLL Lock Indication .................................................................. 36 Input Data Assembler ................................................................ 22 Additional Features ........................................................................ 37 Inverse CCI Filter ....................................................................... 23 Output Shift Keying (OSK) ....................................................... 37 Fixed Interpolator (4x) .............................................................. 23 Manual OSK............................................................................ 37 Programmable Interpolating Filter .......................................... 24 Automatic OSK....................................................................... 37 QDUC Mode ........................................................................... 24 Profiles ......................................................................................... 38 BFI Mode ................................................................................. 24 I/O_UPDATE Pin ...................................................................... 38 Quadrature Modulator .............................................................. 25 Automatic I/O Update ............................................................... 38 DDS Core..................................................................................... 25 Power-Down Control ................................................................ 39 Inverse Sinc Filter ....................................................................... 25 General-Purpose I/O (GPIO) Port .......................................... 39 Output Scale Factor (OSF) ........................................................ 26 Synchronization of Multiple Devices ........................................... 40 14-Bit DAC .................................................................................. 26 Overview ..................................................................................... 40 Auxiliary DAC ........................................................................ 26 Clock Generator ......................................................................... 40 Rev. C | Page 2 of 64 Data Sheet AD9957 Sync Generator ............................................................................40 I/O_RESET--Input/Output Reset ........................................ 48 Sync Receiver ...............................................................................41 I/O_UPDATE--Input/Output Update ................................ 48 Setup/Hold Validation ................................................................42 Serial I/O Timing Diagrams ...................................................... 48 Synchronization Example ..........................................................44 MSB/LSB Transfers ..................................................................... 48 I/Q Path Latency .........................................................................45 I/O_UPDATE, SYNC_CLK, and System Clock Relationships................................................................................ 49 Example ....................................................................................45 Power Supply Partitioning .............................................................46 3.3 V Supplies ..............................................................................46 DVDD_I/O (Pin 11, Pin 15, Pin 21, Pin 28, Pin 45, Pin 56, Pin 66) ......................................................................................46 Register Map and Bit Descriptions ............................................... 50 Register Map ................................................................................ 50 Register Bit Descriptions............................................................ 55 Control Function Register 1 (CFR1) .................................... 55 AVDD (Pin 74 to Pin 77 and Pin 83) ...................................46 Control Function Register 2 (CFR2) .................................... 56 1.8 V Supplies ..............................................................................46 Control Function Register 3 (CFR3) .................................... 58 DVDD (Pin 17, Pin 23, Pin 30, Pin 47, Pin 57, Pin 64) .....46 Auxiliary DAC Control Register........................................... 58 AVDD (Pin 3) ..........................................................................46 I/O Update Rate Register ....................................................... 58 AVDD (Pin 6) ..........................................................................46 RAM Segment Register 0 ....................................................... 58 AVDD (Pin 89 and Pin 92) ....................................................46 RAM Segment Register 1 ....................................................... 59 Serial Programming ........................................................................47 Amplitude Scale Factor (ASF) Register ............................... 59 Control Interface--Serial I/O ....................................................47 Multichip Sync Register ......................................................... 59 General Serial I/O Operation ....................................................47 Profile Registers........................................................................... 60 Instruction Byte ...........................................................................47 Profile<7:0> Register--Single Tone...................................... 60 Instruction Byte Information Bit Map .................................47 Profile<7:0> Register--QDUC ............................................. 60 Serial I/O Port Pin Descriptions ...............................................47 RAM Register .......................................................................... 60 SCLK--Serial Clock................................................................47 GPIO Configuration Register ............................................... 60 CS--Chip Select Bar ...............................................................47 GPIO Data Register ................................................................ 60 SDIO--Serial Data Input/Output .........................................47 Outline Dimensions ........................................................................ 61 SDO--Serial Data Out ...........................................................48 Ordering Guide ........................................................................... 61 Rev. C | Page 3 of 64 AD9957 Data Sheet REVISION HISTORY 4/12--Rev. B to Rev. C Changes to Table 1 ............................................................................ 7 Changes to Table 3 .......................................................................... 11 Change to Sync Generator Section............................................... 41 Changes to Sync Receiver Section and Setup/Hold Validation Section .............................................................................................. 42 Changes to Table 13 ........................................................................ 50 Changes to Table 19 ........................................................................ 57 Changes to Table 26 ........................................................................ 59 10/10--Rev. A to Rev. B Changes to Data Rate in Features Section ..................................... 1 Changes to Specifications Section .................................................. 6 Added EPAD Notation to Figure 4 and Table 3 ........................... 9 Changes to XTAL_SEL Pin Description ...................................... 11 Changes to BlackFin Interface (BFI) Mode Section .................. 18 Changes to Figure 30 and Figure 31 ............................................. 22 Changes to Programmable Interpolating Filter Section ............ 24 Changes to Fifth Paragraph of Quadrature Modulator Section...... 25 Changes to RAM Segment Registers Section ............................. 27 Changes to RAM Playback Operation Section ........................... 28 Changes to Control Interface--Serial I/O Section ..................... 47 Added to I/O_UPDATE, SYNC_CLK, and System Clock Relationships Section and Figure 64 ............................................ 49 Changes to Default Values of Profile 0 Register--Single Tone (0x0E) and Profile 0 Register--QDUC (0x0E) in Table 14 ....... 51 Changes to Default Values in Table 15......................................... 52 Changes to Default Values in Table 16......................................... 53 Changes to Default Values in Table 17......................................... 54 Updated Outline Dimensions ....................................................... 61 1/08--Rev. 0 to Rev. A Changes to REFCLK Multiplier Specification ...............................3 Changes to I/O_Update/Profile<2:0>/RT Timing Characteristics and I/Q Input Timing Characteristics .................5 Replaced Pin Configuration and Function Descriptions Section.................................................................................................8 Changes to Figure 25 Through Figure 29.................................... 15 Deleted Table 4, Renumbered Sequentially ................................ 20 Changes to DDS Core Section ...................................................... 24 Changes to Figure 47 and Table 6................................................. 33 Replaced Synchronization of Multiple Devices Section ............ 39 Added I/Q Path Latency Section .................................................. 44 Added Power Supply Partitioning Section .................................. 45 Changes to General Serial I/O Operation Section ..................... 46 Changes to Table 13 ....................................................................... 48 Changes to Table 14 ....................................................................... 49 Changes to Table 19 ....................................................................... 54 Changes to Table 20 ....................................................................... 56 Changes to GPIO Configuration Register and GPIO Data Register Sections ........................................................ 58 5/07--Revision 0: Initial Version Rev. C | Page 4 of 64 Data Sheet AD9957 SPECIFICATIONS ELECTRICAL SPECIFICATIONS AVDD (1.8V) and DVDD (1.8V) = 1.8 V 5%, AVDD (3.3V) = 3.3 V 5%, DVDD_I/O (3.3V) = 3.3 V 5%, T = 25C, RSET = 10 k, IOUT = 20 mA, external reference clock frequency = 1000 MHz with REFCLK multiplier disabled, unless otherwise noted. Table 1. Parameter REF_CLK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Maximum REFCLK Input Divider Frequency Minimum REFCLK Input Divider Frequency External Crystal Input Capacitance Input Impedance (Differential) Input Impedance (Single-Ended) Duty Cycle REF_CLK Input Level REFCLK MULTIPLIER VCO GAIN CHARACTERISTICS VCO Gain (KV) @ Center Frequency REFCLK_OUT CHARACTERISTICS Maximum Capacitive Load Maximum Frequency DAC OUTPUT CHARACTERISTICS Full-Scale Output Current Gain Error Output Offset Differential Nonlinearity Integral Nonlinearity Output Capacitance Residual Phase Noise REFCLK Multiplier Test Conditions/Comments Min Disabled Enabled Full temperature range Full temperature range 60 3.2 1500 REFCLK multiplier disabled REFCLK multiplier enabled Single-ended Differential 45 40 50 100 VCO0 range setting VCO1 range setting VCO2 range setting VCO3 range setting VCO4 range setting VCO5 range setting 2 8.6 -10 Typ 1900 25 25 3 2.8 1.4 Max Unit 1000 1 60 MHz MHz MHz MHz MHz pF k k % % mV p-p mV p-p 35 55 60 1000 2000 429 500 555 750 789 850 MHz/V MHz/V MHz/V MHz/V MHz/V MHz/V 20 25 pF MHz 20 31.6 +10 2.3 0.8 1.5 5 @ 1 kHz Offset, 20 MHz AOUT Disabled Enabled @ 20x Enabled @ 100x AC Voltage Compliance Range SPURIOUS-FREE DYNAMIC RANGE (SFDR SINGLE TONE) fOUT = 20.1 MHz fOUT = 98.6 MHz fOUT = 201.1 MHz fOUT = 397.8 MHz -152 -140 -140 -0.5 +0.5 -70 -69 -61 -54 Rev. C | Page 5 of 64 mA %FS A LSB LSB pF dBc/Hz dBc/Hz dBc/Hz V dBc dBc dBc dBc AD9957 Parameter NOISE SPECTRAL DENSITY (NSD) Single Tone fOUT = 20.1 MHz fOUT = 98.6 MHz fOUT = 201.1 MHz fOUT = 397.8 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fOUT = 25 MHz fOUT = 50 MHz fOUT = 100 MHz MODULATOR CHARACTERISTICS Input Data Error Vector Magnitude WCDMA--FDD (TM1), 3.84 MHz Bandwidth, 5 MHz Channel Spacing Adjacent Channel Leakage Ratio (ACLR) Data Sheet Test Conditions/Comments Min Maximum SCLK Rise/Fall Time Minimum Data Setup Time to SCLK Minimum Data Hold Time to SCLK Maximum Data Valid Time in Read Mode I/O_UPDATE/PROFILE<2:0>/RT TIMING CHARACTERISTICS Minimum Pulse Width Max Unit -167 -162 -157 -151 dBm/Hz dBm/Hz dBm/Hz dBm/Hz -82 -78 -73 dBc dBc dBc 0.53 0.77 % % 0.35 % -78 dBc -78 dBc 70 Mbps ns ns ns ns ns ns I/Q rate = 62.5 MSPS; 16x interpolation 2.5 Msymbols/s, QPSK, 4x oversampled 270.8333 ksymbols/s, GMSK, 32x oversampled 2.5 Msymbols/s, 256-QAM, 4x oversampled IF = 143.88 MHz Carrier Feedthrough SERIAL PORT TIMING CHARACTERISTICS Maximum SCLK Frequency Minimum SCLK Pulse Width Typ Low High 4 4 2 5 0 11 High Minimum Setup Time to SYNC_CLK Minimum Hold Time to SYNC_CLK I/Q INPUT TIMING CHARACTERISTICS Maximum PDCLK Frequency Minimum I/Q Data Setup Time to PDCLK Minimum I/Q Data Hold Time to PDCLK Minimum TxEnable Setup Time to PDCLK Minimum TxEnable Hold Time to PDCLK MISCELLANEOUS TIMING CHARACTERISTICS Wake-Up Time 3 Fast Recovery Mode Full Sleep Mode Minimum Reset Pulse Width High DATA LATENCY (PIPELINE DELAY) Data Latency Single Tone Mode Frequency, Phase-to-DAC Output 1 SYNC_CLK cycle ns ns 1.75 0 250 MHz ns ns ns ns 1.75 0 1.75 0 1 8 5 SYSCLK cycles4 s SYSCLK cycles 4 79 SYSCLK cycles4 150 Rev. C | Page 6 of 64 Data Sheet Parameter CMOS LOGIC INPUTS Voltage Logic 1 Logic 0 Current Logic 1 Logic 0 Input Capacitance XTAL_SEL INPUT Logic 1 Voltage Logic 0 Voltage Input Capacitance CMOS LOGIC OUTPUTS Voltage Logic 1 Logic 0 POWER SUPPLY CURRENT DVDD_I/O (3.3V) Pin Current Consumption DVDD (1.8V) Pin Current Consumption AVDD (3.3V) Pin Current Consumption AVDD (1.8V) Pin Current Consumption POWER CONSUMPTION Single Tone Mode Continuous Modulation Inverse Sinc Filter Power Consumption Full Sleep Mode AD9957 Test Conditions/Comments Min Typ Max Unit 0.8 V V 2.0 90 90 2 150 150 1.25 0.6 2 A A pF V V pF 1 mA load 2.8 0.4 QDUC mode QDUC mode QDUC mode QDUC mode 8x interpolation 16 610 28 105 800 1400 150 12 V V mA mA mA mA 1800 200 40 mW mW mW mW The system clock is limited to 750 MHz maximum in BFI mode. The gain value for VCO range Setting 5 is measured at 1000 MHz. 3 Wake-up time refers to the recovery from analog power-down modes. The longest time required is for the Reference Clock Multiplier PLL to relock to the reference. 4 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency, the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier and divider are not used, the SYSCLK frequency is the same as the external reference clock frequency. 1 2 Rev. C | Page 7 of 64 AD9957 Data Sheet ABSOLUTE MAXIMUM RATINGS DIGITAL INPUTS Table 2. DVDD_I/O Rating 2V 4V -0.7 V to +4 V -0.7 V to +2.2 V 5 mA -65C to +150C -40C to +85C 22C/W 2.8C/W 150C 300C AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING ESD DIODES MAY COUPLE DIGITAL NOISE ONTO POWER PINS. 06384-003 INPUT Figure 2. Equivalent Input Circuit DAC OUTPUTS AVDD Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. IOUT IOUT MUST TERMINATE OUTPUTS TO AGND FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. Figure 3. Equivalent Output Circuit ESD CAUTION Rev. C | Page 8 of 64 06384-055 Parameter AVDD (1.8V), DVDD (1.8V) Supplies AVDD (3.3V), DVDD_I/O (3.3V) Supplies Digital Input Voltage XTAL_SEL Digital Output Current Storage Temperature Range Operating Temperature Range JA JC Maximum Junction Temperature Lead Temperature, Soldering (10 sec) Data Sheet AD9957 1 2 AGND NC NC AGND DAC_RSET AVDD (3.3V) AGND 87 86 85 84 83 82 AVDD (3.3V) AVDD (1.8V) 88 AVDD (3.3V) REF_CLK 89 76 REF_CLK 90 AGND AVDD (1.8V) 91 77 NC 92 AGND REFCLK_OUT 93 78 XTAL_SEL 94 79 AGND 95 IOUT NC 96 IOUT NC 97 80 NC 98 81 NC 99 PIN 1 INDICATOR 75 AVDD (3.3V) 74 AVDD (3.3V) AGND NC AVDD (1.8V) 3 73 AGND 4 72 AGND 5 71 AVDD (1.8V) 6 70 I/O_RESET CS SYNC_IN+ 7 69 SCLK SYNC_IN- 8 68 SYNC_OUT+ 9 67 SDO SDIO SYNC_OUT- 10 66 DVDD_I/O (3.3V) 11 65 AD9957 SYNC_SMP_ERR 12 TQFP-100 (E_PAD) TOP VIEW (Not to Scale) DGND 13 MASTER_RESET 14 DVDD_I/O (3.3V) DGND 64 DVDD (1.8V) 63 DGND DGND 62 DVDD_I/O (3.3V) 15 61 DGND 16 60 NC OSK DVDD (1.8V) 17 59 I/O_UPDATE EXT_PWR_DWN 18 PLL_LOCK 19 58 DGND DVDD (1.8V) CCI_OVFL 20 56 DVDD_I/O (3.3V) 21 55 DVDD_I/O (3.3V) SYNC_CLK 57 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD SHOULD BE SOLDERED TO GROUND. Figure 4. Pin Configuration Rev. C | Page 9 of 64 D1 49 D0 50 D2 48 DGND 46 DVDD (1.8V) 47 D3 44 DVDD_I/O (3.3V) 45 D5/SPORT I-DATA 42 D4/SPORT Q-DATA 43 TxENABLE/FS 41 D6 39 PDCLK 40 RT D8 37 D7 38 51 D10 35 D9 36 D17 25 D12 33 D11 34 PROFILE1 PROFILE2 D14 31 D13 32 52 DVDD (1.8V) 30 PROFILE0 53 DVDD_I/O (3.3V) 28 DGND 29 54 D16 26 D15 27 DGND 22 DVDD (1.8V) 23 NC 24 06384-004 NC PLL_LOOP_FILTER 100 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9957 Data Sheet Table 3. Pin Function Descriptions Pin No. 1, 24, 61, 72, 86, 87, 93, 97 to 100 2 3, 6, 89, 92 74 to 77, 83 17, 23, 30, 47, 57, 64 11, 15, 21, 28, 45, 56, 66 4, 5, 73, 78, 79, 82, 85, 88, 96 13, 16, 22, 29, 46, 58, 62, 63, 65 7 Mnemonic NC I/O 1 Description Not Connected. Allow device pin to float. PLL_LOOP_FILTER AVDD (1.8V) AVDD (3.3V) DVDD (1.8V) I I I I PLL-Loop Filter Compensation. See External PLL Loop Filter Components section. Analog Core VDD. 1.8 V analog supplies. Analog DAC VDD. 3.3 V analog supplies. Digital Core VDD. 1.8 V digital supplies. DVDD_I/O (3.3V) I Digital Input/Output VDD. 3.3 V digital supplies. AGND I Analog Ground. DGND I Digital Ground. SYNC_IN+ I 8 SYNC_IN- I 9 SYNC_OUT+ O 10 SYNC_OUT- O 12 SYNC_SMP_ERR O 14 MASTER_RESET I 18 EXT_PWR_DWN I 19 PLL_LOCK O 20 CCI_OVFL O 25 to 27, 31 to 39, 42 to 44, 48 to 50 42 43 40 41 D<17:0> I/O SPORT I-DATA SPORT Q-DATA PDCLK TxENABLE/FS I I O I 51 RT I 52 to 54 PROFILE<2:0> I 55 SYNC_CLK O Synchronization Signal, Digital Input (Rising Edge Active). Synchronization signal from external master to synchronize internal subclocks. See the Synchronization of Multiple Devices section. Synchronization Signal, Digital Input (Falling Edge Active). Synchronization signal from external master to synchronize internal subclocks. See the Synchronization of Multiple Devices section. Synchronization Signal, Digital Output (Rising Edge Active). Synchronization signal from internal device subclocks to synchronize external slave devices. See the Synchronization of Multiple Devices section. Synchronization Signal, Digital Output (Falling Edge Active). Synchronization signal from internal device subclocks to synchronize external slave devices. See the Synchronization of Multiple Devices section. Synchronization Sample Error, Digital Output (Active High). A high on this pin indicates that the AD9957 did not receive a valid sync signal on SYNC_IN+/SYNC_IN-. See the Synchronization of Multiple Devices section. Master Reset, Digital Input (Active High). This pin clears all memory elements and sets registers to default values. External Power-Down, Digital Input (Active High). A high level on this pin initiates the currently programmed power-down mode. See the Power-Down Control section for further details. If unused, tie to ground. PLL Lock, Digital Output (Active High). A high on this pin indicates that the clock multiplier PLL has acquired lock to the reference clock input. CCI Overflow Digital Output, Active High. A high on this pin indicates a CCI filter overflow. This pin remains high until the CCI overflow condition is cleared. Parallel Data Input Bus (Active High). These pins provide the interleaved, 18-bit, digital, I and Q vectors for the modulator to upconvert. Also used for a GPIO port in Blackfin interface mode. In Blackfin interface mode, this pin serves as the I-data serial input. In Blackfin interface mode, this pin serves as the Q-data serial input. Parallel Data Clock, Digital Output (Clock). See the Signal Processing section for details. Transmit Enable, Digital Input (Active High). See the Signal Processing section for details. In Blackfin interface mode, this pin serves as the FS input to receive the RFS output signal from the Blackfin. RAM Trigger, Digital Input (Active High). This pin provides control for the RAM amplitude scaling function. When this function is engaged, a high sweeps the amplitude from the beginning RAM address to the end. A low sweeps the amplitude from the end RAM address to the beginning. If unused, connect to ground or supply. Profile Select Pins, Digital Inputs (Active High). These pins select one of eight phase/frequency profiles for the DDS core (single tone or carrier tone). Changing the state of one of these pins transfers the current contents of all I/O buffers to the corresponding registers. State changes should be set up to the SYNC_CLK pin. Output System Clock/4, Digital Output (Clock). The I/O_UPDATE and PROFILE<2:0> pins should be set up to the rising edge of this signal. Rev. C | Page 10 of 64 Data Sheet AD9957 Pin No. 59 Mnemonic I/O_UPDATE I/O 1 I/O 60 OSK I 67 SDIO I/O 68 SDO O 69 SCLK I 70 CS I 71 I/O_RESET I 80 IOUT O 81 IOUT O 84 DAC_RSET O 90 91 REF_CLK REF_CLK I I 94 REFCLK_OUT O 95 XTAL_SEL I (EPAD) Exposed Pad (EPAD) 1 Description Input/Output Update; Digital Input Or Output (Active High) Depending on the Internal I/O Update Active Bit. A high on this pin indicates a transfer of the contents of the I/O buffers to the corresponding internal registers. Output Shift Keying, Digital Input (Active High). When using OSK (manual or automatic), this pin controls the OSK function. See the Output Shift Keying (OSK) section of the data sheet for details. When not using OSK, tie this pin high. Serial Data Input/Output, Digital Input/Output (Active High). This pin can be either unidirectional or bidirectional (default), depending on configuration settings. In bidirectional serial port mode, this pin acts as the serial data input and output. In unidirectional, it is an input only. Serial Data Output, Digital Output (Active High). This pin is only active in unidirectional serial data mode. In this mode, it functions as the output. In bidirectional mode, this pin is not operational and should be left floating. Serial Data Clock. Digital clock (rising edge on write, falling edge on read). This pin provides the serial data clock for the control data path. Write operations to the AD9957 use the rising edge. Readback operations from the AD9957 use the falling edge. Chip Select, Digital Input (Active Low). Bringing this pin low enables the AD9957 to detect serial clock rising/falling edges. Bringing this pin high causes the AD9957 to ignore input on the serial data pins. Input/Output Reset, Digital Input (Active High). Rather than resetting the entire device during a failed communication cycle, when brought high, this pin resets the state machine of the serial port controller and clears any I/O buffers that have been written since the last I/O update. When unused, tie this pin to ground to avoid accidental resets. Open-Source DAC Complementary Output Source. Analog output, current mode. Connect through 50 to AGND. Open-Source DAC Output Source. Analog output, current mode. Connect through 50 to AGND. Analog Reference Pin. This pin programs the DAC output full-scale reference current. Attach a 10 k resistor to AGND. Reference Clock Input. Analog input. See the REFCLK Overview section for more details. Complementary Reference Clock Input. Analog input. See the REFCLK Overview section for more details. Reference Clock Output. Analog output. See the REFCLK Overview section for more details. Crystal Select (1.8 V Logic). Analog input (active high). Driving the XTAL_SEL pin high enables the internal oscillator to be used with a crystal resonator. If unused, connect it to AGND. The EPAD should be soldered to ground. I = input, O = output. Rev. C | Page 11 of 64 AD9957 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1 1 0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 1 -70 -70 -80 -80 -90 START 0Hz 50MHz/DIV -90 -100 STOP 500MHz CENTER 102MHz 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 1 -70 -80 -80 06384-050 -70 -90 -100 START 0MHz 50MHz/DIV -100 STOP 500MHz CENTER 222MHz 5kHz/DIV SPAN 50kHz Figure 9. Narrow-Band View of Figure 6 (with Carrier And Lower Sideband Suppression) 1 1 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 1 -90 Figure 6. 15.625 kHz Quadrature Tone, Carrier = 222 MHz, CCI = 16, fS = 1 GHz 0 SPAN 50kHz 1 1 0 -60 5kHz/DIV Figure 8. Narrow-Band View of Figure 5 (with Carrier and Lower Sideband Suppression) Figure 5. 15.625 kHz Quadrature Tone, Carrier = 102 MHz, CCI = 16, fS = 1 GHz 06384-051 -100 06384-049 06384-048 1 -50 1 -60 -60 -70 -70 -80 -80 -90 -100 START 0Hz 50MHz/DIV 06384-053 06384-052 1 -90 -100 STOP 500MHz Figure 7. 15.625 kHz Quadrature Tone, Carrier = 372 MHz, CCI = 16, fS = 1 GHz CENTER 372MHz 5kHz/DIV SPAN 50kHz Figure 10. Narrow-Band View of Figure 7 (with Carrier and Lower Sideband Suppression) Rev. C | Page 12 of 64 AD9957 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 06384-044 0 START 0Hz 50MHz/DIV -100 STOP 500MHz Figure 11. QPSK, 7.8125 Msymbols/s, 4x Oversampled Raised Cosine, = 0.25, CCI = 8, Carrier = 102 MHz, fS = 1 GHz -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 06384-045 0 -10 -100 START 0MHz 50MHz/DIV -100 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 06384-046 0 START 0Hz 50MHz/DIV CENTER 222MHz 2MHz/DIV SPAN 20MHz Figure 15. Narrow-Band View of Figure 12 Figure 12. QPSK, 7.8125 Msymbols/s, 4x Oversampled Raised Cosine, = 0.25, CCI = 8, Carrier = 222 MHz, fS = 1 GHz -100 SPAN 20MHz -90 STOP 500MHz -90 2MHz/DIV Figure 14. Narrow-Band View of Figure 11 0 -90 CENTER 102MHz 06384-042 -100 -90 06384-043 -90 06384-041 Data Sheet -90 -100 STOP 500MHz Figure 13. QPSK, 7.8125 Msymbols/s, 4x Oversampled Raised Cosine, = 0.25, CCI = 8, Carrier = 372 MHz, fS = 1 GHz Rev. C | Page 13 of 64 CENTER 372MHz 2MHz/DIV SPAN 20MHz Figure 16. Narrow-Band View of Figure 13 AD9957 Data Sheet -50 -90 fOUT = 397.8MHz -100 -55 -110 MAGNITUDE (dBc/Hz) SFDR (dBc) SFDR WITHOUT PLL -60 SFDR WITH PLL -65 fOUT = 201.1MHz -120 fOUT = 98.6MHz -130 -140 -150 -70 0 50 100 150 200 250 300 350 -170 10 400 100 06384-061 06384-058 100M fOUT = 397.8MHz -100 -50 MAGNITUDE (dBc/ Hz) HIGH SUPPLY -55 SFDR (dBc) 10M -90 LOW SUPPLY -60 -65 fOUT = 201.1MHz -110 -120 -130 -140 fOUT = 20.1MHz -70 06384-059 -150 0 50 100 150 200 250 300 350 400 -160 10 450 fOUT = 98.6MHz 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) FREQUENCY OUT (MHz) Figure 21. Residual Phase Noise Using the REFCLK Multiplier, REFCLK = 50 MHz with 20x Multiplication, System Clock = 1 GHz Figure 18. SFDR vs. Output Frequency and Supply (5%) in Single Tone Mode, REFCLK = 1 GHz 1200 -50 DVDD 1.8V -40C 1000 POWER DISSIPATION (mW) +85C -55 -60 -65 -70 800 600 400 AVDD 1.8V AVDD 3.3V DVDD 3.3V 06384-060 200 0 50 100 150 200 250 300 350 400 450 0 100 06384-062 SFDR (dBc) 1M Figure 20. Residual Phase Noise, System Clock = 1 GHz -45 -75 100k FREQUENCY OFFSET (Hz) Figure 17. Wideband SFDR vs. Output Frequency in Single Tone Mode, PLL with REFCLK = 15.625 MHz x 64 -75 10k 1k FREQUENCY OUT (MHz) 06384-054 -75 -160 fOUT = 20.1MHz 200 300 400 500 600 700 800 900 1000 SYSTEM CLOCK FREQUENCY (MHz) FREQUENCY OUT (MHz) Figure 19. SFDR vs. Frequency and Temperature in Single Tone Mode, REFCLK = 1 GHz Rev. C | Page 14 of 64 Figure 22. Power Dissipation vs. System Clock (PLL Disabled) Data Sheet AD9957 1200 -20 -30 DVDD 1.8V -40 800 -50 -60 600 -70 -80 400 -90 AVDD 1.8V 200 0 400 AVDD 3.3V -100 500 600 700 800 900 06384-064 DVDD 3.3V 06384-063 POWER DISSIPATION (mW) 1000 -110 CENTER 143.86MHz 1000 SYSTEM CLOCK FREQUENCY (MHz) Figure 23. Power Dissipation vs. System Clock (PLL Enabled) 2.55MHz/DIV SPAN 25.5MHz Tx CHANNEL BANDWIDTH: 3.84MHz W-CDMA SGFF FWD POWER: -11.88dBm ADJACENT CHANNEL BANDWIDTH: 3.84MHz SPACING: 3MHz LOWER: -78.27dB UPPER: -78.50dB ADJACENT CHANNEL BANDWIDTH: 3.84MHz SPACING: 10MHz LOWER: -81.42dB UPPER: -81.87dB Figure 24. Typical ACLR for Wideband CDMA Rev. C | Page 15 of 64 AD9957 Data Sheet MODES OF OPERATION than that of the DAC. An internal chain of rate interpolation filters the user data and upsamples to the DAC sample rate. Combined, the filters provide for programmable rate interpolation while suppressing spectral images and retaining the original baseband spectrum. OVERVIEW The AD9957 has three basic operating modes. Quadrature modulation (QDUC) mode (default) Interpolating DAC mode Single tone mode QDUC mode employs both the DDS and the rate interpolation filters. In this case, two parallel banks of rate interpolation filters allow baseband processing of in-phase and quadrature (I/Q) signals with the DDS providing the carrier signal to be modulated by the baseband signals. A detailed block diagram of the AD9957 is shown in Figure 25. The active mode is selected via the operating mode bits in Control Function Register 1 (CFR1). Single tone mode allows the device to operate as a sinusoidal generator with the DDS driving the DAC directly. The inverse sinc filter is available in all three modes. AD9957 PW CCI (1x TO 63x) IS cos (t+) Q FTW CCI (1x TO 63x) 18 HALF-BAND FILTERS (4x) 16 INVERSE CCI QS 8 DAC GAIN DDS sin (t+) CLOCK AUX DAC 8-BIT DAC_RSET DAC 14-BIT INVERSE SINC FILTER HALF-BAND FILTERS (4x) 16 INVERSE CCI I 18 BLACKFIN INTERFACE I/Q IN 18 DATA ASSEMBLER AND FORMATTER Interpolating DAC mode bypasses the DDS, allowing the user to deliver baseband data to the device at a sample rate lower IOUT IOUT OUTPUT SCALE FACTOR REFCLK_OUT SYSCLK CLOCK MODE OSK /2 PDCLK PARALLEL DATA TIMING AND CONTROL TxENABLE INTERNAL CLOCK TIMING AND CONTROL PLL REF_CLK REF_CLK XTAL_SEL 2 2 Figure 25. Detailed Block Diagram Rev. C | Page 16 of 64 06384-005 MASTER_RESET PLL_LOCK PLL_LOOP_FILTER IS QS RT SDIO SDO SCLK I/O_RESET CS I/O_UPDATE IQ SYNC_IN 3 POWER DOWN CONTROL RAM EXT_PWR_DWN SERIAL I/O PORT CCI_OVFL OSK PROGRAMMING REGISTERS PROFILE FTW PW SYNC_OUT * * * Data Sheet AD9957 The PROFILE and I/O_UPDATE pins are also synchronous to the PDCLK. QUADRATURE MODULATION MODE The DDS core provides a quadrature (sine and cosine) local oscillator signal to the quadrature modulator, where the interpolated I and Q samples are multiplied by the respective phase of the carrier and summed together, producing a quadrature modulated data stream. This data stream is routed through the inverse sinc filter (optionally), and the output scaling multiplier. Then it is applied to the 14-bit DAC to produce the quadrature modulated analog output signal. AD9957 PW CCI (1x TO 63x) IS cos (t+) Q FTW CCI (1x TO 63x) 18 HALF-BAND FILTERS (4x) QS 16 8 DAC GAIN DDS sin (t+) CLOCK AUX DAC 8-BIT DAC_RSET DAC 14-BIT INVERSE SINC FILTER HALF-BAND FILTERS (4x) INVERSE CCI 16 INVERSE CCI 18 I 18 BLACKFIN INTERFACE I/Q IN DATA ASSEMBLER AND FORMATTER A block diagram of the AD9957 operating in QDUC mode is shown in Figure 26; grayed items are inactive. The parallel input accepts 18-bit I- and Q-words in time-interleaved fashion. That is, an 18-bit I-word is followed by an 18-bit Q-word, then the next 18-bit I-word, and so on. One 18-bit I-word and one 18-bit Q-word together comprise one internal sample. The data assembler and formatter de-interleave the I- and Q-words so that each sample propagates along the internal data pathway in parallel fashion. Both I and Q data paths are active; the parallel data clock (PDCLK) serves to synchronize the input of I/Q data to the AD9957. IOUT IOUT OUTPUT SCALE FACTOR REFCLK_OUT SYSCLK CLOCK MODE OSK /2 PDCLK PARALLEL DATA TIMING AND CONTROL TxENABLE INTERNAL CLOCK TIMING AND CONTROL PLL REF_CLK REF_CLK XTAL_SEL 2 2 SYNC_OUT SYNC_IN Figure 26. Quadrature Modulation Mode Rev. C | Page 17 of 64 06384-006 MASTER_RESET PLL_LOCK PLL_LOOP_FILTER IS QS RT SDIO SDO SCLK I/O_RESET CS I/O_UPDATE IQ EXT_PWR_DWN 3 POWER DOWN CONTROL RAM OSK SERIAL I/O PORT CCI_OVFL PROGRAMMING REGISTERS PROFILE FTW PW AD9957 Data Sheet The Blackfin interface includes an additional pair of half-band filters in both I and Q signal paths (not shown explicitly in the diagram). The two half-band filters increase the interpolation of the baseband data by a factor of four, relative to the normal QDUC mode. BLACKFIN INTERFACE (BFI) MODE The synchronization of the serial data occurs through the PDCLK signal. In BFI mode, the PDCLK signal is effectively the bit clock for the serial data. Note that the system clock is limited to 750 MHz in BFI mode. AD9957 PW CCI (1x TO 63x) IS cos (t+) Q FTW CCI (1x TO 63x) 18 HALF-BAND FILTERS (4x) QS 16 8 DAC GAIN DDS sin (t+) CLOCK AUX DAC 8-BIT DAC_RSET DAC 14-BIT INVERSE SINC FILTER HALF-BAND FILTERS (4x) INVERSE CCI 16 INVERSE CCI 2 I 18 BLACKFIN INTERFACE I/Q IN DATA ASSEMBLER AND FORMATTER A subset of the QDUC mode is the Blackfin interface (BFI) mode, shown in Figure 27; grayed items are inactive. In this mode, a separate I and Q serial bit stream is applied to the baseband data port instead of parallel data-words. The two serial inputs provide for 16-bit I- and Q-words (unlike the 18-bit words in normal QDUC mode). The serial bit streams are delivered to the Blackfin interface. The Blackfin interface converts the 16-bit serial data into 16-bit parallel data to propagate down the signal processing chain. IOUT IOUT OUTPUT SCALE FACTOR REFCLK_OUT SYSCLK CLOCK MODE OSK /2 PDCLK PARALLEL DATA TIMING AND CONTROL TxENABLE INTERNAL CLOCK TIMING AND CONTROL PLL REF_CLK REF_CLK XTAL_SEL 2 2 SYNC_OUT SYNC_IN Figure 27. Quadrature Modulation Mode, Blackfin Interface Rev. C | Page 18 of 64 06384-007 MASTER_RESET PLL_LOCK PLL_LOOP_FILTER IS QS RT SDIO SDO SCLK I/O_RESET CS I/O_UPDATE IQ EXT_PWR_DWN 3 POWER DOWN CONTROL RAM OSK SERIAL I/O PORT CCI_OVFL PROGRAMMING REGISTERS PROFILE FTW PW Data Sheet AD9957 INTERPOLATING DAC MODE No modulation takes place in the interpolating DAC mode; therefore, the spectrum of the data supplied at the parallel port remains at baseband. However, a sample rate conversion takes place based on the programmed interpolation rate. The interpolation hardware processes the signal, effectively performing an oversample with a zero-stuffing operation. The original input spectrum remains intact and the images that otherwise would occur from the sample rate conversion process are suppressed by the interpolation signal chain. A block diagram of the AD9957 operating in interpolating DAC mode is shown in Figure 28; grayed items are inactive. In this mode, the Q data path, DDS, and modulator are all disabled; only the I data path is active. AD9957 PW CCI (1x TO 63x) IS cos (t+) Q FTW CCI (1x TO 63x) 18 HALF-BAND FILTERS (4x) QS 16 8 DAC GAIN DDS sin (t+) CLOCK AUX DAC 8-BIT DAC_RSET DAC 14-BIT INVERSE SINC FILTER HALF-BAND FILTERS (4x) INVERSE CCI 16 INVERSE CCI 18 I 18 BLACKFIN INTERFACE I/Q IN DATA ASSEMBLER AND FORMATTER As in quadrature modulation mode, the PDCLK pin functions as a clock, synchronizing the input of data to the AD9957. OUTPUT SCALE FACTOR IOUT IOUT REFCLK_OUT SYSCLK CLOCK MODE OSK /2 PDCLK PARALLEL DATA TIMING AND CONTROL TxENABLE INTERNAL CLOCK TIMING AND CONTROL PLL REF_CLK REF_CLK XTAL_SEL 2 2 SYNC_OUT SYNC_IN Figure 28. Interpolating DAC Mode Rev. C | Page 19 of 64 06384-008 MASTER_RESET PLL_LOCK PLL_LOOP_FILTER IS QS RT SDIO SDO SCLK I/O_RESET CS I/O_UPDATE I Q EXT_PWR_DWN 3 POWER DOWN CONTROL RAM OSK SERIAL I/O PORT CCI_OVFL PROGRAMMING REGISTERS PROFILE FTW PW AD9957 Data Sheet SINGLE TONE MODE cosine or sine output of the DDS. The sinusoid at the DDS output can be scaled using a 14-bit amplitude scale factor (ASF) and optionally routed through the inverse sinc filter. Single tone mode offers the output shift keying (OSK) function. It provides the ability to ramp the amplitude scale factor between zero and an arbitrary preset value over a programmable time interval. AD9957 PW CCI (1x TO 63x) IS cos (t+) Q FTW CCI (1x TO 63x) 18 HALF-BAND FILTERS (4x) QS 16 8 DAC GAIN DDS sin (t+) CLOCK AUX DAC 8-BIT DAC_RSET DAC 14-BIT INVERSE SINC FILTER HALF-BAND FILTERS (4x) INVERSE CCI 16 INVERSE CCI 10 I 18 BLACKFIN INTERFACE I/Q IN DATA ASSEMBLER AND FORMATTER A block diagram of the AD9957 operating in single tone mode is shown in Figure 29; grayed items are inactive. In this mode, both I and Q data paths are disabled from the 18-bit parallel data port up to, and including, the modulator. The internal DDS core produces a single frequency signal based on the programmed tuning word. The user may select either the IOUT IOUT OUTPUT SCALE FACTOR REFCLK_OUT SYSCLK CLOCK MODE OSK /2 PDCLK PARALLEL DATA TIMING AND CONTROL TxENABLE INTERNAL CLOCK TIMING AND CONTROL PLL REF_CLK REF_CLK XTAL_SEL 2 2 SYNC_OUT SYNC_IN Figure 29. Single Tone Mode Rev. C | Page 20 of 64 06384-009 MASTER_RESET PLL_LOCK PLL_LOOP_FILTER IS QS RT SDIO SDO SCLK I/O_RESET CS I/O_UPDATE I Q EXT_PWR_DWN 3 POWER DOWN CONTROL RAM OSK SERIAL I/O PORT CCI_OVFL PROGRAMMING REGISTERS PROFILE FTW PW Data Sheet AD9957 SIGNAL PROCESSING For a better understanding of the operation of the AD9957, it is helpful to follow the signal path in quadrature modulation mode from the parallel data port to the output of the DAC, examining the function of each block (see Figure 26). The internal system clock (SYSCLK) signal that generates from the timing source provided to the REF_CLK pins provides all timing within the AD9957. PARALLEL DATA CLOCK (PDCLK) The AD9957 generates a signal on the PDCLK pin, which is a clock signal that runs at the sample rate of the parallel data port. PDCLK serves as a data clock for the parallel port in QDUC and interpolating DAC modes; in BFI mode, it is a bit clock. Normally, the device uses the rising edges on PDCLK to latch the user-supplied data into the data port. Alternatively, the PDCLK Invert bit selects the falling edges as the active edges. Furthermore, the PDCLK enable bit is used to switch off the PDCLK signal. Even when the output signal is turned off via the PDCLK enable bit, PDCLK continues to operate internally. The device uses PDCLK internally to capture parallel data. Note that PDCLK is Logic 0 when disabled. In QDUC mode, the AD9957 expects alternating I- and Qdata-words at the parallel port (see Figure 31). Each active edge of PDCLK captures one 18-bit word; therefore, there are two PDCLK cycles per I/Q pair. In BFI mode, the AD9957 expects two serial bit streams, each segmented into 16-bit words with PDCLK indicating each new bit. In either case, the output clock rate is fPDCLK as explained in the Input Data Assembler section. In QDUC applications that require a consistent timing relationship between the internal SYSCLK signal and the PDCLK signal, the PDCLK rate control bit is used to slightly alter the operation of PDCLK. When this bit is set, the PDCLK rate is reduced by a factor of two. This causes rising edges on PDCLK to latch incoming I-words and falling edges to latch incoming Q-words. Again, the edge polarity assignment is reversible via the PDCLK Invert bit. TRANSMIT ENABLE PIN (TxENABLE) The AD9957 accepts a user-generated signal applied to the TxENABLE pin that gates the user supplied data. Polarity of the TxENABLE pin is set using the TxENABLE invert bit (see the Register Map section for details). When TxENABLE is true, the device latches data into the device on the expected edge of PDCLK (based on the PDCLK invert bit). When TxENABLE is false, the device ignores the data supplied to the port, even though the PDCLK may continue to operate. Furthermore, when the TxENABLE pin is held false, then the device either forces the 18-bit data-words to Logic 0s, or it retains the last value present on the data port prior to TxENABLE switching to the false state (see the data assembler hold last value bit in the Register Map section). Alternatively, rather than operating the TxENABLE pin as a gate for framing bursts of data, it can be driven with a clock signal operating at the parallel port data rate. When driven by a clock signal, the transition from the false to true state must meet the required setup and hold times on each cycle to ensure proper operation. In QDUC mode, on the false-to-true edge of TxENABLE, the device is ready to receive the first I-word. The first I-word is latched into the device coincident with the active edge of PDCLK. The next active edge of PDCLK latches in a Q-word, and so on, until TxENABLE is returned to a static false state. The user may reverse the ordering of the I- and Q-words via the Q-First Data Pairing bit. Furthermore, the user must ensure that an even number of data words are delivered to the device as it must capture both an I- and a Q-word before the data is processed along the signal chain. In interpolating DAC mode, TxENABLE operation is similar to QDUC mode, but without the need for I/Q data pairing; the even-number-of-PDCLK-cycles rule does not apply. In BFI mode, operation of the TxENABLE pin is similar except that instead of the false-to-true edge marking the first I-word, it marks the first I and Q bits in a serial frame. The user must ensure that all 16-bits of a serial frame are delivered because the device must capture a full 16-bit I- and Q-word before the data is processed along the signal chain. The timing relationships between TxENABLE, PDCLK, and DATA are shown in Figure 30, Figure 31, and Figure 32. Rev. C | Page 21 of 64 AD9957 Data Sheet TxENABLE tDS PDCLK tDH tDS I1 I2 I3 IK - 1 IK 06384-010 I0 D<17:0> tDH Figure 30. 18-Bit Parallel Port Timing Diagram--Interpolating DAC Mode TxENABLE tDS PDCLK tDH tDS Q0 I1 Q1 IN QN 06384-011 I0 D<17:0> tDH Figure 31. 18-Bit Parallel Port Timing Diagram--Quadrature Modulation Mode TxENABLE PDCLK I DATA I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 Q DATA Q0 Q1 Q2 Q3 Q4 Q5 Q7 Q6 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16n - 1 06384-012 I16n - 1 Figure 32. Dual Serial I/Q Bit Stream Timing Diagram, BFI Mode INPUT DATA ASSEMBLER When the PDCLK rate control bit is active in QDUC mode, however, the frequency of PDCLK becomes The input to the AD9957 is an 18-bit parallel data port in QDUC mode or interpolating DAC mode. In BFI mode, it operates as a dual serial data port. f PDCLK = In QDUC mode, it is assumed that two consecutive 18-bit words represent the real (I) and imaginary (Q) parts of a complex number of the form, I + jQ. The 18-bit words are supplied to the input of the AD9957 at a rate of f PDCLK = f SYSCLK 2R f SYSCLK 4R with PDCLK rate control active In the interpolating DAC mode, the rate of PDCLK is the same as QDUC mode with the PDCLK rate control bit active, that is, f PDCLK = for QDUC mode where: fSYSCLK (for all of the PDCLK equations in this section) is the sample rate of the DAC. R (for all of the PDCLK equations in this section) is the interpolation factor of the programmable interpolation filter. f SYSCLK for interpolating DAC mode 4R In BFI mode, the 18-bit parallel input converts to a dual serial input that is, one pin is assigned as the serial input for the I-words and one pin is assigned as the serial input for the Q-words. The other 16 pins are not used. Furthermore, each I- and Q-word has a 16-bit resolution. fPDCLK is the bit rate of the I- and Q-data streams and is given by Rev. C | Page 22 of 64 f PDCLK = f SYSCLK R for BFI mode Data Sheet AD9957 INVERSE CCI FILTER The inverse cascaded comb integrator (CCI) filter predistorts the data, compensating for the slight attenuation gradient imposed by the CCI filter (see the Programmable Interpolating Filter section). Data entering the first half-band filter occupies a maximum bandwidth of 1/2 fIQ as defined by Nyquist (where fIQ is the sample rate at the input of the first half-band filter); see Figure 33. If the CCI filter is used, the inband attenuation gradient can pose a problem for applications requiring an extremely flat pass band. For example, if the spectrum of the data supplied to the AD9957 occupies a significant portion of the 1/2 fDATA region, the higher frequencies of the data spectrum are slightly more attenuated than the lower frequencies (the worst-case overall droop from f = 0 to 1/2 fDATA is <0.8 dB). The inverse CCI filter has a response characteristic that is the inverse of the CCI filter response over the 1/2 fIQ region. FIXED INTERPOLATOR (4x) This block is a fixed 4x rate interpolator, implemented as a cascade of two half-band filters. Together, the sampling rate of these two filters increases by a factor of four while preserving the spectrum of the baseband signal applied at the input. Both are linear phase filters; virtually no phase distortion is introduced within their pass bands. Their combined insertion loss is 0.01 dB, preserving the relative amplitude of the input signal. The filters are designed to deliver a composite performance that yields a usable pass band of 40% of the input sample rate. Within that pass band, ripple does not exceed 0.002 dB peak-to-peak. The stop band extends from 60% to 340% of the input sample rate and offers a minimum of 85 dB attenuation. Figure 34 and Figure 35 show the composite response of the two half-band filters. 10 0 -10 -20 -30 -40 (dB) Encoding and pulse shaping of symbols must be implemented before the data is presented to the input of the AD9957. Data delivered to the input of the AD9957 may be formatted as either twos complement or offset binary (see the Data Format bit in Table 13). In BFI mode, the bit sequence order can be set to either MSB-first or LSB-first (via the Blackfin Bit Order bit). -50 -60 -70 -80 -90 INBAND ATTENUATION GRADIENT 06384-014 -100 -110 -120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fI CCI FILTER RESPONSE Figure 34. Half-Band 1 and Half-Band 2 Composite Response (Frequency Scaled to Input Sample Rate of Half-Band 1) 0.010 0.008 0.006 0.004 0.002 (dB) Figure 33. CCI Filter Response The product of the two responses yields an extremely flat pass band (0.05 dB over the baseband Nyquist bandwidth) eliminating the inband attenuation gradient introduced by the CCI filter. The cost is a slight attenuation of the input signal (approximately 0.5 dB for a CCI interpolation rate of 2, and 0.8 dB for higher interpolation rates). The inverse CCI filter can be bypassed using the appropriate bit in the register map; it is automatically bypassed if the CCI interpolation rate is 1x. When bypassed, power to the stage turns off to reduce power consumption. 0 -0.002 -0.004 -0.006 06384-015 4fIQ fIQ 1/2fIQ 06384-013 f -0.008 -0.010 0 0.1 0.2 0.3 0.4 0.5 fI Figure 35. Composite Pass-Band Detail (Frequency Scaled to Input Sample Rate of Half-Band 1) In BFI mode, there are two additional half-band filters resident, yielding a total fixed interpolation factor of 16x. The extra BFI filters use the same filter tap coefficient values as the QDUC half-band filters, but their data pathway is 16 bits (instead of 18 bits as with the QDUC half-band filters). As such, baseband quantization noise is higher in BFI mode. Rev. C | Page 23 of 64 AD9957 Data Sheet Knowledge of the frequency response of the half-band filters is essential to understanding their impact on the spectral properties of the input signal. This is especially true when using the quadrature modulator to upconvert a baseband signal containing complex data symbols that have been pulse shaped. Consider that a complex symbol is represented by a real (I) and an imaginary (Q) component, thus requiring two digital words to represent a single complex sample of the form I + jQ. The sample rate associated with a sequence of complex symbols is referred to as fSYMBOL. If pulse shaping is applied to the symbols, the sample rate must be increased by some integer factor, M (a consequence of the pulse shaping process). This new sample rate (fIQ) is related to the symbol rate by fIQ = MfSYMBOL where fIQ is the rate at which complex samples must be supplied to the input of the first half-band filter in both (I and Q) signal paths. This rate should not be confused with the rate at which data is supplied to the AD9957. Typically, pulse shaping is applied to the baseband symbols via a filter having a raised cosine response. In such cases, an excess bandwidth factor (, 0 1) is used to modify the bandwidth of the data. For = 0, the data bandwidth corresponds to fSYMBOL/2; for = 1, the data bandwidth extends to fSYMBOL. Figure 36 shows the relationship between , the bandwidth of the raised cosine response, and the response of the first half-band filter. response portion of the diagram to the right, as it must remain aligned with the corresponding MfSYMBOL point on the frequency axis of the raised cosine spectral diagram. However, if fIQ shifts to the right, so does the half-band response, proportionally. The result is that the raised cosine spectral mask always lies within the flat portion (dc to 0.4 fIQ) of the pass band response of the first half-band filter, regardless of the choice of so long as M > 2. Therefore, for M > 2, the first half-band filter has absolutely no negative impact on the spectrum of the baseband signal when raised cosine pulse shaping is employed. For the case of M = 2, a problem can arise. This is highlighted by the shaded area in the tail of the = 1 trace on the raised cosine spectral mask diagram. Notice that this portion of the raised cosine spectral mask extends beyond the flat portion of the half-band response and causes unwanted amplitude and phase distortion as the signal passes through the first half-band filter. To avoid this, simply ensure that 0.6 when M = 2. PROGRAMMABLE INTERPOLATING FILTER The programmable interpolator is implemented as a low-pass CCI filter. It is programmable by a 6-bit control word, giving a range of 2x to 63x interpolation. The programmable interpolator is bypassed when programmed for an interpolation factor of 1. When bypassed, power to the stage is removed and the inverse CCI filter is also bypassed, because its compensation is not needed. The output of the programmable interpolator is the data from the 4x interpolator further upsampled by the CCI filter, according to the rate chosen by the user. This results in the upsampling of the input data by a factor of 8x to 252x in steps of four. TYPICAL SPECTRUM OF A RANDOM SYMBOL SEQUENCE NYQUIST BAND WIDTH The transfer function of the CCI interpolating filter is 1/2fSYMBOL fSYMBOL f 2fSYMBOL 3fSYMBOL R -1 H ( f ) = e - j (2 fk ) k= 0 RAISED COSINE SPECTRAL MASK =1 =0 = 0.5 1/2fSYMBOL fSYMBOL (1) where R is the programmed interpolation factor, and f is the frequency normalized to fSYSCLK. SAMPLE RATE FOR 2x OVERSAMPLED PULSE SHAPING Note that minimum R requirements exist depending on the mode and frequency of fSYSCLK. The minimum R setting is defined under the follo wing conditions. f 2fSYMBOL 5 4fSYMBOL QDUC Mode HALF-BAND FILTER RESPONSE If fSYSCLK is between 500 MSPS to 1 GSPS, then the minimum R is 2. INPUT SAMPLE RATE OF FIRST HALF-BAND FILTER fIQ If fSYSCLK is less than 500 MSPS, then the minimum R is 1. 2fIQ f 06384-016 0.4fIQ 1/2fIQ INPUT SAMPLE RATE OF FIRST HALF-BAND FILTER Figure 36. Effect of the Excess Bandwidth Factor () The responses in Figure 36 reflect the specific case of M = 2 (the interpolation factor for the pulse shaping operation). Increasing Factor M shifts the location of the fIQ point on the half-band BFI Mode If fSYSCLK is between 500 MSPS to 750 MSPS, then the minimum R is 3. If fSYSCLK is between 250 MSPS to 500 MSPS, then the minimum R is 2. If fSYSCLK is less than 250 MSPS, then the minimum R is 1. Rev. C | Page 24 of 64 Data Sheet AD9957 QUADRATURE MODULATOR The digital quadrature modulator stage shifts the frequency of the baseband spectrum of the incoming data stream up to the desired carrier frequency (a process known as upconversion). At this point, the baseband data, which was delivered to the device at an I/Q sample rate of fIQ, has been upsampled to a rate equal to the frequency of SYSCLK, making the data sampling rate equal to the sampling rate of the carrier signal. The frequency of the carrier signal is controlled by a direct digital synthesizer (DDS). The DDS very precisely generates the desired carrier frequency from the internal reference clock (SYSCLK). The carrier is applied to the I and Q multipliers in quadrature fashion (90 phase offset) and summed, yielding a data stream that represents the quadrature modulated carrier. The modulation is performed digitally, avoiding the phase offset, gain imbalance, and crosstalk issues commonly associated with analog modulators. Note that the modulated, so-called signal is a number stream sampled at the rate of SYSCLK, the same rate at which the DAC is clocked. The orientation of the modulated signal with respect to the carrier is controlled by a spectral invert bit. This bit resides in each of the eight profile registers. By default, the time domain output of the quadrature modulator takes the form I(t) x cos(t) - Q(t) x sin(t) (2) When the spectral invert bit is asserted, it becomes I(t) x cos(t) + Q(t) x sin(t) (3) DDS CORE The direct digital synthesizer (DDS) block generates sine and/or cosine signals. In single tone mode, the DDS generates either a digital sine or cosine waveform based on the select DDS sine output bit. In QDUC mode, the DDS generates the quadrature carrier reference signal that digitally modulates the I/Q baseband signal. The DDS output frequency is tuned using registers accessed via the serial I/O port. This allows for both precise tuning and instantaneous changing of the carrier frequency. The equation relating output frequency (fOUT) of the DDS to the frequency tuning word (FTW) and the system clock (fSYSCLK) is FTW f OUT = 32 f SYSCLK 2 (4) where FTW is a decimal number from 0 to 2,147,483,647 (231 - 1). Solving for FTW yields f FTW = round 2 32 OUT f SYSCLK where the round() function means to round the result to the nearest integer. For example, for fOUT = 41 MHz and fSYSCLK = 122.88 MHz, then FTW = 1,433,053,867 (0x556AAAAB). In single tone mode, the DDS frequency, phase, and amplitude are all programmable via the serial I/O port. The amplitude is controlled by means of a digital multiplier using a 14-bit fractional scale value called the amplitude scale factor (ASF). The LSB weight is 2-14, yielding a multiplier range of 0 to 0.99993896484375 (1 - 2-14). To bypass the ASF multiplier, program the appropriate control register bit (see the details of CFR2<24> in the Register Bit Descriptions section). When bypassed, the ASF multiplier clocks are disabled to conserve power. The phase offset is controlled by means of a digital adder that uses a 14-bit offset value called the phase offset word (POW). The adder is situated between the phase accumulator and the angle-to-amplitude conversion logic in the DDS core. The adder applies the POW to the instantaneous phase values produced by the DDS phase accumulator. The adder is MSB aligned with the phase accumulator yielding an LSB weight of 2-14 (which equates to a resolution of ~0.022 or ~0.000383 radians). Both the ASF and the POW are available for each of the eight profiles. INVERSE SINC FILTER The sampled carrier data stream is the input to the digital-toanalog converter. The DAC output spectrum is shaped by the characteristic sin(x)/x (or sinc) envelope, due to the intrinsic zero-order hold effect associated with DAC-generated signals. The shape of the sinc envelope is well known and can be compensated for. This compensation is provided by the inverse sinc filter preceding the DAC. The inverse sinc filter is implemented as a digital FIR filter. Its response characteristic very nearly matches the inverse of the sinc envelope, as shown in Figure 37 (along with the sinc envelope for comparison). The inverse sinc filter is enabled through a bit in the register map. The filter tap coefficients are listed in Table 4. The filter predistorts the data prior to its arrival at the DAC to compensate for the sinc envelope that otherwise distorts the spectrum. When the inverse sinc filter is enabled, it introduces a ~3.0 dB insertion loss. The inverse sinc compensation is effective for output frequencies up to 40% (nominally) of the DAC sample rate. Table 4. Inverse Sinc Filter Tap Coefficients Tap No. 1 2 3 4 (5) Rev. C | Page 25 of 64 Tap Value -35 +134 -562 +6729 Tap No. 7 6 5 4 AD9957 Data Sheet In Figure 37, it can be seen that the sinc envelope introduces a frequency dependent attenuation that can be as much as 4 dB at the Nyquist frequency (half of the DAC sample rate). Without the inverse sinc filter, the DAC output also suffers from the frequency dependent droop of the sinc envelope. The inverse sinc filter effectively flattens the droop to within 0.05 dB as shown in Figure 38, which shows the corrected sinc response with the inverse sinc filter enabled. 1 SINC The AD9957 incorporates an integrated 14-bit current-output DAC. The output current is delivered as a balanced signal using two outputs. The use of balanced outputs reduces the amount of common-mode noise at the DAC output, increasing signal-tonoise ratio. An external resistor (RSET) connected between the DAC_RSET pin and AGND establishes a reference current. The full-scale output current of the DAC (IOUT) is a scaled version of the reference current (see the Auxiliary DAC section that follows). Proper attention should be paid to the load termination to keep the output voltage within the specified compliance range, as voltages developed beyond this range cause excessive distortion and can damage the DAC output circuitry. 0 (dB) -1 Auxiliary DAC -2 INVERSE SINC 06384-017 -3 -4 14-BIT DAC 0 0.1 0.2 0.3 0.4 The full-scale output current of the main DAC (IOUT) is controlled by an 8-bit auxiliary DAC. An 8-bit code word stored in the appropriate register map location sets IOUT according to the following equation: 0.5 IOUT = FREQUENCY RELATIVE TO DAC SAMPLE RATE Figure 37. Sinc and Inverse Sinc Responses 86.4 CODE 1 + 96 RSET (6) where: RSET is the value of the RSET resistor (in ohms). CODE is the 8-bit value supplied to the auxiliary DAC (default is 127). -2.8 -2.9 For example, with RSET = 10,000 and CODE = 127, IOUT = 20.07 mA. (dB) COMPENSATED RESPONSE -3.1 06384-018 -3.0 0 0.1 0.2 0.3 0.4 0.5 FREQUENCY RELATIVE TO DAC SAMPLE RATE Figure 38. DAC Response with Inverse Sinc Compensation OUTPUT SCALE FACTOR (OSF) In QDUC and interpolating DAC modes, the output amplitude is controlled using an 8-bit digital multiplier. The 8-bit multiplier value is called the output scale factor (OSF) and is programmed via the appropriate control registers. It is available for each of the eight profiles. The LSB weight is 2-7, which yields a multiplier range of 0 to 1.9921875 (2 - 2-7). The gain extends to nearly a factor of 2 to provide a means to overcome the intrinsic loss through the modulator when operating in the quadrature modulation mode. In interpolating DAC mode, the OSF should not be programmed to exceed unity, as clipping can result. Programming the 8-bit multiplier to unity gain (0x80) bypasses the stage and reduces power consumption. Rev. C | Page 26 of 64 Data Sheet AD9957 RAM CONTROL RAM OVERVIEW The AD9957 has an integrated 1024 x 32-bit RAM. This RAM is only accessible when the AD9957 is operating in QDUC or interpolating DAC mode. The RAM has two fundamental modes of operation: data entry/retrieve mode and playback mode. The mode is selected by programming the RAM Enable bit in CFR1 via the serial I/O port. Data entry/retrieve mode is used to load or read back the RAM contents via the serial I/O port. Playback mode is used to deliver RAM data to one of two internal destinations: the baseband scaling multipliers (see Figure 25, the IS and QS labels) or the baseband signal chain (see Figure 25, the I and Q labels). In both cases, the RAM can be used to apply an arbitrary, timevarying waveform to the selected destination. A block diagram of the RAM and its control elements is shown in Figure 39. The external parallel data port is disabled when the baseband signal chain serves as the RAM playback destination. 3 16 10 10 RAM SEGMENT REGISTERS UP/DOWN COUNTER I I CHANNEL IS 32 16 32 SERIAL I/O PORT RAM DATA U/D 10 Q ADDRESS CLK SDIO SDO SCLK I/O_RESET CS (MSBs) Q QS 16 (LSBs) 06384-019 Q CHANNEL Two dedicated registers (RAM Segment Register 0 and RAM Segment Register 1) control the operation of the RAM. Each contains the following: 10-bit start address word 10-bit end address word 16-bit address step rate word 3-bit RAM playback mode word When programming these registers, the user must ensure that the end address is greater than the start address. DDS CLOCK BASEBAND DATA CLOCK STATE MACHINE RAM SEGMENT REGISTERS * * * * RT RAM MODE ADDRESS STEP RATE START ADDRESS END ADDRESS Q-channel bits. In playback mode, when driving data directly into the baseband signal chain, the 16-bit data-words are considered to be signed (that is, twos complement) values. The 16-bit I-and Q-words are MSB aligned with the 18-bit I and Q baseband data path. The two remaining LSBs of each 18-bit baseband channel are driven by the MSB of the respective channel. This ensures correct polarity coding when the 16-bit I and Q data from the RAM translates into 18-bit words for the baseband signal chain. Alternatively, when the RAM is driving the baseband scaling multipliers in playback mode, the RAM data is considered to represent unsigned, fractional values with a range of 0 to 1 - 2-16. Figure 39. RAM Block Diagram With the RAM segment registers, the user can arbitrarily partition the RAM into two independent memory segments. The segment boundaries are specified with the start and end address words in each RAM segment register. The playback rate is controlled by the address step rate word (only meaningful when the baseband scaling multipliers serve as the playback destination). If the baseband signal chain serves as the RAM playback destination, the 16-bit address step rate words must be set to 1. The playback mode of the RAM is controlled via the RAM playback mode word. RAM STATE MACHINE In Figure 39, the serial I/O port is used to program the contents of the two RAM segment registers as well as to load and retrieve the RAM contents. The state machine takes care of incrementing or decrementing the RAM address locations and controlling the timing of the RAM address and data for proper operation. The I-channel and Q-channel multiplexers route RAM data to baseband scaling multipliers (IS/QS) or directly to the baseband signal chain (I/Q) when the RAM is used in playback mode. The state of the RAM playback destination bit determines the destination of the RAM data during playback. An I/O update (or a profile change) is necessary to enact a state change of the RAM enable or RAM playback destination bits, or any of the RAM segment register bits. The 32-bit RAM data bus is partitioned so that the 16 MSBs are designated as I-channel bits and the 16 LSBs are designated as The state machine acts as an address generator for the RAM. It is clocked by either the serial I/O port (when the RAM is operating in the load/retrieve mode) or the baseband data clock (when the RAM is in playback mode). The state machine uses the RAM mode bits of the active RAM segment register to establish the proper sequence through the specified address range. RAM TRIGGER (RT) PIN The RAM state machine monitors the RT pin for logic state transitions. Any state transition triggers the state machine into action. The direction of the logic state transition on the RT pin determines which RAM segment register the state machine uses for playback instructions. RAM Segment Register 0 is used if the state machine detects a 0-to-1 transition; RAM Segment Register 1 is used if a 1-to-0 transition is detected. Rev. C | Page 27 of 64 AD9957 Data Sheet LOAD/RETRIEVE RAM OPERATION Loading or retrieving the RAM contents is a three-step process. rate when the playback destination is the baseband scaling multipliers. Although RAM load/retrieve operations via the serial I/O port take precedence over playback, it is recommended that the user not attempt RAM access via the serial I/O port when the RAM enable bit is set. 1. Program the RAM segment registers with start and end addresses defining the boundaries of each independent RAM segment. 2. Toggle the RT pin with the appropriate transition to select the desired RAM segment register. 3. Using the serial I/O port, write (or read) the address range specified by the selected RAM segment register. Figure 41 is a block diagram showing the functional components used for RAM playback operation when the internal destination is the baseband scaling multipliers. 3 Figure 40 shows the RAM block diagram when used for loading or retrieve operations. CLK STATE MACHINE RAM UP/DOWN COUNTER I I CHANNEL IS 32 16 32 SERIAL I/O PORT STATE MACHINE U/D 10 Q DATA CLK ADDRESS DDS CLOCK BASEBAND DATA CLOCK SDIO SDO SCLK I/O_RESET CS (LSBs) NOTES 1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY. UP/DOWN COUNTER I I CHANNEL IS 32 16 32 SDIO SDO SCLK I/O_RESET CS (MSBs) Q CHANNEL Q 16 QS (LSBs) Figure 41. RAM Playback to Baseband Scaling Multipliers 16 06384-020 Q QS RAM NOTES 1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY. (MSBs) Q CHANNEL U/D 10 Q 06384-021 10 RAM SEGMENT REGISTERS SERIAL I/O PORT 10 RAM SEGMENT REGISTERS DDS CLOCK BASEBAND DATA CLOCK RT RAM MODE ADDRESS STEP RATE START ADDRESS END ADDRESS DATA 16 10 10 RT RAM MODE ADDRESS STEP RATE START ADDRESS END ADDRESS ADDRESS 3 16 Figure 40. RAM Load/Retrieve Operation During a load or retrieve operation, the state machine controls an up/down counter to step through the required RAM locations. The counter is synchronized with the serial I/O port so that the serial/parallel conversion of the 32-bit words is correctly timed with the generation of the appropriate RAM address to properly execute the desired read or write operation. The up/down counter always increments through the address range during serial I/O port operations. Because the RAM segment registers are completely independent, it is possible to define overlapping address ranges. However, doing so causes the overlapping address locations to be overwritten by the most recent write operation. It is recommended that the user avoid defining overlapping address ranges. RAM PLAYBACK OPERATION When the RAM has been loaded, it can be used for playback operation. The destination of the playback data is selected via the RAM playback destination bit. The active RAM segment register is selected by the appropriate transition of the RT pin. The active RAM segment register directs the internal state machine by defining the RAM address range occupied by the data and the RAM playback mode. It also defines the playback During playback to the baseband scaling multipliers, the address step rate word in the active RAM segment register sets the rate at which RAM data samples are delivered to the multipliers. The following equations define the RAM sample rate and sample interval (t): RAM Sample Rate = t = f SYSCLK 4 RM 4 RM f SYSCLK where: R is the rate interpolation factor for the CCI filter. M is the 16-bit value of the address step rate word stored in the active RAM segment register. If the RAM enable bit is set and the baseband scaling multipliers are selected as the playback destination, then assertion of an I/O update or profile change causes the multipliers to be driven with a static value of zero. A subsequent state change on the RT pin causes the multipliers to be driven by the data played back from the RAM instead of the static zero value. Figure 42 is a block diagram showing RAM playback operation when the internal destination is the baseband data path. During playback to the baseband data path, the state machine increments/ decrements the RAM address at the baseband data rate (the address step rate must be set to 1). Rev. C | Page 28 of 64 Data Sheet 3 16 10 10 AD9957 RAM MODE ADDRESS STEP RATE START ADDRESS END ADDRESS RT RAM Ramp-Up Mode SDIO SDO SCLK I/O_RESET CS In ramp-up mode, upon assertion of an I/O update or a state change on the RT pin, the RAM begins playback operation using the parameters programmed into the selected RAM segment register. Data is extracted from RAM over the specified address range contained in the start address and end address of the active RAM segment register. The data is delivered at the appropriate rate and to the destination as specified by the RAM playback destination bit. RAM SEGMENT REGISTERS RAM UP/DOWN COUNTER I I CHANNEL IS 32 16 32 SERIAL I/O PORT U/D 10 Q DATA CLK STATE MACHINE ADDRESS DDS CLOCK BASEBAND DATA CLOCK (MSBs) Q 16 QS (LSBs) NOTES 1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY. 06384-022 Q CHANNEL Figure 42. RAM Playback to Baseband Data Path OVERVIEW OF RAM PLAYBACK MODES The RAM is operational in any one of four different playback modes. * * * * The playback rate is governed by the timer internal to the RAM state machine and its period (t) is determined by the state of the RAM playback destination bit as detailed in the RAM playback operation section. The internal state machine begins extracting data from the RAM at the start address and continues to extract data until it reaches the end address. Upon reaching this address, the state machine halts. A graphic representation of the ramp-up mode appears in Figure 43. The upper trace shows the progression of the RAM address from the start address to the end address for the active RAM segment register. The address value advances by one with each timeout of the timer internal to the state machine. The circled numbers indicate specific events, explained as follows: Ramp-up Bidirectional ramp Continuous bidirectional ramp Continuous recirculate RAM playback is only functional when the AD9957 is programmed for either the QDUC or interpolating DAC mode. The RAM playback mode is selected via the 3-bit RAM playback mode word located in each of the RAM segment registers. Thus, the RAM playback mode is segment dependent. The RAM playback mode bits are detailed in Table 5. Event 1--an I/O update or state transition on the RT pin. This event initializes the state machine to the start address of the active RAM segment register. Event 2--the state machine reaches the end address of the active RAM segment register and halts. Table 5. RAM Playback Modes RAM Playback Mode Bits<2:0> 001 010 011 100 000, 101, 110, 111 1 PDCLK CYCLE OR M DDS CLOCK CYCLES RAM Playback Mode Ramp-up Bidirectional ramp Continuous bidirectional ramp Continuous recirculate Not Valid t END ADDRESS RAM ADDRESS 1 I/O_UPDATE OR RT TRANSITION 1 Figure 43. Ramp-Up Timing Diagram Rev. C | Page 29 of 64 2 06384-023 START ADDRESS The continuous bidirectional ramp and continuous recirculate modes are not available when the baseband scaling multipliers serve as the destination of RAM playback. AD9957 Data Sheet A Logic 1 to Logic 0 transition on the RT pin instructs the state machine to switch to RAM Segment Register 1 and to decrement through the address range starting with the end address. As long as the RT pin remains Logic 0, the state machine continues to play back the RAM data until it reaches the start address, at which point the state machine halts. RAM Bidirectional Ramp Mode This mode is unique in that the RAM segment playback mode word of both RAM segment registers must be programmed for RAM bidirectional ramp mode. In bidirectional ramp mode, upon assertion of an I/O update, the RAM readies for playback operation using the parameters programmed into RAM Segment Register 0. The data is delivered at the appropriate rate and to the destination as specified by the RAM playback destination bit. It is important to note that RAM Segment Register 1 is played back in reverse order for bidirectional ramp mode. This must be kept in mind when the RAM contents are loaded via the serial I/O port when bidirectional ramp mode is the intended playback mode. The playback rate is governed by the timer that is internal to the RAM state machine, and its period (t) is determined by the state of the RAM playback destination bit as detailed in the RAM Playback Operation section. A graphic representation of the bidirectional ramp mode appears in Figure 44. It demonstrates the action of the state machine in response to the RT pin. If the RT pin changes states before the state machine reaches the programmed start or end address, the internal timer is restarted and the direction of the address counter reversed. Playback begins upon a 0 to 1 logic transition on the RT pin. This instructs the state machine to increment through the address range specified in RAM Segment Register 0 starting with the start address. As long as the RT pin remains Logic 1, the state machine continues to play back the RAM data until it reaches the end address, at which point the state machine halts. 1 0 RAM SEGMENT 0 1 0 1 PDCLK CYCLE OR M DDS CLOCK CYCLES END ADDRESS NUMBER 0 RAM ADDRESS t t t 1 START ADDRESS NUMBER 0 END ADDRESS NUMBER 1 RAM ADDRESS t t START ADDRESS NUMBER 1 RT PIN 1 2 3 4 5 6 Figure 44. Bidirectional Ramp Timing Diagram Rev. C | Page 30 of 64 7 8 06384-024 I/O_UPDATE Data Sheet AD9957 The circled numbers in Figure 44 indicate specific events, explained as follows: Event 5--the RT pin switches to Logic 1. The state machine initializes to the start address of RAM Segment Register 0, resets the internal timer, and begins incrementing the RAM address counter. Event 1--an I/O update or profile change activates the RAM bidirectional ramp mode. Event 2--the RT pin switches to Logic 1. The state machine initializes to the start address of RAM Segment Register 0 and begins incrementing the RAM address counter. Event 6--the RT pin switches to Logic 0. The state machine initializes to the end address of RAM Segment Register 1, resets the internal timer, and begins decrementing the RAM address counter. Event 3--the RT pin remained at Logic 1 long enough for the state machine to reach the end address of RAM Segment Register 0, at which point the address counter is halted. Event 7--the RT pin remained at Logic 0 long enough for the state machine to reach the start address of RAM Segment Register 1, at which point the address counter is halted. Event 4--the RT pin switches to Logic 0. The state machine initializes to the end address of RAM Segment Register 1, resets the internal timer, and begins decrementing the RAM address counter. Event 8--the RT pin switches to Logic 1. The state machine initializes to the start address of RAM Segment Register 0, resets the internal timer, and begins incrementing the RAM address counter. Rev. C | Page 31 of 64 AD9957 Data Sheet 1 PDCLK CYCLE OR M DDS CLOCK CYCLES t END ADDRESS RAM ADDRESS 1 t 1 3 2 06384-025 START ADDRESS I/O_UPDATE OR RT TRANSITION Figure 45. Continuous Bidirectional Ramp Timing Diagram RAM Continuous Bidirectional Ramp Mode In continuous bidirectional ramp mode, upon assertion of an I/O update or a state change on the RT pin, the RAM begins playback operation using the parameters programmed into the selected RAM segment register. Data is extracted from RAM over the specified address range contained in the start address and end address. The data is delivered at the appropriate rate and to the destination as specified by the RAM playback destination bit. The playback rate is governed by the timer internal to the RAM state machine and its period (t) is determined by the state of the RAM playback destination bit as detailed in the RAM Playback Operation section. After initialization, the internal state machine begins extracting data from the RAM at the start address of the active RAM segment register and increments the address counter until it reaches the end address, at which point the state machine reverses the direction of the address counter and begins decrementing through the address range. Whenever one of the terminal addresses is reached, the state machine reverses the address counter; the process continues indefinitely. Note that a change in state of the RT pin aborts the current waveform and the newly selected RAM segment register is used to initiate a new waveform. A graphic representation of the continuous bidirectional ramp mode is shown in Figure 45. The circled numbers in Figure 45 indicate specific events, explained as follows: Event 1--an I/O update or state change on the RT pin has activated the RAM continuous bidirectional ramp mode. The state machine initializes to the start address of the active RAM segment register. The state machine begins incrementing through the specified address range. Event 2--the state machine reaches the end address of the active RAM segment register. Event 3--the state machine reaches the start address of the active RAM segment register. The continuous bidirectional ramp continues indefinitely until the next I/O update or state change on the RT pin. Rev. C | Page 32 of 64 Data Sheet AD9957 1 PDCLK CYCLE OR M DDS CLOCK CYCLES t END ADDRESS RAM ADRESS 1 START ADDRESS 2 1 4 3 5 06384-026 I/O_UPDATE OR RT TRANSITION Figure 46. Continuous Recirculate Timing Diagram RAM Continuous Recirculate Mode The continuous recirculate mode mimics ramp-up mode, except that when the state machine reaches the end address of the active RAM segment register, it does not halt. Instead, the next timeout of the internal timer causes the state machine to jump to the start address of the active RAM segment register. This process continues indefinitely until an I/O update or state change on the RT pin. A state change on the RT pin aborts the current waveform and the newly selected RAM segment register initiates a new waveform. A graphic representation of the continuous recirculate mode is shown in Figure 46. The circled numbers in Figure 46 indicate specific events, which are explained as follows: Event 1--an I/O update or state change on the RT pin occurs. This initializes the state machine to the start address of the active RAM segment register and causes the state machine to begin incrementing the address counter at the appropriate rate. Event 2--the state machine reaches the end address of the active RAM segment register. Event 3--the state machine switches to the start address of the active RAM segment register. The state machine continues to increment the address counter. Event 4--the state machine again reaches the end address of the active RAM segment register. Event 5--the state machine switches to the start address of the active RAM segment register. The state machine continues to increment the address counter. Event 4 and Event 5 repeat until an I/O update or state change occurs on the RT pin. Rev. C | Page 33 of 64 AD9957 Data Sheet CLOCK INPUT (REF_CLK) REFCLK OVERVIEW The AD9957 supports a number of options for producing the internal SYSCLK signal (that is, the DAC sample clock) via the REF_CLK/REF_CLK input pins. The REF_CLK input can be driven directly from a differential or single-ended source, or it can accept a crystal connected across the two input pins. There is also an internal phase-locked loop (PLL) multiplier that can be independently enabled. A block diagram of the REF_CLK functionality is shown in Figure 47. The various input configurations are controlled by means of the XTAL_SEL pin and control bits in the CFR3 register. Figure 47 also shows how the CFR3 control bits are associated with specific functional blocks. XTAL_SEL PLL_LOOP_FILTER 95 2 Table 6. REFCLK_OUT Buffer Control CFR3<29:28> 00 01 10 11 REFCLK_OUT Buffer Disabled Low output current Medium output current High output current CRYSTAL DRIVEN REF_CLK When using a crystal at the REF_CLK input, the resonant frequency should be approximately 25 MHz. Figure 48 shows the recommended circuit configuration. DRV0 CFR3 <29:28> 2 90 REF_CLK 91 REF_CLK XTAL PLL ENABLE CFR3 <8> REFCLK INPUT SELECT LOGIC 39pF Figure 48. Crystal Connection Diagram ENABLE PLL_LOOP_FILTER IN PLL REF_CLK 90 CHARGE PUMP DIVIDE REF_CLK 91 2 1 /2 0 ICP CFR3 <21:19> OUT 7 N CFR3 <7:1> REFCLK INPUT REFCLK INPUT DIVIDER RESETB DIVIDER BYPASS CFR3<14> CFR3<15> VCO SELECT 1 0 SYSCLK 3 VCO SEL CFR3 <26:24> 06384-028 1 0 39pF 06384-027 REFCLK_OUT 94 Figure 47. REF_CLK Block Diagram The PLL enable bit is used to choose between the PLL path or the direct input path. When the direct input path is selected, the REF_CLK/REF_CLK pins must be driven by an external signal source. Input frequencies up to 2 GHz are supported. For input frequencies greater than 1 GHz, the input divider must be enabled for proper operation of the device. When the PLL is enabled, a buffered clock signal is available at the REFCLK_OUT pin. This clock signal is the same frequency as the REF_CLK input. This is especially useful when a crystal is connected, because it gives the user a replica of the crystal clock for driving other external devices. The REFCLK_OUT buffer is controlled by two bits as listed in Table 6. DIRECT DRIVEN REF_CLK When driving the REF_CLK/REF_CLK inputs directly from a signal source, either single-ended or differential signals can be used. With a differential signal source, the REF_CLK/REF_CLK pins are driven with complementary signals and ac-coupled with 0.1 F capacitors. With a single-ended signal source, either a single-ended-to-differential conversion can be employed or the REF_CLK input can be driven single-ended directly. In either case, 0.1 F capacitors are used to ac couple both REF_CLK/REF_CLK pins to avoid disturbing the internal dc bias voltage of ~1.35 V. See Figure 49 for more details. The REF_CLK/REF_CLK input resistance is ~2.5 k differential (~1.2 k single-ended). Most signal sources have relatively low output impedances. The REF_CLK/REF_CLK input resistance is relatively high; therefore, its effect on the termination impedance is negligible and can usually be chosen to be the same as the output impedance of the signal source. The bottom two examples in Figure 49 assume a signal source with a 50 output impedance. Rev. C | Page 34 of 64 Data Sheet AD9957 Figure 51 shows the boundaries of the VCO frequency ranges over the full range of temperature and supply voltage variation for an individual device selected from the population. Figure 51 shows that the VCO frequency ranges for a single device always overlap when operated over the full range of conditions. 0.1F DIFFERENTIAL SOURCE, DIFFERENTIAL INPUT. 90 REF_CLK PECL, LVPECL, OR LVDS DRIVER TERMINATION 91 REF_CLK 0.1F BALUN (1:1) SINGLE-ENDED SOURCE, DIFFERENTIAL INPUT. In conclusion, if a user wants to retain a single default value for CFR3<26:24>, a frequency that falls into one of the ranges found in Figure 50 should be selected. Additionally, for any given individual device, the VCO frequency ranges overlap, meaning that any given device exhibits no gaps in its frequency coverage across VCO ranges over the full range of conditions. 0.1F 90 REF_CLK 50 91 REF_CLK 0.1F 0.1F SINGLE-ENDED SOURCE, SINGLE-ENDED INPUT. FLOW = 920 FHIGH = 1030 VCO5 90 REF_CLK 50 FLOW = 760 FHIGH = 875 VCO4 0.1F 06384-029 91 REF_CLK FLOW = 650 FHIGH = 790 VCO3 Figure 49. Direct Connection Diagram FLOW = 530 FHIGH = 615 VCO2 PHASE-LOCKED LOOP (PLL) MULTIPLIER 06384-057 FLOW = 400 FHIGH = 460 VCO0 395 495 595 695 (MHz) 795 895 995 Figure 50. VCO Ranges Including Atypical Wafer Process Skew FLOW = 810 FHIGH = 1180 VCO5 FLOW = 646 FHIGH = 966 VCO4 The PLL output frequency range (fSYSCLK) is constrained to the range of 420 MHz fSYSCLK 1 GHz by the internal VCO. In addition, the user must program the VCO to one of six operating ranges such that fSYSCLK falls within the specified range. Figure 50 and Figure 51 summarize these VCO ranges. FLOW = 574 FHIGH = 904 VCO3 FLOW = 469 FHIGH = 709 VCO2 FLOW = 402 FHIGH = 602 VCO1 FLOW = 342 FHIGH = 522 VCO0 335 06384-056 Figure 50 shows the boundaries of the VCO frequency ranges over the full range of temperature and supply voltage variation for all devices from the available population. The implication is that multiple devices chosen at random from the population and operated under widely varying conditions may require different values to be programmed into CFR3<26:24> to operate at the same frequency. For example, Part A chosen randomly from the population, operating in an ambient temperature of -10C with a system clock frequency of 900 MHz may require CFR3<26:24> to be set to 100b. Whereas Part B chosen randomly from the population, operating in an ambient temperature of 90C with a system clock frequency of 900 MHz may require CFR3<26:24> to be set to 101b. If a frequency plan is chosen such that the system clock frequency operates within one set of boundaries (as shown in Figure 51), the required value in CFR3<26:24> is consistent from part to part. FLOW = 455 FHIGH = 530 VCO1 An internal phase-locked loop (PLL) provides users of the AD9957 the option to use a reference clock frequency that is significantly lower than the system clock frequency. The PLL supports a wide range of programmable frequency multiplication factors (12x to 127x) as well as a programmable charge pump current and external loop filter components (connected via the PLL_LOOP_FILTER pin). These features add an extra layer of flexibility to the PLL, allowing optimization of phase noise performance and flexibility in frequency plan development. The PLL is also equipped with a PLL_LOCK pin. 435 535 635 735 835 (MHz) 935 Figure 51. Typical VCO Ranges Table 7. VCO Range Bit Settings VCO SEL Bits (CFR3<26:24>) 000 001 010 011 100 101 110 111 Rev. C | Page 35 of 64 VCO Range VCO0 VCO1 VCO2 VCO3 VCO4 VCO5 PLL Bypassed PLL Bypassed 1035 1135 AD9957 Data Sheet PLL CHARGE PUMP The charge pump current (ICP) is programmable to provide the user with additional flexibility to optimize the PLL performance. Table 8 lists the bit settings vs. the nominal charge pump current. Table 8. PLL Charge Pump Current ICP (CFR3<21:19>) 000 001 010 011 100 101 110 111 In the prevailing literature, this configuration yields a thirdorder, Type II PLL. To calculate the loop filter component values, begin with the feedback divider value (N), the gain of the phase detector (KD), and the gain of the VCO (KV) based on the programmed VCO SEL bit settings (see Table 1 for KV). The loop filter component values depend on the desired open-loop bandwidth (fOL) and phase margin (), as follows: Charge Pump Current, ICP (A) 212 237 262 287 312 337 363 387 EXTERNAL PLL LOOP FILTER COMPONENTS The PLL_LOOP_FILTER pin provides a connection interface to attach the external loop filter components. The ability to use custom loop filter components gives the user more flexibility to optimize the PLL performance. The PLL and external loop filter components are shown in Figure 52. AVDD Nf OL K D KV C1 = K D K V tan() 2N (f OL ) 2 (8) C2 = K D K V 1 - sin( ) N (2f OL )2 cos( ) (9) (7) where: KD equals the programmed value of ICP. KV is taken from Table 1. Ensure that proper units are used for the variables in Equation 7 through Equation 9. ICP must be in amps, not A as appears in Table 8; KV must be in Hz/V, not MHz/V as listed in Table 1; the loop bandwidth (fOL) must be in Hz; the phase margin () must be in radians. For example, suppose the PLL is programmed such that ICP = 287 A, KV = 625 MHz/V, and N = 25. If the desired loop bandwidth and phase margin are 50 kHz and 45, respectively, the loop filter component values are R1 = 52.85 , C1 = 145.4 nF, and C2 = 30.11 nF. C1 C2 R1 1 1 + sin( ) R1 = PLL_LOOP_FILTER 2 PLL LOCK INDICATION REFCLK PLL PLL IN CP VCO PLL OUT /N 06384-030 PFD When the PLL is in use, the PLL_LOCK pin provides an active high indication that the PLL has locked to the REFCLK input signal. When the PLL is bypassed, the PLL_LOCK pin defaults to Logic 0. Figure 52. REFCLK PLL External Loop Filter Rev. C | Page 36 of 64 Data Sheet AD9957 ADDITIONAL FEATURES OUTPUT SHIFT KEYING (OSK) The OSK function (Figure 53) is only available in single tone mode. It allows the user to control the output signal amplitude of the DDS. Both manual and automatic modes are available. OSK 60 OSK ENABLE AUTO OSK ENABLE MANUAL OSK EXTERNAL LOAD ARR AT I/O_UPDATE AMPLITUDE RAMP RATE (ASF<31:16>) 16 AMPLITUDE SCALE FACTOR (ASF<15:2>) 14 14 TO DDS AMPLITUDE CONTROL PARAMETER 2 DDS CLOCK 06384-031 AMPLITUDE STEP SIZE (ASF<1:0>) OSK CONTROLLER Figure 53. OSK Block Diagram The operation of the OSK function is governed by four control register bits, the external OSK pin, and the entire 32 bits of the ASF register. The primary control for the OSK block is the OSK enable bit. When this bit is set, the OSK function is enabled; otherwise, the OSK function is disabled. When disabled, the other OSK input controls are ignored and the internal clocks are shut down to conserve power. When the OSK function is enabled, automatic and manual operation is selected via the Select Auto-OSK bit. When this bit is set, the automatic mode is active; otherwise, the manual mode is active. Manual OSK In manual mode, output amplitude is varied by successive write operations to the amplitude scale factor portion of the ASF register. The rate at which amplitude changes can be applied to the output signal is limited by the speed of the serial I/O port. In manual mode, the OSK pin functionality depends on the state of the manual OSK external control bit. It is either inoperative or used to switch the output amplitude between the programmed amplitude scale factor value and zero. When operational, a Logic 0 on the OSK pin forces the output amplitude to zero whereas a Logic 1 on the OSK pin causes the output amplitude to be scaled by the amplitude scale factor value. Automatic OSK In automatic mode, the OSK function automatically generates a linear amplitude vs. time profile (or amplitude ramp). The amplitude ramp is controlled via three parameters, as follows: * * * The maximum amplitude scale factor The amplitude step size The time interval between steps The amplitude ramp parameters reside in the 32-bit ASF register and are programmed via the serial I/O port. The amplitude step interval is set using the 16-bit amplitude ramp rate portion of the ASF register (Bits<31:16>). The maximum amplitude scale factor is set using the 14-bit amplitude scale factor in the ASF register (Bits<15:2>). The amplitude step size is set using the 2-bit amplitude step size portion of the ASF register (Bits<1:0>). The direction of the ramp (positive or negative slope) is controlled by the external OSK pin. When the OSK pin is a Logic 1, the slope is positive; otherwise, it is negative. The step interval is controlled by a 16-bit programmable timer that is clocked at a rate of 1/4 fSYSCLK. The timer period sets the interval between amplitude steps. The step time interval (t) is given by t = 4M f SYSCLK where M is the 16-bit number stored in the amplitude ramp rate portion of the ASF register. For example, if fSYSCLK = 750 MHz and M = 23,218 (0x5AB2), then t 123.8293 s. The output of the OSK function is a 14-bit unsigned data bus that controls the amplitude of the DDS output (as long as the OSK enable bit is Logic 1). When the OSK pin is Logic 1, the OSK output value starts at 0 and increments by the programmed amplitude step size until it reaches the programmed maximum amplitude value. When the OSK pin is Logic 0, the OSK output starts at its present value and decrements by the programmed amplitude step size until it reaches 0. The OSK output does not necessarily attain the maximum amplitude--the OSK pin may switch to Logic 0 before attaining the maximum value. The OSK output does not necessarily reach a value of zero--the OSK pin may switch to Logic 1 before attaining the zero value. The OSK output is initialized to 0 at power-up. It is also set to 0 when the OSK enable bit is Logic 0 or when the OSK enable bit is Logic 1, but the Select Auto-OSK bit is Logic 0. The amplitude step size of the OSK output is set by the amplitude step size bits in the ASF register according to the values listed in Table 9. The step size refers to the LSB weight of the 14-bit OSK output. The OSK output cannot exceed the maximum amplitude value programmed into the ASF register. Rev. C | Page 37 of 64 AD9957 Data Sheet Table 9. OSK Amplitude Step Size I/O_UPDATE PIN ASF<1:0> 00 01 10 11 By default, the I/O_UPDATE pin is an input that serves as a strobe signal to allow synchronous update of the device operating parameters. For example, frequency, phase, and amplitude control words for the DDS can be programmed using the serial I/O port. However, the serial I/O port is an asynchronous interface; consequently, programming of the device operating parameters using the I/O port is not synchronized with the internal timing. Using the pin, I/O_UPDATE, the user can synchronize the application of certain programmed operating parameters with external circuitry when new parameters are programmed into the I/O registers. A rising edge on I/O_UPDATE initiates transfer of the register contents to the internal workings of the device. Amplitude Step Size 1 2 4 8 As mentioned earlier, the step interval is controlled by a 16-bit programmable timer. Normally, this timer is loaded with the programmed timing value whenever the timer expires, thus initiating a new timing cycle. However, three events cause the timer to have its timing value reloaded prior to the timer expiring. One such event is when the Select Auto-OSK bit is transitioned from a Logic 0 state to a Logic 1 state followed by an I/O update. A second such event is a change of state in the OSK pin. The third event is dependent on the status of the Load ARR @ I/O Update bit. If this bit is Logic 0, no action occurs; otherwise, when the I/O_UPDATE pin is asserted (or a profile change occurs), the timer resets to its initial starting point. PROFILES Each of the three operating modes of the AD9957 support the use of profiles, which consist of a group of registers containing pertinent operating parameters for a particular operating mode. Profiles enable rapid switching between parameter sets. Profile parameters are programmed via the serial I/O port. Once programmed, a specific profile is activated by means of three external pins (PROFILE<2:0>). A particular profile is activated by providing the appropriate logic levels to the profile control pins per the settings listed in Table 10. AUTOMATIC I/O UPDATE The AD9957 offers an option whereby the I/O update function is asserted automatically rather than relying on an external signal supplied by the user. This feature is enabled by setting the Internal I/O Update Active bit in CFR2. When this feature is active, the I/O_UPDATE pin becomes an output pin. It generates an active high pulse each time an internal I/O update occurs. The duration of the pulse is approximately 12 cycles of SYSCLK. This I/O update strobe can be used to notify an external controller that the device has generated an I/O update internally. The repetition rate of the internal I/O update is programmed via the serial I/O port. Two parameters control the repetition rate. The first parameter consists of the two I/O update rate control bits in CFR2. The second parameter is the 32-bit word in the I/O update rate register that sets the range of an internal counter. Table 10. Profile Control Pins PROFILE<2:0> 000 001 010 011 100 101 110 111 The transfer of programmed data from the programming registers to the internal hardware is also accomplished by changing the state of the profile pins. Active Profile 0 1 2 3 4 5 6 7 The I/O update rate control bits establish a divide by 1, 2, 4, or 8 of a clock signal that runs at 1/4 fSYSCLK. The output of the divider clocks the aforementioned 32-bit internal counter. The repetition rate of the I/O update is given by Consider an application of basic two-tone frequency shift keying (FSK) where binary data is transmitted by selecting between two different frequencies: a mark frequency (Logic 1) and a space frequency (Logic 0). To accommodate FSK, the Profile 0 register is programmed with the appropriate frequency tuning word for a space, and the Profile 1 register is programmed with the appropriate frequency tuning word for a mark. Then, with the PROFILE1 and PROFILE2 pins tied to Logic 0, the PROFILE0 pin is used to transmit the data bits. The logic state of the PROFILE0 pin causes the appropriate mark and space frequencies to be generated. f I / O _ UPDATE f SYSCLK 2A B where: A is the value of the 2-bit word comprising the I/O update rate control bits. B is the value of the 32-bit word stored in the I/O update rate register. If B is programmed to 0x0003 or less, the I/O_UPDATE pin no longer pulses, but assumes a static Logic 1 state. Rev. C | Page 38 of 64 Data Sheet AD9957 POWER-DOWN CONTROL The AD9957 offers the ability to independently power down four specific sections of the device. Power-down functionality applies to the digital core, DAC, auxiliary DAC, and REFCLK input. A power-down of the digital core disables the ability to update the serial I/O port. However, the digital power-down bit can still be cleared via the serial port to prevent the possibility of a nonrecoverable state. Software power-down is controlled through four independent power-down bits in CFR1. Software control requires forcing the EXT_PWR_DWN pin to a Logic 0 state. In this case, setting the desired power-down bits (via the serial I/O port) powers down the associated functional block; clearing the bits restores the function. Alternatively, all four functions can be simultaneously powered down via external hardware control through the EXT_PWR_DWN pin. Forcing this pin to Logic 1 powers down all four circuit blocks, regardless of the state of the power-down bits. That is, the independent power-down bits in CFR1 are ignored and overridden when EXT_PWR_DWN is Logic 1. Based on the state of the external power-down control bit, the EXT_PWR_DWN pin produces either a full power-down or a fast recovery power-down. The fast recovery power-down mode maintains power to the DAC bias circuitry and the PLL, VCO, and input section of the REFCLK circuitry. Although the fast recovery power-down does not conserve as much power as the full power-down, it allows the device to very quickly awaken from the power-down state. GENERAL-PURPOSE I/O (GPIO) PORT Each of these 16 pins is assigned a unique bit in both the 16-bit GPIO configuration register and the 16-bit GPIO data register. The status of each bit in the GPIO configuration register assigns the associated pin as either a GPIO input or output (0 = input, 1 = output) based on the data listed in Table 11. When a GPIO pin is programmed as an output, the logic state written to the associated bit of the GPIO data register (via the serial I/O port) appears at the GPIO pin. When a GPIO pin is programmed as an input, the logic state of the GPIO pin can be read (via the serial I/O port) in the associated bit position in the GPIO data register. Note that the GPIO data register does not require an I/O update. Table 11. GPIO Pins vs. Configuration and Data Register Bits Pin Label D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D3 D2 D1 D0 The GPIO function is only available when the AD9957 is programmed for QDUC mode and the Blackfin interface mode is active. Because the Blackfin serial interface uses only two of the 18 parallel data port pins (D<5:4>), the remaining 16 pins (D<17:6> and D<3:0>) are available as a GPIO port. Rev. C | Page 39 of 64 Configuration Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD9957 Data Sheet SYNCHRONIZATION OF MULTIPLE DEVICES OVERVIEW The internal clocks of the AD9957 provide the timing for the propagation of data along the baseband signal processing path. These internal clocks are derived from the internal system clock (SYSCLK) and are all submultiples of the SYSCLK frequency. The logic state of all of these clocks in aggregate during any given SYSCLK cycle defines a unique clock state. The clock state advances with each cycle of SYSCLK, but the sequence of clock states is periodic. By definition, multiple devices are synchronized when their clock states match and they transition between states simultaneously. Clock synchronization allows the user to asynchronously program multiple devices, but synchronously activate the programming by applying a coincident I/O update to all devices. It also allows multiple devices to operate in unison when the parallel port is in use with either the QDUC or interpolating DAC mode (see Figure 59) or when the dual serial port (BlackFin interface) is in use. The function of the synchronization logic in the AD9957 is to force the internal clock generator to a predefined state coincident with an external synchronization signal applied to the SYNC_IN pins. Forcing multiple devices to the same clock state coincident with the same external signal is, by definition, synchronization. Figure 54 is a block diagram of the synchronization function. The synchronization logic consists of two independent blocks, a sync generator and a sync receiver, both of which use the local SYSCLK signal for internal timing. CLOCK GENERATOR The clock generator provides the necessary timing for the internal workings of the AD9957. The goal of the synchronization mechanism is to force the clock generator to a known state coincident with an external synchronization signal. The clock generator consists of three separate clock trees (see Figure 55). The first is a common clock generator that is active for all programmed modes of operation (single tone, QDUC, or interpolating DAC). The common clock generates the SYNC_CLK signal that appears at Pin 55. The second clock generator is active when the device is programmed for the interpolating DAC mode or quadrature modulation mode using the parallel data port. It uses the SYSCLK/2 output of the common clock as its primary timing source. The third clock generator is active when the device is programmed for quadrature modulation mode using the BlackFin interface. COMMON CLOCK GENERATOR SYNC PULSE /2 SYSCLK /2 SYNC_CLK CLOCK GENERATOR FOR INTERPOLATING DAC MODE OR QUADRATURE MODULATION MODE WITH THE PARALLEL DATA PORT 90 /R REF_CLK /2 PDCLK 91 6 SYNC GENERATOR DELAY REF_CLK INPUT CIRCUITRY SYNC POLARITY SYNC GENERATOR ENABLE SYSCLK The synchronization mechanism relies on the premise that the REFCLK signal appearing at each device is edge aligned with all others resulting from the external REFCLK distribution system (see Figure 59). CLOCK GENERATOR FOR QUADRATURE MODULATION MODE WITH THE BLACKFIN INTERFACE 5 /2 /2 SYNC_OUT 10 6 SYNC STATE PRESET VALUE /2 /2 Figure 55. Clock Generator SYNC RECEIVER DELAY 5 SYNC GENERATOR INPUT DELAY AND EDGE DETECTION 7 SETUP AND HOLD VALIDATION 12 The sync generator block is shown in Figure 56. It is activated via the Sync Generator Enable bit. It allows for one AD9957 in a group to function as a master timing source with the remaining devices slaved to the master. SYNC_IN 8 SYNC RECEIVER SYNC_SMP_ERR 6 4 SYNC STATE SYNC SYNC PRESET VALUE VALIDATION TIMING DELAY VALIDATION DISABLE 06384-032 INTERNAL CLOCKS CLOCK GENERATOR SYNC RECEIVER ENABLE /R 9 06384-065 SYNC GENERATOR Figure 54. Synchronization Circuit Block Diagram Rev. C | Page 40 of 64 Data Sheet /16 D Q /2R 5 0 R 1 SYNC POLARITY 9 PROGAMMABLE DELAY SYNC_OUT 10 LVDS DRIVER SYNC GENERATOR DELAY SYNC GENERATOR ENABLE 06384-033 SYSCLK AD9957 Figure 56. Sync Generator The sync generator produces an LVDS-compatible clock signal with a 50% duty cycle that appears at the SYNC_OUT pins. The frequency of the SYNC_OUT signal can be one of two possible rates. With the AD9957 programmed for any of the following modes: * * * Single tone mode Quadrature modulation mode with the CCI filter bypassed (that is, interpolation factor is 1) Interpolating DAC mode with the CCI filter bypassed (that is, interpolation factor is 1) f SYSCLK 16 With the AD9957 programmed for the QDUC or interpolating DAC mode and with the CCI filter not bypassed (that is, R>1) the frequency of SYNC_OUT is given by f SYNC _ OUT The sync receiver block (shown in Figure 57) is activated via the Sync Receiver Enable bit. The sync receiver consists of three subsections: the input delay and edge detection block, the internal clock generator block, and the setup-and-hold validation block. The clock generator block remains operational even when the sync receiver is not enabled. The sync receiver accepts an LVDS-compatible signal at the SYNC_IN pins. Typically, the signal applied to the SYNC_IN pins originates from the SYNC_OUT of another AD9957 functioning as a master timing unit. The sync receiver expects a periodic synchronization pulse that meets certain frequency requirements based on the operating mode of the AD9957. When programmed for single tone mode, the frequency of SYNC_IN must satisfy f SYNC _ IN = f SYSCLK 4M where M is any integer greater than zero. When programmed for quadrature modulation mode (using the parallel data port) or interpolating DAC mode, the frequency of SYNC_IN must satisfy The frequency of SYNC_OUT is given by: f SYNC _ OUT = SYNC RECEIVER f = SYSCLK 32R where R is the programmed interpolation factor of the CCI filter. The signal at the SYNC_OUT pins is edge aligned with either the rising or falling edge of the internal SYSCLK signal as determined by the Sync Polarity bit. Because the SYNC_OUT signal is synchronized with the internal SYSCLK of the master device, the master device SYSCLK serves as the reference timing source for all slave devices. f SYNC _ IN = f SYSCLK 16(R + M ) where R is the programmed CCI interpolation factor and M is any integer greater than or equal to zero. When programmed for quadrature modulation mode using the BlackFin interface, the frequency of SYNC_IN must satisfy f SYNC _ IN = f SYSCLK 32(R + M ) where R is the programmed CCI interpolation factor and M is any integer greater than or equal to zero. The user can adjust the output delay of the SYNC_OUT signal in steps of ~75 ps by programming the 5-bit sync generator delay word via the serial I/O port. The programmable output delay facilitates added edge timing flexibility to the overall synchronization mechanism. Rev. C | Page 41 of 64 AD9957 Data Sheet CLOCK STATE SYNC STATE PRESET VALUE LVDS RECEIVER SYNC_IN+ 7 SYNC_IN- 8 SYNC_SMP_ERR 12 SYNC RECEIVER DELAY 5 PROGAMMABLE DELAY SYNC RECEIVER ENABLE RISING EDGE DETECTOR AND STROBE GENERATOR P R E S E T Q0 . . . . . . INTERNAL CLOCKS QN LOAD CLOCK GENERATOR SETUP AND HOLD VALIDATION SYNC TIMING VALIDATION DISABLE 6 SYSCLK 4 SYNC VALIDATION DELAY SYNC PULSE 06384-034 DELAYED SYNC-IN SIGNAL Figure 57. Sync Receiver When a device other than another AD9957 provides the SYNC_IN signal it must be LVDS compatible. Furthermore, although SYNC_IN is typically considered to be a periodic clock signal, it is not an absolute requirement. It is feasible to drive the SYNC_IN pins with a single synchronization pulse as long as its edge transition meets the setup/hold timing required for the internally generated sync pulse (as detailed later in this section). However, using a periodic SYNC_IN signal has the distinct advantage that should any of the devices arbitrarily lose synchronization it automatically resynchronizes with the arrival of the next SYNC_IN edge. The 5-bit sync receiver delay word in the multichip sync register delays the SYNC_IN signal in steps of ~75 ps. This provides the ability to time align the arrival of the SYNC_IN signal to multiple devices by compensating for unequal propagation times. The edge detection logic in the sync receiver generates a synchronization pulse (sync pulse) having a duration of one SYSCLK cycle with a repetition rate equal to that of the signal applied to the SYNC_IN pins. To produce the sync pulse, the strobe generator samples the delayed rising edge of the SYNC_IN signal with the rising edge of the local SYSCLK. The generation of this sync pulse is crucial to the operation of the synchronization mechanism, because it performs the task of placing the clock generator into a known state. The sync pulse presets the R-divider stage of the internal clock generator, which behaves as a presettable downcounter (see Figure 55). The programmable 6-bit sync state preset value word in the multichip sync register establishes the preset state. The preset state is only active for a single SYSCLK period, after which the clock generator is free to cycle through its state sequence until the next sync pulse arrives (see Figure 55). In addition to presetting the R-divider, the sync pulse also synchronously presets the other dividers to a proper state in order to preserve the cadence of the clock tree. The ability to program the clock state preset value provides the flexibility to synchronize devices, but with specific relative clock state offsets by assigning a different sync state preset value word to each device in a group. This flexibility is limited, however, because the sync state preset value must adhere to certain bounds to satisfy internal timing requirements. Regardless of the programmed sync state preset value, the preset value is internally constrained to the range, 2 to R, where R is the CCI filter interpolation factor. A programmed value of 0 or 1 is forced to 2, whereas a programmed value greater than R is forced to R. SETUP/HOLD VALIDATION Synchronization of the AD9957 internal clock generator with other external devices relies on the ability of the sync receiver's edge detection circuit to generate a valid sync pulse. This requires proper sampling of the rising edge of the delayed SYNC_IN signal with the rising edge of the local SYSCLK. If the edge timing of these signals fails to meet the setup or hold time requirements of the internal latches in the edge detection circuitry, the proper generation of a sync pulse is in jeopardy. The setup-and-hold validation block (see Figure 58) gives the user a means to validate that proper edge timing exists between the two signals. The Sync Timing Validation Disable bit in Control Function Register 2 controls whether or not the setupand-hold validation block is active. The validation block makes use of a specified time window (programmable in increments of ~75 ps via the 4-bit sync validation delay word in the multichip sync register). The setup validation and hold validation circuits use latches identical to those in both the rising edge detector and strobe generator. The programmable time window skews the timing between the local SYSCLK signal and the delayed sync-in signal. If the hold validation and setup validation circuits fail to produce the same logic states, it is an indication of a possible setup or hold violation. The check logic of Figure 58 monitors the state of the setup and hold validation latches. If they are not equal (that is, a potential setup/hold violation exists), a Logic 1 is stored in an internal validation result latch; otherwise, a Logic 0 is stored. The state of validation result latch appears at the SYNC_SMP_ERR pin. Rev. C | Page 42 of 64 Data Sheet AD9957 Because the programmed value of the sync validation delay establishes the time window for a setup/hold measurement, the amount of delay is an important consideration for proper operation of the validation block. The value chosen should represent a small fraction of the SYSCLK period. For example, if the SYSCLK frequency is 1 GHz (1000 ps period), then a reasonable sync validation delay value is 4 (~300 ps). This allows the validation block to ensure that the local SYSCLK and the delayed SYNC_IN edges exhibit at least 300 ps of timing separation. Choosing too large a value can cause the validation block to indicate a setup/hold violation when one does not exist. Choosing too small a value can cause the validation block to miss a setup/hold violation when one actually exists. The validation result latch is in a reset state whenever the sync receiver is disabled, which forces the SYNC_SMP_ERR pin to a Logic 0 state. To reset the validation result latch when the sync receiver is active, however, requires the use of the Sync Timing Validation Disable bit in the multichip sync register. To make a setup/hold validation measurement is a two-step process. First, write a Logic 1 to the sync timing validation disable bit. Then, to make a measurement, write a Logic 0. The first action resets the validation result latch and holds it in a reset state; the second action releases the reset state and enables the validation result latch to capture a setup/hold validation measurement. Each time a new setup/hold validation check is desired, this two-step procedure must be performed. SYNC RECEIVER RISING EDGE DETECTOR AND STROBE GENERATOR FROM SYNC RECEIVER DELAY LOGIC D Q SYNC PULSE TO CLOCK GENERATION LOGIC SETUP AND HOLD VALIDATION DQ 4 4 4 SYNC VALIDATION DELAY CHECK LOGIC SETUP VALIDATION DELAY 12 SYNC_SMP_ERR DQ DELAY HOLD VALIDATION SYNC TIMING VALIDATION DISABLE Figure 58. Sync Timing Validation Block Rev. C | Page 43 of 64 06384-036 SYSCLK AD9957 Data Sheet SYNCHRONIZATION EXAMPLE To accomplish the synchronization of multiple devices provide each AD9957 with a SYNC_IN signal that is edge aligned across all the devices. If the SYNC_IN signal is edge aligned at all devices, and all devices have the same sync receiver delay and sync state preset value, then they all have matching clock states (that is, they are synchronized). Figure 59 shows this concept with three AD9957s in synchronization. One device operates as a master timing unit with the others synchronized to the master. The master device must have its SYNC_IN pins included as part of the synchronization distribution and delay equalization mechanism. This ensures that the master maintains synchronous timing with the other units. The synchronization mechanism begins with the clock distribution and delay equalization block, which ensures that all devices receive an edge-aligned REFCLK signal. However, even though the REFCLK signal is edge aligned among all devices, this alone does not guarantee that the clock state of each internal clock CLOCK DISTRIBUTION AND DELAY EQUALIZATION EDGE ALIGNED AT REF_CLK INPUTS generator is coordinated with the others. This is the role of the synchronization and delay equalization block. This block accepts the SYNC_OUT signal generated by the master device and redistributes it to the SYNC_IN input of the slave units (as well as feeding it back to the master). The goal of the redistributed SYNC_OUT signal from the master device is to deliver an edgealigned SYNC_IN signal to all of the sync receivers. Assuming that all devices share the same REFCLK edge timing (due to the clock distribution and delay equalization block) and that all devices share the same SYNC_IN edge timing (due to the synchronization and delay equalization block), then all devices should be generating an internal sync pulse in unison (assuming all have the same value for the sync receiver delay). With the further stipulation that all devices have the same sync state preset value, then the synchronized sync pulses cause all of the devices to assume the same predefined clock state simultaneously. That is, all devices have their internal clocks fully synchronized. CLOCK SOURCE (FOR EXAMPLE, AD951x) REF_CLK PDCLK DATA FPGA NUMBER 1 SYNC SYNC IN OUT REF_CLK PDCLK DATA FPGA AD9957 AD9957 MASTER DEVICE EDGE ALIGNED AT SYNC_IN INPUTS. NUMBER 2 SYNC SYNC IN OUT SYNCHRONIZATION DISTRIBUTION AND DELAY EQUALIZATION (FOR EXAMPLE AD951x) REF_CLK AD9957 NUMBER 3 SYNC SYNC IN OUT Figure 59. Multichip Synchronization Example Rev. C | Page 44 of 64 06384-035 FPGA PDCLK DATA Data Sheet AD9957 I/Q PATH LATENCY The I/Q latency through the AD9957 is easiest to describe in terms of system clock (SYSCLK) cycles and is a function of the AD9957 configuration (that is, which mode and which optional features are engaged). The I/Q latency is primarily affected by the programmable CCI rate. The values in Table 12 should be considered estimates because observed latency may be data dependent. The latency was calculated using the linear delay model for FIR filters. N = CCI rate (programmable interpolation rate, 2 to 63, 1 if bypassed). In BFI mode, the latency through the AD9957 may not be constant for multiple transmissions. This is due to the relationship between the phase of the clock that drives the first half-band filter and the frame sync signal coming from the Blackfin, which is unknown and denoted as x in Table 12. The design successfully transfers data from the data assembler logic to the signal process path by updating a parallel register at the proper time. The data is transferred from the parallel register to the signal processing chain and all timing has been verified regardless of the phase relationship between the updating of the parallel register and the signal processing clock. Example Quadrature modulation mode = 18-bit parallel data Reference clock multiplier = bypassed Input scale multiplier = off Inverse CCI = off CCI rate = 20 Inverse SINC = on Output scale = off Latency = (16 x 20) + (4 x 20) + (4 x 20) + (69 x 20) + (4 x 20 + 8) + 22 + 8 + 2 + 8 = 1988 SYSCLKs Table 12. Stage Input Demuxplexer Quadrature Modulation Mode--Parallel 16N Input Scale Multiplier Active: 8N Bypassed: 4N Active: 8N Bypassed: 4N 69N Active: 4N + 8 Bypass: 2N + 4 22 Active: 8 Bypass: 2 Active: 12 Bypass: 2 8 Inverse CCI Filter Half-Band Filters CCI Filter Modulator Inverse Sinc Filter Output Scale Multiplier DAC Interface Quadrature Modulation Mode--BFI (16 + x)N where x = 0 to 15 Not available in BFI mode Active: 8N Bypassed: 4N 345N Active: 4N + 8 Bypass: 2N + 4 22 Active: 8 Bypass: 2 Active: 12 Bypass: 2 8 Rev. C | Page 45 of 64 Interpolation DAC Mode 28N Active: 8N Bypassed: 4N Active: 8N Bypassed: 4N 69N Active: 4N + 8 Bypass: 2N + 4 0 Active: 8 Bypass: 2 Active: 12 Bypass: 2 8 AD9957 Data Sheet POWER SUPPLY PARTITIONING The AD9957 features multiple power supplies, and their power consumption varies with its configuration. This section covers which power supplies can be grouped together and how the power consumption of each block varies with frequency. The values quoted in this section are for comparison only. Refer to Table 1 for exact values. With each group, bypass capacitors of 1 F in parallel with a 10 F capacitor should be used. 1.8 V SUPPLIES DVDD (Pin 17, Pin 23, Pin 30, Pin 47, Pin 57, Pin 64) These pins can be grouped together. Their current consumption increases linearly with the system clock frequency. A system clock of 1 GHz produces a typically current consumption of 610 mA in QDUC mode. There is also a slight (~5%) increase as fOUT increases from 50 MHz to 400 MHz. AVDD (Pin 3) The recommendations here are for typical applications, for which there are four groups of power supplies: 3.3 V digital, 3.3 V analog, 1.8 V digital, and 1.8 V analog. Applications demanding the highest performance may require additional power supply isolation. 3.3 V SUPPLIES DVDD_I/O (Pin 11, Pin 15, Pin 21, Pin 28, Pin 45, Pin 56, Pin 66) These 3.3 V supplies can be grouped together. The power consumption on these pins varies dynamically with serial port activity. AVDD (Pin 74 to Pin 77 and Pin 83) These are 3.3 V DAC power supplies that typically consume about 28 mA. At a minimum, a ferrite bead should be used to isolate these from other 3.3 V supplies, with a separate regulator being ideal. The current consumption of these supplies consist mainly of biasing current and do not vary with frequency. This 1.8 V supply powers the REFCLK multiplier (PLL) and consumes about 7 mA. For applications demanding the highest performance with the PLL enabled, this supply should be isolated from other 1.8 V AVDD supplies with a separate regulator. For less demanding applications this supply can be run off the same regulator as Pin 89, Pin 92 with a ferrite bead to isolate Pin 3 from Pin 89, and Pin 89. The loop filter for the PLL should directly connect to Pin 3. If the PLL is bypassed, pin 3 should still be powered, but isolation is not critical. AVDD (Pin 6) This pin can be grouped together with the DVDD 1.8V supply pins. For the highest performance, a ferrite bead should be used for isolation, with a separate regulator being ideal. AVDD (Pin 89 and Pin 92) This 1.8 V supply for the REFCLK input consumes about 15 mA. The supply can be run off the same as Pin 3 with a ferrite bead to isolate Pin 3 from Pin 89 and Pin 92. At a minimum, a ferrite bead should be used to isolate these from other 1.8 V supplies. However, for applications demanding the highest performance, a separate regulator is recommended. Rev. C | Page 46 of 64 Data Sheet AD9957 SERIAL PROGRAMMING CONTROL INTERFACE--SERIAL I/O The AD9957 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The interface allows read/write access to all registers that configure the AD9957. MSB-first or LSB-first transfer formats are supported. In addition, the serial interface port can be configured as a single pin input/output (SDIO) allowing a two-wire interface, or it can be configured as two unidirectional pins for input/output (SDIO/SDO), enabling a 3-wire interface. Two optional pins (I/O_RESET and CS) enable greater flexibility for designing systems with the AD9957. For a read cycle, Phase 2 is the same as the write cycle with the following differences: Data is read from the active registers, not the serial port buffer, and data is driven out on the falling edge of SCLK. Note that to read back any profile register (0x0E to 0x15), the three external profile pins must be used. For example, if the profile register is Profile 5 (0x13) then PROFILE<0:2> pins must equal 101.This is not required to write to profile registers. INSTRUCTION BYTE The instruction byte contains the following information as shown in the instruction byte bit map. Instruction Byte Information Bit Map GENERAL SERIAL I/O OPERATION There are two phases to a serial communications cycle. The first is the instruction phase to write the instruction byte into the AD9957. The instruction byte contains the address of the register to be accessed (see the Register Map and Bit Descriptions section) and defines whether the upcoming data transfer is a write or read operation. For a write cycle, Phase 2 represents the data transfer between the serial port controller to the serial port buffer. The number of bytes transferred is a function of the register being accessed. For example, when accessing the Control Function Register 2 (Address 0x01), Phase 2 requires that four bytes be transferred. Each bit of data is registered on each corresponding rising edge of SCLK. The serial port controller expects that all bytes of the register be accessed; otherwise, the serial port controller is put out of sequence for the next communication cycle. However, one way to write fewer bytes than required is to use the I/O_RESET pin feature. The I/O_RESET pin function can be used to abort an I/O operation and reset the pointer of the serial port controller. After an I/O reset, the next byte is the instruction byte. Note that every completed byte written prior to an I/O reset is preserved in the serial port buffer. Partial bytes written are not preserved. At the completion of any communication cycle, the AD9957 serial port controller expects the next eight rising SCLK edges to be the instruction byte for the next communication cycle. After a write cycle, the programmed data resides in the serial port buffer and is inactive. I/O_UPDATE transfers data from the serial port buffer to active registers. The I/O update can either be sent after each communication cycle or when all serial operations are complete. In addition, a change in profile pins can initiate an I/O update. MSB D7 R/W D6 X D5 X D4 A4 D3 A3 D2 A2 D1 A1 LSB D0 A0 R/W--Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation. Cleared indicates a write operation. X, X--Bit 6 and Bit 5 of the instruction byte are don't cares. A4, A3, A2, A1, A0--Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. SERIAL I/O PORT PIN DESCRIPTIONS SCLK--Serial Clock The serial clock pin is used to synchronize data to and from the AD9957 and to run the internal state machines. CS--Chip Select Bar An active low input that allows more than one device on the same serial communications line. The SDO and SDIO pins go to a high impedance state when this input is high. If driven high during any communications cycle, that cycle is suspended until CS is reactivated low. Chip select (CS) can be tied low in systems that maintain control of SCLK. SDIO--Serial Data Input/Output Data is always written into the AD9957 on this pin. However, this pin can be used as a bidirectional data line. Bit 1 of CFR1, Register Address 0x00, controls the configuration of this pin. The default is cleared, which configures the SDIO pin as bidirectional. Rev. C | Page 47 of 64 AD9957 Data Sheet SDO--Serial Data Out SERIAL I/O TIMING DIAGRAMS Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9957 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. Figure 60 through Figure 63 provide basic examples of the timing relationships between the various control signals of the serial I/O port. Most of the bits in the register map are not transferred to their internal destinations until assertion of an I/O update, which is not included in the timing diagrams that follow. I/O_RESET--Input/Output Reset MSB/LSB TRANSFERS I/O_RESET synchronizes the I/O port state machines without affecting the addressable registers contents. An active high input on the I/O_RESET pin causes the current communication cycle to abort. After I/O_RESET returns low (Logic 0), another communication cycle can begin, starting with the instruction byte write. The AD9957 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by Bit 0 in Control Function Register 1 (0x00). The default format is MSB first. If LSB first is active, all data, including the instruction byte, must follow LSB-first convention. Note that the highest number found in the bit range column for each register is the MSB and the lowest number is the LSB for that register (see the Register Map and Bit Descriptions section and Table 13). I/O_UPDATE--Input/Output Update The I/O_UPDATE initiates the transfer of written data from the I/O port buffer to active registers. I/O_UPDATE is active on the rising edge and its pulse width must be greater than one SYNC_CLK period. It is either an input or output pin depending on the programming of the Internal I/O Update Active bit. INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO I7 I5 I6 D7 I0 I1 I2 I3 I4 D6 D0 D1 D2 D3 D4 D5 06384-037 SCLK Figure 60. Serial Port Write Timing--Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK I6 I7 I5 I4 I3 I2 I1 I0 DON'T CARE DO7 SDO DO6 DO5 DO4 DO3 DO2 DO1 06384-038 SDIO DO0 Figure 61. 3-Wire Serial Port Read Timing--Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0 06384-039 SCLK Figure 62. Serial Port Write Timing--Clock Stall High INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO I7 I6 I5 I4 I3 I2 I1 I0 DO7 DO6 DO5 DO4 Figure 63. 2-Wire Serial Port Read Timing--Clock Stall High Rev. C | Page 48 of 64 DO3 DO2 DO1 DO0 06384-040 SCLK Data Sheet AD9957 I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK RELATIONSHIPS The I/O_UPDATE pin is used to transfer data from the serial I/O buffer to the active registers in the device. Data in the buffer is inactive. SYNC_CLK is a rising edge active signal. It is derived from the system clock and a divide-by-4 frequency divider. SYNC_CLK, which is externally provided, can be used to synchronize external hardware to the AD9957 internal clocks. I/O_UPDATE initiates the start of a buffer transfer. It can be sent synchronously or asynchronously relative to the SYNC_CLK. If the setup time between these signals is met, then constant latency (pipeline) to the DAC output exists. For example, if repetitive changes to phase offset via the SPI port is desired, the latency of those changes to the DAC output is constant; otherwise, a time uncertainty of one SYNC_CLK period is present. By default, the I/O_UPDATE pin is an input that serves as a strobe signal to allow synchronous update of the device operating parameters. A rising edge on I/O_UPDATE initiates transfer of the register contents to the internal workings of the device. Alternatively, the transfer of programmed data from the programming registers to the internal hardware can be accomplished by changing the state of the PROFILE[2:0] pins. The timing diagram shown in Figure 64 depicts when the data in the buffer is transferred to the active registers. SYSCLK A B SYNC_CLK I/O_UPDATE DATA IN I/O BUFFERS N N-1 N N+1 N+1 N+2 THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B. Figure 64. I/O_UPDATE Transferring Data from I/O Buffer to Active Registers Rev. C | Page 49 of 64 06384-161 DATA IN REGISTERS AD9957 Data Sheet REGISTER MAP AND BIT DESCRIPTIONS REGISTER MAP Note that the highest number found in the Bit Range column for each register in the following tables is the MSB and the lowest number is the LSB for that register. Table 13. Control Registers Register Name (Serial Address) Control Function Register 1 CFR1 (0x00) Bit Range (Internal Address) <31:24> <23:16> Bit 7 (MSB) RAM Enable Manual OSK External Control <15:8> <7:0> Control Function Register 2 CFR2 (0x01) <31:24> <23:16> Control Function Register 3 CFR3 (0x02) Auxiliary DAC Control Register (0x03) I/O Update Rate Register (0x04) Bit 6 Bit 5 Open Inverse Sinc Filter Enable Open Digital PowerDown Blackfin Interface Mode Active DAC PowerDown Blackfin Bit Order <15:8> Internal SYNC_CLK Enable I/O Update Active I/O Update Rate Control <7:0> Open <31:24> <23:16> <15:8> <7:0> <31:24> <23:16> <15:8> <7:0> <31:24> <23:16> <15:8> <7:0> Data Assembler Hold Last Value Open Open REFCLK REFCLK Input Input Divider Divider Bypass ResetB Bit 4 RAM Playback Destination Bit 3 Clear CCI Bit 0 Bit 1 (LSB) Operating Mode Bit 2 Open Open Autoclear Phase Accumulator REFCLK Input Power-Down Open Clear Phase Accumulator Aux DAC Power-Down External Auto Power-Down Power-Down Control Enable Open Blackfin Early Frame Sync Enable Load ARR @ I/O Update OSK Enable SDIO Input Only Open PDCLK Rate Control Data Format PDCLK Enable Sync Timing Validation Disable PDCLK Invert TxEnable Invert Select DDS Sine Output Select AutoOSK LSB First Open Open N<6:0> Open Open Open FSC<7:0> I/O Update Rate<31:24> I/O Update Rate<23:16> I/O Update Rate<15:8> I/O Update Rate<7:0> Rev. C | Page 50 of 64 0x00 0x00 0x00 Enable Profile Registers as ASF Source Read Effective FTW 0x00 Q-First Data Pairing 0x08 Open DRV0<1:0> ICP<2:0> Default Value 0x00 0x40 0x20 VCO SEL<2:0> Open PLL Enable Open 0x1F 0x3F 0x40 0x00 0x00 0x00 0x7F 0x7F 0xFF 0xFF 0xFF 0xFF Data Sheet AD9957 Table 14. RAM, ASF, Multichip Sync, and Profile 0 Registers Register Name (Serial Address) RAM Segment Register 0 (0x05) Bit Range (Internal Address) <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> RAM Segment Register 1 (0x06) <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> Amplitude Scale Factor (ASF) Register (0x09) Multichip Sync Register (0x0A) Profile 0 Register--Single Tone (0x0E) Profile 0 Register--QDUC (0x0E) <31:24> <23:16> <15:8> <7:0> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> Bit 7 (MSB) Bit 6 RAM End Address 0<1:0> RAM Start Address 0<1:0> RAM End Address 1<1:0> RAM Start Address 1<1:0> Bit5 Bit 4 Bit 3 Bit 2 RAM Address Step Rate 0<15:8> RAM Address Step Rate 0<7:0> RAM End Address 0<9:2> Open Bit 1 Bit 0 (LSB) Default Value RAM Start Address 0<9:2> Open RAM Playback Mode 0<2:0> RAM Address Step Rate 1<15:8> RAM Address Step Rate 1<7:0> RAM End Address 1<9:2> Open RAM Start Address 1<9:2> Open RAM Playback Mode 1<2:0> Amplitude Ramp Rate<15:8> Amplitude Ramp Rate<7:0> Amplitude Scale Factor<13:6> Amplitude Scale Factor<5:0> Amplitude Step Size<1:0> Sync Validation Delay<3:0> Sync Sync Sync Open Receiver Generator Generator Enable Enable Polarity Sync State Preset Value<5:0> Open Sync Generator Delay<4:0> Open Sync Receiver Delay<4:0> Open Open Amplitude Scale Factor<13:8> Amplitude Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> CCI Interpolation Rate<7:2> Spectral Invert Inverse CCI Bypass Output Scale Factor Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> Rev. C | Page 51 of 64 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0xB5 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 AD9957 Data Sheet Table 15. Profile 1, Profile 2, and Profile 3 Registers Register Name (Serial Address) Profile 1 Register-- Single Tone (0x0F) Profile 1 Register-- QDUC (0x0F) Profile 2 Register-- Single Tone (0x10) Profile 2 Register-- QDUC (0x10) Profile 3 Register-- Single Tone (0x11) Profile 3 Register-- QDUC (0x11) Bit Range (Internal Address) <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> Bit 7 (MSB) Bit 6 Open Open Open Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Amplitude Scale Factor<13:8> Amplitude Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> CCI Interpolation Rate<7:2> Spectral Invert Output Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> Amplitude Scale Factor<13:8> Amplitude Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> CCI Interpolation Rate<7:2> Spectral Invert Output Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> Amplitude Scale Factor<13:8> Amplitude Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> CCI Interpolation Rate<7:2> Spectral Invert Output Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> Rev. C | Page 52 of 64 Bit 0 (LSB) Inverse CCI Bypass Inverse CCI Bypass Inverse CCI Bypass Default Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Data Sheet AD9957 Table 16. Profile 4, Profile 5, and Profile 6 Registers Register Name (Serial Address) Profile 4 Register-- Single Tone (0x12) Profile 4 Register-- QDUC (0x12) Profile 5 Register-- Single Tone (0x13) Profile 5 Register-- QDUC (0x13) Profile 6 Register-- Single Tone (0x14) Profile 6 Register-- QDUC (0x14) Bit Range (Internal Address) <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> Bit 7 (MSB) Bit 6 Open Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Amplitude Scale Factor<13:8> Amplitude Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> CCI Interpolation Rate<7:2> Spectral Invert Output Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> Open Amplitude Scale Factor<13:8> Amplitude Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> CCI Interpolation Rate<7:2> Spectral Invert Output Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> Open Amplitude Scale Factor<13:8> Amplitude Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> CCI Interpolation Rate<7:2> Spectral Invert Output Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> Rev. C | Page 53 of 64 Bit 0 (LSB) Inverse CCI Bypass Inverse CCI Bypass Inverse CCI Bypass Default Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 AD9957 Data Sheet Table 17. Profile 7, RAM, GPIO Configuration, and GPIO Data Registers Register Name (Serial Address) Profile 7 Register-- Single Tone (0x15) Profile 7 Register-- QDUC (0x15) RAM Register (0x16) GPIO Configuration Register (0x18) GPIO Data Register (0x19) Bit Range (Internal Address) <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> Bit 7 (MSB) <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <31:0> Bit 0 Bit 3 Bit 2 Bit 1 (LSB) Open Amplitude Scale Factor<13:8> Amplitude Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> CCI Interpolation Rate<7:2> Spectral Inverse CCI Invert Bypass Output Scale Factor<7:0> Phase Offset Word<15:8> Phase Offset Word<7:0> Frequency Tuning Word<31:24> Frequency Tuning Word<23:16> Frequency Tuning Word<15:8> Frequency Tuning Word<7:0> RAM Word<31:0> <15:0> GPIO Configuration<15:0> 0x00 <15:0> GPIO Data<15:0> 0x00 Bit 6 Bit 5 Bit 4 Rev. C | Page 54 of 64 Default Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Data Sheet AD9957 REGISTER BIT DESCRIPTIONS The serial I/O port registers span an address range of 0 to 25 (0x00 to 0x19 in hexadecimal notation). This represents a total of 26 registers. However, six of these registers are unused, yielding a total of 20 available registers. The unused registers are 7, 8, 11 to 13, and 23 (0x07 to 0x08, 0x0B to 0x0D, and 0x17). The number of bytes assigned to the registers varies. That is, the registers are not of uniform depth; each contains the number of bytes necessary for its particular function. Additionally, the registers are assigned names according to their functionality. In some cases, a register is given a mnemonic descriptor. For example, the register at Serial Address 0x00 is named Control Function Register 1 and is assigned the mnemonic CFR1. The following section provides a detailed description of each bit in the AD9957 register map. For cases in which a group of bits serve a specific function, the entire group is considered as a binary word and described in aggregate. This section is organized in sequential order of the serial addresses of the registers. Following each subheading are the individual bit descriptions for that particular register. The location of the bit(s) in the register are indicated by <A> or <A:B>, where A and B are bit numbers. The notation, <A:B>, specifies a range of bits from most significant to least significant bit position. For example, <5:2> means bit positions 5 down to 2, inclusive, with Bit 0 identifying the LSB of the register. Unless otherwise stated, programmed bits are not transferred to their internal destinations until the assertion of an I/O update or profile change. Control Function Register 1 (CFR1) Address 0x00, four bytes are assigned to this register. Table 18. Bit Descriptions for CFR1 Register Bit (s) 31 Mnemonic RAM Enable 30:29 28 Open RAM Playback Destination 27:26 25:24 Open Operating Mode 23 Manual OSK External Control 22 Inverse Sinc Filter Enable 21 Clear CCI 20:17 16 Open Select DDS Sine Output 15:14 13 Open Autoclear Phase Accumulator 12 11 Open Clear Phase Accumulator 10 Load ARR @ I/O Update Description 0: disables RAM playback functionality (default). 1: enables RAM playback functionality. Ineffective unless CFR1<31> = 1. 0: RAM playback data routed to baseband scaling multipliers (default). 1: RAM playback data routed to baseband I/Q data path. 00: quadrature modulation mode (default). 01: single tone mode. 1x: interpolating DAC mode. Ineffective unless CFR1<9:8> = 10b. 0: OSK pin inoperative (default). 1: OSK pin enabled for manual OSK control (see the Output Shift Keying (OSK) section). 0: inverse sinc filter bypassed (default). 1: inverse sinc filter active. This bit is automatically cleared by the serial I/O port controller. This operation requires several internal clock cycles to complete, during which time the data supplied to the CCI input by the baseband signal chain is ignored. The inputs are forced to all zeros to flush the CCI data path, after which the CCI accumulators are reset. 0: normal operation of the CCI filter (default). 1: initiates an asynchronous reset of the accumulators in the CCI filter. Ineffective unless CFR1<25:24> = 01b. 0: cosine output of the DDS is selected (default). 1: sine output of the DDS is selected. 0: normal operation of the DDS phase accumulator (default). 1: synchronously resets the DDS phase accumulator any time I/O_UPDATE is asserted or a profile change occurs. 0: normal operation of the DDS phase accumulator (default). 1: asynchronous, static reset of the DDS phase accumulator. 0: normal operation of the OSK amplitude ramp rate timer (default). 1: OSK amplitude ramp rate timer reloaded any time I/O_UPDATE is asserted or a profile change occurs. Rev. C | Page 55 of 64 AD9957 Bit (s) 9 Mnemonic OSK (Output Shift Keying) Enable 8 Select Auto-OSK 7 Digital PowerDown 6 DAC Power-Down 5 REFCLK Input Power-Down 4 Auxiliary DAC Power-Down 3 External PowerDown Control 2 Auto Power-Down Enable 1 SDIO Input Only 0 LSB First Data Sheet Description 0: OSK disabled (default). 1: OSK enabled. Ineffective unless CFR1<9> = 1. 0: manual OSK enabled (default). 1: automatic OSK enabled. This bit is effective without the need for an I/O update. 0: clock signals to the digital core are active (default). 1: clock signals to the digital core are disabled. 0: DAC clock signals and bias circuits are active (default). 1: DAC clock signals and bias circuits are disabled. This bit is effective without the need for an I/O update. 0: REFCLK input circuits and PLL are active (default). 1: REFCLK input circuits and PLL are disabled. 0: auxiliary DAC clock signals and bias circuits are active (default). 1: auxiliary DAC clock signals and bias circuits are disabled. 0: assertion of the EXT_PWR_DWN pin affects full power-down (default). 1: assertion of the EXT_PWR_DWN pin affects fast recovery power-down. Ineffective when CFR1<25:24> = 01b. 0: disable power-down (default). 1: when the TxEnable pin is Logic 0, the baseband signal processing chain is flushed of residual data and the clocks are automatically stopped. Clocks restart when the TxENABLE pin is a Logic 1. 0: configures the SDIO pin for bidirectional operation; 2-wire serial programming mode (default). 1: configures the serial data I/O pin (SDIO) as an input only pin; 3-wire serial programming mode. 0: configures the serial I/O port for MSB first format (default). 1: configures the serial I/O port for LSB first format. Control Function Register 2 (CFR2) Address 0x01, four bytes are assigned to this register. Table 19. Bit Descriptions for CFR2 Register Bit (s) 31 Mnemonic Blackfin Interface Mode Active 30 Blackfin Bit Order 29 Blackfin Early Frame Sync Enable 28:25 24 Open Enable Profile Registers as ASF Source 23 Internal I/O Update Active 22 SYNC_CLK Enable Description Valid only when CFR1<25:24> = 00b (quadrature modulation mode). 0: Pin D<17:0> configured as an 18-bit parallel port (default). 1: Pin D<5:4> configured as a dual serial port compatible with the Blackfin serial interface. Pin D<17:6> and Pin D<3:0> become available as a 16-bit GPIO port. Valid only when CFR2<31> = 1. 0: the dual serial port (BFI) configured for MSB first operation (default). 1: the dual serial port (BFI) configured for LSB first operation. Valid only when CFR2<31> = 1. 0: the dual serial port (BFI) configured to be compatible with Blackfin late frame sync operation (default). 1: the dual serial port (BFI) configured to be compatible with Blackfin early frame sync operation. Valid only when CFR1<25:24> = 01b (single tone mode) and CFR1<9>=0 (OSK disabled). 0: amplitude scale factor bypassed (unity gain). 1: the active profile register determines the amplitude scale factor. This bit is effective without the need for an I/O update. 0: serial I/O programming is synchronized with external assertion of the I/O_UPDATE pin, which is configured as an input pin (default). 1: serial I/O programming is synchronized with an internally generated I/O update signal (the internally generated signal appears at the I/O_UPDATE pin, which is configured as an output pin). 0: the SYNC_CLK pin is disabled; static Logic 0 output. 1: the SYNC_CLK pin generates a clock signal at 1/4 fSYSCLK; use of synchronization of the serial I/O port (default). Rev. C | Page 56 of 64 Data Sheet Bit (s) 21:17 16 Mnemonic Open Read Effective FTW 15:14 I/O Update Rate Control 13 PDCLK Rate Control 12 Data Format 11 PDCLK Enable 10 PDCLK Invert 9 TxEnable Invert 8 Q-First Data Pairing 7 6 Open Data Assembler Hold Last Value 5 Sync Timing Validation Disable 4:0 Open AD9957 Description 0: a serial I/O port read operation of the FTW register reports the contents of the FTW register (default). 1: a serial I/O port read operation of the FTW register reports the actual 32-bit word appearing at the input to the DDS phase accumulator. Ineffective unless CFR2<23> = 1. Sets the prescale ratio of the divider that clocks the I/O update timer as follows: 00: divide-by-1 (default). 01: divide-by-2. 10: divide-by-4. 11: divide-by-8. Ineffective unless CFR2<31> = 0 and CFR1<25:24> = 00b. 0: PDCLK operates at the input data rate (default). 1: PDCLK operates at 1/2 the input data rate; useful for maintaining a consistent relationship between I/Q words at the parallel data port and the internal clocks of the baseband signal processing chain. 0: the data-words applied to Pin D<17:0> are expected to be coded as twos complement (default). 1: the data-words applied to Pin D<17:0> are expected to be coded as offset binary. 0: the PDCLK pin is disabled and forced to a static Logic 0 state; the internal clock signal continues to operate and provide timing to the data assembler. 1: the internal PDCLK signal appears at the PDCLK pin (default). 0: normal PDCLK polarity; Q-data associated with Logic 1, I-data with Logic 0 (default). 1: inverted PDCLK polarity. 0: normal TxENABLE polarity; Logic 0 is standby, Logic 1 is transmit (default). 1: inverted TxENABLE polarity; Logic 0 is transmit, Logic 1 is standby. 0: an I/Q data pair is delivered as I-data first, followed by Q-data (default). 1: an I/Q data pair is delivered as Q-data first, followed by I-data. Ineffective when CFR1<25:24> = 01b. 0: when the TxENABLE pin is false, the data assembler ignores the input data and internally forces zeros on the baseband signal path (default). 1: when the TxENABLE pin is false, the data assembler ignores the input data and internally forces the last value received on the baseband signal path. 0: enables the setup and hold validation circuit to take a measurement; the measurement result appears at the SYNC_SMP_ERR pin; a Logic 1 at this pin indicates a potential setup/hold violation whereas a Logic 0 indicates that a setup/hold violation has not been detected; the measurement result is latched and held until this bit is set to a Logic 1. 1: resets the setup and hold validation measurement circuit forcing the SYNC_SMP_ERR pin to a static Logic 0 condition (default); the measurement circuit is effectively disabled until this bit is restored to a Logic 0 state. Rev. C | Page 57 of 64 AD9957 Data Sheet Control Function Register 3 (CFR3) Address 0x02, four bytes are assigned to this register. Table 20. Bit Descriptions for CFR3 Register Bit (s) 31:30 29:28 27 26:24 23:22 21:19 18:16 15 Mnemonic Open DRV0 Open VCO SEL Open ICP Open REFCLK Input Divider Bypass 14 REFCLK Input Divider ResetB 13:9 8 Open PLL Enable 7:1 0 N Open Description Controls REFCLK_OUT pin (see Table 6 for details); default is 01b. Selects frequency band of the VCO in the REFCLK PLL (see Table 7 for details); default is 111b. Selects the charge pump current in the REFCLK PLL (see Table 8 for details); default is 111b. 0: input divider is selected (default). 1: input divider is bypassed. 0: input divider is reset. 1: input divider operates normally (default). 0: REFCLK PLL bypassed (default). 1: REFCLK PLL enabled. This 7-bit number is divide modulus of the REFCLK PLL feedback divider; default is 0000000b. Auxiliary DAC Control Register Address 0x03, four bytes are assigned to this register. Table 21. Bit Descriptions for Auxiliary DAC Control Register Bit(s) 31:8 7:0 Mnemonic Open FSC Description This 8-bit number controls the full-scale output current of the main DAC (see the Auxiliary DAC section); default is 0xFF. I/O Update Rate Register Address 0x04, four bytes are assigned to this register. This register is effective without the need for an I/O update. Table 22. Bit Descriptions for I/O Update Rate Register5 Bit(s) 31:0 Mnemonic I/O Update Rate Description Ineffective unless CFR2<23> = 1. This 32-bit number controls the automatic I/O update rate (see the Automatic I/O Update section); default is 0xFFFFFFFF. RAM Segment Register 0 Address 0x05, six bytes are assigned to this register. This register is effective without the need for an I/O update. This register is only active if CFR1<31> = 1 and there is a Logic 0-to-Logic 1 transition on the RT pin. Table 23. Bit Descriptions for RAM Segment Register 0 Bit(s) 47:32 31:22 21:16 15:6 5:3 2:0 Mnemonic RAM Address Step Rate 0 RAM End Address 0 Open RAM Start Address 0 Open RAM Playback Mode 0 Description This 16-bit number controls the rate at which the RAM state machine steps through the specified RAM address range. This 10-bit number identifies the ending address for the RAM state machine. This 10-bit number identifies the starting address for the RAM state machine. This 3-bit number identifies the playback mode for the RAM state machine (see Table 5). Rev. C | Page 58 of 64 Data Sheet AD9957 RAM Segment Register 1 Address 0x06, six bytes are assigned to this register. This register is only active if CFR1<31> = 1 and there is a Logic 1 to Logic 0 transition on the RT pin. Table 24. Bit Descriptions for RAM Segment Register 1 Bit(s) 47:32 31:22 21:16 15:6 5:3 2:0 Mnemonic RAM Address Step Rate 1 RAM End Address 1 Open RAM Start Address 1 Open RAM Playback Mode 1 Description This 16-bit number controls the rate at which the RAM state machine steps through the specified RAM address range. This 10-bit number identifies the ending address for the RAM state machine. This 10-bit number identifies the starting address for the RAM state machine. This 3-bit number identifies the playback mode for the RAM state machine (see Table 5). Amplitude Scale Factor (ASF) Register Address 0x09, four bytes are assigned to this register. This register is only active if CFR1<9> = 1. Table 25. Bit Descriptions for ASF Register Bit(s) 31:16 Mnemonic Amplitude Ramp Rate 15:2 Amplitude Scale Factor 1:0 Amplitude Step Size Description Ineffective unless CFR1<8> = 1. This 16-bit number controls the rate at which the OSK controller updates amplitude changes to the DDS. If CFR1<8> = 0 and CFR1<23> = 0, then this 14-bit number is the amplitude scale factor for the DDS. If CFR1<8> = 0 and CFR1<23> = 1, then this 14-bit number is the amplitude scale factor for the DDS when the OSK pin is Logic 1. If CFR1<8> = 1, then this 14-bit number sets a ceiling on the maximum allowable amplitude scale factor for the DDS. Ineffective unless CFR1<8> = 1. This 2-bit number controls the step size for amplitude changes to the DDS (see Table 9). Multichip Sync Register Address 0x0A, four bytes are assigned to this register. Table 26. Bit Descriptions for the Multichip Sync Register Bit(s) 31:28 Mnemonic Sync Validation Delay 27 Sync Receiver Enable 26 Sync Generator Enable 25 Sync Generator Polarity 24 23:18 Open Sync State Preset Value 17:16 15:11 Open Sync Generator Delay 10:8 7:3 Open Sync Receiver Delay 2:0 Open Description Default is 0000b. This 4-bit number sets the timing skew (in ~75 ps increments) between SYSCLK and the delayed sync-in signal for the synchronization validation block in the synchronization receiver. 0: synchronization clock receiver disabled (default). 1: synchronization clock receiver enabled. 0: synchronization clock generator disabled (default). 1: synchronization clock generator enabled. 0: synchronization clock generator coincident with the rising edge of the system clock (default). 1: synchronization clock generator coincident with the falling edge of the system clock. Default is 000000b. This 6-bit number is the state that the internal clock generator assumes when it receives a sync pulse. Default is 00000b. This 5-bit number sets the output delay (in ~75 ps increments) of the synchronization generator. Default is 00000b. This 5-bit number sets the delay input delay (in ~75 ps increments) of the synchronization receiver. Rev. C | Page 59 of 64 AD9957 Data Sheet PROFILE REGISTERS There are eight consecutive serial I/O addresses (0x0E to 0x15) dedicated to device profiles. All eight profile registers are either single tone profiles or QDUC profiles depending on the device operating mode specified by CFR1<25:24>. During operation, the active profile register is determined via the external PROFILE<2:0> pins. Single tone profiles control: DDS frequency (32 bits), DDS phase offset (16 bits), and DDS amplitude scaling (14 bits). QDUC profiles control: DDS frequency (32 bits), DDS phase offset (16 bits), output amplitude scaling (8 bits), CCI filter interpolation factor, inverse CCI bypass, and spectral invert. The QDUC profiles also selectively apply to the interpolating DAC operating mode: only output scaling, CCI filter interpolation factor, and inverse CCI bypass apply; all others (DDS frequency, output amplitude scaling, and spectral invert) are ignored. Profile<7:0> Register--Single Tone Address 0x0E to 0x15, eight bytes are assigned to this register. Table 27. Bit Descriptions for Profile<7:0> Registers--Single Tone Bit(s) 63:62 61:48 47:32 31:0 Mnemonic Open Amplitude Scale Factor Phase Offset Word Frequency Tuning Word Description This 14-bit number controls the DDS output amplitude. This 16-bit number controls the DDS phase offset. This 32-bit number controls the DDS frequency. Profile<7:0> Register--QDUC Address 0x0E to 0x15, eight bytes are assigned to this register. Table 28. Bit Descriptions for Profile<7:0> Registers--QDUC Bit(s) 63:58 57 Mnemonic CC Interpolation Rate Spectral Invert 56 Inverse CCI Bypass 55:48 47:32 31:0 Output Scale Factor Phase Offset Word Frequency Tuning Word Description This 6-bit number is the rate interpolation factor for the CCI filter. 0: the modulator output takes the form: I(t) x cos(ct) - Q(t) x sin(ct). 1: the modulator output takes the form: I(t) x cos(ct) + Q(t) x sin(ct). 0: the inverse CCI filter is enabled. 1: the inverse CCI filter is bypassed. This 8-bit number controls the output amplitude. This 16-bit number controls the DDS phase offset. This 32-bit number controls the DDS frequency. RAM Register Address 0x16, four bytes are assigned to this register. Table 29. Bit Descriptions for RAM Register Bit(s) 31:0 Mnemonic RAM Word Description The number of 32-bit words written to RAM is defined by the start and end address in RAM Segment Register 0 or RAM Segment Register 1. GPIO Configuration Register Address 0x18, two bytes are assigned to this register. Table 30. Bit Descriptions for GPIO Configuration Register Bit(s) 15:0 Mnemonic GPIO Configuration Description See the General-Purpose I/O (GPIO) Port section for details. GPIO Data Register Address 0x19, two bytes are assigned to this register. Table 31. Bit Descriptions for GPIO Data Register Bits 15:0 Mnemonic GPIO Data Description Read or write based on the contents of the GPIO Configuration register. See the General-Purpose I/O (GPIO) Port section for details. Rev. C | Page 60 of 64 Data Sheet AD9957 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 76 100 1 75 76 75 100 1 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) 5.00 SQ 0 MIN 0.15 0.05 SEATING PLANE 0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY 51 25 26 BOTTOM VIEW (PINS UP) 51 50 26 0.50 BSC LEAD PITCH VIEW A 25 50 0.27 0.22 0.17 VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 042209-A 1.05 1.00 0.95 Figure 65. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9957BSVZ AD9957BSVZ-REEL AD9957/PCBZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 100-Lead Thin Quad Flat Package Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package Exposed Pad [TQFP_EP] Evaluation Board Z = RoHS Compliant Part. Rev. C | Page 61 of 64 Package Option SV-100-4 SV-100-4 AD9957 Data Sheet NOTES Rev. C | Page 62 of 64 Data Sheet AD9957 NOTES Rev. C | Page 63 of 64 AD9957 Data Sheet NOTES (c)2007-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06384-0-4/12(C) Rev. C | Page 64 of 64 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: AD9957BSVZ AD9957BSVZ-REEL AD9957/PCBZ