Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - (c) NXP N.V. (year). All rights reserved or (c) Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - (c) Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia 74HC03; 74HCT03 Quad 2-input NAND gate; open-drain output Rev. 4 -- 27 November 2015 Product data sheet 1. General description The 74HC03; 74HCT03 is a quad 2-input NAND gate with open-drain outputs. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits Input levels: For 74HC03: CMOS level For 74HCT03: TTL level Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number 74HC03D Package Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HCT03D 74HC03DB 74HCT03DB 74HC03PW 74HCT03PW 74HC03; 74HCT03 NXP Semiconductors Quad 2-input NAND gate; open-drain output 4. Functional diagram $ % < $ % < $ % < $ % < PQD Fig 1. < $ % *1' DDD Logic symbol Fig 2. DDE IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning +& +&7 +& +&7 $ 9&& % % $ 9&& < $ % % < < $ $ < % % % < $ *1' < $ % < *1' $ < DDD Fig 4. DDD Pin configuration SO14 Fig 5. Pin configuration (T)SSOP14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 74HC_HCT03 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 27 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 2 of 14 74HC03; 74HCT03 NXP Semiconductors Quad 2-input NAND gate; open-drain output 6. Functional description Table 3. Function table[1] Input Output nA nB nY L L Z L H Z H L Z H H L [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VO output voltage Conditions Min Max Unit 0.5 +7 V [1] 0.5 +7 V - 20 mA - 20 mA input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V [1] IO output current 0.5 V < VO - 25 mA ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C - 500 mW IIK [2] total power dissipation Ptot SO14 and (T)SSOP14 packages [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage Conditions 74HC03 74HCT03 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate - - 625 - - - VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 74HC_HCT03 Product data sheet VCC = 2.0 V All information provided in this document is subject to legal disclaimers. Rev. 4 -- 27 November 2015 ns/V (c) NXP Semiconductors N.V. 2015. All rights reserved. 3 of 14 74HC03; 74HCT03 NXP Semiconductors Quad 2-input NAND gate; open-drain output 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V 74HC03 VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V VI = VIH or VIL - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - 0.1 - - 1 - 1 A IOZ OFF-state output current per input pin; VI = VIL; VO = VCC or GND; other inputs at VCC or GND; VCC = 6.0 V; IO = 0 A - - 0.5 - 5.0 - 10 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - 2.0 - - 20 - 40 A CI input capacitance - 3.5 - - - - - pF 74HCT03 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1 - 1 A IOZ OFF-state output current per input pin; VI = VIL; VO = VCC or GND; other inputs at VCC or GND; VCC = 5.5 V; IO = 0 A - - 0.5 - 5.0 - 10 A 74HC_HCT03 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 27 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 4 of 14 74HC03; 74HCT03 NXP Semiconductors Quad 2-input NAND gate; open-drain output Table 6. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 A ICC additional supply current per input pin; VI = VCC 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 100 360 - 450 - 490 A CI input capacitance - 3.5 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for test circuit, see Figure 7. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) 74HC03 tpd propagation delay nA, nB to nY; see Figure 6 [1] VCC = 2.0 V - 28 95 120 145 ns VCC = 4.5 V - 10 19 24 29 ns VCC = 5.0 V; CL = 15 pF - 8 - - - ns - 8 16 20 25 ns VCC = 2.0 V - 19 75 95 110 ns VCC = 4.5 V - 7 15 19 22 ns - 6 13 16 19 ns - 4 - - - pF VCC = 6.0 V tt transition time [2] see Figure 6 VCC = 6.0 V CPD power dissipation capacitance 74HC_HCT03 Product data sheet per package; VI = GND to VCC [3] All information provided in this document is subject to legal disclaimers. Rev. 4 -- 27 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 5 of 14 74HC03; 74HCT03 NXP Semiconductors Quad 2-input NAND gate; open-drain output Table 7. Dynamic characteristics ...continued GND = 0 V; CL = 50 pF; for test circuit, see Figure 7. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 12 24 30 36 ns - 10 - - - ns 74HCT03 [1] propagation delay nA, nB to nY; see Figure 6 tpd VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tt transition time VCC = 4.5 V; see Figure 6 [2] CPD power dissipation capacitance per package; VI = GND to VCC 1.5 V [3] [1] - 7 15 19 22 ns - 4 - - - pF tpd is the same as tPLZ and tPZL. [2] tt is the same as tTHL. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 11. Waveforms 9, 90 Q$Q%LQSXW *1' W3/= W3=/ 9&& Q<RXWSXW 90 92/ 9; W7+/ DDD Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Table 8. Input to output propagation delays Measurement points Type Input Output VM VM VX 74HC03 0.5VCC 0.5VCC 0.1VCC 74HCT03 1.3 V 1.3 V 0.1VCC 74HC_HCT03 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 27 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 6 of 14 74HC03; 74HCT03 NXP Semiconductors Quad 2-input NAND gate; open-drain output 9, W: QHJDWLYH SXOVH 90 9 WI WU WU WI 9, SRVLWLYH SXOVH 9 90 90 90 W: 9&& 9&& * 9, 92 5/ 6 RSHQ '87 &/ 57 DDG Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 7. Table 9. Test circuit for measuring switching times Test data Type Input Load S1 position VI tr, tf CL RL tPZL, tPLZ 74HC03 VCC 6 ns 15 pF, 50 pF 1 k VCC 74HCT03 3.0 V 6 ns 15 pF, 50 pF 1 k VCC 74HC_HCT03 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 27 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 7 of 14 74HC03; 74HCT03 NXP Semiconductors Quad 2-input NAND gate; open-drain output 12. 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All rights reserved. 8 of 14 74HC03; 74HCT03 NXP Semiconductors Quad 2-input NAND gate; open-drain output 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ = 4 $ $ $ $ SLQLQGH[ /S / GHWDLO; Z 0 ES H PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 Fig 9. 5()(5(1&(6 ,(& -('(& -(,7$ 02 (8523($1 352-(&7,21 ,668('$7( Package outline SOT337-1 (SSOP14) 74HC_HCT03 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 27 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 9 of 14 74HC03; 74HCT03 NXP Semiconductors Quad 2-input NAND gate; open-drain output 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ = 4 $ SLQLQGH[ $ $ $ /S / H GHWDLO; Z 0 ES PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ 02 (8523($1 352-(&7,21 ,668('$7( Fig 10. Package outline SOT402-1 (TSSOP14) 74HC_HCT03 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 27 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 10 of 14 74HC03; 74HCT03 NXP Semiconductors Quad 2-input NAND gate; open-drain output 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT03 v.4 20151127 Product data sheet - 74HC_HCT03 v.3 Modifications: 74HC_HCT03 v.3 Modifications: * Type numbers 74HC03N and 74HCT03N (SOT27-1) removed. 20130627 Product data sheet - 74HC_HCT03_CNV v.2 * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. * Legal texts have been adapted to the new company name where appropriate. 74HC_HCT03_CNV v.2 19970827 74HC_HCT03 Product data sheet Product specification - All information provided in this document is subject to legal disclaimers. Rev. 4 -- 27 November 2015 - (c) NXP Semiconductors N.V. 2015. All rights reserved. 11 of 14 74HC03; 74HCT03 NXP Semiconductors Quad 2-input NAND gate; open-drain output 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT03 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 27 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 13 of 14 NXP Semiconductors 74HC03; 74HCT03 Quad 2-input NAND gate; open-drain output 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 November 2015 Document identifier: 74HC_HCT03 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Nexperia: 74HCT03D/AUJ NXP: 74HC03D/AUJ