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1. General description
The 74HC03; 74HCT 03 is a quad 2-input NAND gate with open-drain outputs. Inputs
include clamp diodes that enable the use of current limiting resistors to interface inputs to
voltages in excess of VCC.
2. Features and benefits
Input levels:
For 74HC03: CMOS level
For 74HCT03: TTL level
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115 -A ex ce ed s 20 0 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
Rev. 4 — 27 November 2015 Product data sheet
Table 1. Ordering information
Type number Package
Temper ature range Name Description Version
74HC03D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
3.9 mm SOT108-1
74HCT03D
74HC03DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm SOT337-1
74HCT03DB
74HC03PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74HCT03PW
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 2 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
4. Functional diagram
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)
PQD
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Fig 4. Pin configuration SO14 Fig 5. Pin configuration (T)SSOP14
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Table 2. Pin description
Symbol Pin Description
1A to 4A 1, 4, 9, 12 data input
1B to 4B 2, 5, 10, 13 data input
1Y to 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
VCC 14 supply voltage
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 3 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 3. Function table[1]
Input Output
nA nB nY
LLZ
LHZ
HLZ
HHL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
VOoutput voltage [1] 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V [1] -20 mA
IOK output clamping current VO<0.5 V [1] -20 mA
IOoutput curren t 0.5 V < VO-25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation [2]
SO14 and (T)SSOP14
packages -500mW
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC03 74HCT03 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V i nput transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 4 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC03
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V -0.1- - 1-1A
IOZ OFF-state
output current per input pin; VI=V
IL;
VO=V
CC or GND;
other inputs at VCC or GND;
VCC =6.0V; I
O=0A
- - ±0.5 - ±5.0 - ±10 A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V -2.0- - 20 - 40A
CIinput
capacitance -3.5- - - - -pF
74HCT03
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20A - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =5.5V --0.1 - 1-1A
IOZ OFF-state
output current per input pin; VI=V
IL;
VO=V
CC or GND;
other inputs at VCC or GND;
VCC = 5.5 V; IO=0A
- - ±0.5 - ±5.0 - ±10 A
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 5 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
10. Dynamic characteristics
ICC supply current VI = VCC or GND; IO=0A;
VCC =5.5V --2.0- 20 - 40A
ICC additional
supply current per input pin;
VI=V
CC 2.1 V; IO=0A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
- 100 360 - 450 - 490 A
CIinput
capacitance -3.5- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
GND = 0 V; CL= 50 pF; for test circuit, see Figure 7.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ Max Max
(85 C) Max
(125 C)
74HC03
tpd propagation delay nA, nB to nY; see Figure 6 [1]
VCC = 2.0 V - 28 95 120 145 n s
VCC = 4.5 V - 10 19 24 29 ns
VCC = 5.0 V; CL=15pF - 8 - - - ns
VCC = 6.0 V - 8 16 20 25 ns
tttransition time see Figure 6 [2]
VCC = 2.0 V - 19 75 95 110 ns
VCC = 4.5 V - 7 15 19 22 ns
VCC = 6.0 V - 6 13 16 19 ns
CPD power dissipation
capacitance per package; VI=GNDtoV
CC [3] -4- - -pF
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 6 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
[1] tpd is the same as tPLZ and tPZL.
[2] tt is the same as tTHL.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD=C
PD VCC2fiN+ (CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
11. Waveforms
74HCT03
tpd propagation delay nA, nB to nY; see Figure 6 [1]
VCC = 4.5 V - 12 24 30 36 ns
VCC = 5.0 V; CL=15pF - 10 - - - ns
tttransition time VCC = 4.5 V; see Figure 6 [2] - 7 15 19 22 ns
CPD power dissipation
capacitance per package;
VI=GNDtoV
CC 1.5 V [3] -4- - -pF
Table 7. Dynamic characteristics …continued
GND = 0 V; CL= 50 pF; for test circuit, see Figure 7.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ Max Max
(85 C) Max
(125 C)
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Input to output propagation delays
DDD
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Table 8. Measur emen t points
Type Input Output
VMVMVX
74HC03 0.5VCC 0.5VCC 0.1VCC
74HCT03 1.3 V 1.3 V 0.1VCC
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 7 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 7. Test circuit for measuring switching times
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Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPZL, tPLZ
74HC03 VCC 6ns 15pF, 50pF 1kVCC
74HCT03 3.0 V 6 ns 15 pF, 50 pF 1 kVCC
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 8 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
12. Package outline
Fig 8. Package outline SOT108-1 (SO14)
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74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 9 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
Fig 9. Package outline SOT337-1 (SSOP14)
81,7 $
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74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 10 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
Fig 10. Package outline SOT402-1 (TSSOP14)
81,7 $
$
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74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 11 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Tr ansistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT03 v.4 201511 27 Product data sheet - 74HC_HCT03 v.3
Modifications: •Type numbers 74HC03N and 74HCT 03N (SOT27-1) removed.
74HC_HCT03 v.3 20130627 Product data sheet - 74HC_HCT03_CNV v.2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
74HC_HCT03_CNV v.2 19970827 Product specification - -
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 12 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
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[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
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Product [short] data sheet Production This document contains the product specification.
74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 November 2015 13 of 14
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
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16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC03; 74HCT03
Quad 2-input NAND gate; open-drain output
© NXP Semiconductors N.V. 2015. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 November 2015
Document identifier: 74HC_HCT03
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Functional description . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Recommended operating conditions. . . . . . . . 3
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16 Contact information. . . . . . . . . . . . . . . . . . . . . 13
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
