SC628
System Clock Generator Supporting
Synchronous/Asynchronous PCI System Board Designs
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.2 6/16/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 1 of 6
PRODUCT FEATURES
Supports Synchronous / Asynchronous PCI
system board designs with P54, P55, and P6,
Cyrix and AMD CPU’s.
12 CPU clocks for SDRAM support.
90 mA buffer switching current @ 3.3V
Current controlled buffers for lower EMI.
Selectable Offset Delay between CPU and PCI
clocks.
F.A.S.T. (Frequency Augmentation System
Test) function for increased host/PCI speed.
Optional common or mixed supply mode:
VDD=VDDq=3.3V, VDD=3.3V, VDDq=2.5V.
34 Pin SSOP.
BLOCK DIAGRAM
FREQUENCY TABLE
Selectors Outputs(MHz)
S2 S1 S0 CPU PCI F.A.S.T.
0 0 0 83.33 33.33 3.25%
0 0 1 75.17 37.59 4.76%
0 1 0 55.07 27.54 4.76%
0 1 1 TEST TEST TEST
1 0 0 50.11 25.06 4.76%
1 0 1 66.66 33.33 4.76%
1 1 0 60.14 30.07 4.76%
1 1 1 75.17 30.07 4.76%
CONNECTION DIAGRAM
REF
PLL1
PCI DELAY
CONTROL UNIT
PLL2
S0
S1
F.A.S.T.
48MHz
24MHz
XIN
XOUT
B
B
CPU(0:7), (10:12)
12
REF0 / F.A.S.T.
B
VDDQ
CPU(8:9)/S(0:1)
PCI(0:5)
6
DLY
S2
VDD 1
Xin 2
Xout 3
VSS 4
CPU1 / S2 5
CPU2 6
CPU3 7
VDDQ 8
CPU4 9
CPU5 10
VSS 11
CPU6 12
CPU7 13
VDDQ 14
REF0 / F.A.S.T.34 REF1 / DLY
33 VDD32 24 MHZ
31 48 MHZ30 VSS29 PCI128 PCI227 VDD26 PCI325 PCI424 VSS23 PCI522 PCI621
CPU8 / S1 15
CPU9 / S0 16 VSS20 CPU1219
CPU10 17 CPU1118
REF1 / DLY
SC628
System Clock Generator Supporting
Synchronous/Asynchronous PCI System Board Designs
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.2 6/16/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 2 of 6
PIN DESCRIPTION
Xin, Xout - On-chip reference oscillator buffer. These pins are connected to the terminals of a parallel (or anti-)
resonant crystal. Xin may also be used as input for an externally generated signal; in this case Xout must be left
unconnected (floating.)
CPU(1:12) - Low skew host clocks outputs. CPU1 / S2, CPU8 / S1, and CPU9 / S0 are bidirectionals pins. During
power-up these pins are in input mode and are considered frequency select lines; they have internal pull-ups (see
table, page 1 for frequency selection, and fig.2 page 4, for selection application note). When the power reaches the
VDD rail, the select data is latched internally to the IC and these pins become CPU clock outputs. (See Fig.1) These
pins are powered by VDDQ at either 2.5 or 3.3 volts.
PCI(1:6) - Low skew PCI clock outputs. These outputs are synchronous to CPU clocks except when selectors are set
to (000) or (111) in the frequency table where the PCI clocks are Pseudo-synchronous.
REF0 / F.A.S.T., REF1 / DLY - These are bidirectional pins. During power-up, These pins are in input mode and are
used for enabling the F.A.S.T. mode and for selecting the offset delay between CPU and PCI clocks (See table
below); they have internal pull-ups. When F.A.S.T. is low (see fig.2 page 4, for selection application note), CPU and
PCI frequencies are increased by a certain percentage as listed in the table on page 1. When the power reaches the
VDD rail (See Fig.1), the select data is latched internally to the IC and these pins become buffered outputs of the
crystal.
DLY Toff (nS)
select MIN TYP MAX
11 4
00 2
48MHz - USB clock output.
24MHz - SIO clock output
VSS - Circuit ground.
VDD - 3.3 volt power supply.
A 0.1µF capacitor must be placed as close as possible to each VDD pin.
Otherwise the filtering intent of the cap will be neutralized by the trace lead inductance.
VDDQ -
3.3 or 2.5 volt power supply for CPU clocks.
Power Supply
CPU1 / S2
CPU8 / S1
CPU9 / S0
REF0 / F.A.S.T.
REF1 / DLY
Hi-Z (tristate), inputs toggle , outputs
Fig.1
VDD
SC628
System Clock Generator Supporting Synchronous/Asynchronous
PCI System Board Designs
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.2 6/16/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 3 of 6
MAXIMUM RATINGS
Voltage Relative to VSS: -0.3V
Voltage Relative to VDD: 0.3V
Storage Temperature: -65ºC to 150ºC
Ambient Temperature: -55ºC to +125ºC
Maximum Operating Supply: 7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to its circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS <(Vin,Vout)< VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either Vss or VDD).
ELECTRICAL CHARACTERISTICS
Characteristic Symbol Min Typ Max Units Conditions
Input Low Voltage VIL - - 0.8 Vdc
Input High Voltage VIH 2.0 - - Vdc S2, S1, S0, F.A.S.T., DLY
Current on Pull (up/down) IIL, IIH -66, 5 µA
Output Low Voltage
IOL = 12mA VOL - - 0.4 Vdc All outputs
Output High Voltage
IOH=12mA VOH 2.4 - - Vdc
Tri-State leakage Current IOZ --10µA
Dynamic Supply Current IDD - - TBD mA CPU* = 66.6 MHz
Static Supply Current IDD - - TBD µA Xin = 1
Short Circuit Current IOS 25 - - mA 1 output at a time - max 30 sec.
VDD = 3.3V + 10%. TA = 0ºC to 70ºC
SC628
System Clock Generator Supporting Synchronous/Asynchronous PCI
System Board Designs
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.2 6/16/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 4 of 6
SWITCHING CHARACTERISTICS
Characteristic Symbol Min Typ Max Units Conditions
Output Rise (0.8V - 2.0V) tTLH, - - 1.5 nS 40 pF load. ALL OUTPUTS*
and Fall (2.0V-0.8V) time tTHL - - 1.5 nS 40 pF load. ALL OUTPUTS*
Output duty cycle 45 50 55 % Measured at 1.5V
CPU*-Skew t1SKW - - 250 pS Measured at 1.5V
PCI*-Skew t2SKW - - 500 pS Measured at 1.5V
CPU* - PCI* OFFSET tOFF11 - 4 nS Measured at 1.5V, DLY = 1
CPU* - PCI* OFFSET tOFF00 - 2 nS Measured at 1.5V, DLY = 0
Cycle to cycle ∆Period ∆P- - + 250 pS Measured at 1.5V on CPU*
Jitter Absolute tjab - - 500 pS Measured at 1.5V on CPU*
Switching current (AC) Iol, Ioh - 90 - mA CPU* and PCI* outputs
VDD = 3.3V + 10%. TA = 0ºC to 70ºC
PCB LAYOUT RECOMMENDATION
This is only a layout recommendation for best
performance and lower EMI. The designer may
choose a differnent approach such as using VDD
traces instead of islands (dashed areas). Also, the
designer may choose to use more than one bead.
Regardless of which way the layout is implemented,
Bypass caps : C3, C4, C5, C6, and C7 (all 0.1µF)
should always be used and placed as close to their
VDD pins as possible. C8 (22µF) is for EMI reduction.
Caps should be multilayer low impedance at high
frequencies such as Z5U material.
Via to VCC plane
Via to VDD island
Via to GND plane
IMISC628
C8
FB1
VCC
C7
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C5
C4
C3
C6
16
15
19
20
17 18
SC628
System Clock Generator Supporting Synchronous/Asynchronous PCI
System Board Designs
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.2 6/16/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 5 of 6
SELECTOR APPLICATION
Pins 5, 15, 16, 33 and 34 are bidirectional pins and are used for selecting the output frequency of the CPU clocks,
enabling the F.A.S.T. mode, and/or selecting delay time (Toff) between CPU and PCI clocks. During power-up of the
SC628, these pins are in input mode (see Fig1, page 2), therefore, they are considered input select pins S2, S1, S0,
F.A.S.T, and DLY. ( see Fig. 1, page2) . I nternal t o the I C, t hese pins hav e l arge val ue pul l -ups, ther ef ore, if a select i on “1”
is the default. If a selection “0” is required, then an external 10KΩ pull-down is required as in Fig.2.
Note : the Selection resistor 10 KΩ must be placed close the pin and before the dedamping resistor (Rd).
PACKAGE DRAWINGS AND DIMENSIONS
34 PIN SSOP OUTLINE DIMENSIONS
INCHES MILLIMETERS
SYMBOL MIN NOM MAX MIN NOM MAX
A 0.097 0.101 0.104 2.46 2.56 2.64
A10.0050 0.009 0.0115 0.127 0.22 0.29
A2 0.090 0.092 0.094 2.29 2.34 2.39
B 0.014 0.016 0.019 0.35 0.41 0.48
C 0.0091 0.010 0.0125 0.23 0.25 0.32
D 0.701 0.706 0.711 17.81 17.93 18.06
E 0.292 0.296 0.299 7.42 7.52 7.59
e 0.040 BSC 1.016 BSC
H 0.400 0.406 0.410 10.16 10.31 10.41
a 0.10 0.013 0.016 0.25 0.33 0.41
L 0.024 0.032 0.040 0.61 0.81 1.02
a0º4º8º 0º4º8º
X 0.085 0.093 0.100 2.16 2.36 2.54
IMISC628 Applicable to pins :
5, 15, 16, 33, 34
10KΩ
Rd
Jumper
To load
Fig. 2
Be
A
A1
A2
EH
a
L
C
D
SC628
System Clock Generator Supporting Synchronous/Asynchronous PCI
System Board Designs
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.2 6/16/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 6 of 6
ORDERING INFORMATION
Part Number Package Type Production Flow
IMISC628BYB 34 Pin SSOP Commercial, 0° C to + 70° C
Marking: Example: IMI
SC628BYB
Date Code, Lot #
IMISC628BYB
Flow
B = Commerical, 0° C to + 70 C°
Package
Y = SSOP
Revision
IMI Device Number
