Quad, 10-Bit nanoDAC with 2 ppm/C Reference, I2C Interface AD5316R Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD GND VREF AD5316R VLOGIC 2.5V REFERENCE DAC REGISTER INPUT REGISTER STRING DAC A SCL VOUTA BUFFER INTERFACE LOGIC SDA A1 A0 DAC REGISTER INPUT REGISTER STRING DAC B VOUTB BUFFER DAC REGISTER INPUT REGISTER STRING DAC C VOUTC BUFFER INPUT REGISTER DAC REGISTER STRING DAC D VOUTD BUFFER POWER-ON RESET GAIN = x1/x2 RSTSEL GAIN LDAC RESET POWERDOWN LOGIC Figure 1. APPLICATIONS Digital gain and offset adjustment Programmable attenuators Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5316R, a member of the nanoDAC(R) family, is a low power, quad, 10-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm x 3 mm LFCSP package and in a TSSOP package. Table 1. Related Devices The AD5316R also incorporates a power-on reset circuit and a RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. The part contains a per-channel power-down feature that reduces the current consumption of the device in power-down mode to 4 A at 3 V. 1. The AD5316R uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic. Rev. C Interface SPI I2 C 1 Reference Internal External Internal External 12-Bit AD5684R AD5684 AD5694R AD5694 10-Bit AD5317R AD5317 AD53161 The AD5316R and the AD5316 are not pin-to-pin or software compatible. PRODUCT HIGHLIGHTS 2. 3. Precision DC Performance. Total unadjusted error: 0.1% of FSR maximum Offset error: 1.5 mV maximum Gain error: 0.1% of FSR maximum Low Drift 2.5 V On-Chip Reference. 2 ppm/C typical temperature coefficient 5 ppm/C maximum temperature coefficient Two Package Options. 3 mm x 3 mm, 16-lead LFCSP 16-lead TSSOP Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2012-2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 10819-001 Low drift 2.5 V on-chip reference: 2 ppm/C typical Tiny package: 3 mm x 3 mm, 16-lead LFCSP Total unadjusted error (TUE): 0.1% of FSR maximum Offset error: 1.5 mV maximum Gain error: 0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User-selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility 400 kHz I2C-compatible serial interface 4 I2C addresses available Low glitch: 0.5 nV-sec Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply -40C to +105C temperature range AD5316R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 I2C Slave Address ........................................................................ 18 Applications ....................................................................................... 1 Serial Operation ......................................................................... 18 Functional Block Diagram .............................................................. 1 Write Operation.......................................................................... 18 General Description ......................................................................... 1 Read Operation........................................................................... 19 Product Highlights ........................................................................... 1 Multiple DAC Readback Sequence .......................................... 19 Revision History ............................................................................... 2 Power-Down Operation ............................................................ 20 Specifications..................................................................................... 3 Load DAC (Hardware LDAC Pin) ........................................... 20 AC Characteristics ........................................................................ 4 LDAC Mask Register ................................................................. 21 Timing Characteristics ................................................................ 5 Hardware Reset Pin (RESET) ................................................... 21 Absolute Maximum Ratings ............................................................ 6 Reset Select Pin (RSTSEL) ........................................................ 21 Thermal Resistance ...................................................................... 6 Internal Reference Setup ........................................................... 22 ESD Caution .................................................................................. 6 Solder Heat Reflow ..................................................................... 22 Pin Configurations and Function Descriptions ........................... 7 Long-Term Temperature Drift ................................................. 22 Typical Performance Characteristics ............................................. 8 Thermal Hysteresis .................................................................... 22 Terminology .................................................................................... 14 Applications Information .............................................................. 23 Theory of Operation ...................................................................... 16 Microprocessor Interfacing ....................................................... 23 Digital-to-Analog Converter .................................................... 16 AD5316R to ADSP-BF531 Interface ........................................ 23 Transfer Function ....................................................................... 16 Layout Guidelines....................................................................... 23 DAC Architecture ....................................................................... 16 Galvanically Isolated Interface ................................................. 23 Serial Interface ............................................................................ 17 Outline Dimensions ....................................................................... 24 Write and Update Commands .................................................. 17 Ordering Guide .......................................................................... 24 REVISION HISTORY 5/2017--Rev. B to Rev. C Changes to Features Section............................................................ 1 Changes to Table 2 Summary.......................................................... 3 Changes to Table 3 ............................................................................ 4 Changes to Table 4 Summary.......................................................... 5 Changes to Table 5 ............................................................................ 6 Changes to VLOGIC Pin Description and RESET Pin Description, Table 7 ................................................................................................ 7 Changes to Figure 13 to Figure 16 .................................................. 9 Changes to Figure 17 to Figure 21 ................................................ 10 Changes to Figure 27 ...................................................................... 11 Changes to Figure 34 ...................................................................... 12 Changes to Figure 35 ...................................................................... 13 Changes to Hardware Reset (RESET) Section ............................ 21 Added Long-Term Temperature Drift Section and Figure 47; Renumbered Sequentially.............................................................. 22 Changes to Ordering Guide .......................................................... 24 2/2014--Rev. A to Rev. B Change to Table 2 ..............................................................................3 Change to Table 7 ..............................................................................9 Deleted Figure 7, Renumbered Sequentially .................................8 Deleted Long-Term Temperature Drift Section and Figure 48 .......................................................................................... 22 7/2012--Rev. 0 to Rev. A Change to Features Section ..............................................................1 Change to Relative Accuracy Parameter in Table 2 ......................3 Change to Differential Nonlinearity Parameter in Table 2 ..........3 Changes to Ordering Guide .......................................................... 24 7/2012--Revision 0: Initial Version Rev. C | Page 2 of 24 Data Sheet AD5316R SPECIFICATIONS VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.62 V VLOGIC 5.5 V; RL = 2 k; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE 3 Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Total Unadjusted Error Min Short-Circuit Current 6 Load Impedance at Rails 7 Power-Up Time REFERENCE OUTPUT Output Voltage 8 Reference TC 9 Output Impedance4 Output Voltage Noise4 Output Voltage Noise Density4 Load Regulation, Sourcing4 Load Regulation, Sinking4 Output Current Load Capability4 Line Regulation4 Thermal Hysteresis4 LOGIC INPUTS4 Input Current Input Low Voltage, VINL Input High Voltage, VINH Pin Capacitance 0.12 0.5 0.5 1.5 1.5 0.1 0.1 0.1 0.2 Unit 1 1 0.15 2 Bits LSB LSB mV mV % of FSR % of FSR % of FSR % of FSR V/C ppm mV/V V 3 2 V/mA V 0.4 +0.1 +0.01 0.02 0.01 0 0 Capacitive Load Stability Resistive Load 5 Load Regulation Max 10 Offset Error Drift4 Gain Temperature Coefficient4 DC Power Supply Rejection Ratio4 DC Crosstalk4 OUTPUT CHARACTERISTICS 4 Output Voltage Range Typ VREF 2 x VREF 2 10 1 80 80 40 25 2.5 2.4975 2 0.04 12 240 20 40 5 100 125 25 V V nF nF k V/mA V/mA mA s 2.5025 5 2 0.3 x VLOGIC 0.7 x VLOGIC 2 Rev. C | Page 3 of 24 Test Conditions/Comments 1, 2 Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register External reference, gain = 2, TSSOP Internal reference, gain = 1, TSSOP Of FSR/C DAC code = midscale; VDD = 5 V 10% Due to single channel, full-scale output change Due to load current change Due to power-down (per channel) Gain = 1 Gain = 2 (see Figure 25) RL = RL = 1 k DAC code = midscale 5 V 10%; -30 mA IOUT +30 mA 3 V 10%; -20 mA IOUT +20 mA See Figure 25 Coming out of power-down mode; VDD = 5 V V ppm/C V p-p nV/Hz V/mA V/mA mA V/V ppm ppm At TA See the Terminology section A V V pF Per pin 0.1 Hz to 10 Hz At TA, f = 10 kHz, CL = 10 nF At TA At TA VDD 3 V At TA First cycle Additional cycles AD5316R Parameter LOGIC OUTPUTS (SDA)4 Output Low Voltage, VOL Floating State Output Capacitance POWER REQUIREMENTS VLOGIC ILOGIC VDD Data Sheet Min Typ Max Unit Test Conditions/Comments 1, 2 0.4 V pF ISINK = 3 mA 5.5 3 5.5 5.5 V A V V 0.7 1.3 4 6 mA mA A A 4 1.8 2.7 VREF + 1.5 IDD Normal Mode 10 0.59 1.1 1 All Power-Down Modes 11 Gain = 1 Gain = 2 VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V Internal reference off Internal reference on, at full scale -40C to +85C -40C to +105C Temperature range is -40C to +105C. The AD5316R and the AD5316 are not pin-to-pin or software compatible. 3 DC specifications are tested with the outputs unloaded, unless otherwise noted. Upper dead band (10 mV) exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD with gain = 2. Linearity calculated using a reduced code range of 4 to 1020. 4 Guaranteed by design and characterization; not production tested. 5 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to 30 mA up to a junction temperature of 110C. 6 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded during current limit. Operation above the specified maximum junction temperature may impair device reliability. 7 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 x 1 mA = 25 mV (see Figure 25). 8 Initial accuracy presolder reflow is 750 V; output voltage includes the effects of preconditioning drift. See the Solder Heat Reflow section. 9 Reference is trimmed and tested at two temperatures and is characterized from -40C to +105C. Reference temperature coefficient is calculated as per the box method. See the Terminology section for more information. 10 Interface inactive. All DACs active. DAC outputs unloaded. 11 All DACs powered down. 1 2 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.62 V VLOGIC 5.5 V; RL = 2 k; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1, 2 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Total Harmonic Distortion 4 Output Noise Spectral Density Output Noise Min Typ 5 0.8 0.5 0.13 0.1 0.2 0.3 -80 300 Max 7 6 Unit s V/s nV-sec nV-sec nV-sec nV-sec nV-sec dB nV/Hz V p-p Guaranteed by design and characterization; not production tested. See the Terminology section. 3 Temperature range is -40C to +105C; typical at 25C. 4 Digitally generated sine wave at 1 kHz. 1 2 Rev. C | Page 4 of 24 Test Conditions/Comments 3 1/4 to 3/4 scale settling to 1 LSB 1 LSB change around major carry transition At TA, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz DAC code = midscale, 10 kHz, gain = 2, internal reference enabled 0.1 Hz to 10 Hz Data Sheet AD5316R TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; 1.62 V VLOGIC 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter 1, 2 t1 t2 t3 t4 t5 t6 3 t7 t8 t9 t10 4 t114, 5 t12 t13 tSP 6 C B5 Min 2.5 0.6 1.3 0.6 100 0 0.6 0.6 1.3 0 20 + 0.1CB 20 400 0 Max Unit s s s s ns s s s s ns ns ns ns ns pF 0.9 300 300 50 400 Description SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD,STA, start/repeated start hold time tSU,DAT, data setup time tHD,DAT, data hold time tSU,STA, repeated start setup time tSU,STO, stop condition setup time tBUF, bus free time between a stop condition and a start condition tR, rise time of SCL and SDA when receiving tF, fall time of SCL and SDA when transmitting/receiving LDAC pulse width SCL rising edge to LDAC rising edge Pulse width of suppressed spike Capacitive load for each bus line See Figure 2. Guaranteed by design and characterization; not production tested. A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the SCL falling edge. 4 tR and tF are measured from 0.3 x VDD to 0.7 x VDD. 5 CB is the total capacitance of one bus line in pF. 6 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns. 1 2 3 Timing Diagram START CONDITION REPEATED START CONDITION STOP CONDITION SDA t9 t10 t11 t4 t3 SCL t4 t2 t6 t1 t5 t7 t8 t12 t13 LDAC1 t12 LDAC2 10819-002 NOTES 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. Figure 2. 2-Wire Serial Interface Timing Diagram Rev. C | Page 5 of 24 AD5316R Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. THERMAL RESISTANCE Table 5. JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. This value was measured using a JEDEC standard 4-layer board with zero airflow. For the LFCSP package, the exposed pad must be tied to GND. Parameter VDD to GND VLOGIC to GND VOUT to GND VREF to GND Digital Input Voltage to GND1 SDA and SCL to GND Operating Temperature Range Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb Free (J-STD-020) 1 Rating -0.3 V to +7 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VLOGIC + 0.3 V -0.3 V to +7 V -40C to +105C -65C to +150C 125C 260C Table 6. Thermal Resistance Package Type 16-Lead LFCSP 16-Lead TSSOP ESD CAUTION Excluding SDA and SCL. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 6 of 24 JA 70 112.6 Unit C/W C/W Data Sheet AD5316R PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUTA 1 12 A1 GND 2 11 SCL GAIN 8 LDAC 7 SDA 6 VOUTD 5 RSTSEL 15 RESET VOUTA 3 14 A1 13 SCL 12 A0 VOUTC 6 11 VLOGIC VOUTD 7 10 GAIN SDA 8 9 LDAC VDD 5 9 VLOGIC VOUTC 4 16 GND 4 10 A0 VDD 3 VREF 1 VOUTB 2 AD5316R TOP VIEW (Not to Scale) 10819-007 13 RESET 14 RSTSEL 16 VOUTB 15 VREF AD5316R NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. 10819-006 TOP VIEW (Not to Scale) Figure 4. 16-Lead TSSOP Pin Configuration Figure 3. 16-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions LFCSP 1 2 3 Pin No. TSSOP 3 4 5 Mnemonic VOUTA GND VDD 4 5 6 6 7 8 VOUTC VOUTD SDA 7 9 LDAC 8 10 GAIN 9 10 11 11 12 13 VLOGIC A0 SCL 12 13 14 15 A1 RESET 14 16 RSTSEL 15 1 VREF 16 17 2 N/A VOUTB EPAD Description Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Power Supply Input. The part can be operated from 2.7 V to 5.5 V. The supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. LDAC can be operated in two modes, asynchronous update mode and synchronous update mode. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data; all DAC outputs are simultaneously updated. This pin can also be tied permanently low. Gain Select Pin. When this pin is tied to GND, all four DAC outputs have a span of 0 V to VREF. When this pin is tied to VLOGIC, all four DAC outputs have a span of 0 V to 2 x VREF. Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Address Input. Sets the first LSB of the 7-bit slave address. Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 24-bit input shift register. Address Input. Sets the second LSB of the 7-bit slave address. Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is activated (low), the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. When RESET is low, all LDAC pulses are ignored. If the pin is not used, tie it permanently to VLOGIC. If the pin is forced low at power-up, the POR circuit does not initialize correctly until the pin is released. Power-On Reset Pin. When this pin is tied to GND, all four DACs are powered up to zero scale. When this pin is tied to VLOGIC, all four DACs are powered up to midscale. Reference Voltage. The AD5316R has an internal reference. When the internal reference is used, VREF is the reference output pin. When an external reference is used, VREF is the reference input pin. By default, the internal reference is used, and this pin is a reference output. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Exposed Pad. The exposed pad must be tied to GND. Rev. C | Page 7 of 24 AD5316R Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.5020 VDD = 5V DEVICE 1 DEVICE 2 DEVICE 3 DEVICE 4 DEVICE 5 2.5015 2.5010 VDD = 5V TA = 25C VREF (V) 2.5005 2.5000 1 2.4995 2.4990 -20 0 20 40 60 80 100 120 TEMPERATURE (C) CH1 2V 10819-112 2.4980 -40 10819-212 2.4985 M1.0s Figure 8. Internal Reference Noise, 0.1 Hz to 10 Hz Figure 5. Internal Reference Voltage vs. Temperature 2.5000 90 VDD = 5V TA = 25C VDD = 5V 80 2.4999 70 VREF (V) NUMBER OF UNITS 2.4998 60 50 40 2.4997 2.4996 30 2.4995 20 2.4994 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TEMPERATURE DRIFT (ppm/C) 2.4993 -0.005 10819-250 0 -0.001 0.001 0.003 0.005 ILOAD (A) Figure 6. Reference Output Temperature Drift Histogram 1600 -0.003 10819-113 10 Figure 9. Internal Reference Voltage vs. Load Current 2.5002 VDD = 5V TA = 25C TA = 25C DEVICE 1 1400 2.5000 2.4998 VREF (V) 1000 800 DEVICE 3 2.4996 600 2.4994 400 2.4992 200 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 7. Internal Reference Noise Spectral Density vs. Frequency 2.4990 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) Figure 10. Internal Reference Voltage vs. Supply Voltage Rev. C | Page 8 of 24 10819-117 0 10 DEVICE 2 10819-111 NSD (nV/ Hz) 1200 Data Sheet AD5316R 0.15 0.5 0.12 0.09 0.3 ERROR (LSB) INL (LSB) 0.06 0.1 -0.1 0.03 INL 0 DNL -0.03 -0.06 -0.09 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V 0 156 312 468 624 780 936 CODE -0.15 10819-118 -0.5 VDD = 5V TA = 25C -0.12 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VREF (V) Figure 11. INL 10819-125 -0.3 Figure 14. INL Error and DNL Error vs. VREF 0.5 0.15 0.12 0.3 0.09 ERROR (LSB) DNL (LSB) 0.06 0.1 -0.1 0.03 INL 0 DNL -0.03 -0.06 -0.3 156 312 468 624 780 936 CODE 0.12 0.08 0.09 0.06 0.06 0.04 ERROR (% of FSR) 0.10 INL 0 DNL -0.03 -0.06 0.02 0 FULL-SCALE ERROR GAIN ERROR -0.02 -0.04 -0.09 -0.06 -0.12 -0.08 VDD = 5V INTERNAL REFERENCE = 2.5V -0.10 -20 0 20 40 -40 60 110 TEMPERATURE (C) 10819-124 ERROR (LSB) 0.15 VDD = 5V INTERNAL REFERENCE = 2.5V -0.15 -40 10 5.2 Figure 15. INL Error and DNL Error vs. Supply Voltage Figure 12. DNL 0.03 4.7 SUPPLY VOLTAGE (V) 60 80 100 120 TEMPERATURE (C) Figure 16. Gain Error and Full-Scale Error vs. Temperature Figure 13. INL Error and DNL Error vs. Temperature Rev. C | Page 9 of 24 10819-127 0 -0.12 TA = 25C INTERNAL REFERENCE = 2.5V -0.15 2.7 3.2 3.7 4.2 10819-119 -0.5 10819-126 -0.09 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V AD5316R Data Sheet 0.10 1.2 0.8 0.6 ZERO-CODE ERROR 0.2 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 0.06 0.05 0.04 0.03 0.02 0.01 0 -40 10819-128 OFFSET ERROR 0 -40 0.07 0.08 0.08 TOTAL UNADJUSTED ERROR (% of FSR) 0.10 ERROR (% of FSR) 0.06 0.04 0.02 GAIN ERROR 0 FULL-SCALE ERROR -0.04 4.7 5.2 10819-129 -0.06 SUPPLY VOLTAGE (V) 40 60 80 100 120 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 TA = 25C INTERNAL REFERENCE = 2.5V -0.10 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) Figure 18. Gain Error and Full-Scale Error vs. Supply Voltage Figure 21. TUE vs. Supply Voltage, Gain = 1 1.5 TOTAL UNADJUSTED ERROR (% of FSR) 0 1.0 0.5 ZERO-CODE ERROR 0 OFFSET ERROR -0.5 -1.0 TA = 25C INTERNAL REFERENCE = 2.5V -1.5 2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) 10819-130 ERROR (mV) 20 Figure 20. TUE vs. Temperature 0.10 -0.08 TA = 25C INTERNAL REFERENCE = 2.5V -0.10 2.7 3.2 3.7 4.2 0 TEMPERATURE (C) Figure 17. Zero-Code Error and Offset Error vs. Temperature -0.02 -20 10819-132 0.4 0.08 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 -0.08 VDD = 5V -0.09 T = 25C A INTERNAL REFERENCE = 2.5V -0.10 0 156 312 468 Figure 19. Zero-Code Error and Offset Error vs. Supply Voltage 624 CODE Figure 22. TUE vs. Code Rev. C | Page 10 of 24 780 936 1023 10819-133 ERROR (mV) 1.0 VDD = 5V 0.09 INTERNAL REFERENCE = 2.5V 10819-131 TOTAL UNADJUSTED ERROR (% of FSR) VDD = 5V 1.4 INTERNAL REFERENCE = 2.5V Data Sheet AD5316R 7 VDD = 5V TA = 25C EXTERNAL REFERENCE = 2.5V 25 VDD = 5V 6 TA = 25C INTERNAL REFERENCE = 2.5V 5 GAIN = 2 20 0xFFFF 15 VOUT (V) HITS 4 10 0xC000 3 0x8000 2 0x4000 1 0x0000 0 5 560 580 600 620 640 IDD (mA) -2 -0.06 10819-135 540 -0.04 -0.02 0.02 0.04 0.06 Figure 26. Source and Sink Capability at 5 V Figure 23. IDD Histogram with External Reference, 5 V 5 VDD = 5V 30 T = 25C A INTERNAL REFERENCE = 2.5V 25 VDD = 3V TA = 25C 4 GAIN = 1 EXTERNAL REFERENCE = 2.5V 3 0xFFFF 20 0xC000 VOUT (V) 15 2 0x8000 0x4000 1 10 0x0000 0 5 -1 1000 1020 1040 1060 1080 1100 1120 1140 IDD FULL SCALE (mA) -2 -0.06 10819-136 0 -0.04 -0.02 0 0.02 0.04 0.06 LOAD CURRENT (A) Figure 24. IDD Histogram with Internal Reference, VREF = 2.5 V, Gain = 2 10819-139 HITS 0 LOAD CURRENT (A) 10819-138 -1 0 Figure 27. Source and Sink Capability at 3 V 1.0 1.4 0.8 1.2 0.6 0.4 CURRENT (mA) SINKING, 5V 0 -0.2 SOURCING, 5V -0.4 5 10 15 0.8 0.6 EXTERNAL REFERENCE, FULL-SCALE 20 25 LOAD CURRENT (mA) 30 0 -40 10 60 TEMPERATURE (C) Figure 28. Supply Current vs. Temperature Figure 25. Headroom/Footroom vs. Load Current Rev. C | Page 11 of 24 110 10819-140 -1.0 0 ZERO CODE 0.2 SOURCING, 2.7V -0.8 1.0 0.4 -0.6 10819-200 VOUT (V) SINKING, 2.7V 0.2 FULL-SCALE AD5316R Data Sheet 4.0 3.5 2.5008 VOUTA VOUTB VOUTC VOUTD 3.0 2.5003 VOUT (V) VOUT (V) 2.5 2.0 2.4998 1.5 CHANNEL B TA = 25C VDD = 5.25V INTERNAL REFERENCE = 2.5V CODE = 0x7FFF TO 0x8000 ENERGY = 0.227206nV-sec 2.4993 80 160 2.4988 10819-141 320 TIME (s) 0 6 8 10 6 VOUTA VOUTB VOUTC VOUTD VDD 0.003 VOUTB VOUTC VOUTD 5 0.03 3 0.02 2 0.01 1 0 0 0.001 0 -0.001 10819-142 -1 15 10 5 VDD (V) 4 VOUT AC-COUPLED (V) 0.002 0.04 TA = 25C INTERNAL REFERENCE = 2.5V -0.01 -10 0 -5 12 Figure 32. Digital-to-Analog Glitch Impulse 0.06 TIME (s) -0.002 0 5 15 10 20 25 TIME (s) Figure 30. Power-On Reset to 0 V Figure 33. Analog Crosstalk, VOUTA 3 VOUTA VOUTB VOUTC VOUTD T GAIN = 2 2 VOUT (V) GAIN = 1 1 0 -5 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V 0 5 TIME (s) Figure 31. Exiting Power-Down to Midscale 10 VDD = 5V TA = 25C EXTERNAL REFERENCE = 2.5V CH1 2V M1.0s A CH1 802mV 10819-146 1 10819-143 VOUT (V) 4 TIME (s) Figure 29. Settling Time 0.05 2 10819-145 VDD = 5V 0.5 TA = 25C INTERNAL REFERENCE = 2.5V 1/4 TO 3/4 SCALE 0 10 20 40 10819-144 1.0 Figure 34. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V External Reference Rev. C | Page 12 of 24 Data Sheet AD5316R 20 T VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V 0 -20 THD (dBV) -40 1 -60 -80 -100 -120 -140 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V A CH1 802mV 0 FREQUENCY (Hz) Figure 35. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference Figure 37. Total Harmonic Distortion at 1 kHz 1600 VDD = 5V TA = 25C 1400 INTERNAL REFERENCE = 2.5V 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 10819-149 M1.0s -180 10819-147 CH1 2V -160 4.0 FULL-SCALE MIDSCALE ZERO-SCALE 3.9 3.8 1200 0nF 0.1nF 0.22nF 4.7nF 10nF VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V VOUT (V) 800 600 3.6 3.5 3.4 3.3 400 3.2 200 100 1k 10k FREQUENCY (Hz) 100k 1M Figure 36. Noise Spectral Density 3.0 1.590 1.595 1.600 1.605 1.610 1.615 1.620 1.625 TIME (ms) Figure 38. Settling Time vs. Capacitive Load Rev. C | Page 13 of 24 1.630 10819-150 3.1 0 10 10819-148 NSD (nV/ Hz) 3.7 1000 AD5316R Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Figure 11 shows a typical INL vs. code plot. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. The AD5316R is guaranteed monotonic by design. Figure 12 shows a typical DNL vs. code plot. Zero-Code Error Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5316R because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. Figure 17 shows a plot of zero-code error vs. temperature. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD - 1 LSB. Full-scale error is expressed as a percentage of the full-scale range (% of FSR). Figure 16 shows a plot of full-scale error vs. temperature. Gain Error Gain error is a measurement of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed in % of FSR. Gain Temperature Coefficient Gain temperature coefficient is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/C. Offset Error Offset error is a measurement of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. It can be negative or positive. Offset Error Drift Offset error drift is a measurement of the change in offset error with changes in temperature. It is expressed in V/C. DC Power Supply Rejection Ratio (PSRR) DC PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for midscale output of the DAC. It is measured in mV/V. VREF is held at 2.5 V, and VDD is varied by 10%. Output Voltage Settling Time The output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 32). Digital Feedthrough Digital feedthrough is a measurement of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Noise Spectral Density (NSD) Noise spectral density is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/Hz) and is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/Hz. Figure 36 shows a plot of noise spectral density. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in V. DC crosstalk due to load current change is a measurement of the impact that a change in load current on one DAC has on another DAC kept at midscale. It is expressed in V/mA. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is expressed in nV-sec. Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC in response to a change in the output of another DAC. To measure analog crosstalk, load one of the input registers with a full-scale code change (all 0s to all 1s and vice versa), and then execute a software LDAC and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-sec. Rev. C | Page 14 of 24 Data Sheet AD5316R DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC in response to a digital code change and subsequent analog output change of another DAC. It is measured by loading one channel with a full-scale code change (all 0s to all 1s and vice versa) using the write to and update commands while monitoring the output of another channel that is at midscale. The energy of the glitch is expressed in nV-sec. Total Harmonic Distortion (THD) THD is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC; THD is a measurement of the harmonics present on the DAC output. It is measured in dB. Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measurement of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/C, as follows: VREFmax - VREFmin 6 TC = x 10 VREFnom x TempRange where: VREFmax is the maximum reference output measured over the total temperature range. VREFmin is the minimum reference output measured over the total temperature range. VREFnom is the nominal reference output voltage, 2.5 V. TempRange is the specified temperature range of -40C to +105C. Rev. C | Page 15 of 24 AD5316R Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER The AD5316R is a quad, 10-bit, serial input, voltage output DAC with an internal reference. The part operates from supply voltages of 2.7 V to 5.5 V. Data is written to the AD5316R in a 24-bit word format via a 2-wire serial interface. The AD5316R incorporates a power-on reset circuit to ensure that the DAC output powers up to a known output state. The device also has a software power-down mode that reduces the typical current consumption to 1 A. The resistor string structure is shown in Figure 40. Each resistor in the string has a value R. The code loaded to the DAC register determines the node on the string from which the voltage is tapped off and fed into the output amplifier. The voltage is tapped off by closing one of the switches that connect the string to the amplifier. Because the AD5316R is a string of resistors, it is guaranteed monotonic. VREF R TRANSFER FUNCTION The internal reference is on by default. Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by R R TO OUTPUT AMPLIFIER D VOUT = VREF x Gain N 2 DAC ARCHITECTURE The DAC architecture consists of a string DAC followed by an output amplifier. Figure 39 shows a block diagram of the DAC architecture. VREF 2.5V REF RESISTOR STRING REF (-) GND VOUTX GAIN (GAIN = 1 OR 2) Figure 39. Single DAC Channel Architecture Block Diagram 10819-052 DAC REGISTER R Figure 40. Resistor String Structure Internal Reference The AD5316R on-chip reference is on at power-up but can be disabled via a write to a control register. For more information, see the Internal Reference Setup section. The 2.5 V, 2 ppm/C internal reference provides a full-scale output of 2.5 V or 5 V, depending on the state of the GAIN pin. The internal reference is available at the VREF pin. This buffered reference is capable of driving external loads of up to 10 mA. Output Amplifiers REF (+) INPUT REGISTER R 10819-053 where: VREF is the value of the external reference. Gain is the gain of the output amplifier and is set to 1 by default. The gain can be set to 1 or 2 using the gain select pin. When the GAIN pin is tied to GND, all four DAC outputs have a span of 0 V to VREF. When this pin is tied to VDD, all four DAC outputs have a span of 0 V to 2 x VREF. D is the decimal equivalent of the binary code that is loaded to the DAC register (0 to 1023). N is the DAC resolution (10 bits). The output buffer amplifier can generate rail-to-rail voltages on its output for an output range of 0 V to VDD. The actual range depends on the value of VREF, the GAIN pin, the offset error, and the gain error. The GAIN pin selects the gain of the output. * * When this pin is tied to GND, all four outputs have a gain of 1, and the output range is from 0 V to VREF. When this pin is tied to VDD, all four outputs have a gain of 2, and the output range is from 0 V to 2 x VREF. The output amplifiers are capable of driving a load of 1 k in parallel with 2 nF to GND. The slew rate is 0.8 V/s with a 1/4 to 3/4 scale settling time of 5 s. Rev. C | Page 16 of 24 Data Sheet AD5316R Table 9. Address Bits and Selected DACs SERIAL INTERFACE The AD5316R has a 2-wire, I2C-compatible serial interface (see the I2C-Bus Specification, Version 2.1, January 2000, available from Philips Semiconductor). See Figure 2 for a timing diagram of a typical write sequence. The AD5316R can be connected to an I2C bus as a slave device, under the control of a master device. The AD5316R supports standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10-bit addressing or general call addressing. DAC D 0 0 0 0 0 0 0 1 1 ... 1 Input Shift Register The input shift register of the AD5316R is 24 bits wide. Data is loaded into the device, MSB first, as a 24-bit word under the control of the serial clock input, SCL. The input shift register consists of an 8-bit command byte and a 16-bit data-word (see Figure 41). The first eight MSBs make up the command byte. 0 1 0 0 0 0 0 0 1 0 1 1 1 1 X1 1 0 0 1 1 X1 1 0 1 0 1 X1 1 Any combination of DAC channels can be selected using the address bits. Commands can be executed on one DAC channel, any two or three DAC channels, or on all four DAC channels, depending on the address bits selected (see Table 9). Table 8. Command Definitions 0 Selected DAC Channels1 DAC A DAC B DAC A and DAC B DAC C DAC A and DAC C DAC B and DAC C DAC A, DAC B, and DAC C DAC D DAC A and DAC D ... All DACs The 8-bit command byte is followed by two data bytes, which contain the data-word. The data-word comprises the 10-bit input code, followed by six don't care bits (see Figure 41). The data bits are transferred to the input register on the 24 falling edges of SCL. The first four bits of the command byte are the command bits (C3, C2, C1, and C0), which control the mode of operation of the device (see Table 8). The last four bits of the command byte are the address bits (DAC D, DAC C, DAC B, and DAC A), which select the DAC that is operated on by the command (see Table 9). Command Bits C3 C2 C1 C0 0 0 0 0 0 0 0 1 DAC A 1 0 1 0 1 0 1 0 1 ... 1 WRITE AND UPDATE COMMANDS Command No operation Write to Input Register n (dependent on LDAC) Update DAC Register n with contents of Input Register n Write to and update DAC Channel n Power down/power up DAC Hardware LDAC mask register Software reset (power-on reset) Internal reference setup register Reserved For more information about the LDAC function, see the Load DAC (Hardware LDAC Pin) section. Write to Input Register n (Dependent on LDAC) Command 0001 allows the user to write to each DAC's dedicated input register individually. When LDAC is low, the input register is transparent (if not controlled by the LDAC mask register). Update DAC Register n with Contents of Input Register n Command 0010 loads the DAC registers/outputs with the contents of the input registers selected by the address bits (see Table 9) and updates the DAC outputs directly. X = don't care. Write to and Update DAC Channel n (Independent of LDAC) Command 0011 allows the user to write to the DAC registers and update the DAC outputs directly, independent of the state of the LDAC pin. DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 C3 C2 C1 COMMAND C0 DAC D DAC C DAC B DAC A DAC ADDRESS COMMAND BYTE D9 D8 D7 D6 D5 D4 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D3 D2 D1 D0 X X X X X X DAC DATA DAC DATA DATA HIGH BYTE DATA LOW BYTE Figure 41. Input Shift Register Contents Rev. C | Page 17 of 24 10819-300 1 Address Bits DAC C DAC B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 ... ... 1 1 AD5316R Data Sheet I2C SLAVE ADDRESS 3. The AD5316R has a 7-bit I2C slave address. The five MSBs are 00011 and the two LSBs (A1 and A0) are set by the state of the A1 and A0 address pins. The ability to make hardwired changes to A1 and A0 allows the user to incorporate up to four AD5316R devices on one bus (see Table 10). 4. Table 10. Device Address Selection A1 Pin Connection GND GND VLOGIC VLOGIC A0 Pin Connection GND VLOGIC GND VLOGIC A1 Bit 0 0 1 1 A0 Bit 0 1 0 1 WRITE OPERATION SERIAL OPERATION When writing to the AD5316R, the user must begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The AD5316R requires two bytes of data for the DAC and a command byte that controls various DAC functions. Three bytes of data must, therefore, be written to the DAC with the command byte followed by the most significant data byte and the least significant data byte, as shown in Figure 42. All these data bytes are acknowledged by the AD5316R. A stop condition follows. The 2-wire I C serial bus protocol operates as follows: 2 2. The master initiates a data transfer by establishing a start condition when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address. The slave device with the transmitted address responds by pulling SDA low during the 9th clock pulse (this is called the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its input shift register. 1 1 9 9 SCL 0 SDA 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 ACK BY AD5316R START BY MASTER DB16 ACK BY AD5316R FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 1 9 SCL (CONTINUED) SDA (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 FRAME 3 MOST SIGNIFICANT DATA BYTE DB9 DB8 DB7 DB6 ACK BY AD5316R Figure 42. I2C Write Operation Rev. C | Page 18 of 24 DB5 DB4 DB3 DB2 FRAME 4 LEAST SIGNIFICANT DATA BYTE DB1 DB0 ACK BY STOP BY AD5316R MASTER 10819-303 1. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). Transitions on the SDA line must occur during the low period of SCL; SDA must remain stable during the high period of SCL. After all data bits are read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the 9th clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse and then high again during the 10th clock pulse to establish a stop condition. Data Sheet AD5316R READ OPERATION MULTIPLE DAC READBACK SEQUENCE When reading data back from the AD5316R, the user must begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte must be followed by the command byte, which determines both the read command that is to follow and the pointer address to read from; the command byte is also acknowledged by the DAC. The user configures the channel to read back the contents of one or more DAC registers and sets the readback command to active using the command byte. When reading data back from multiple AD5316R DACs, the user begins with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte must be followed by the command byte, which is also acknowledged by the DAC. The user selects the first channel to read back using the command byte. Following this, the master establishes a repeated start condition, and the address is resent with R/W = 1. This byte is acknowledged by the DAC, indicating that it is prepared to transmit data. The first two bytes of data are then read from DAC Input Register n (selected using the command byte), most significant byte first, as shown in Figure 43. The next two bytes read back are the contents of DAC Input Register n + 1, and the next bytes read back are the contents of DAC Input Register n + 2. Data is read from the DAC input registers in this auto-incremented fashion until a NACK followed by a stop condition follows. If the contents of DAC Input Register D are read out, the next two bytes of data that are read are the contents of DAC Input Register A. Following this, the master establishes a repeated start condition, and the address is resent with R/W = 1. This byte is acknowledged by the DAC, indicating that it is prepared to transmit data. Two bytes of data are then read from the DAC, as shown in Figure 43. A NACK condition from the master, followed by a stop condition, completes the read sequence. If more than one DAC is selected, Channel A is read back by default. 1 9 1 9 SCL 0 SDA 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 ACK BY AD5316R START BY MASTER DB16 ACK BY AD5316R FRAME 2 COMMAND BYTE FRAME 1 SLAVE ADDRESS 1 9 1 9 SCL 0 SDA 0 0 REPEATED START BY MASTER 1 1 A1 A0 R/W DB15 DB14 DB13 ACK BY AD5316R FRAME 3 SLAVE ADDRESS 1 DB12 DB11 DB10 DB9 DB8 ACK BY MASTER FRAME 4 MOST SIGNIFICANT DATA BYTE n 9 9 1 SCL (CONTINUED) DB7 DB6 DB5 DB4 DB3 DB2 FRAME 5 LEAST SIGNIFICANT DATA BYTE n DB1 DB0 DB15 DB14 DB13 DB12 ACK BY MASTER Figure 43. I2C Read Operation Rev. C | Page 19 of 24 DB11 DB10 FRAME 6 MOST SIGNIFICANT DATA BYTE n + 1 DB9 DB8 NACK BY MASTER STOP BY MASTER 10819-304 SDA (CONTINUED) AD5316R Data Sheet POWER-DOWN OPERATION Table 11. Modes of Operation PDx1 0 PDx0 0 0 1 1 1 0 1 AMPLIFIER POWER-DOWN CIRCUITRY VOUTX RESISTOR NETWORK Figure 44. Output Stage During Power-Down The bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when power-down mode is activated. However, the contents of the DAC registers are unaffected in power-down mode, and the DAC registers can be updated while the device is in power-down mode. The time required to exit power-down is typically 2.5 s for VDD = 5 V. Any or all DACs (DAC A to DAC D) can be powered down to the selected mode by setting the corresponding bits in the input shift register. See Table 12 for the contents of the input shift register during the power-down/power-up operation. When both Bit PDx1 and Bit PDx0 (where x is the DAC selected) in the input shift register are set to 0, the part works normally with its normal power consumption of 1.1 mA at 5 V. When Bit PDx1, Bit PDx0, or both Bit PDx1 and Bit PDx0 are set to 1, the part is in power-down mode. In power-down mode, the supply current falls to 4 A at 5 V. To reduce the current consumption further, the on-chip reference can be powered off (see the Internal Reference Setup section). LOAD DAC (HARDWARE LDAC PIN) The AD5316R DAC has double buffered interfaces consisting of two banks of registers: input registers and DAC registers. The user can write to any combination of the input registers (see Table 9). Updates to the DAC registers are controlled by the LDAC pin. OUTPUT AMPLIFIER In power-down mode, the output stage is internally switched from the output of the amplifier to a resistor network of known values. In this way, the output impedance of the part is known when the part is in power-down mode. VREF 10-BIT DAC LDAC DAC REGISTER VOUTX INPUT REGISTER Table 11 lists the three power-down options. The output is connected internally to GND through either a 1 k or a 100 k resistor, or it is left open-circuited (three-state). The output stage is illustrated in Figure 44. SCL SDA INPUT SHIFT REGISTER 10819-059 Operating Mode Normal Operation Power-Down Modes 1 k to GND 100 k to GND Three-State DAC 10819-058 Command 0100 is designated for the power-down function. The AD5316R provides three separate power-down modes (see Table 11). These power-down modes are software programmable by setting Bit DB7 to Bit DB0 in the input shift register (see Table 12). Two bits are associated with each DAC channel. Table 11 shows how the state of these two bits corresponds to the mode of operation of the device. Figure 45. Simplified Diagram of Input Loading Circuitry for a Single DAC Table 12. 24-Bit Input Shift Register Contents for Power-Down/Power-Up Operation 1 DB23 (MSB) DB22 DB21 DB20 0 1 0 0 Command bits (C3 to C0) 1 DB19 to DB16 X Address bits (don't care) DB15 to DB8 X Don't care DB7 DB6 PDD1 PDD0 Power-down select, DAC D X = don't care. Rev. C | Page 20 of 24 DB5 DB4 PDC1 PDC0 Power-down select, DAC C DB3 DB2 PDB1 PDB0 Power-down select, DAC B DB0 DB1 (LSB) PDA1 PDA0 Power-down select, DAC A Data Sheet AD5316R Table 13. LDAC Overwrite Definition Instantaneous DAC Updating (LDAC Held Low) Load LDAC Register For instantaneous updating of the DACs, LDAC is held low while data is clocked into the input register using Command 0001. Both the addressed input register and the DAC register are updated on the 24th clock, and the output begins to change (see Table 14). LDAC Bit (DB3 to DB0) 0 1 Deferred DAC Updating (LDAC Pulsed Low) For deferred updating of the DACs, LDAC is held high while data is clocked into the input register using Command 0001. All DAC outputs are asynchronously updated by pulling LDAC low after the 24th clock. The update occurs on the falling edge of LDAC. 1 LDAC Pin LDAC Operation 1 or 0 X1 Determined by the LDAC pin. DAC channels are updated. (DAC channels see LDAC pin as 1.) X = don't care. HARDWARE RESET PIN (RESET) RESET is an active low reset that allows the outputs to be cleared to either zero scale or midscale. The clear code value is user selectable via the reset select pin (RSTSEL). It is necessary to keep RESET low for a minimum of 30 ns to complete the operation. LDAC MASK REGISTER Command 0101 is reserved for the software LDAC function. When this command is executed, the address bits are ignored. When writing to the DAC using Command 0101, the 4-bit LDAC mask register (DB3 to DB0) is loaded. Bit DB3 of the LDAC mask register corresponds to DAC D; Bit DB2 corresponds to DAC C; Bit DB1 corresponds to DAC B; and Bit DB0 corresponds to DAC A. When the RESET signal is returned high, the output remains at the cleared value until a new value is programmed. The outputs cannot be updated with a new value while the RESET pin is low. There is also a software executable reset function that resets the DAC to the power-on reset code. Command 0110 is designated for this software reset function (see Table 8). Any events on LDAC during a power-on reset are ignored. If the RESET pin is pulled low at power-up, the device does not initialize correctly until the pin is released. The default value of these bits is 0; that is, the LDAC pin works normally. Setting any of these bits to 1 forces the selected DAC channel to ignore transitions on the LDAC pin, regardless of the state of the hardware LDAC pin. This flexibility is useful in applications where the user wishes to select which channels respond to the LDAC pin. RESET SELECT PIN (RSTSEL) The AD5316R contains a power-on reset circuit that controls the output voltage during power-up. When the RSTSEL pin is tied to GND, the outputs power up to zero scale (note that this is outside the linear region of the DAC). When the RSTSEL pin is tied to VDD, the outputs power up to midscale. The outputs remain powered up at the level set by the RSTSEL pin until a valid write sequence is made to the DAC. The LDAC mask register allows the user extra flexibility and control over the hardware LDAC pin (see Table 13). Setting the LDAC bit (DB3 to DB0) to 0 for a DAC channel allows the hard-ware LDAC pin to control the updating of that channel. Table 14. Write Commands and LDAC Pin Truth Table 1 Command 0001 Description Write to Input Register n (dependent on LDAC) 0010 Update DAC Register n with contents of Input Register n 0011 Write to and update DAC Channel n Hardware LDAC Pin State VLOGIC GND 2 VLOGIC Input Register Contents Data update Data update No change GND No change VLOGIC GND Data update Data update DAC Register Contents No change (no update) Data update Updated with input register contents Updated with input register contents Data update Data update A high to low transition on the hardware LDAC pin always updates the contents of the DAC register with the contents of the input register on channels that are not masked (blocked) by the LDAC mask register. 2 When the LDAC pin is permanently tied low, the LDAC mask bits are ignored. 1 Rev. C | Page 21 of 24 AD5316R Data Sheet INTERNAL REFERENCE SETUP LONG-TERM TEMPERATURE DRIFT By default, the internal reference is on at power-up. To reduce the supply current, the on-chip reference can be turned off. Command 0111 is reserved for setting up the internal reference. To turn off the internal reference, set the software programmable bit, DB0, in the input shift register using Command 0111, as shown in Table 16. Table 15 shows how the state of the DB0 bit corresponds to the mode of operation. Figure 47 shows the change in the VREF (ppm) value after 1000 hours at 25C ambient temperature. Action Reference on (default) Reference off SOLDER HEAT REFLOW As with all IC reference voltage circuits, the reference value experiences a shift induced by the soldering process. Analog Devices, Inc., performs a reliability test called precondition to mimic the effect of soldering a device to a board. The output voltage specification in Table 2 includes the effect of this reliability test. Figure 46 shows the effect of solder heat reflow (SHR) as measured through the reliability test (precondition). 60 POSTSOLDER HEAT REFLOW 50 PRESOLDER HEAT REFLOW 100 80 60 40 20 0 -20 0 100 200 300 400 500 600 700 800 900 1000 ELAPSED TIME (Hours) Figure 47. Reference Drift Through to 1000 Hours THERMAL HYSTERESIS Thermal hysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold, then to hot, and then back to ambient. Thermal hysteresis data is shown in Figure 48. It is measured by sweeping the temperature from ambient to -40C, then to +105C, and then back to ambient. The VREF delta is then measured between the two ambient measurements (shown in blue in Figure 48). The same temperature sweep and measurements were immediately repeated, and the results are shown in red in Figure 48. 40 HITS 120 10819-247 Internal Reference Setup Register (Bit DB0) 0 1 INTERNAL REFERENCE DRIFT (PPM) Table 15. Internal Reference Setup Register 140 9 30 8 20 FIRST TEMPERATURE SWEEP SUBSEQUENT TEMPERATURE SWEEPS 7 6 2.498 2.499 2.500 2.501 2.502 VREF (V) HITS 0 10819-060 10 5 4 3 Figure 46. SHR Reference Voltage Shift 2 0 -200 -150 -100 -50 DISTORTION (ppm) 0 50 10819-062 1 Figure 48. Thermal Hysteresis Table 16. 24-Bit Input Shift Register Contents for Internal Reference Setup Command 1 DB23 (MSB) 0 1 DB22 DB21 1 1 Command bits (C3 to C0) DB20 1 DB19 to DB16 X Address bits (don't care) X = don't care. Rev. C | Page 22 of 24 DB15 to DB1 X Don't care DB0 (LSB) 1 or 0 Reference setup register Data Sheet AD5316R APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5316R is via a serial bus that uses a standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 2-wire interface consisting of a clock signal and a data signal. AD5316R TO ADSP-BF531 INTERFACE For enhanced thermal, electrical, and board level performance, solder the exposed pad on the bottom of the LFCSP package to the corresponding thermal land paddle on the PCB. Design thermal vias into the PCB land paddle area to further improve heat dissipation. The GND plane on the device can be increased (as shown in Figure 50) to provide a natural heat sinking effect. The I2C interface of the AD5316R is designed for easy connection to industry-standard DSPs and microcontrollers. Figure 49 shows the AD5316R connected to the Analog Devices Blackfin(R) processor. The Blackfin processor has an integrated I2C port that can be connected directly to the I2C pins of the AD5316R. AD5316R BOARD ADSP-BF531 LDAC RESET Figure 50. Paddle Connection to Board GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. Figure 49. AD5316R to ADSP-BF531 Interface LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The PCB on which the AD5316R is mounted should be designed so that the AD5316R lies on the analog plane. The AD5316R should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply, located as close to the package as possible, ideally right up against the device. The 10 F capacitor is the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types; these capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. In systems where many devices are on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. The Analog Devices iCoupler(R) products provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5316R makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 51 shows a 4-channel isolated interface to the AD5316R using the ADuM1400. For more information, visit http://www.analog.com/icouplers. CONTROLLER SERIAL CLOCK IN SERIAL DATA OUT RESET OUT LOAD DAC OUT The AD5316R LFCSP models have an exposed pad beneath the device. Connect this pad to the GND supply for the part. For optimum performance, use special considerations to design the motherboard and to mount the package. Rev. C | Page 23 of 24 ADuM1400 VIA VIB VIC VID ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE Figure 51. Isolated Interface VOA VOB VOC VOD TO SCL TO SDA TO RESET TO LDAC 10819-167 PF9 PF8 SCL SDA 10819-164 GPIO1 GPIO2 10819-166 GND PLANE AD5316R AD5316R Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR 0.30 0.23 0.18 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 1.75 1.60 SQ 1.45 EXPOSED PAD 9 TOP VIEW 0.80 0.75 0.70 4 5 8 0.50 0.40 0.30 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW 08-16-2010-E 3.10 3.00 SQ 2.90 COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 52. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm x 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8 0 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 53. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model1 AD5316RBCPZ-RL7 AD5316RBRUZ AD5316RBRUZ-RL7 EVAL-AD5316RDBZ 1 Resolution 10 Bits 10 Bits 10 Bits Temperature Range -40C to +105C -40C to +105C -40C to +105C Accuracy (INL) 0.5 LSB 0.5 LSB 0.5 LSB Reference Tempco (ppm/C) 5 (max) 5 (max) 5 (max) Package Description 16-Lead LFCSP_WQ 16-Lead TSSOP 16-Lead TSSOP Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2012-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10819-0-5/17(C) Rev. C | Page 24 of 24 Package Option CP-16-22 RU-16 RU-16 Branding DJT