2005-2017 Microchip Technology Inc. DS20005051D-page 1
Features
Single Voltage Read and Write Operations
- 2.7-3.6V
Serial Interface Architect ure
- SPI Compatible: Mode 0 and Mode 3
High Speed Cloc k Frequency
- Up to 50 MHz
Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
Low Power Consumption:
- Active Read Current: 10 mA (typical)
- S t andby Current: 5 µA (typical)
Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 32 KByte overlay blocks
- Uniform 64 KByte overlay blocks
Fast Erase and Byte-Program:
- Ch ip-Era se T ime: 35 ms (typic al)
- S ector- /Bl ock-E ra se Time : 18 ms (ty pica l)
- B yte-Pro gram Time : 7 µs (ty pical )
Auto Addres s Increment (AAI) Programming
- Decrease total chip programming time over
Byt e-Progr am oper atio ns
•End-of-Write Detection
- Software polling the BUSY bit in S t atus Register
- B usy St at us r ead out on S O p in i n AAI Mo de
Hold Pin (HOLD#)
- Suspends a serial sequence to the memory
without deselecting the device
Write Protection (WP#)
- Enables/Disables the Lock-Down function of the
status register
Software Write Protect ion
- W rite pro tecti on throug h Block- Protec tion bit s in
status register
Temperature Range
- Commercial: 0°C to +70°C
- Ind ustr ial: -40° C to +85° C
Pack age s A vailable
- 8-lead SOIC (200 mils)
- 8-lead SOIC (150 mils)
- 8-contact WSON (6mm x 5mm)
All devices are RoHS compliant
Product Description
The 2 5 ser ies Se rial Flas h famil y feat ures a fou r-wi re,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ulti-
mately lowers total system costs. The SST25VF040B
devices are enhanced with improved operating fre-
quency and even lower power consumption.
SST25VF040B SPI serial flash memories are manu-
factured with proprietary, high-performance CMOS
SuperFlash technology. The split-gate cell design and
thick-o xide tunn eling inj ector att ain bett er reliabil ity and
manufacturability compared with alternate approaches.
SST25VF040B devices significantly improve perfor-
mance and reliability, while lowering power consump-
tion. Th e devices write (Progr am or Erase) with a si ngle
power supply of 2.7-3.6V for SST25VF040B. The total
energy consumed is a function of the applied voltage,
current, and time of application. Since for any given
voltage range, the SuperFlash technology uses less
current to program and has a shorter erase time, the
total energy consumed during any Erase or Program
operation is less than alternative flash memory techno l-
ogies.
The SST25VF0 40B device is of fered in an 8 -lead SOIC
(200 mils), 8-lead SOIC (150 mils), and 8-contact
WSON (6mm x 5mm ) packages . See Figure 2-1 for pin
assignments.
SST25VF040B
4 Mbit SPI Serial Flash
SST25VF040B
DS20005051D-page 2 2005-2017 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
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Most Current Data Sheet
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last character of the literature number is the version number , (e.g., DS30000000A is version A of document DS30000000).
Errata
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2005-2017 Microchip Technology Inc. DS20005051D-page 3
SST25VF040B
1.0 BLOCK DIAGRAM
FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM
1295 B1.
0
I/O Buffers
and
Data Latches
SuperFlash
Memory
X - Decoder
Control Logic
Address
Buffers
and
Latches
CE#
Y - Decoder
SCK SI SO WP# HOLD#
Serial Interface
SST25VF040B
DS20005051D-page 4 2005-2017 Microchip Technology Inc.
2.0 PIN DESCRIPTION
FIGURE 2-1: PIN ASSIGNMENTS
TABLE 2-1: PIN DESCRIPTION
Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI Serial Data Input To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Output s Flas h busy st atu s du ring AAI Program mi ng when reco nfi gur ed as R Y/ BY#
pin. See “Hardware End-o f-Write Detection” on page 11 for details.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for
the duration of any command sequence.
WP# Write Protect The W r ite Pro tec t (WP# ) pin is used to en abl e/d is abl e BPL bi t in th e s t atu s reg is ter.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting
the device.
VDD Power Supp ly To provide power supply voltage: 2.7-3.6V for SST25VF040B
VSS Ground
1
2
3
4
8
7
6
5
CE#
SO
WP#
VSS
VDD
HOLD#
SCK
SI
Top View
1295 08-soic S2A P1.0
8-Lead SOIC
1
2
3
4
8
7
6
5
CE#
SO
WP#
VSS
Top View
VDD
HOLD#
SCK
SI
1295 08-wson QA P2.0
8-Contact WSON
2005-2017 Microchip Technology Inc. DS20005051D-page 5
SST25VF040B
3.0 MEMORY ORGANIZATION
Th e S ST25VF 040B Su p erF l as h me mo r y ar ray is or g a-
nized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable
blocks.
4.0 DEVICE OPERATION
The S ST 25V F0 40 B is accessed thro ugh the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is
used to select the device, and data is accessed through
the Serial Data Inpu t (SI), Serial Data Output (SO), an d
Serial Clock (SCK).
The SST25VF040B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
betwee n th e t w o m ode s, as s how n in Fig ure 4-1, is th e
state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The
SCK si gnal is low for M ode 0 a nd SCK sig nal is high for
Mode 3. For bo th modes, the Seri al Data In (SI) is sam-
pled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
FIGURE 4- 1: SP I PRO TOCOL
4.1 Hold Operation
The HOLD# pin is used to pause a serial sequence
underway with the SPI flash memory wi thout resetting
the clocking sequence. To activate the HOLD# mode,
CE# must be in active low state. The HOLD# mode
begins when the SCK active low state coincides with
the f all in g e dge of the HOLD# si gn al. The H O LD m od e
ends when the HOLD# signal’s rising edge coincides
with the SCK active low state.
If the falling edge of the HOLD# signal does not coin-
cide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the
active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active
low state, then the device exits in Hold mode when the
SCK next reaches the active low state. See Figure 4-2
for Hold Condition waveform.
Once the device enters Hold mode , SO will be in high-
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven ac tive high during a Hold condition, it
resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold
condition. To resume communication with the device,
HOLD# must be driven ac tive high, and CE# must be
driven active low. See Figure 5-3 for Hold timing.
FIGURE 4-2: HOLD CONDITION WAVEFORM
1295 SPIprot.0
MODE 3
SCK
SI
SO
CE# MODE 3
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MODE 0MODE 0
HIGH IMPEDANCE
MSB
MSB
Active Hold Active Hold Active
1295 HoldCond.0
SCK
HOLD#
SST25VF040B
DS20005051D-page 6 2005-2017 Microchip Technology Inc.
4.2 Write Protection
SST25VF040B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protec-
tion bits (BP3, BP2, BP1, BP0, and BPL) in the status
register provide Write protection to the memory array
and the status register. See T able 4-3 for the Block-Pro-
tection description.
4.2.1 WRITE PROTECT PIN (WP#)
The Write Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-
Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.
4.3 Status Register
The software status register provides status on
whether the flash memory array is available for any
Read or Write operation, whether the device is Write
enabled , and the s t ate of the Mem ory Write protectio n.
During an inter nal Erase or Program op eration, the st a-
tus regis ter may be read on ly to de termine the compl e-
tion of an operation in progress. Table 4-2 describes
the function of each bit in the software status register.
4.3.1 BUSY
The Busy bit determines whether there is an internal
Erase or Program operation in progress. A “1” for the
Busy bit indicates the device is busy with an operation
in progress. A “0” indicates the device is ready for the
next valid operation.
4.3.2 WRITE ENABLE LATCH (WEL)
The Write-Enable-Latch bit indicates the status of the
internal memory Write Enable Latch. If the Write-
Enable-Latch bit is set to “1”, it indicates the device is
Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept
any memory Write (Program/Erase) commands. The
Write- Enable-L atch bit is automatically reset under t he
following conditions:
Power-up
Write-Disable (WRDI) instruction completion
Byt e-Program instruction completion
Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
memory address
Sector-Erase instruction completion
Block-Era se instruc ti on compl eti on
Chip-Erase instruction completion
Write -Status-Regis ter ins truc tio ns
TABLE 4-1: CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION
WP# BPL Execute WRSR Instruction
L 1 Not Allowed
L0Allowed
HXAllowed
TABLE 4-2: SOFTWARE S TATUS REGISTER
Bit Name Function Default at
Power-up Read/Write
0 BUSY 1 = Internal Write operation is in progress
0 = No internal Write operation is in progress 0R
1 WEL 1 = Device is memory Write enabled
0 = Device is not memory Write enabled 0R
2 BP0 Indicate current level of block write protection (See Table 4-3)1 R/W
3 BP1 Indicate current level of block write protection (See Table 4-3)1 R/W
4 BP2 Indicate current level of block write protection (See Table 4-3)1 R/W
5 BP3 Indicate current level of block write protection (See Table 4-3)0 R/W
6 AAI Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
0R
7 BPL 1 = BP3, BP2, BP1, BP0 are read-only bits
0 = BP3, BP2, BP1, BP0 are read/writable 0R/W
2005-2017 Microchip Technology Inc. DS20005051D-page 7
SST25VF040B
4.3.3 AUTO ADDRESS INCREMENT (AAI)
The Auto Address Increment Programming-Status bit
provides status on whether the device is in AAI pro-
grammi ng mode or Byte-Pro gram mode . The defaul t at
power up is Byte-Program mode.
4.3.4 BLOCK PROTECTION (BP3,BP2,
BP1, BP0)
The Block- Protection (BP3, BP2, BP1 , BP0) bits d efine
the size of the memory area, as defin ed in Table 4-3, to
be software protected against any memory Write (Pro-
gram or Erase) operation. The Write-Status-Register
(WRSR) instruction is used to program the BP3, BP2,
BP1 and BP0 bi t s as l on g as WP# i s h igh or th e Bl ock -
Protect-Lock (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are all 0. After power-
up, BP3, BP2, BP1 and BP0 are set to 1.
4.3.5 BLOCK PROTECTION LOCK-DOWN
(BPL)
WP# pin driven low (VIL), enables the Block-Protection-
Lock-Dow n (BPL) bit. When BPL is set to 1, it prev ent s
any further alteration of the BPL, BP3, BP2, BP1, and
BP0 bits. When the WP# pin is driven high (VIH), the
BPL bit has no ef fect and i ts va lue is “Don’ t Care”. Aft er
power-up, the BPL bit is reset to 0.
TABLE 4-3: SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25VF040B1
1. X = Don’t Care (RESERVED) default is “0
Protection Level
Status Register Bit2
2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Pr otected)
Protected Memory Addres s
BP3 BP2 BP1 BP0 4 Mbit
None X 0 0 0 None
Upper 1/8 X 0 0 1 70000H-7FFFFH
Upper 1/4 X 0 1 0 60000H-7FFFFH
Upper 1/2 X 0 1 1 40000H-7FFFFH
All Blocks X 1 0 0 00000H-7FFFFH
All Blocks X 1 0 1 00000H-7FFFFH
All Blocks X 1 1 0 00000H-7FFFFH
All Blocks X 1 1 1 00000H-7FFFFH
SST25VF040B
DS20005051D-page 8 2005-2017 Microchip Technology Inc.
4.4 Instructions
Instructions are used to read, write (Erase and Pro-
gram), and configure the SST25VF040B. The instruc-
tion bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte-Program, Auto Address Increment (AAI) program-
ming, Sector-Erase, Block-Erase, Write-Status-Regis-
ter, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The com-
plete list of instructions is provided in Table 4-4. All
instructions are synchronize d off a high to low transition
of CE#. Inputs will be accepted on the rising edge of
SCK sta rting wit h th e m os t sig nifi ca nt bit. CE# m ust b e
drive n low b efore a n ins tructio n is entered and m ust b e
driven high after the last bit of the instruction has been
shif ted in (except for Rea d, Read-ID, and Read-S t atus-
Register instructions). Any low to high transition on
CE#, before receiving the last bit of an instruction bus
cycle, will terminate the instruction in progress and
return the device to standby mode. Instruction com-
mands (Op Code), addresses, and data are all input
from the most sig nif ic ant bit (MSB) first.
TABLE 4-4: DEVICE OPERATION INSTRUCTIONS
Instruction Description Op Code Cycle1
1. One bus cycle is eight clock periods.
Address
Cycle(s)2
2. Address bits above the most significant bit of each density can be VIL or VIH.
Dummy
Cycle(s) Data
Cycle(s)
Read Read Memory 0000 0011b (03H) 3 0 1 to
High-Speed Read Read Memory at higher spee d 0000 1011b (0BH) 3 1 1 to
4 KByte Sector-
Erase3
3. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
Erase 4 KByte of memory array 0010 0000b (20H) 3 0 0
32 KByte Block-
Erase4
4. 32KByte Block Erase addresses: use AMS-A15, rem aining addresses are don’t care but must be set either at VIL or VIH.
Erase 32 KByte block of memory
array 0101 0010b (52H) 3 0 0
64 KByte Block-
Erase5
5. 64KByte Block Erase addresses: use AMS-A16, rem aining addresses are don’t care but must be set either at VIL or VIH.
Erase 64 KByte block of memory
array 1101 1000b (D 8H) 3 0 0
Chip-Erase Erase Full Memory Array 0110 0000b (60H)
or
1100 0111b (C7H)
000
Byte-Program To Program One Data Byte 0000 0010b (02H) 3 0 1
AAI-Word-Program6
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data
to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be pro-
grammed into the
initial address [A23-A1] with A 0=1.
Auto Address Increment Program-
ming 1010 1101b (ADH) 3 0 2 to
RDSR7
7. The Read-Stat us-Reg ister is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
Read-Status-Register 0000 0101b (05H) 0 0 1 to
EWSR Enable-Write-Status-Register 0101b 0000b (50H) 0 0 0
WRSR Write-Status-Register 0000 0001b (01H) 0 0 1
WREN Write-Enable 0000 0110b (06H) 0 0 0
WRDI Write-Disable 0000 0100b (04H) 0 0 0
RDID8
8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID
and device ID output stream is continuous until terminated by a low-to-high transition on CE #.
Read-ID 1001 0000b (90H)
or
1010 1011b (ABH)
301 to
JEDEC-ID JEDEC ID read 1001 1111b (9FH) 0 0 3 to
EBSY Enable SO to output RY/BY# status
during AAI programming 0111 0000b (70H) 0 0 0
DBSY Disable SO as RY/BY#
status during AAI programming 1000 0000b (80H) 0 0 0
2005-2017 Microchip Technology Inc. DS20005051D-page 9
SST25VF040B
4.4.1 READ (25 MHZ)
The Read instruction, 03H, supports up to 25 MHz
Read. The device outputs the data starting from the
specified address location. The data output stream is
continuous through all addresses until terminated by a
low to high transition on CE#. The internal address
pointer will automatically increment until the highest
memory address is reache d. Once the highes t memory
address is reached, the address pointer will automati-
cally increment to the beginning (wrap-around) of the
address space. Once the data from address location
1FFFFFH has been read, the next output will be from
address location 000000H.
The Read instruction is initiated by executing an 8-bit
comma nd, 03H, followed by addres s bit s [A23-A0]. CE#
must remain active low for the duration of the Read
cycle. See Figure 4-3 for the Read sequenc e.
FIGURE 4-3: READ SEQUENCE
4.4.2 HIGH-SPEED-READ (50 MHZ)
The High-Speed-Read instruction supporting up to 50
MHz Read is initiated by executing an 8-bit command,
0BH, followed by address bits [A23-A0] and a dummy
byte. CE# must remain active low for the duration of the
High-Speed-Read cycle. See Figure 4-4 for the High-
Speed-Re ad seq uence.
Following a dummy cycle, the High-Speed-Read
instruction outputs the data starting from the specified
address location. The data o utput st ream is contin uous
through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached . Once the hig hest memory address
is reach ed, the addre ss pointe r will auto matical ly incre-
ment to the beginning (wrap-around) of the address
space. Once the data from address location 7FFFFH
has been read, the next output will be from address
location 00000H.
FIGURE 4-4: HIGH-SPEED-READ SEQUENCE
1295 ReadSeq.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
03
HIGH IMPEDANCE
15 16 23 24 31 32 39 40 7047 48 55 56 63 64
N+2 N+3 N+4N N+1
DOUT
MSB MSB
MSB
MODE 0
MODE 3
DOUT DOUT DOUT DOUT
1295 HSRdSeq.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.0B
HIGH IMPEDANCE
15 16 23 24 31 32 39 40 47 48 55 56 63 64
N+2 N+3 N+4
NN+1
X
MSB
MSB
MSB
MODE 0
MODE 3
DOUT DOUT DOUT DOUT
80
71 72
DOUT
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH)
SST25VF040B
DS20005051D-page 10 2005-2017 Microchip Technology Inc.
4.4.3 BYTE-PROGRAM
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte
must be in the erased state (FFH ) when initiatin g a Pro-
gram operation. A Byte-Program instruction applied to a
protecte d memory are a will be igno red.
Prior to a ny Write operati on, the Write -Enable (WREN)
instruction must be executed. CE# must remain active
low for the duration of the Byte-Program instruction.
The Byte-Program instruction is initiated by executing
an 8-bit comm an d, 02H, followed by address bit s [A23-
A0]. Following the address, the data is input in order
from MSB (bit 7) to LSB (bit 0). CE# must be driven
high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait
TBP for the completion of the internal self-timed Byte-
Program operation. See Figure 4-5 for the Byte-Pro-
gram sequence.
FIGURE 4-5: BYTE-PROGRAM SEQUEN CE
4.4.4 AUTO ADDRESS INCREMENT (AAI)
WORD-PROGRAM
The AAI program instruction allows multiple bytes of
data to be programmed without re-issuing the next
sequential address location. This feature decreases
total programming time when multiple bytes or entire
memory array is to be programmed. An AAI Word pro-
gram instruction pointing to a protected memory area
will be ignore d. The se lected addres s range must be in
the erased state (FFH) when initiating an AAI Word
Program operation. While within AAI Word Program-
ming sequence, only the following instructions are
valid: for software end-of-write detection—AAI Word
(ADH), WRDI (04H), and RDSR (05H); for hardware
end-of-write detection—AAI Word (ADH) and WRDI
(04H). There are three options to determine the com-
pletion of each AAI Word program cycle: hardware
detecti on by readi ng the Seria l Output, so ft ware dete c-
tion by polling the BUSY bit in the software status reg-
ister, or wait TBP. Refer to“End-of-Write Detection” for
details.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. Initiate the AAI Word
Program instruction by executing an 8-bit command,
ADH, follow ed by ad dress bits [A23-A0]. Following the
addresses, two bytes of data are input sequentially,
each on e from MSB (Bi t 7) to L SB (Bit 0). Th e first byte
of dat a (D0) is programmed into the initial address [A23-
A1] with A0=0, the second byte of Data (D1) is pro-
grammed into the initial address [A23-A1] with A0=1.
CE# must be driven high before executing the AAI
Word Program instruction. Check the BUSY status
before entering the next valid command. Once the
device indicates it is no longer busy, data for the next
two sequential addresses may be programmed, fol-
lowed by the next two, and so on.
When pr o gra mm in g the l as t de sir e d wo r d, or t h e hi gh -
est unprotected memory address, check the busy sta-
tus using either the hardware or software (RDSR
instruction) method to check for program completion.
Once programming is complete, use the applicable
method to terminate AAI. If the device is in Software
End-of-Write Detection mode, execute the Write-Dis-
able (WRDI) instruction, 04H. If the device is in AAI
Hardware End-of-Write Detection mode, execute the
Write-Disable (WRDI) instruction, 04H, followed by the
8-bit DBSY command, 80H. There is no wrap mode
during AAI programming once the highest unprotected
memory address is reached. See Figures 4-8 and 4-9
for the AAI Word programming sequence.
4.4.5 END-OF-WRITE DETECTION
There are three methods to determine completion of a
program cycle during AAI Word programming: hard-
ware detection by reading the Serial Output, software
detectio n by polli ng the BUSY bi t in the Sof tware S t atus
Register, or wait TBP. The Hardware End-of-Write
detection method is described in the section below.
2005-2017 Microchip Technology Inc. DS20005051D-page 11
SST25VF040B
4.4.6 HARDWARE END-OF-WRITE
DETECTION
The Hardware End-of-Write detection method elimi-
nate s the ov erhead of polli ng the Busy bi t in the Soft-
ware Status Register during an AAI Word program
operation. The 8-bit command, 70H, configures the
Serial Output (SO) pin to indicate Flash Busy status
during AAI W ord prog ramming. (see Figure 4-6) The 8-
bit co mm an d , 70 H , mu st b e ex ec ute d pr io r to i ni tia t i ng
an AAI Word-Program instruction. Once an internal
programming operation begins, asserting CE# will
imme diately drive the stat us of the internal flash status
on the SO pin. A ‘0’ indicates the device is busy and a
‘1’ indi cat es the de vice is ready for the ne xt inst ructio n.
De-asserting CE# will return the SO pin to tri-state.
While in AAI and Hardware End-of-Write detection
mode, the only valid instructions are AAI Word (ADH)
and WRDI (04H).
To exit AAI Hardware End-of-Write detection, first exe-
cute WRD I in str uct i on, 04H, to re set the Writ e- Ena b le-
Latch bit (WEL=0) and AAI bit. Then ex ecute the 8-bit
DBSY command , 80H, to disabl e RY/BY# status during
the AAI command. See Figures 4-7 and 4-8.
FIGURE 4-6: ENABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
FIGURE 4-7: DISABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
CE#
SO
SI
SCK
01234567
70
HIGH IMPEDANCE
MODE 0
MODE 3
1295 EnableSO.0
MSB
CE#
SO
SI
SCK
01234567
80
HIGH IMPEDANCE
MODE 0
MODE 3
1295 DisableSO.0
MSB
SST25VF040B
DS20005051D-page 12 2005-2017 Microchip Technology Inc.
FIGURE 4-8: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
HARDWARE END-OF-WRITE DETECTION
FIGURE 4-9: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
SOFTWARE END-OF-WRITE DETECTION
CE#
SI
SCK
SO
1295 AAI.HW.3
Check for Flash Busy Status to load next valid
1
command
Load AAI command, Address, 2 bytes data
0
AAA
AD D0 AD
MODE 3
MODE 0
D1 D2 D3
7
WREN
EBSY
07078 32 4715 16 23 24 31 04039 7 8 15 16 23
D
OUT
WRDI followed by DBSY
to exit AAI Mode
WRDI RDSR
7015
780
DBSY
70
CE# cont.
SI cont.
SCK cont.
SO cont.
Last 2
Data Bytes
AD
D
n-1 Dn
7 8 15 16 23
0
Check for Flash Busy Status to load next valid
1
command
Note: 1. Valid comm ands during AAI program ming: AA I command or WRDI com mand
2. User must configure the SO pin to output Flash Busy status during AAI programming
078 32 4715 16 23 24 31 04039 7 8 15 16 23 7 8 15 16 23 70 157800
CE#
SI
SCK
SO DOUT
MODE 3
MODE 0
1295 AAI.SW.1
W ait TBP or poll Software Status
register to load next valid1 command
Last 2
Data Bytes WRDI to exit
AAI Mode
Load AAI command, Address, 2 bytes data
AAAAD D0 ADD1 D2 D3 AD Dn-1 Dn
WRDI
RDSR
Note: 1. Valid commands during AAI programm ing: AA I command or WRDI com mand
2005-2017 Microchip Technology Inc. DS20005051D-page 13
SST25VF040B
4.4.7 4-KBYTE SECTOR-ERASE
The Sector-Erase instruction clears all bits in the
selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area w ill be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must
remain active low for the duration of any command
sequence. The Sector-Erase instruction is initiated by
execut ing an 8 -bit com mand, 20 H, foll owed by address
bits [A23-A0] . Addre ss bits [ AMS-A12] (AMS = Most Sig-
nificant address) are used to determine the sector
address (S AX), remain ing address bits c a n be V IL or VIH.
CE# must be dri ven high bef or e the i nst ruc tio n is e xe-
cuted. The user may poll the Busy bit in the software
status register or wait TSE for the completion of the
internal self-timed Sector-Erase cy cle. See Figure 4-10
for the Sector-Erase sequence.
FIGURE 4-10: SECTOR-ERASE SEQUENC E
4.4.8 32-KBYTE AND 64-KBYTE BLOCK-
ERASE
The 32-KByte Block-Erase instruction clears all bits in
the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area w ill be
ignored. The 64-KByte Block-Erase instruction clears all bits
in the selected 64 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN ) inst ruct ion must b e exec ute d. CE# m us t re ma i n
active low for the duration of any command sequence.
The 32-KByte Block-Erase instruction is initiated by
execut ing an 8 -bit com mand, 52 H, foll owed by address
bits [A 23-A0]. Address bits [AMS-A15] (AMS =Most Sig-
nificant Address) are used to determine block address
(BAX), remaining address bits can be VIL or VIH. CE#
must be driven high before the instruction is executed. The
64-KByte Block-Erase instruction is initiated by executing an
8-bit command D8H, followed by address bits [A23-A0].
Address bits [AMS-A16] are used t o determine block address
(BAX), remaining address bits can be VIL or VIH. CE# must
be driven high before the instruction is executed. The user
may poll the Busy bit in the software status register or wait
TBE for the completion of the internal self-timed 32-
KByte Block-Erase or 64-KByte Block-Erase cycles.
See Figures 4-11 and 4-12 for the 32-KByte Block-
Erase and 64-KByte Block-Erase s equences.
FIGURE 4-11 : 32-KBYTE BLOCK-ERASE SE QUENCE
C
E#
SO
SI
S
CK
ADD.
012345678
ADD. ADD.
20
HIGH IMPEDANCE
15 16 23 24 31
MODE 0
MODE 3
1295 SecErase.
0
MSBMSB
C
E#
SO
SI
S
CK
ADDR
012345678
ADDR ADDR
52
HIGH IMPEDANCE
15 16 23 24 31
MODE 0
MODE 3
1295 32KBklEr.
0
MSB MSB
SST25VF040B
DS20005051D-page 14 2005-2017 Microchip Technology Inc.
FIGURE 4-12: 64-KBYTE BLOCK-ERASE SE QU ENCE
4.4.9 CHIP-ERASE
The Chip-Erase instruction clears all bits in the device
to FFH. A Chip-Erase instruction will be ignored if any
of the memory area is protected. Prior to any Write oper-
ation, the Write-Enable (WREN) instruction must be exe-
cuted. CE# must remain active low for the duration of
the Chip-Erase instruction sequence. The Chip-Erase
ins tructi on is i nitiat ed by execut ing a n 8-b it com mand,
60H or C7H. CE# must be driven high before the instruction
is exec uted. Th e user ma y poll the Busy bit in the software
status register or wait TCE for the completion of the
internal self-timed Chip-Erase cycle. See Figure 4-13
for the Chip-Erase sequence.
FIGURE 4-13: CHIP-ERASE SE QUENCE
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
D8
HIGH IMPEDANCE
15 16 23 24 31
MODE 0
MODE 3
1295 63KBlkEr.0
MSB MSB
CE#
SO
SI
SCK
01234567
60 or C7
HIGH IMPEDANCE
MODE 0
MODE 3
1295 ChEr.0
MSB
2005-2017 Microchip Technology Inc. DS20005051D-page 15
SST25VF040B
4.4.10 READ-STATUS-REGISTER (RDSR)
The Read-Status-Register (RDSR) instruction allows
reading of the status register. The status register may
be read at any time even during a Write (Program/
Erase) operation. When a Write operation is in prog-
ress, the Busy bit may be checked before sending any
new commands to assure that the new commands are
properly received by the device. CE# must be driven
low b efo re t he R DS R i nst ruc tion is entere d a nd rem ai n
low until the status data is read. Read-Status-Register
is continuous with ongoing clock cycles until it is termi-
nated b y a low t o high tr ansition of the CE#. See Figure
4-14 for the RDSR instruction sequence.
FIGURE 4-14: READ-STATUS-REGIS TER (RD SR) SEQUENCE
4.4.11 WRITE-ENABLE (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit in the Status Register to 1 allowing
Write operations to occur. The WREN instruction must
be executed pri or to any W rite (Progr am/Eras e) opera-
tion. The WREN instruction may also be used to allow
execution of the Write-S tatus-Register (WRSR) instruc-
tion; however, the Write-Enable-Latch bit in the Status
Register will be cleared upon the rising edge CE# of the
WRSR in stru cti on . CE# m us t b e d r iven high before th e
WREN instruction is executed.
FIGURE 4-15: WRITE ENABLE (WREN) SEQUENCE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
1295 RDSRseq.0
MODE 3
SCK
SI
SO
CE#
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
05
MODE 0
HIGH IMPEDANCE
Status
Register Out
MSB
MSB
C
E#
SO
SI
S
CK
01234567
06
HIGH IMPEDANCE
MODE 0
MODE 3
1295 WREN
.0
MSB
SST25VF040B
DS20005051D-page 16 2005-2017 Microchip Technology Inc.
4.4.12 WRITE-DISABLE (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new
Write op era t i ons fro m oc cu r ri ng . The WRD I inst r u cti on
will not terminate any programming operation in prog-
ress. Any program operation in progress may continue
up to TBP after executing the WRDI instruction. CE#
must be driven high before the WR DI instruction is exe-
cuted.
FIGURE 4-16: WRITE DISABLE (WRDI) S EQUENCE
4.4.13 ENABLE-WRITE-STATUS-
REGISTER (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction
and opens the status register for alteration. The Write-
Status-Register instruction must be executed immedi-
ately after the execution of the Enable-Write-Status-
Register instruction. This two-step instruction
sequence of the EWSR instruction followed by the
WRSR instruction works like SDP (software data pro-
tection) command structure which prevents any acci-
dent al alteration of the stat us register values. CE# must
be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction
is executed.
4.4.14 WRITE-STATUS-REGISTER (WRSR)
The Write-Status-Register instruction writes new val-
ues to the BP3, BP2, BP1, BP0, and BPL bits of the st a-
tus register. CE# must be driven low before the
command sequence of the WRSR instruction is
entered a nd driven hig h before the WR SR instructio n is
executed. See Figure 4-17 for EWSR or WREN and
WRSR instruction sequences.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to “1”.
When the WP# is low, the BPL bi t ca n o nly be se t from
“0” to “1” to lock -down the st atus register , bu t cannot be
reset from “1” to “0”. When WP# is high, the lock-down
function of the BPL bit is disabled and the BPL, BP0,
and BP1 and BP2 bits in the status register can all be
changed. As long as BPL bit is set to 0 or WP# pin is
driven high (VIH) prior to the low-to-high transition of the
CE# pin at the end of the WRSR instruction, the bits in
the status register can all be altered by the WRSR
instruction. In this case, a single WRSR instruction can
set the BPL bit to “1” to lock down the status register a s
well as a ltering the BP0, BP1, a nd BP2 bits at the same
time. See Table 4-1 for a su mm ar y des cr ipt i o n of WP#
and BPL functions.
FIGURE 4-17: ENA BLE-WRITE-STATUS-REGISTER (EWSR) OR WRITE-ENABLE (WREN) AND
WRITE-STATUS-REGISTER (WRSR) SEQUENCE
C
E#
SO
SI
S
CK
01234567
04
HIGH IMPEDANCE
MODE 0
MODE 3
1295 WRDI
.0
MSB
1295 EWSR.0
MODE 3
HIGH IMPEDANCE
MODE 0
STATUS
REGISTER IN
76543210
MSBMSBMSB 01
MODE 3
SCK
SI
SO
CE#
MODE 0
50 or 06
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
2005-2017 Microchip Technology Inc. DS20005051D-page 17
SST25VF040B
4.4.15 JEDEC READ-ID
The JEDEC Read-ID instruction identifies the device as
SST25VF040B and the manufacturer as Microchip.
The devic e inform ation ca n be read from executing the
8-bit command, 9FH. Following the JEDEC Read-ID
instruction, the 8-bit manufacturer ’s ID, BFH, is output
from the device. After that, a 16-bit device ID is shifted
out on the SO pin. Byte 1, BFH, id entifies the manufac-
ture r a s Mic roc hip . B yte 2, 25 H, iden tifi es the m e mory
type as SPI Serial Flash. Byte 3, 8DH, identifies the
device as SST25VF040B. The instruction sequence is
shown in Figure 4-18. The JEDEC Read ID instruction
is te rmi n at e d b y a low to hi gh t r an sit i on on CE # a t any
time during data output.
FIGURE 4-18: JEDEC READ-ID SEQUENCE
25 8D
1295 JEDECID.1
CE#
SO
SI
SCK
012345678
HIGH IMPEDANCE
15 1614 28 29 30 31
BF
MODE 3
MODE 0
MSBMSB
9 10111213 1718 32 34
9F
19 20 21 22 23 3324 25 26 27
TABLE 4-5: JEDEC READ-ID DATA
Manufacturer’s ID Device ID
Memory Type Memory Capacity
Byte1 Byte 2 Byte 3
BFH 25H 8DH
SST25VF040B
DS20005051D-page 18 2005-2017 Microchip Technology Inc.
4.4.16 READ-ID (RDID)
The Read-ID instruction (RDID) identifies the devices
as SS T 25 V F 04 0B and manu facturer as Microchip . This
command is backward compatible to all SST25xFxxxA
dev ices an d sho uld be u sed as defa ult de vice i dent ifi-
cation when multiple versions of SPI Serial Flash
devices are used in a design. The device information
can be read from executing an 8-bit command, 90H or
ABH, followed by address bits [A23-A0]. Following the
Read-ID instru ction, the ma nufacturer’s ID is located in
address 00000H and the device ID is located in
address 00001 H. On ce the devic e is i n Rea d-ID mod e,
the manufacturer’s and device ID output data toggles
betwee n address 00000 H and 0000 1H until termin ated
by a low to high transition on CE#.
Refer to Tables 4-5 and 4-6 for device identification
data.
FIGURE 4-19: READ-ID SEQUENCE
1295 RdID.
0
C
E#
SO
SI
S
CK
00
012345678
00 ADD1
90 or AB
HIGH IMPEDANCE
15 16 23 24 31 32 39 40 47 48 55 56 63
BF Device ID BF Device ID
Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.
Device ID = 8DH for SST25VF040B
1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.
HIGH
IMPEDANC
E
MODE 3
MODE 0
MSB MSB
MSB
TABLE 4-6: PRODUCT IDENTIFICATION
Address Data
Manufacturer’s ID 00000H BFH
Device ID
SST25VF040B 00001H 8DH
2005-2017 Microchip Technology Inc. DS20005051D-page 19
SST25VF040B
5.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applie3d conditions greater than those listed under “Absolute Max-
imum Stress Rat ings” may cause pe rmanent damag e to the device. Thi s is a stress rat ing only and func-
tional operation of the device at these conditions or conditions greater than those defined in the operational
sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may
affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential. . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
TABLE 5-1: OPERATING RANGE
Range Ambient Te mp VDD
Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V
TABLE 5-2: AC CONDITIONS OF TEST1
1. See Figures 5-5 and 5-6
Input Rise/Fall Time Output Load
5ns CL = 30 pF
TABLE 5-3: DC OPERATING CHARACTERISTICS
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDDR Read Current 10 mA CE#=0.1 VDD/0.9 VDD@25 MHz, SO=open
IDDR2 Read Current 15 mA CE#=0.1 VDD/0.9 VDD@50 MHz, SO=open
IDDW Program and Erase Current 30 mA CE#=VDD
ISB Standby Current 20 µA CE#=VDD, VIN=VDD or VSS
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VIH Input High Voltage 0.7 VDD VV
DD=VDD Max
VOL Output Low Voltage 0.2 V I OL=100 µA, VDD=VDD Min
VOL2 Ou tput Low Voltage 0.4 V IOL=1.6 mA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA , VDD=VDD Min
TABLE 5-4: CAPACITANCE (TA = 25°C, F=1 M Hz, OTH ER PINS OPEN)
Parameter Description Test Condition Maximum
COUT1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Output Pin Cap ac itance VOUT = 0V 12 pF
CIN1Input Capacitance VIN = 0V 6 pF
SST25VF040B
DS20005051D-page 20 2005-2017 Microchip Technology Inc.
TABLE 5-5: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
NEND1Endurance 10,000 Cycles JEDEC Standard A117
TDR1Data Retention 100 Years JEDEC Standard A103
ILTH1Latch Up 100 + IDD mA JEDEC Standard 78
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 5-6: AC OPERATING CHARACTERISTICS
Symbol Parameter
25 MHz 50 MHz
UnitsMin Max Min Max
FCLK1
1. Maximum clock frequency for Read Instruction, 03H, is 25 MHz
Serial Clock Frequency 25 50 MHz
TSCKH Serial Clock High Time 18 9 ns
TSCKL Serial Clock Low Time 18 9 ns
TSCKR2
2. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements
Serial Clock Rise Time (Slew Rate) 0.1 0.1 V/ns
TSCKF Serial Clock Fall Time (Slew Rate) 0.1 0.1 V/ns
TCES3
3. Relative to SCK.
CE# Active Setup Time 10 5 ns
TCEH3CE# Active Hold Time 10 5 ns
TCHS3CE# Not Active Setup Time 10 5 ns
TCHH3CE# Not Active Hold Time 10 5 ns
TCPH CE# High Time 100 50 ns
TCHZ CE# High to High-Z Output 15 8 ns
TCLZ SCK Low to Low-Z Output 0 0 ns
TDS Data In Setup Time 5 2 ns
TDH Data In Hold Ti me 5 5 ns
THLS HOLD# Low Setup Time 10 5 ns
THHS HOLD# High Setup Time 10 5 ns
THLH HOLD# Low Hold Ti me 10 5 ns
THHH HOLD# High Hold Time 10 5 ns
THZ HOLD# Low to High-Z Output 20 8 ns
TLZ HOLD# High to Low-Z Output 15 8 ns
TOH Output Hold from SCK Change 0 0 ns
TVOutput Valid from SCK 15 8 ns
TSE Sector-Erase 25 25 ms
TBE Block-Erase 25 25 ms
TSCE Chip-Erase 50 50 ms
TBP Byte-Program 10 10 µs
2005-2017 Microchip Technology Inc. DS20005051D-page 21
SST25VF040B
FIGURE 5-1: SERIAL INPUT TIMING DIAGRAM
FIGURE 5-2: SERIAL OUTPUT TIMING DIAGRAM
FIGURE 5-3: HOLD TIMING DIAGRAM
HIGH-Z HIGH-Z
C
E#
SO
SI
S
CK
MSB LSB
TDS TDH
TCHH TCES TCEH TCHS
TSCKR
TSCKF
T
CPH
1295 SerIn
.0
1295 SerOut.0
CE#
SI
SO
SCK
MSB
T
CLZ
T
V
T
SCKH
T
CHZ
T
OH
T
SCKL
LSB
T
HZ
T
LZ
T
HHH
T
HLS
T
HLH
T
HHS
1295 Hold.0
HOLD#
CE#
SCK
SO
SI
SST25VF040B
DS20005051D-page 22 2005-2017 Microchip Technology Inc.
5.1 Power-Up Specifications
All functionalities and DC specifications are specified
for a VDD ramp rate of greater than 1V per 100 ms (0v
- 3.0V in less than 300 ms). See Table 5-7 and Figure
5-4 for more information.
FIGURE 5-4: POWER-UP TIMING DIAGRAM
FIGURE 5-5: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TABLE 5-7: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol Parameter Minimum Units
TPU-READ1
1. This parameter is measured only for initial qualification and afte r a design or process change that could affect this parame-
ter.
VDD Min to Read Operation 100 µs
TPU-WRITE1VDD Min to Write Operation 100 µs
Tim
e
V
DD
Min
V
DD
Max
V
DD
Device fully accessible
T
PU-READ
T
PU-WRITE
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
1295 PwrUp.
0
1295 IORef
.0
REFERENCE POINTS OUTPUTINPUT?
VHT
VLT
VHT
VLT
V
IHT
VILT
AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement refer-
ence points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10% 90%)
are <5 ns.
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
2005-2017 Microchip Technology Inc. DS20005051D-page 23
SST25VF040B
FIGURE 5-6: A TEST LOAD EXAMPLE
1295 TstLd.0
T O TESTER
TO DUT
C
L
SST25VF040B
DS20005051D-page 24 2005-2017 Microchip Technology Inc.
6.0 PACKAGING DIAGRAMS
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing C04-14005A Sheet 1 of 1
8-Lead Small Outline Integrated Circuit (S2AE/F) - .208 Inch Body [SOIC]
Note:
1. All linear dimensions are in millimeters (max/min).
2. Coplanarity: 0.1 mm
3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
2005-2017 Microchip Technology Inc. DS20005051D-page 25
SST25VF040B
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing C04-14003A Sheet 1 of 1
8-Lead Small Outline Integrated Circuit (SAE/F) - 5x6 mm Body [SOIC]
Note:
1. Complies with JEDEC publication 95 MS-012 AA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
SST25VF040B
DS20005051D-page 26 2005-2017 Microchip Technology Inc.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing C04-14008A Sheet 1 of 1
8-Lead Very, Very Thin Small Outline No-Leads (QAE/F) - 5x6 mm Body [WSON]
Note:
1. All linear dimensions are in millimeters (max/min).
2. Untoleranced dimensions (shown with box surround)
are nominal target dimensions.
3. The external paddle is electrically connected to the
die back-side and possibly to certain VSS leads.
This paddle can be soldered to the PC board;
it is suggested to connect this paddle to the VSS of the unit.
Connection of this paddle to any other voltage potential can
result in shorts and/or electrical malfunction of the device.
2005-2017 Microchip Technology Inc. DS20005051D-page 27
SST25VF040B
TABLE 6-1: REVISION HISTORY
Revision Description Date
00 Initial release of data sheet Sep 2005
01 Migrated document to a Data Sheet
Updated Surface Mount Solder Reflow Temperature information Jan 2006
02 Added 8-Lead SOIC (150 mils) package drawing.
Updated Features and Product Description to include new package informa-
tion.
Updated Pin-Assignment, Figure 2-1
Revised Fi gur e 4-8 and Figure 4-9
Jul 2007
03 Updated document to reflect upgraded clock frequency to 80 MHz globally
Updated Features
Changed maximum frequency to 80 MHz in Table 4-4 on page 8
Added IDDR3 to Table 5-3 on page 19
Added 80 MHz column to Table 5-6 on page 20
Updated Product Ordering Information and Valid Combinations on page 29
Mar 2009
04 Updated Product Ordering Information and Valid Combinations on page 29
Added “Power-Up Specifications” on page 22
Modified High-S peed-Read values in Table 4-4 on page 8 and “High-Speed-
Read (50 MHz)” on page 9
Jun 2009
05 Added 50/33 MHz information throughout.
Separated AC and DC Characteristics for SST25VF040B-50-4C-xxxF &
SST25VF040B-80-4I-xxxE
Oct 2009
06 Updated “Auto Address Increment (AAI) Word-Program”, “End-of-Write
Detection”, and “Hardware End-of-Write Detection” on page 11.
Revised Figures 4-8 and 4-9 on page 12.
Updated document to new format.
Feb 2011
ARemoved “Recommended System Power-up Timings” from page 29.
Released document under letter revision system.
Updated Spec number from S71295 to DS25051
Sep 2011
BEOL of all 80 MHz parts. Replacement parts are the 50 MHz counterparts
found in this document.
Removed all 80 MHz information. See DS20005264.
Updated document to new format.
Replaced all package drawings with drawings in the new format.
Feb 2014
CCorrected an address bit on page 13 Jun 2015
DAdded Units column and corrected typo in Table 5-6.July 2017
SST25VF040B
DS20005051D-page 28 2005-2017 Microchip Technology Inc.
THE MICROCHIP WEB SITE
Microc hip pro vides on line s upport v ia our W WW site at
www.microchip.com. This we b s ite is u sed as a m ean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following informa-
tion:
Product Support – Data sh eet s and errat a, app li-
cation notes and sample programs, design
resources, user’s guides and hardware support
docum ent s, lat est sof tware re lease s and ar chive d
software
General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip c onsultant
program member listing
Business of Microc hip – Product selector and
orde ring guide s, lat est Microchip press releases ,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
change s, updates, re visions or e rrata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on “Cus-
tomer Change Notification” and follow the registration
instructions.
CUSTO ME R SU PP OR T
Users of Microchip products can receive assistance
through sev eral channe ls :
Distributo r or Representative
Local Sale s Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their dist ribu tor, representa-
tive or Field Application Engineer (FAE) for support
Local sales offices are also available to help custom-
ers. A listing of sa les offic es and loca tions is i ncluded in
the back of this document.
Technical supp ort is avai labl e through th e web site
at: http://microchip.com/support
2005-2017 Microchip Technology Inc. DS20005051D-page 29
SST25VF040B
7.0 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. XX
XX
Operatin g
Device
Device: SST25VF040B = 4 Mbit, 2.7-3.6V, SPI Flash Memory
Operating
Frequency: 50 = 50 MHz
Minimum
Endurance 4 = 10,000 cycles
Temperature: I = -40°C to +85°C
C = 0°C to +70°C
Package: QAF/QAE1= WSON (6mm x 5mm Body) , 8-lead
S2AF/S2AE1= SOIC (200 mil Body), 8-lead
SAF/SAE1= SOIC (150 mm Body), 8-lead
1. Suffix E = Matte T in finish
Suffix F = Nickel plating with Gold top (outer) layer finish
Tape and
Reel Flag: T = Tape and Reel
Va li d C omb in a t i ons:
SST25VF040B-50-4C-SAF
SST25VF040B-50-4C-SAF-T
SST25VF040B-50-4I-SAF
SST25VF040B-50-4I-SAF-T
SST25VF040B-50-4I-SAE
SST25VF040B-50-4I-SAE-T
SST25VF040B-50-4C-S2AF
SST25VF040B-50-4C-S2AF-T
SST25VF040B-50-4I-S2AF
SST25VF040B-50-4I-S2AF-T
SST25VF040B-50-4I-S2AE
SST25VF040B-50-4I-S2AE-T
SST25VF040B-50-4C-QAF
SST25VF040B-50-4C-QAF-T
SST25VF040B-50-4I-QAF
SST25VF040B-50-4I-QAF-T
SST25VF040B-50-4I-QAE
SST25VF040B-50-4I-QAE-T
X
Tape/Reel
Indicator
Frequency
XX
Package
Temp
Range
Minimum
Endurance
SST25VF040B
DS20005051D-page 30 2005-2017 Microchip Technology Inc.
NOTES:
2005-2017 Microchip Technology Inc. DS20005051D-page 31
Information contained in this publication regarding device
applications a nd the lik e is provided only f or yo ur convenience
and may be supers ed ed by u pda t es . It is y our responsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microch ip name and logo, the Microchip logo, AnyRate, A V R,
AVR logo , AVR Freaks, Beac onThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kle e r, LANCheck, LI N K MD, m aX Stylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are regi stered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other c ountries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Anal og-for-the-Digital Age, Any
Capacitor, AnyIn, AnyO ut, Bod yCo m, chipK IT, chipKIT logo,
CodeGuard, CryptoAuthent i cation, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Progra mming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNe t, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Ser ial Quad I/O, SMART-I.S., SQI ,
SuperSwitcher, SuperSwitcher II, Total Endura nce, TSHARC,
USBCheck, V ariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a serv ice mark of Microchip Technology Incorporated in
the U.S.A.
Silicon S tor age Technology is a regis tered tradema rk of Microchi p
Technology Inc. in other countries.
GestIC i s a registered trademark of Microchi p Technol ogy
Germany II GmbH & Co. KG, a subsidiary of Microchip T echnology
Inc., in other countries.
All ot her trademarks mentioned herein are property of their
respective companies.
© 2005-2017, Microchip Technology I ncorporated, All Rights
Reserved.
ISBN: 978-1-5224-0976-2
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that it s family of products is one of t he most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellec tual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microch ip rece ived IS O/T S-16 94 9:20 09 certificat ion for i ts worldwid e
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPI C® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20005051D-page 32 2005-2017 Microchip Technology Inc.
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