1
LT1185
1185ff
Low Dropout Regulator
■
Low Resistance Pass Transistor: 0.25
Ω
■
Dropout Voltage: 0.75V at 3A
■
±
1% Reference Voltage
■
Accurate Programmable Current Limit
■
Shutdown Capability
■
Internal Reference Available
■
Full Remote Sense
■
Low Quiescent Current: 2.5mA
■
Good High Frequency Ripple Rejection
■
Available in 5-Lead TO-220 and DD Packages
The LT1185 uses a saturation-limited NPN transistor as
the pass element. This device gives the linear dropout
characteristics of a FET pass element with significantly
less die area. High efficiency is maintained by using special
anti-saturation circuitry that adjusts base drive to track
load current. The “on resistance” is typically 0.25Ω.
Accurate current limit is programmed with a single 1/8W
external resistor, with a range of zero to three amperes. A
second, fixed internal limit circuit prevents destructive
currents if the programming current is accidentally over-
ranged. Shutdown of the regulator output is guaranteed
when the program current is less than 1µA, allowing
external logic control of output voltage.
The LT1185 has all the protection features of previous
LTC regulators, including power limiting and thermal
shutdown.
5V, 3A Regulator with 3.5A Current Limit Dropout Voltage
+
–
2.37k
2.67k
2µF
TANT
REF GND
FB
VOUT
VIN LT1185
2µF
TANT
RLIM*
4.3k
+
–
VIN
6V TO 16V VOUT
5V AT 3A
LT1185 • TA01
*CURRENT LIMIT = 15k/R
LIM
= 3.5A
+
+
LOAD CURRENT (A)
0
V
IN
– V
OUT
(V)
0.8
1.0
1.2
4
LT1185 • TA02
0.6
0.4
0123
0.2
1.6
1.4
T
J
= 125°C
T
J
= –55°C
T
J
= 25°C
The LT
®
1185 is a 3A low dropout regulator with adjustable
current limit and remote sense capability. It can be used as
a positive output regulator with floating input or as a
standard negative regulator with grounded input. The
output voltage range is 2.5V to 25V, with ±1% accuracy on
the internal reference voltage.
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATIO
U
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
2
LT1185
1185ff
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
2
4
1
3
GND FB
REF
VIN (CASE)
VOUT
K PACKAGE
4-LEAD TO-3 METAL CAN
BOTTOM VIEW
ORDER PART
NUMBER LT1185MK ORDER PART
NUMBER
LT1185CT
LT1185IT
θ
JC MAX
= 2.5°C/W, θ
JA
= 50°C/W
T PACKAGE
5-LEAD PLASTIC TO-220
REF
VOUT
VIN
FB
GND
FRONT VIEW
TAB IS VIN
5
4
3
2
1
θ
JC MAX
= 2.5°C/W, θ
JA
= 35°C/W
*See Application Section for details on calculating Operation Junction Temperature
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
(Note 1)
OBSOLETE PACKAGE
ORDER PART
NUMBER
LT1185CQ
LT1185IQ
T
JMAX
= 150°C, θ
JA
= 30°C/W
Q PACKAGE
5-LEAD PLASTIC DD
FRONT VIEW
TAB
IS
V
IN
REF
V
OUT
V
IN
FB
GND
5
4
3
2
1
PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Voltage (At FB Pin) 2.37 V
Reference Voltage Tolerance (At FB Pin) (Note 2) V
IN
– V
OUT
= 5V, V
OUT
= V
REF
0.3 ±1%
1mA ≤ I
OUT
≤ 3A ●1±2.5 %
V
IN
– V
OUT
= 1.2V to V
IN
= 30V
P ≤ 25W (Note 6), V
OUT
= 5V
T
MIN
≤ T
J
≤ T
MAX
(Note 9)
Feedback Pin Bias Current V
OUT
= V
REF
●0.7 2 µA
Droput Voltage (Note 3) I
OUT
= 0.5A, V
OUT
= 5V 0.20 0.37 V
I
OUT
= 3A, V
OUT
= 5V 0.67 1.00 V
The ● denotes specifications which apply over the operating temperature range, otherwise specifications are at TA = 25°C.
Adjustable version, VIN = 7.4V, VOUT = 5V, IOUT = 1mA, RLIM = 4.02k, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Input Voltage .......................................................... 35V
Input-Output Differential ......................................... 30V
FB Voltage ................................................................ 7V
REF Voltage .............................................................. 7V
Output Voltage ........................................................ 30V
Output Reverse Voltage ............................................ 2V
Operating Ambient Temperature Range
LT1185C ............................................... 0°C to 70°C
LT1185I ............................................. – 40°C to 85°C
LT1185M (OBSOLETE) .................... –55°C to 125°C
Operating Junction Temperature Range*
Control Section
LT1185C ............................................. 0°C to 125°C
LT1185I .......................................... – 40°C to 125°C
LT1185M (OBSOLETE) ................... –55°C to 150°C
Power Transistor Section
LT1185C ............................................. 0°C to 150°C
LT1185I .......................................... – 40°C to 150°C
LT1185M (OBSOLETE) ................... –55°C to 175°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
3
LT1185
1185ff
The ● denotes specifications which apply over the operating temperature range, otherwise specifications are at TA = 25°C.
Adjustable version, VIN = 7.4V, VOUT = 5V, IOUT = 1mA, RLIM = 4.02k, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Load Regulation (Note 7) I
OUT
= 5mA to 3A 0.05 0.3 %
V
IN
– V
OUT
= 1.5V to 10V, V
OUT
= 5V
Line Regulation (Note 7) V
IN
– V
OUT
= 1V to 20V, V
OUT
= 5V 0.002 0.01 %/V
Minimum Input Voltage I
OUT
= 1A (Note 4), V
OUT
= V
REF
4.0 V
I
OUT
= 3A 4.3 V
Internal Current Limit (See Graph for 1.5V ≤ V
IN
– V
OUT
≤ 10V 3.3 3.6 4.2 A
Guaranteed Curve) (Note 12) ●3.1 4.4 A
V
IN
– V
OUT
= 15V ●2.0 3.0 4.2 A
V
IN
– V
OUT
= 20V ●1.0 1.7 2.6 A
V
IN
– V
OUT
= 30V ●0.2 0.4 1.0 A
External Current Limit 5k ≤ R
LIM
≤ 15k, V
OUT
= 1V ●15k A•Ω
Programming Constant (Note 11)
External Current Limit Error 1A ≤ I
LIM
≤ 3A 0.02 I
LIM
0.06 I
LIM
+ 0.03 A
R
LIM
= 15k • A/I
LIM
●0.04 I
LIM
0.09 I
LIM
+ 0.05 A
Quiescent Supply Current I
OUT
= 5mA, V
OUT
= V
REF
●2.5 3.5 mA
4V ≤ V
IN
≤ 25V (Note 5)
Supply Current Change with Load V
IN
– V
OUT
= V
SAT
(Note 10) ●25 40 mA/A
V
IN
– V
OUT
≥ 2V ●10 25 mA/A
REF Pin Shutoff Current ●0.4 2 7 µA
Thermal Regulation (See Applications V
IN
– V
OUT
= 10V 0.005 0.014 %/W
Information) I
OUT
= 5mA to 2A
Reference Voltage Temperature Coefficient (Note 8) 0.003 0.01 %/°C
Thermal Resistance Junction to Case TO-3 Control Area 1 °C/W
Power Transistor 3 °C/W
TO-220 Control Area 1 °C/W
Power Transistor 3 °C/W
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Reference voltage is guaranteed both at nominal conditions (no
load, 25°C) and at worst-case conditions of load, line, power and
temperature. An intermediate value can be calculated by adding the effects
of these variables in the actual application. See the Applications
Information section of this data sheet.
Note 3: Dropout voltage is tested by reducing input voltage until the
output drops 1% below its nominal value. Tests are done at 0.5A and 3A.
The power transistor looks basically like a pure resistance in this range so
that minimum differential at any intermediate current can be calculated by
interpolation; V
DROPOUT
= 0.25V + 0.25Ω • I
OUT
. For load current less than
0.5A, see graph.
Note 4: “Minimum input voltage” is limited by base emitter voltage drive
of the power transistor section, not saturation as measured in Note 3. For
output voltages below 4V, “minimum input voltage” specification may limit
dropout voltage before transistor saturation limitation.
Note 5: Supply current is measured on the ground pin, and does not
include load current, R
LIM
, or output divider current.
Note 6: The 25W power level is guaranteed for an input-output voltage of
8.3V to 17V. At lower voltages the 3A limit applies, and at higher voltages
the internal power limiting may restrict regulator power below 25W. See
graphs.
Note 7: Line and load regulation are measured on a pulse basis with a
pulse width of ≈2ms, to minimize heating. DC regulation will be affected
by thermal regulation and temperature coefficient of the reference. See
Applications Information section for details.
Note 8: Guaranteed by design and correlation to other tests, but not
tested.
Note 9: T
JMIN
= 0°C for the LT1185C, –40°C for LT1185I, and –55°C for
the LT1185M. Power transistor area and control circuit area have different
maximum junction temperatures. Control area limits are T
JMAX
= 125°C for
the LT1185C and LT1185I and 150°C for the LT1185M. Power area limits
are 150°C for LT1185C and LT1185I and 175°C for LT1185M.
Note 10: V
SAT
is the maximum specified dropout voltage;
0.25V + 0.25 • I
OUT
.
Note 11: Current limit is programmed with a resistor from REF pin to GND
pin. The value is 15k/I
LIM
.
Note 12: For V
IN
– V
OUT
= 1.5V; V
IN
= 5V, V
OUT
= 3.5V. V
OUT
= 1V for all
other current limit tests.
ELECTRICAL CHARACTERISTICS
4
LT1185
1185ff
Ripple Rejection vs Frequency
Ground Pin Current
INPUT-OUTPUT DIFFERENTIAL (V)
0
0
OUTPUT CURRNT (A)
1
2
3
510 15 20
LT1185 • TPC01
25
4
5
30
TYPICAL
TEST POINTS
GUARANTEED
LIMIT
GUARANTEED
LIMIT
Internal Current Limit
INPUT VOLTAGE (V)
0
GROUND PIN CURRENT (mA)
8
10
12
15 25
LT1185 • TPC02
6
4
510 20 30 35
2
0
VOUT = 5V
*DOES NOT INCLUDE REF CURRENT
OR OUTPUT DIVIDER CURRENT
ILOAD = 0
TJ = 25°C
Quiescent Ground Pin Current*
JUNCTION TEMPERATURE (°C)
–50
VOLTAGE (V)
2.37
2.38
2.39
150
LT1185 • TPC03
2.36
2.35
2.33 050 100
2.34
2.41
2.40
–25 25 75 125
Feedback Pin Voltage
Temperature Drift
LOAD CURRENT (A)
0
CURRENT (mA)
80
100
120
4
LT1185 • TPC04
60
40
0123
20
160
140
T
J
= 25°C
REGULATOR JUST AT
DROPOUT POINT
V
IN
– V
OUT
= 5V
FREQUENCY (Hz)
–20
RATIO VOUT/VIN (dB)
–40
–60
–80
–100
100 10k 100k 1M
LT1185 • TPC05
0
1k
ALL OUTPUT
VOLTAGES
WITH 0.05µF
ACROSS R2
VOUT = 5V
VIN – VOUT = 1.5V
Load Transient Response
TIME (µs)
04810
LT1185 • TPC06
26 12 14 16
0.1A t
r
,
f
≤ 100ns
C
OUT
= 2.2µF, ESR = 1Ω
C
OUT
= 2.2µF, ESR = 2Ω
V
OUT
= 5V
I
OUT
= 1A
100mV
∆I
LOAD
Output Impedance
FREQUENCY (Hz)
0.01
IMPEDANCE (Ω)
0.1
1
10
1M10k 100k
LT1183 • TPC07
0.001
1k
OUTPUT IMPEDANCE IS
SET BY OUTPUT CAPACITOR
ESR IN THIS REGION
VOUT = 5V
IOUT = 1A
COUT = 2.2µF
TYPICAL PERFOR A CE CHARACTERISTICS
UW
5
LT1185
1185ff
Block Diagram
A simplified block diagram of the LT1185 is shown in
Figure 1. A 2.37V bandgap reference is used to bias the
input of the error amplifier A1, and the reference amplifier
A2. A1 feeds a triple NPN pass transistor stage which has
the two driver collectors tied to ground so that the main
pass transistor can completely saturate. This topology
normally has a problem with unlimited current in Q1 and
Q2 when the input voltage is less than the minimum
required to create a regulated output. The standard “fix”
for this problem is to insert a resistor in series with Q1 and
Q2 collectors, but this resistor must be low enough in
value to supply full base current for Q3 under worst-case
Figure 1. Block Diagram
300mV I1
2µA
R1
350Ω200mV
D2 D4 D3
–
+
A5
–+
A4
–+
A3
VIN
R2
0.055Ω
–+
A1
–
+
A2
VREF
2.37V
VOUT
FB
GND
RLIM (EXTERNAL)
REF
D1
LT1185 • BD
Q1
Q2
Q3
Q4
conditions, resulting in very high supply current when the
input voltage is low. To avoid this situation, the LT1185
uses an auxiliary emitter on Q3 to create a drive limiting
feedback loop which automatically adjusts the drive to Q1
so that the base drive to Q3 is just enough to saturate Q3,
but no more. Under saturation conditions, the auxiliary
emitter is acting like a collector to shunt away the output
current of A1. When the input voltage is high enough to
keep Q3 out of saturation, the auxiliary emitter current
drops to zero even when Q3 is conducting full load current.
APPLICATIO S I FOR ATIO
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6
LT1185
1185ff
Amplifier A2 is used to generate an internal current through
Q4 when an external resistor is connected from the REF
pin to ground. This current is equal to 2.37V divided by
R
LIM
. It generates a current limit sense voltage across R1.
The regulator will current limit via A4 when the voltage
across R2 is equal to the voltage across R1. These two
resistors essentially form a current “amplifier” with a gain
of 350/0.055 = 6,360. Good temperature drift is inherent
because R1 and R2 are made from the same diffusions.
Their ratio, not absolute value, determines current limit.
Initial accuracy is enhanced by trimming R1 slightly at
wafer level. Current limit is equal to 15kΩ/R
LIM
.
D1 and I
1
are used to guarantee regulator shutdown when
REF pin current drops below 2µA. A current less than 2µA
through Q4 causes the +input of A5 to go low and shut
down the regulator via D2.
A3 is an internal current limit amplifier which can override
the external current limit. It provides “goof proof” protec-
tion for the pass transistor. Although not shown, A3 has
a nonlinear foldback characteristic at input-output volt-
ages above 12V to guarantee safe area protection for Q3.
See the graph, Internal Current Limit in the Typical Perfor-
mance Characteristics of this data sheet.
Setting Output Voltage
The LT1185 output voltage is set by two external resistors
(see Figure 2). Internal reference voltage is trimmed to
2.37V so that a standard 1% 2.37k resistor (R1) can be
used to set divider current at 1mA. R2 is then selected
from:
for R1 = 2.37k and V
REF
= 2.37V, this reduces to:
R2 = V
OUT
– 2.37k
suggested values of 1% resistors are shown.
VOUT R2 WHEN R1 = 2.37k
5V 2.67k
5.2V 2.87k
6V 3.65k
12V 9.76k
15V 12.7k
Output Capacitor
The LT1185 has a collector output NPN pass transistor,
which makes the open-loop output impedance much
higher than an emitter follower. Open-loop gain is a direct
function of load impedance, and causes a main-loop
“pole” to be created by the output capacitor, in addition to
an internal pole in the error amplifier. To ensure loop
stability, the output capacitor must have an ESR (effective
series resistance) which has an upper limit of 2Ω, and a
lower limit of 0.2 divided by the capacitance in µF. A 2µF
output capacitor, for instance, should have a maximum
ESR of 2Ω, and a minimum of 0.2/2 = 0.1Ω. These values
are easily encompassed by standard solid tantalum
capacitors, but occasionally a solid tantalum unit will have
abnormally high ESR, especially at very low tempera-
tures. The suggested 2µF value shown in the circuit
applications should be increased to 4.7µF for – 40°C and
–55°C designs if the 2µF units cannot be guaranteed to
stay below 2Ω at these temperatures.
Although solid tantalum capacitors are suggested, other
types can be used if they meet the ESR requirements.
Standard aluminum electrolytic capacitors need to be
upward of 25µF in general to hold 2Ω maximum ESR,
especially at low temperatures. Ceramic, plastic film, and
monolithic capacitors have a problem with ESR being too
low
. These types should have a 1Ω carbon resistor in
series to guarantee loop stability.
The output capacitor should be located close to the regu-
lator (≤3") to avoid excessive impedance due to lead
inductance. A six inch lead length (2 • 3") will generate an
extra 0.8Ω inductive reactance at 1MHz, and unity-gain
frequency can be up to that value.
For remote sense applications, the capacitor should still be
located close to the regulator. Additional capacitance can
be added at the remote sense point, but the remote
capacitor must be at least 2µF solid tantalum. It cannot be
a low ESR type like ceramic or mylar unless a 0.5Ω to 1Ω
carbon resistor is added in series with the capacitor. Logic
boards with multiple low ESR bypass capacitors should
have a solid tantalum unit added in parallel whose value is
approximately five times the combined value of low ESR
capacitors.
R2 = (VOUT – 2.37) R1
VREF
APPLICATIO S I FOR ATIO
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7
LT1185
1185ff
Large output capacitors (electrolytic or solid tantalum)
will not cause the LT1185 to oscillate, but they will cause
a damped “ringing” at light load currents where the ESR
of the capacitor is several orders of magnitude lower than
the load resistance. This ringing only occurs as a result of
transient load or line conditions and normally causes no
problems because of its low amplitude (≤25mV).
Heat Sinking
The LT1185 will normally be used with a heat sink. The size
of the heat sink is determined by load current, input and
output voltage, ambient temperature, and the thermal
resistance of the regulator, junction-to-case (θ
JC
). The
LT1185 has two separate values for θ
JC
: one for the power
transistor section, and a second, lower value for the
control section. The reason for two values is that the
power transistor is capable of operating at higher continu-
ous temperature than the control circuitry. At low power
levels, the two areas are at nearly the same temperature,
and maximum temperature is limited by the control area.
At high power levels, the power transistor will be at a
significantly higher temperature than the control area
and its maximum operating temperature will be the
limiting factor.
To calculate heat sink requirements, you must solve a
thermal resistance formula twice, one for the power
transistor and one for the control area. The
lowest
value
obtained for heat sink thermal resistance must be used. In
these equations, two values for maximum junction tem-
perature and junction-to-case thermal resistance are used,
as given in Electrical Specifications.
Example: A commercial version of the LT1185 in the
TO-220 package is to be used with a maximum ambient
temperature of 60°C. Output voltage is 5V at 2A. Input
voltage can vary from 6V to 10V. Assume an interface
resistance of 1°C/W.
First solve for control area, where the maximum junction
temperature is 125°C for the TO-220 package, and
θ
JC
= 1°C/W:
Next, solve for power transistor limitation, with
T
JMAX
= 150°C, θ
JC
= 3°C/W:
The lowest number must be used, so heat sink resistance
must be less than 4.2°C/W.
Some heat sink data sheets show graphs of heat sink
temperature rise vs power dissipation instead of listing a
value for thermal resistance. The formula for θ
HS
can be
rearranged to solve for maximum heat sink temperature
rise:
∆T
HS
= T
JMAX
– T
AMAX
– P(θ
JC
+ θ
CHS
)
Using numbers from the previous example:
∆T
HS
= 125°C – 60 – 10.5(1 + 1) = 44°C control
section
∆T
HS
= 150°C – 60 – 10.5(3 + 1) = 48°C power
transistor
The smallest rise must be used, so heat sink temperature
rise must be less than 44°C at a power level of 10.5W.
For board level applications, where heat sink size may be
critical, one is often tempted to use a heat sink which
barely meets the requirements. This is permissible
if
correct assumptions were made concerning maximum
ambient temperature and power levels. One complicating
P = (10V – 5V) (2A) + 2A
40 (10V) = 10.5W
θHS = 125°C – 60°C
10.5W – 1°C/W – 1°C/W = 4.2°C/W
θHS = 150 – 60
10.5 – 3 – 1 = 4.6°C/W
θ
HS
= (T
JMAX
– T
AMAX
)
P– θ
JC
– θ
CHS
.
θ
HS
= Maximum heat sink thermal resistance
θ
JC
= LT1185 junction-to-case thermal resistance
θ
CHS
= Case-to-heat sink (interface) thermal
resistance, including any insulating washers
T
JMAX
= LT1185 maximum operating junction
temperature
T
AMAX
= Maximum ambient temperature in
customers application
P = Device dissipaton
= (V
IN
– V
OUT
) (I
OUT
) + I
OUT
40 (V
IN
)
APPLICATIO S I FOR ATIO
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8
LT1185
1185ff
factor is that local ambient temperature may be somewhat
higher because of the point source of heat. The conse-
quences of excess junction temperature include poor
reliability, especially for plastic packages, and the possi-
bility of thermal shutdown or degraded electrical charac-
teristics. The final design should be checked
in situ
with a
thermocouple attached to the regulator case under worst-
case conditions of high ambient, high input voltage and
full load.
What About Overloads?
IC regulators with thermal shutdown, like the LT1185,
allow heat sink designs which concentrate on worst-case
“normal” conditions and ignore “fault” conditions. An
output overload or short may force the regulator to exceed
its maximum junction temperature rating, but thermal
shutdown is designed to prevent regulator failure under
these conditions. A word of caution however; thermal
shutdown temperatures are typically 175°C in the control
portion of the die and 180°C to 225°C in the power
transistor section. Extended operation at these tempera-
tures can cause permanent degradation of plastic encap-
sulation. Designs which may be subjected to extended
periods of overload should either use the hermetic TO-3
package or increase heat sink size. Foldback current
limiting can be implemented to minimize power levels
under fault conditions.
External Current Limit
The LT1185 requires a resistor to set current limit. The
value of this resistor is 15k divided by the desired current
limit (in amps). The resistor for 2A current limit would be
15k/2A = 7.5k. Tolerance over temperature is ±10%, so
current limit is normally set 15% above maximum load
current. Foldback limiting can be employed if short-circuit
current must be lower than full load current (see Typical
Applications).
The LT1185 has internal current limiting which will over-
ride external current limit if power in the pass transistor
is excessive. The internal limit is ≈3.6A with a foldback
characteristic which is dependent on input-output volt-
age, not output voltage
per se
(see Typical Performace
Characteristics)
.
Ground Pin Current
Ground pin current for the LT1185 is approximately 2mA
plus I
OUT
/40. At I
OUT
= 3A, ground pin current is typically
2mA + 3/40 = 77mA. Worst case guarantees on the ratio of
I
OUT
to ground pin current are contained in the Electrical
Specifications.
Ground pin current can be important for two reasons. It
adds to power dissipation in the regulator and it can affect
load/line regulation if a long line is run from the ground pin
to load ground. The additional power dissipation is found
by multiplying ground pin current by input voltage. In a
typical example, with V
IN
= 8V, V
OUT
= 5V and I
OUT
= 2A, the
LT1185 will dissipate (8V – 5V)(2A) = 6W in the pass
transistor and (2A/40)(8V) = 0.4W in the internal drive
circuitry. This is only a 1.5% efficiency loss, and a 6.7%
increase in regulator power dissipation, but these values
will increase at higher output voltages.
Ground pin current can affect regulation as shown in
Figure 2. Parasitic resistance in the ground pin lead will
create a voltage drop which
increases
output voltage as
load current is increased. Similarly, output voltage can
decrease
as input voltage increases because the “I
OUT
/40”
component of ground pin current drops significantly at
higher input-output differentials. These effects are small
enough to be ignored for local regulation applications, but
APPLICATIO S I FOR ATIO
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Figure 2. Proper Connection of Positive Sense Lead
+
–
R1*
2.37k
R2
REF GND
FB
VOUT
VIN LT1185
RLIM
+
–
VIN
VOUT
LT1185 • F02
LOAD
PARASITIC
LEAD RESISTANCES
– rb +
IGND
ra
*R1 SHOULD BE CONNECTED DIRECTLY TO GROUND LEAD, NOT TO THE LOAD,
SO THAT ra ≈ 0Ω. THIS LIMITS THE OUTPUT VOLTAGE ERROR TO (IGND)(rb).
ERRORS CREATED BY ra ARE MULTIPLIED BY (1 + R2/R1). NOTE THAT VOUT
INCREASES
WITH INCREASING GROUND PIN CURRENT. R2 SHOULD BE CONNECTED
DIRECTLY TO LOAD FOR REMOTE SENSING
9
LT1185
1185ff
APPLICATIO S I FOR ATIO
WUUU
Figure 3. Shutdown Techniques
R
LIM
†
4k
+
–
V
IN
R6
30k
R7
2.4k
†
R1
R2
V
OUT
+
Q1
2N3906
*
LT1185 • F3a
*CMOS LOGIC
†
FOR HIGHER VALUES OF R
LIM
, MAKE R7 = (R
LIM
)(0.6)
5V
R5
300k
+
REF GND
FB
V
OUT
V
IN
LT1185
5V Logic, Positive Regulated Output 5V Logic, Negative Regulated Output
RLIM
–
LT1185 • F03b
REF GND
FB
VOUT
LT1185VIN
R4
33k
5V
“HI” = OUTPUT “OFF”
3 EA 1N4148
VIN
Q1
2N3906
for remote sense applications, they may need to be con-
sidered. Ground lead resistance of 0.4Ω would cause an
output voltage error of up to (3A/40)(0.4Ω) = 30mV, or
0.6% at V
OUT
= 5V. Note that if the sense leads are
connected as shown in Figure 2, with r
a
≈ 0Ω, this error is
a fixed number of millivolts, and does not increase as a
function of DC output voltage.
Shutdown Techniques
The LT1185 can be shut down by open-circuiting the REF
pin. The current flowing into this pin must be less than
0.4µA to guarantee shutdown. Figure 3 details several
ways to create the “open” condition, with various logic
levels. For variations on these schemes, simply remember
that the voltage on the REF pin is 2.4V negative with
respect to the ground pin.
Output Overshoot
Very high input voltage slew rate during start-up may
cause the LT1185 output to overshoot. Up to 20% over-
shoot could occur with input voltage ramp-up rate exceed-
ing 1V/µs. This condition cannot occur with normal 50Hz
to 400Hz rectified AC inputs because parasitic resistance
and inductance will limit rate of rise even if the power
switch is closed at the peak of the AC line voltage. This
assumes that the switch is in the AC portion of the circuit.
If instead, a switch is placed directly in the regulator input
so that a large filter capacitor is precharged, fast input slew
rates will occur on switch closure. The output of the
regulator will slew at a rate set by current limit and output
capacitor size; dVdt = I
LIM
/C
OUT
. With I
LIM
= 3.6A and C
OUT
= 2.2µF, the output will slew at 1.6V/µs and overshoot can
occur. This overshoot can be reduced to a few hundred
millivolts or less by increasing the output capacitor to
10µF and/or reducing current limit so that output slew rate
is held below 0.5V/µs.
A second possibility for creating output overshoot is
recovery from an output short. Again, the output slews at
a rate set by current limit and output capacitance. To avoid
overshoot, the ratio I
LIM
/C
OUT
should be less than
0.5 × 10
6
. Remember that load capacitance can be added
to C
OUT
for this calculation. Many loads will have multiple
supply bypass capacitors that total more than C
OUT
.
10
LT1185
1185ff
Thermal Regulation
IC regulators have a regulation term not found in discrete
designs because the power transistor is thermally coupled
to the reference. This creates a shift in the output voltage
which is proportional to power dissipation in the regulator.
∆V
OUT
= P(K1 + K2 θ
JA
)
= (I
OUT
)(V
IN
– V
OUT
)(K1 + K2 θ
JA
)
K1 and K2 are constants. K1 is a fast time constant effect
caused by die temperature
gradients
which are estab-
lished within 50ms of a power change. K1 is specified on
the data sheet as thermal regulation, in percent per watt.
K2 is a long time constant term caused by the temperature
drift of the regulator reference voltage. It is also specified,
but in percent per degree centigrade. It must be multiplied
by overall thermal resistance, junction-to-ambient, θ
JA
.
As an example, assume a 5V regulator with an input
voltage of 8V, load current of 2A, and a total thermal
resistance of 4°C/W, including junction-to-case, (use
control area specification), interface, and heat sink resis-
tance. K1 and K2, respectively, from the data sheet are
0.014%/W and 0.01%/°C.
∆V
OUT
= (2A)(8V – 5V)(0.014 + 0.01 • 4)
= 0.32%
This shift in output voltage could be in either direction
because K1 and K2 can be either positive or negative.
Thermal regulation is already included in the worst case
reference specification.
Output Voltage Reversal
Some IC regulators suffer from a latch-up state when their
output is forced to a reverse voltage of as little as one diode
drop. The latch-up state can be triggered without a fault
condition when the load is connected to an opposite
polarity supply instead of to ground. If the second supply
is turned on first, it will pull the output of the first supply
to a reverse voltage through the load. The first supply may
then latch off when turned on. This problem is particularly
annoying because the diode clamps which should always
be used to protect against polarity reversal do not usually
stop the latch-up problem.
The LT1185 is designed to allow output reverse polarity of
several volts without damage or latch-up, so that a simple
diode clamp can be used.
APPLICATIO S I FOR ATIO
WUUU
11
LT1185
1185ff
Foldback Current Limiting
–
LT1185 • TA03a
V
IN
R4
5.36k
R3
15k
Q1
2N3906
R1
2.37k
+
–
2µF
TANT
REFGND
FB
V
OUT
LT1185V
IN
+
V
OUT
2µF
TANT
R2
2.61k
+
+
Auxiliary + 12V Low Dropout Regulator for Switching Supply
I
OUT
V
OUT
(NORMALIZED)
0.6
0.8
1.0
LT1185 • TA03b
0.4
0.2
0
1.2
1.4
1.6
I
SHORT-CIRCUIT
= 15k
R3
+I
FULL LOAD
= 15k
R3
10.8k
R4
LT1185 • TA04
RLIM R1
2.37k
R2
9.76k
12V
REGULATED
AUXILIARY
5V
MAIN
OUTPUT
*
*
5V
CONTROL
PRIMARY
*DIODE CONNECTION INDICATES A FLYBACK
SWITCHING TOPOLOGY, BUT FORWARD
CONVERTERS MAY ALSO BE USED
+
+
+
REF GND
FB
VOUT
VIN LT1185
TYPICAL APPLICATIO S
U
12
LT1185
1185ff
Time Delayed Start-Up
Low Input Voltage Monitor Tracks Dropout Characteristics
+
–
REF GND
FB
VOUT
LT1185VIN
RLIM***
D1
D2
R3**
15k
C3*
D3
†
C2
2.2µF
VIN
R2
R1
2.37k
C1
2.2µF
TANT
+
–
VOUT
LT1185 • TA06
ALL DIODES 1N4148
*SEE CHART FOR DELAY TIME VERSUS (C3)(R3//RLIM) PRODUCT
**FOR LONG DELAY TIMES, REPLACE D2 WITH 2N3906 TRANSISTOR AND USE R3 ONLY FOR
CALCULATING DELAY TIME. R3 CAN INCREASE TO 100k
***ILIM IS ≈11k/RLIM, INSTEAD OF 15k, BECAUSE OF VOLTAGE DROP IN D1. TEMPERATURE
COEFFICIENT OF ILIM WILL BE ≈0.11%/°C, SO ADEQUATE MARGIN MUST BE ALLOWED
FOR COLD OPERATION
†
D3 PROVIDES FAST RESET OF TIMING. INPUT MUST DROP TO A LOW VALUE TO RESET TIMING
Q1**
+
+
Delay Time
INPUT VOLTAGE (V)
0
TIME CONSTANTS (t)*
1.5
2.0
2.5
15 25
LT1185 • TA07
1.0
0.5
0510 20
3.0
3.5
4.0
30
*t = (R3//R
LIM
)(C3) =
(
)
R3 • R
LIM
R3 + R
LIM
(C3)
TYPICAL APPLICATIO S
U
R6**
1k
+
–
4k R1
2.37k
R2
2.6k
R7
27k
C1
2.2µF
TANT
V
OUT
–
+
OPTIONAL HYSTERESIS
≈2M
LT1006
†
V
–
V
+
3
2
4
7
“LOW” FOR LOW INPUT
OUTPUT SWINGS FROM V
IN+
TO V
IN–
R3
360k
R4**
1k
R5*
0.01Ω
C2
2.2µF
TANT
REF GND
FB
V
OUT
LT1185V
IN
+
–
V
IN
*3" #26 WIRE
**R4 DETERMINES TRIP POINT AT I
OUT
= 0
R6 DETERMINES INCREASE OF TRIP POINT AS I
OUT
INCREASES
TRIP POINT FOR V
IN
= V
OUT
()
1 + R4 • R7
R3 • R6 + I
OUT
R5 • R7
R6
FOR VALUES SHOWN, TRIP POINT FOR V
IN
IS:
V
OUT
+ 0.37V AT I
OUT
= 0 AND V
OUT
= 1.18V AT I
OUT
= 3A
†
DO NOT SUBSTITUTE. OP AMP MUST HAVE COMMON MODE
RANGE EQUAL TO NEGATIVE SUPPLY
LT1185 • TA05
+
+
13
LT1185
1185ff
R1
5.5k
C1
10pF
R2
3k
R3
3k
R4
520Ω
R5
600Ω
R7
500Ω
R6
750Ω
500Ω
R9
2.7k
Q48
R54
4k
R8
6.5k Q9 Q15 Q16
R11
220Ω
R53
10k
R52
10k
C2
R55
30k
R49
700Ω
R56
600Ω
R50
160Ω
10k
R46
8k
Q36
R47
4k
Q51
Q35
R48
2k
R45
1.3k
R40
1k
R42
50k
R43
50k
R44
5k
C3
30pF
R39
1k
D1
R12
2k
R13
2k
R14
3.2k
R17
6k
R15
4k
R16
1k
R18
2k
Q17 Q18 Q19
Q28
R35
20k
C4
10pF
R37
1k
R38
400Ω
C5
10pF
R34
300Ω
R36
20k R38
20k
R28
0.055Ω
R26
1k
R24
6k
R23
80Ω
R19
20k
D4
V
IN
V
OUT
FB
GND
REF
Q52
R31
200Ω
LT1185 • SD
Q20
Q53
Q21
Q22
Q23
Q24
Q25
Q26
Q27
Q29Q30Q31
Q14Q13
Q8
Q12
Q11
Q6
Q5
Q2
Q4
Q1
Q3
Q49 Q47
Q43
Q44
Q41
Q46
Q40
Q34
Q39
Q37
Q50
Q33 Q32
Q7
Q45
Q42
SCHE ATIC DIAGRA
W
W
14
LT1185
1185ff
U
PACKAGE DESCRIPTIO
K Package
4-Lead TO-3 Metal Can
(Reference LTC DWG # 05-08-1311)
T Package
5-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1421)
K4(TO-3) 0801
72°
18°
.490 – .510
(12.45 – 12.95)
R
.470 TP
P.C.D.
.167 – .177
(4.24 – 4.49)
R
.151 – .161
(3.84 – 4.09)
DIA 2 PLC
.655 – .675
(16.64 – 19.05)
1.177 – 1.197
(29.90 – 30.40)
.038 – .043
(0.965 – 1.09)
.060 – .135
(1.524 – 3.429)
.320 – .350
(8.13 – 8.89)
.420 – .480
(10.67 – 12.19)
.760 – .775
(19.30 – 19.69)
T5 (TO-220) 0801
.028 – .038
(0.711 – 0.965)
.067
(1.70) .135 – .165
(3.429 – 4.191)
.700 – .728
(17.78 – 18.491)
.045 – .055
(1.143 – 1.397)
.095 – .115
(2.413 – 2.921)
.013 – .023
(0.330 – 0.584)
.620
(15.75)
TYP
.155 – .195*
(3.937 – 4.953)
.152 – .202
(3.861 – 5.131)
.260 – .320
(6.60 – 8.13)
.165 – .180
(4.191 – 4.572)
.147 – .155
(3.734 – 3.937)
DIA
.390 – .415
(9.906 – 10.541)
.330 – .370
(8.382 – 9.398)
.460 – .500
(11.684 – 12.700)
.570 – .620
(14.478 – 15.748)
.230 – .270
(5.842 – 6.858)
BSC
SEATING PLANE
* MEASURED AT THE SEATING PLANE
OBSOLETE PACKAGE
15
LT1185
1185ff
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
U
PACKAGE DESCRIPTIO
Q Package
5-Lead Plastic DD Pak
(Reference LTC DWG # 05-08-1461)
Q(DD5) 0502
.028 – .038
(0.711 – 0.965)
TYP
.143 +.012
–.020
()
3.632 +0.305
–0.508
.067
(1.702)
BSC
.013 – .023
(0.330 – 0.584)
.095 – .115
(2.413 – 2.921)
.004 +.008
–.004
()
0.102 +0.203
–0.102
.050 ± .012
(1.270 ± 0.305)
.059
(1.499)
TYP
.045 – .055
(1.143 – 1.397)
.165 – .180
(4.191 – 4.572)
.330 – .370
(8.382 – 9.398)
.060
(1.524)
TYP
.390 – .415
(9.906 – 10.541)
15° TYP
.420
.350
.565
.090
.042
.067
RECOMMENDED SOLDER PAD LAYOUT
.325
.205
.080
.565
.090
RECOMMENDED SOLDER PAD LAYOUT
FOR THICKER SOLDER PASTE APPLICATIONS
.042
.067
.420
.276
.320
NOTE:
1. DIMENSIONS IN INCH/(MILLIMETER)
2. DRAWING NOT TO SCALE
.300
(7.620)
.075
(1.905)
.183
(4.648)
.060
(1.524)
.060
(1.524)
.256
(6.502)
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAT SINK
16
LT1185
1185ff
© LINEAR TECHNOLOGY CORPORATION 1994
LT/LWI 0906 REV F • PRINTED IN USA
Logic Controlled 3A Low-Side Switch with Fault Protection
LT1185 • TA08
REF GND
VOUT
LT1185FB
VIN
5V
LOAD 1N4001
ADD FOR
INDUCTIVE LOADS
RLIM
4k
Improved High Frequency Ripple Rejection
+
–
VOUT
+
–
VIN
LT1185 • TA09
RLIM
C2
2.2µF
TANT
R1
2.37k
R2 C3
0.05µF
C1
4.7µF
TANT
NOTE: C3 IMPOVES HIGH FREQUENCY RIPPLE REJECTION BY 6dB AT VOUT = 5V,
AND BY 14dB AT VOUT = 12V. C1 IS INCREASED TO 4.7µF TO ENSURE GOOD STABILTITY
WHEN C3 IS USED
REF GND
FB
VOUT
LT1185VIN
+
PART NUMBER DESCRIPTION COMMENTS
LT1085 7.5A Low Dropout Regulator 1V Dropout Voltage
LT1117 800mA Low Dropout Regulator with Shutdown Reverse Voltage and Reverse Current Protection
LT1120A Micropower Regulator with Comparator and Shutdown 20µA Supply Current, 2.5V Reference Output
LT1129 200mA Micropower Low Dropout Regulator 400mV Dropout Voltage, 50µA Supply Current
LT1175 500mA Negative Low Dropout Micropower Regulator 45µA Supply Current, Adjustable Current Limit
LT1585 4.6A Low Dropout Fast Transient Response Regulator For High Performance Microprocessors
LT1964 200mA, Low Noise Micropower, Negative LDO V
IN
: –0.9V to –20V, V
OUT(MIN)
= –1.21V, V
DO
= 0.34V, I
Q
= 30µA,
I
SD
= 3µA, ThinSOT Package
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
TYPICAL APPLICATIO S
U
