ASAHI KASEI [AK2548] AK2548 7 channel E1 Transceiver FEATURE * 7ch E1 transceiver * Jitter Tolerance: Compliant with ITU-T G.823, I.431 * Transmitter Pulse Shape: Compliant with ITU-T G.703 * Loss of Signal Detection: Compliant with ITU-T G.775 * Return loss: Compliant with ETS 300 166 * Selectable Signal Polarity * Local/Remote Loopback * Parallel/Serial Microprocessor Interface * Single 3.3V5% Operation * Low Power Consumption * Pin-to-pin compatible with AK2546(7 channel T1 transceiver) except serial interface * Small Plastic Package 144pin LQFP BLOCK DIAGRAM R /W (WR) AD7-AD0 MCLK CLKSEL CLKGEN AS(ALE) DS(RD) CS SCLK SDI SDO INT CONTROL RESET TEST1-4 P/S BTS TRANSCEIVER 1 RECOVER TTIP1 SHAPER TRING1 RTIP2-7 Remote Loopback Local Loopback RTIP1 RRING1 LOS1 LOS TRANSCEIVER 2-7 RCLK1 RPOS RNEG1 TCLK1 TPOS TNEG1 LOS2-7 RCLK2-7 RPOS2-7 RNEG2-7 RRING2-7 TTIP2-7 TCLK2-7 TPOS2-7 TNEG2-7 TRING2-7 7 Channel E1 Transceiver Block Diagram C0028-E-00 1 1999/9 ASAHI KASEI [AK2548] GENERAL DESCRIPTION The AK2548 is the 7 channel E1 transceiver for a SDH/SONET MUX, M13 MUX, etc. It includes seven independent transmitters, clock and data recovery, LOS detector, control circuit in one LQFP-144 package which saves space, power consumption and the board design time. Internally generated transmit pulse provides the appropriate pulse shape. 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 AVSS8 TTIP7 TVSS7 TVDD7 TRING7 AVSS7 TTIP6 TVSS6 TVDD6 TRING6 AVSS6 TTIP5 TVSS5 TVDD5 TRING5 AVSS5 TTIP4 TVSS4 TVDD4 TRING4 AVSS4 TTIP3 TVSS3 TVDD3 TRING3 AVSS3 TTIP2 TVSS2 TVDD2 TRING2 AVSS2 TTIP1 TVSS1 TVDD1 TRING1 AVSS1 PIN ASSIGNMENTS (TOP VIEW) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 RNEG1 TCLK2 TPOS2 TNEG2 RCLK2 RPOS2 RNEG2 IOVDD1 IOVSS1 TAVDD1 TAVSS1 TCLK3 TPOS3 TNEG3 RCLK3 RPOS3 RNEG3 DAVSS1 DVSS1 DVDD1 TCLK4 TPOS4 TNEG4 RCLK4 RPOS4 RNEG4 LOS1 LOS2 LOS3 LOS4 RAVDD1 R/W(WR) AS(ALE)/SCLK DS(RD)/SDI CS INT PVDD MCLK PVSS RAVSS2 RAVDD2 RESET RRING7 RTIP7 BTS RRING6 RTIP6 TEST4 RRING5 RTIP5 TEST3 BVSS BGREF BVDD TEST2 RRING4 RTIP4 P/S RRING3 RTIP3 CLKSEL RRING2 RTIP2 TEST1 RRING1 RTIP1 RAVSS1 TCLK7 TPOS7 TNEG7 RCLK7 RPOS7 RNEG7 TCLK6 TPOS6 TNEG6 RCLK6 RPOS6 RNEG6 IOVDD2 IOVSS2 TAVDD2 TAVSS2 TCLK5 TPOS5 TNEG5 RCLK5 RPOS5 RNEG5 DAVSS2 DVSS2 DVDD2 LOS7 LOS6 LOS5 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7/SDO C0028-E-00 2 1999/9 ASAHI KASEI [AK2548] PIN CONDITION Pin No. Pin Name 1 TCLK7 I CMOS 2 TPOS7 I CMOS 3 TNEG7 I CMOS 4 RCLK7 O CMOS 15pF 5 RPOS7 O CMOS 15pF 6 RNEG7 O CMOS 15pF 7 TCLK6 I CMOS 8 TPOS6 I CMOS 9 TNEG6 I CMOS 10 RCLK6 O CMOS 15pF 11 RPOS6 O CMOS 15pF 12 RNEG6 O CMOS 15pF 13 IOVDD2 I Power 14 IOVSS2 I Power 15 TAVDD2 I Power 16 TAVSS2 I Power 17 TCLK5 I CMOS 18 TPOS5 I CMOS 19 TNEG5 I CMOS 20 RCLK5 O CMOS 15pF 21 RPOS5 O CMOS 15pF 22 RNEG5 O CMOS 15pF 23 DAVSS2 I Power 24 DVSS2 I Power 25 DVDD2 I Power 26 LOS7 O CMOS 15pF 27 LOS6 O CMOS 15pF 28 LOS5 O CMOS 15pF 29 AD0 I/O CMOS 50pF 30 AD1 I/O CMOS 50pF 31 AD2 I/O CMOS 50pF 32 AD3 I/O CMOS 50pF 33 AD4 I/O CMOS 50pF 34 AD5 I/O CMOS 50pF 35 AD6 I/O CMOS 50pF 36 AD7/SDO I/O CMOS 50pF C0028-E-00 I/O Pin Type AC Load 3 DC Load Comments 1999/9 ASAHI KASEI [AK2548] Pin No. Pin Name I/O Pin Type 37 R/W(WR) I CMOS 38 AS(ALE)/SCLK I CMOS 39 DS(RD)/SDI I CMOS 40 CS I CMOS 41 INT O Open drain AC Load DC Load Comments PMOS open drain 42 PVDD I Power 43 MCLK I CMOS 44 PVSS I Power 45 RAVSS2 I Power 46 RAVDD2 I Power 47 RESET I CMOS 48 RRING7 I Analog 49 RTIP7 I Analog 50 BTS I CMOS 51 RRING6 I Analog 52 RTIP6 I Analog 53 TEST4 I CMOS 54 RRING5 I Analog 55 RTIP5 I Analog 56 TEST3 I CMOS 57 BVSS I Power 58 BGREF O Analog 59 BVDD I Power 60 TEST2 I CMOS 61 RRING4 I Analog 62 RTIP4 I Analog 63 P/S I CMOS 64 RRING3 I Analog 65 RTIP3 I Analog 66 CLKSEL I CMOS 67 RRING2 I Analog 68 RTIP2 I Analog 69 TEST1 I CMOS 70 RRING1 I Analog 71 RTIP1 I Analog 72 RAVSS1 I Power C0028-E-00 Note 1 Note 1 12k 1% accuracy Note 1 Note 1 4 1999/9 ASAHI KASEI [AK2548] Pin No. Pin Name I/O 73 RAVDD1 I Power 74 LOS4 O CMOS 15pF 75 LOS3 O CMOS 15pF 76 LOS2 O CMOS 15pF 77 LOS1 O CMOS 15pF 78 RNEG4 O CMOS 15pF 79 RPOS4 O CMOS 15pF 80 RCLK4 O CMOS 15pF 81 TNEG4 I CMOS 82 TPOS4 I CMOS 83 TCLK4 I CMOS 84 DVDD1 I Power 85 DVSS1 I Power 86 DAVSS1 I Power 87 RNEG3 O CMOS 15pF 88 RPOS3 O CMOS 15pF 89 RCLK3 O CMOS 15pF 90 TNEG3 I CMOS 91 TPOS3 I CMOS 92 TCLK3 I CMOS 93 TAVSS1 I Power 94 TAVDD1 I Power 95 IOVSS1 I Power 96 IOVDD1 I Power 97 RNEG2 O CMOS 15pF 98 RPOS2 O CMOS 15pF 99 RCLK2 O CMOS 15pF 100 TNEG2 I CMOS 101 TPOS2 I CMOS 102 TCLK2 I CMOS 103 RNEG1 O CMOS 15pF 104 RPOS1 O CMOS 15pF 105 RCLK1 O CMOS 15pF 106 TNEG1 I CMOS 107 TPOS1 I CMOS 108 TCLK1 I CMOS C0028-E-00 Pin Type AC Load 5 DC Load Comments 1999/9 ASAHI KASEI [AK2548] Pin No. Pin Name I/O Pin Type 109 AVSS1 I Power 110 TRING1 O Analog 111 TVDD1 I Power 112 TVSS1 I Power 113 TTIP1 O Analog 114 AVSS2 I Power 115 TRING1 O Analog 116 TVDD2 I Power 117 TVSS2 I Power 118 TTIP2 O Analog 119 AVSS3 I Power 120 TRING3 O Analog 121 TVDD3 I Power 122 TVSS3 I Power 123 TTIP3 O Analog 124 AVSS4 I Power 125 TRING4 O Analog 126 TVDD4 I Power 127 TVSS4 I Power 128 TTIP4 O Analog 129 AVSS5 I Power 130 TRING5 O Analog 131 TVDD5 I Power 132 TVSS5 I Power 133 TTIP5 O Analog 134 AVSS6 I Power 135 TRING6 O Analog 136 TVDD6 I Power 137 TVSS6 I Power 138 TTIP6 O Analog 139 AVSS7 I Power 140 TRING7 O Analog 141 TVDD7 I Power 142 TVSS7 I Power 143 TTIP7 O Analog 144 AVSS8 I Power AC Load DC Load Comments driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output driver output Note 1)Should be connected to VSS externally. C0028-E-00 6 1999/9 ASAHI KASEI [AK2548] PIN FUNCTION Pin Name I/O Function Comment E1 Transceiver TTIP1-7 O Transmit Tip/Ring Output TRING1-7 O Bipolar output over transmit transformer TPOS1-7 I Transmit Positive/Negative Data Input TNEG1-7 I Input on the falling edge of TCLK TCLK1-7 I Transmit Clock Input RTIP1-7 I Receive Tip/Ring Input RRING1-7 I Bipolar Input over receive transformer RPOS1-7 O Receive Positive/Negative Data Output RNEG1-7 O Output on the falling edge of RCLK RCLK1-7 O Receive Clock Output recovered from receive data input LOS1-7 O Loss of signal output Output "high" when detect loss of signal LOSx output is not masked by MLOSx register. TVDD1-7 Positive Power Supply for the Transmit Driver TVSS1-7 Negative Power Supply for the Transmit Driver AVSS1-8 Analog ground . Common Block MCLK I 2.048/32.768MHz External Reference Clock Input AS(ALE) I Address Select(Address Latch Enable) Input INT O Interrupt Output(PMOS open drain, should be tied to GND through a resistor), Active High, INT output goes "high" when the alarm is reported to any one of LOSx, LOTCx or LOMC registers. This pin can be masked by MLOSx, MLOTCx or MLOMC registers. DS(RD) I Data Strobe(Read Enable) Input R/W (WR) I Read/Write(Write Enable) Input CS I Chip Select Input BTS I Bus Type Select Input BTS="H" : Motorola Mode BTS="L" : Intel Mode SCLK I Serial Clock Input SDI I Serial Data Input SDO O Serial Data Output AD0-AD7 I/O Address/Data Input/Output Used for read/write internal registers. C0028-E-00 7 1999/9 ASAHI KASEI Pin Name [AK2548] I/O Function Comment Common Block CLKSEL I MCLK Select Input CLKSEL="H":2.048MHz CLKSEL="L":34.768MHz P/S I Parallel/Serial Port Select P/S="H": Serial Port is selected P/S="L": Parallel Port is selected RESET I Reset Input Active "Low" input pulse over 200ns initializes the internal circuit and forces RPOSx/RNEGx output "low" and LOSx output "high". TEST1,2,3,4 I Factory Use. Should be connected to VSS externally. TAVDD1,2 Positive Power Supply for the analog circuitry in the transmitters TAVSS1,2 Negative Power Supply for the analog circuitry in the transmitters RAVDD1,2 Positive Power Supply for the analog circuitry in the receivers RAVSS1,2 Negative Power Supply for the analog circuitry in the receivers DVDD1,2 Positive Power Supply for Digital DVSS1,2 Negative Power Supply for Digital DAVSS1,2 Ground for Digital IOVDD1,2 Positive Power Supply for I/O IOVSS1,2 Negative Power Supply for I/O BVDD Positive Power Supply for Reference Circuit BVSS Negative Power Supply for Reference Circuit PVDD Positive Power Supply for PLL PVSS Negative Power Supply for PLL BGREF Bandgap Reference Output. 12k1% exeternal register should be connected across this pin and VSS. C0028-E-00 8 1999/9 ASAHI KASEI [AK2548] ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min DC Supply VDD Input Voltage VIN1 Typ Max Units -0.3 6.5 V -0.3 VDD+0.3 V Condition Apply to except for RTIPx, RRINGx VIN2 Input Current IIN Storage Temperature Tstg -3 -55 VDD+0.3 V 10 mA 130 C Apply to RTIPx, RRINGx Note) All voltages with respect to ground. All negative voltage pins=0V. VDD apply to all positive voltage pins. RECOMMENDED OPERATING CONDITIONS Parameter Symbol min typ max Units DC Supply V+ 3.135 3.3 3.465 V Ambient Operating Temperature Ta -40 25 +85 C Condition 3.3V5% Note) All voltages with respect to ground. All negative voltage pins=0V. VDD apply to all positive voltage pins. ELECTORICAL CHARACTERISTICS DC CHARACTERISTICS Parameter Power Consumption(/ch) Symbol 75 min PD 120 typ max 75 160 mW Note1 70 147 mW Digital High-Level Output Voltage VOH Digital Low-Level Output Voltage VOL Digital High-Level Input Voltage VIH Digital Low-Level Input Voltage VIL 0.3VDD V Ii 10 A Input Leak Current Output Current Note1: 0.9VDD Units 0.4 0.7VDD IOH Condition V IOH=-40A V IOL=500A V 1.0 mA INT pin typ: 50% mark, Room temp., VDD 3.3V max: 100% mark, Temp./VDD in all range Not include any other load(ex. External pull up register) except lines. C0028-E-00 9 1999/9 ASAHI KASEI [AK2548] RECEIVER Receiver characteristics are guaranteed on the conditions as shown below. VDD=3.3V5%, VSS, GND=0V,Ta=-40~85C, MCLK frequency: 2.048MHz100ppm, 32.768MHz100ppm. Bipolar input frequency:2.048MHz50ppm(reference input level: 2.37V0p10%@75system, 3V0p10%@120system) Parameter Symbol Min Typ Max Units Condition Input Impedance 5 k Sensitivity -6 dB Note1 Note2 Loss of Signal Threshold 75 0.28 0.4 0.55 V 120 0.35 0.5 0.7 V 170 175 180 bits 12 dB Allowable Consecutive Zeros before LOS S/X tolerance Generated Jitter 16 Low pulse density immunity 1/16 Note3 nspp Note4 Mark ITU-T G.823 Jitter Tolerance Note1: Relative value to the reference level. Compare at 1.024MHz with All mark pattern. Note2: Level at the line side of transformer. Loss of signal is logical OR between an analog loss of signal monitors input level and a digital loss of signal check recovered data stream. Note3: PN15 and AMI 1/4 Mark pattern input. Noise frequency is 1MHz. Note4: PN15 pattern input. Jitter Amplitude(UIpp) Jitter Tolerance(G.823) 36.9 1.5 0.2 1.2x10-5Hz C0028-E-00 Jitter Frequency 10 20Hz 2.4kHz 18kHz 100kHz 1999/9 ASAHI KASEI [AK2548] TRANSMITTER Transmitter characteristics are guaranteed on the conditions as shown below. VDD=3.3V5%,VSS,GND=0V,Ta=-40~85C, MCLK frequency:2.048MHz100ppm, 32.768MHz100ppm Parameter Symbol Min Typ Max Units G.703 Output Pulse Shape Output Pulse Amplitude 75 120 Pulse Amplitude for a 75 space 120 Output Pulse Imbalance amplitudes widths Output Jitter Condition 2.14 2.37 2.60 V0p 2.7 3.0 3.3 V0p -0.237 -0.3 0.237 0.3 V0p V0p -4 -4 4 4 % % 0.05 UIpp 20Hz-100kHz Note 1 Note 1 Return Loss 51kHz-102kHz 9 dB 102kHz-2.048MHz 15 dB 2.048MHz-3.072MHz 11 dB Note1: Turns Ratio, DCR and external resistors are recommended value. (P27) Pulse Mask Template (G.703) 20% 194 ns (244 - 50) 20% V = 100% 10% 10% 269 ns (244 + 25) Nominal pulse 50% 10% 10% 219 ns (244 - 25) 20% 0% 10% 10% 244 ns 488 ns (244 + 244) Note - V corresponds to the nominal peak value. Mask of the pulse at the 2048 kbit/s interface C0028-E-00 11 1999/9 ASAHI KASEI [AK2548] AC CHARACTERISTICS(Clock/Data) Parameter Clock Frequency Clock Pulse Width Symbol MCLK TCLK fci Min Typ Max Units Condition 2.047795 2.048000 2.048204 MHz 100ppm 32.76472 32.76800 32.77127 MHz 244 ns Refer to Fig.2 244 ns Refer to Fig.1 50 % Note1 150 ns Refer to Fig.1 50 ns Refer to Fig.2 ns Refer to Fig.3 tpwhi tpwli Clock Pulse Width RCLK tpwho tpwlo Duty Cycle RCLK TCLK Setup/Hold Time RCLK tsu1 RPOS th1 RNEG Setup/Hold Time TCLK tsu2 TPOS th2 TNEG Rise Time RCLK tr 100 RPOS Note2 RNEG Fall Time TCLK tf 40 TPOS ns Refer to Fig.3 Note2 TNEG Note1) Duty Cycle:(tpwho/( tpwho+tpwlo))x100% Note2) Drive 15pF Load Capacitance C0028-E-00 12 1999/9 ASAHI KASEI [AK2548] tpwho tpwlo 50% 50% RCLK 50% tsur RPOS/RNEG thr 50% Figure 1. Receiver Timing tpwli tpwhi tsut TPOS/TNEG 50% 50% 50% TCLK tht 50% Figure 2. Transmitter Timing tr tf 90% 90% 10% 10% Figure 3. Rise and Fall Times (RCLK,RPOS,RNEG,TCLK,TPOS,TNEG) C0028-E-00 13 1999/9 ASAHI KASEI [AK2548] AC CHARACTERISTICS(Parallel Port) Parameter Symbol Min tcyc 250 Address Setup Time t1 10 -- -- ns Address Hold Time t2 10 -- -- ns AS to DS Delay Time t3 20 -- -- ns DS to AS Delay Time t4 20 -- -- ns Read Data Delay Time t5 -- -- 40 ns Read Data Hold Time t6 -- -- 20 ns R/W Setup Time t7 10 -- -- ns R/W Hold Time t8 10 -- -- ns CS Setup Time t9 10 -- -- ns CS Hold Time t10 15 -- -- ns DS to Write Data Setup Time t11 40 -- -- ns DS to Write Data Hold Time t12 20 -- -- ns DS Pulse Width t13 100 -- -- ns AS Pulse Width t14 20 -- -- ns Address Invalid to DS Delay Time t15 0 -- -- ns Address Setup Time t21 10 -- -- ns Address Hold Time t22 10 -- -- ns ALE to WR Delay Time t23 20 -- -- ns WR to ALE Delay Time t24 20 -- -- ns RD to ALE Delay Time t25 20 -- -- ns Read Data Delay Time t26 -- -- 40 ns Read Data Hold Time t27 -- -- 20 ns CS Setup Time t28 10 -- -- ns CS Hold Time t29 15 -- -- ns DS to Write Data Setup Time t30 40 -- -- ns DS to Write Data Hold Time t31 20 -- -- ns RD Pulse Width t32 100 -- -- ns WR Pulse Width t33 100 -- -- ns ALE Pulse Width t34 20 -- -- ns Address Invalid to RD Delay Time t35 0 -- -- ns Read/Write Cycle Typ Max Units Condition ns Motorola Mode Intel Mode Notes) CL= 50pF on AD0-AD7. All of the timing is specified at 50%VDD. C0028-E-00 14 1999/9 ASAHI KASEI [AK2548] Motorola Mode(READ) CS t10 t9 t13 DS t14 AS AD7-0 t1 t5 t4 t2 Address R/W t6 Data t15 t7 t8 Motorola Mode(WRITE) CS t10 t9 t13 DS t14 AS AD7-0 R/W C0028-E-00 t1 t3 t4 t2 t11 t12 Data Address t7 t8 15 1999/9 ASAHI KASEI [AK2548] Intel Mode(READ) CS t28 t29 WR t34 t25 t26 ALE t21 AD7-0 t22 t27 Address Data t35 t32 RD Intel Mode(WRITE) CS t29 t28 t33 WR t34 t23 t24 ALE t21 AD7-0 t22 t30 t31 Data Address RD C0028-E-00 16 1999/9 ASAHI KASEI [AK2548] AC CHARACTERISTICS(Serial Port) Parameter Symbol min typ max Units SDI Setup Time tp1 25 -- -- ns SDI Hold Time tp2 25 -- -- ns SCLK Low Time tp3 100 -- -- ns SCLK High Time tp4 100 -- -- ns SCLK Rise Time tp5 -- -- 15 ns SCLK Fall Time tp6 -- -- 15 ns CS Setup Time tp7 20 -- -- ns CS Hold Time Tp8 20 -- -- ns CS Inactive Time tp9 100 -- -- ns SCLK to SDO Valid tp10 -- -- 40 ns CS to SDO High Z tp11 -- -- 40 Ns Condition Notes) CL= 50pF. All of the timing is specified at 50%VDD. Serial Port Input Timing tp9 CS tp7 tp4 tp3 tp8 SCLK tp1 SDI tp2 LSB MSB Serial Port Output Timing tp8 CS SCLK 1 2 3 8 9 10 14 15 16 7 8 tp10 SDO High-Z 1 tp5 tp11 2 High-Z tp6 SCLK C0028-E-00 17 1999/9 ASAHI KASEI [AK2548] REGISTER DESCRIPTION REGISTER MAP *A7-A4="0" Address A3 A2 A1 Function A0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 <AD7> <AD6> <AD5> <AD4> <AD3> <AD2> <AD1> <AD0> 0 Status Register (READ ONLY) 0 0 0 0 0 0 0 1 LOS7 LOS6 LOS5 LOS4 LOS3 LOS2 LOS1 (1) (1) (1) (1) (1) (1) (1) LOTC7 LOTC6 LOTC5 LOTC4 LOTC3 LOTC2 LOTC1 LOMC (1) (1) (1) (1) (1) (1) (1) (1) Mask Control Register (WRITE/READ) 0 0 0 0 1 1 0 1 MLOS7 MLOS6 MLOS5 MLOS4 MLOS3 MLOS2 MLOS1 RDEN (1) (1) (1) (1) (1) (1) (1) (0) MLOTC7 MLOTC6 MLOTC5 MLOTC4 MLOTC3 MLOTC2 MLOTC1 MLOMC (1) (1) (1) (1) (1) (1) (1) (1) Channel Control Register (WRITE/READ) 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved TAOS1 EC1 RLOOP1 LLOOP1 POLN1 MSK1 PD1 (0) (0) (0) (0) (1) (1) (1) TAOS2 EC2 RLOOP2 LLOOP2 POLN2 MSK2 PD2 (0) (0) (0) (0) (1) (1) (1) TAOS3 EC3 RLOOP3 LLOOP3 POLN3 MSK3 PD3 (0) (0) (0) (0) (1) (1) (1) TAOS4 EC4 RLOOP4 LLOOP4 POLN4 MSK4 PD4 (0) (0) (0) (0) (1) (1) (1) TAOS5 EC5 RLOOP5 LLOOP5 POLN5 MSK5 PD5 (0) (0) (0) (0) (1) (1) (1) TAOS6 EC6 RLOOP6 LLOOP6 POLN6 MSK6 PD6 (0) (0) (0) (0) (1) (1) (1) TAOS7 EC7 RLOOP7 LLOOP7 POLN7 MSK7 PD7 (0) (0) (0) (0) (1) (1) (1) *Other address is reserved. * Initial value is in ( ). * "<>" show I/O pin name. C0028-E-00 Address A0-A3 should be input via AD0-AD3 pins. 18 1999/9 ASAHI KASEI [AK2548] STATUS REGISTER Symbol LOSx (x=1 to 7) LOTCx (x=1 to 7) LOMC Description Loss of signal alarm for channel x. Read only register. When the loss of signal or the loss of MCLK are detected, LOSx goes High. Loss of TCLK alarm for channel x. Read only register. When the loss of TCLKx is detected, LOTCx goes High. Loss of MCLK alarm. Read only register. When the loss of MCLK is detected, LOMC and LOSx go High. MASK CONTROL REGISTER Symbol MLOSx (x=1 to 7) MLOTCx (x=1 to 7) MLOMC Description Mask loss of signal alarm for channel x. MLOSx is active-high to prevent LOSx from setting INT output "high" . It is possible to read LOSx register regardless of the status of MLOSx. Initial value is "high". Mask loss of TCLK alarm for channel x . MLOTCx is active-high to prevent LOTCx from setting INT output "high" . It is possible to read LOTCx register regardless of the status of MLOTCx. Initial value is "high". Mask loss of MCLK alarm. MLOMC is active-high to prevent LOMC from setting INT output "high" . It is possible to read LOMC register regardless of the status of MLOMC. Initial value is "high". Note) Please refer to "Loss of MCLK theory of operation". (P25) CHANNEL CONTROL REGISTER Symbol RLOOPx/ LLOOPx POLNx PDx MSKx RDEN TAOSx ECx C0028-E-00 Description Loopback mode of channel x is activated through the setting of these register as shown below in Table 1. TIPx/RINGx output polarity is controlled by this register as shown below in Table 2. Initial value is "high". PDx is active-high to set the corresponding transceiver in power down mode. TTIPx and TRINGx go "low". LOSx goes "high" in power down mode. Initial value is "high". MSKx is active-high to prevent LOSx or LOTCx from setting INT output "high". Initial value is "high". RDEN is active-high to prevent RCLK, RPOS, and RNEG output from forcing to "low" or "high" by the detection of Loss of signal. Initial value is "low". TAOS is active-high to output all one's signal from TTIPx and TRINGx. All one's signal synchronized with TCLK. When TCLK is lost, the signal synchronized with MCLK. Application is selected by this register in Table 3. Initial value is low. 19 1999/9 ASAHI KASEI [AK2548] Table 1. Loopback mode Select RLOOPx LLOOPx Function 0 0 Normal 0 1 Local Loop back 1 0 Remote Loop back 1 1 Inhibited (Initial value) Table 2. TIPx/RINGx Polarity Control POLNx POSx/NEGx TIPx/RINGx 1 0 space 1 mark 0 mark 1 space 0 Table 3 Equalizer Control ECx Application 0 E1-Coax(75) 1 E1-Twisted Pair(120) C0028-E-00 (Initial value) 20 1999/9 ASAHI KASEI [AK2548] OUTPUT CONTROL * : don't care LOS: LOSx output and LOSx register Reset, Loss of MCLK, Power down RESET MCLK PD TAOS POLN Loopback Local Remote RDEN TCLK Receive TTIP RCLK Signal TRING RPOS LOS RNEG 0 * * * * * * * * * 0 0 0 1 1 loss * * * * 1 * * * 0 0 0 1 1 loss * * * * 0 * * * 0 0 1 1 1 clocked 1 * * * 1 * * * 0 0 0 1 1 clocked 1 * * * 0 * * * 0 0 1 1 RPOS LOS Normal Operation(RESET=1, MCLK:clocked, PD=0) TAOS Loopback POLN Local Remote 0 0 0 1 RDEN * TCLK Clocked Receive TTIP signal TRING in TPOS RCLK RNEG RCLK TNEG 0 0 0 1 0 Clocked loss TPOS RTIP 0 RRING 0 0 1 RCLK RTIP 0 TNEG 0 0 0 1 * Loss in 0 RRING 0 0 0 1 0 Loss loss 0 0 0 1 0 0 0 1 1 Clocked loss TPOS RCLK RTIP 1 TNEG 0 0 0 1 1 Loss loss 0 RRING RCLK RTIP 1 RRING 0 0 0 0 * Clocked in TPOS RCLK TNEG 0 0 0 0 0 Clocked loss TPOS RTIP 0 RRING 0 1 1 0RCLK RTIP 0 TNEG 0 0 0 0 * Loss in 0 RRING 0 0 0 0 0 Loss loss 0 0 1 1 0 0 0 0 1 clocked loss TPOS RCLK RTIP 1 TNEG 0 0 0 0 1 loss loss 0 RRING RCLK RTIP 1 RRING C0028-E-00 21 1999/9 ASAHI KASEI [AK2548] Normal Operation(RESET=1, MCLK:clocked, PD=0) TAOS Loopback POLN Local Remote 0 0 1 1 RDEN * TCLK clocked Receive TTIP signal TRING in All Mark RCLK RPOS LOS RNEG RCLK RTIP 0 RRING 1 0 0 1 0 clocked loss All Mark 0 0 1 1 0 0 1 * loss in All Mark RCLK RTIP 0 RRING 1 0 0 1 0 loss loss All Mark 0 0 1 1 0 0 1 1 clocked loss All Mark RCLK RTIP 1 RRING 1 0 0 1 1 loss loss All Mark RCLK RTIP 1 RRING 1 0 0 0 * clocked in All Mark RCLK RTIP 0 RRING 1 0 0 0 0 clocked loss All Mark 0 1 1 1 0 0 0 * loss in All Mark RCLK RTIP 0 RRING 1 0 0 0 0 loss loss All Mark 0 1 1 1 0 0 0 1 clocked loss All Mark RCLK RTIP 1 RRING 1 0 0 0 1 loss loss All Mark RCLK RTIP 1 RRING C0028-E-00 22 1999/9 ASAHI KASEI [AK2548] Remote Loopback(RESET=1, MCLK:clocked, PD=0) TAOS Loopback POLN Local Remote 0 1 0 1 RDEN * TCLK * Receive TTIP signal TRING in RTIP RCLK 0 1 1 0 * loss RTIP LOS RNEG RCLK RRING 0 RPOS RTIP 0 RRING 0 0 1 RCLK RTIP 1 RRING 0 0 1 1 1 * loss RTIP RRING 0 0 1 0 * * in RTIP RRING RCLK RRING 0 0 1 0 0 * loss RTIIP RTIP 0 RRING 0 1 1 RCLK RTIP 1 RRING 0 0 1 0 1 * loss RTIP RRING RRING Remote Loopback(RESET=1, MCLK:clocked, PD=0) Loopback TAOS POLN Local Remote 0 1 1 1 RDEN * TCLK * Receive TTIP signal TRING in All Mark RCLK RPOS LOS RNEG RCLK RTIP 0 RRING 1 0 1 1 0 * loss All Mark 0 0 1 1 0 1 1 1 * loss All Mark RCLK RTIP 1 RRING 1 0 1 0 * * in All Mark RCLK RTIP 0 RRING 1 0 1 0 0 * loss All Mark 0 1 1 1 0 1 0 1 * loss All Mark RCLK RTIP 1 RRING C0028-E-00 23 1999/9 ASAHI KASEI [AK2548] Local Loopback(RESET=1, MCLK:clocked, PD=0) TAOS Loopback POLN Local Remote 1 0 0 0 1 0 1 1 RDEN * * TCLK clocked clocked Receive TTIP signal TRING in TPOS TCLK TPOS TNEG (Note) TNEG TPOS TCLK TPOS TNEG (Note) TNEG loss RCLK RPOS LOS RNEG 0 1 0 1 0 1 * loss in 0 0 0 0 0 1 0 1 * loss loss 0 0 0 1 0 1 0 0 * clocked in TPOS TCLK TPOS 0 TNEG (Note) TNEG TPOS TCLK TPOS TNEG (Note) TNEG 0 1 0 0 * clocked loss 1 0 1 0 0 * loss in 0 0 1 0 0 1 0 0 * loss loss 0 0 1 1 Receive TTIP RCLK RPOS LOS signal TRING in All Mark Note) The phase satisfy receive output timing. Local Loopback(RESET=1, MCLK:clocked, PD=0) TAOS POLN Loopback Local Remote 1 0 1 1 1 0 1 1 RDEN * * TCLK clocked clocked loss All Mark RNEG TCLK TPOS (Note) TNEG TCLK TPOS (Note) TNEG 0 1 1 1 0 1 * loss in All Mark 0 0 0 1 1 0 1 * loss loss All Mark 0 0 1 1 1 0 0 * clocked in All Mark TCLK TPOS 0 (Note) TNEG TCLK TPOS (Note) TNEG 1 1 0 0 * clocked loss All Mark 1 1 1 0 0 * loss in All Mark 0 1 0 1 1 0 0 * loss loss All Mark 0 1 1 Note) The phase satisfy receive output timing. C0028-E-00 24 1999/9 ASAHI KASEI [AK2548] THEORY OF OPERATION Loss of signal Loss of signal in channel x is reported by setting LOSx register "high". The receiver will indicate loss of signal upon receiving 175 consecutive zeros or detecting input level being below the threshold(ALOS). LOSx returns to "low" when the received signal returns to 12.5% ones density and not include 100 consecutive zeros. When Loss of Signal is detected in channel x, LOSx register is set "high" and LOSx pin becomes "high". When LOSx is set "high", interrupt will be issued on INT pin if MLOSx is "low". LOSx pin becomes high regardless of MLOSx status. MLOSx is active-high and masks LOSx interrupt. LOSx register represents the current status of received signal regardless of the status of the MLOSx status. Loss of TCLK Loss of TCLKx is reported by setting LOTCx "high". When LOTCx is set "high", INT output becomes "high" if MLOTCx is "low". Even if TCLK return to normal quickly, LOTCx remain "high" for 126us. MLOTCx is active-high and masks LOTCx interrupt. LOTCx represents the current status of TCLKx and can be read regardless of the status of the MLOTCx status. When Loss of TCLKx is detected, TTIPx/TRINGx will be forced to "0". Loss of MCLK Loss of MCLK is reported by setting LOMC "high". When LOMC goes "high", INT output becomes "high" if MLOMC is "low". Even if MCLK return to normal quickly, LOMC remain "high" for 126us. MLOMC is active-high and masks LOMC interrupt. LOMC represents the current status of MCLK and can be read regardless of MLOMC status. When the loss of MCLK is detected, LOSx register and LOSx pin goes "high" at the same time. Therefore all MLOSx register must be set to "high" to prevent loss of MCLK from setting INT output. INT output INT output goes "high" when the alarm is reported to any one of LOSx, LOTCx or LOMC registers. This pin can be masked by MLOSx, MLOTCx or MLOMC registers. C0028-E-00 25 1999/9 ASAHI KASEI [AK2548] Local Loopback In Local Loopback mode, TPOSx,TNEGx,TCLKx signals are looped back to RPOSx, RNEGx, RCLKx output. RTIPx,RRINGx inputs are ignored but loss of signal detection is active. The transmitter in channel x outputs TTIPx,TRINGx normally. Remote Loopback In Remote Loopback mode, RTIPx/RRINGx signals are looped back to TTIPx/TRINGx output. The receiver in channel x output RPOSx,RNEGx,RCLKx normally and detect loss of signal. TPOSx,TNEGx,TCLKx inputs are ignored. When TAOSx is "high", all mark signal is output to TTIPx/TRINGx. Interface Interface to control/status register is selected by P/S pin. interface is selected. When P/S is set to "low", parallel When P/S is set to "high", serial interface is selected. Parallel Interface Bus type(Intel/Motorola) is selected by BTS pin. When BTS is set to "high", Motorola mode is selected. When BTS is set to "low", Intel mode is selected. Serial Interface The timing of serial interface is shown below. CS SCLK SDI R/W A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 SDO High-Z D0 D1 D2 D3 D4 D5 D6 D7 R/W=1: read R/W=0: write C0028-E-00 26 1999/9 ASAHI KASEI [AK2548] RECOMMENDED EXTERNAL CIRCUIT Transmit Circuit AK2548 C1 1:N R1 TTIPx C2 R2 TRINGx Trans Rate R1.R2 C1 C2 75 1:2 8.21% 1uF 470pF 120 1:2.2 9.11% 1uF 470pF Received Circuit AK2548 Rp R1 2:1 RTIPx R3 Rp R4 R2 RRINGx R1,R2 R3,R4 Rp 75 20 130 100 120 82 160 *Rp is protection resistance against surge. Rp is used for surge current limiting. (ITU-T K.41) Recommended Transformer Specification Turns Primary Leakage Ratio Inductance Inductance (Typ) (Min) (Max) Tx Rx C0028-E-00 75 120 1:2 1:2.2 1:2 720uH 720uH 1.2mH 0.3uH 0.3uH 0.3uH 27 Interwinding Capacitance (Max) DCR (Max) pri sec 30pF 30pF 30pF 0.6 0.6 0.6 1.2 1.3 1.2 1999/9 ASAHI KASEI [AK2548] Reference current circuit To determine input reference current, connect 12k1% resistor. AK2548 R1 BGREF R1=12k1% Power Supply To attenuate the power supply noise, connect capacitors between VDD and VSS respectively. The value of the capacitance AK2548 need depend on the condition of the power supply line. Please decide the value of the capacitance after your evaluation. VDD AK2548 C1 Pin name C1 RAVDD1-RAVSS1, RAVDD2-RAVSS2, BVDD-BVSS, 1uF TAVDD1-TAVSS1, TAVDD2-TAVSS2 TVDD1-TVSS1, TVDD2-TVSS2, TVDD3-TVSS3, TVDD4-TVSS4, TVDD5-TVSS5, IOVSS1, TVDD6-TVSS6, IOVDD2-IOVSS2, TVDD7-TVSS7, DVDD1-DVSS1, 0.01uF IOVDD1- DVDD2-DVSS2, PVDD-PVSS C0028-E-00 28 1999/9 ASAHI KASEI [AK2548] PACKAGE 144pin LQFP OUTPUT DIMENSIONS 22.0 20.0 108 73 109 20.0 AK2548 XXXXXXX JAPAN 37 144 1 36 0.10 M 0.20 0.10 0.17 0.04 0.50 0.07 1.70 Max 1.40 22.0 72 C0028-E-00 0.10 0~10 0.500.1 29 1999/9 ASAHI KASEI [AK2548] IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. C0028-E-00 30 1999/9