ASAHI KASEI [AK2548]
C0028-E-00 1999/9
1
AK2548
7 channel E1 Transceiver
FEATURE
• 7ch E1 transceiver
• Jitter Tolerance: Compliant with ITU-T G.823, I.431
• Transmitter Pulse Shape: Compliant with ITU-T G.703
• Loss of Signal Detection: Compliant with ITU-T G.775
• Return loss: Compliant with ETS 300 166
• Selectable Signal Polarity
• Local/Remote Loopback
• Parallel/Serial Microprocessor Interface
• Single 3.3V±5% Operation
• Low Power Consumption
• Pin-to-pin compatible with AK2546(7 channel T1 transceiver) except serial interface
• Small Plastic Package 144pin LQFP
BLOCK DIAGRAM
7 Channel E1 Transceiver Block Diagram
R /W (WR)
TRANSCEIVER 1
TRANSCEIVER 2-7
RECOVER
CLKGEN
MCLK
RTIP1
RRING1
AS(ALE)
RCLK1
RPOS
RNEG1
LOS1
RTIP2-7
RRING2-7
LOS2-7
RCLK2-7
RPOS2-7
RNEG2-7
TCLK2-7
TPOS2-7
TNEG2-7
TEST1-4
SHAPER
TTIP1
TRING1
TNEG1
TPOS
TCLK1
CONTROL
TTIP2-7
TRING2-7
AD7-AD0
RESET
Local Loopback
Remote Loopback
CS
BTS
INT
LOS
CLKSEL
P/S
SCLK
SDI
SDO
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
2
GENERAL DESCRIPTION
The AK2548 is the 7 channel E1 transceiver for a SDH/SONET MUX, M13 MUX, etc.
It includes seven independent transmitters, clock and data recovery, LOS detector, control circuit
in one LQFP-144 package which saves space, power consumption and the board design time.
Internally generated transmit pulse provides the appropriate pulse shape.
PIN ASSIGNMENTS
TCLK7
TPOS7
TNEG7
RCLK7
RPOS7
RNEG7
TCLK6
TPOS6
TNEG6
RCLK6
RPOS6
RNEG6
IOVDD2
IOVSS2
TAVDD2
TAVSS2
TCLK5
TPOS5
TNEG5
RCLK5
RPOS5
RNEG5
DAVSS2
DVSS2
DVDD2
LOS7
LOS6
LOS5
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7/SDO
TCLK1
TPOS1
TNEG1
RCLK1
RPOS1
RNEG1
TCLK2
TPOS2
TNEG2
RCLK2
RPOS2
RNEG2
IOVDD1
IOVSS1
TAVDD1
TAVSS1
TCLK3
TPOS3
TNEG3
RCLK3
RPOS3
RNEG3
DAVSS1
DVSS1
DVDD1
TCLK4
TPOS4
TNEG4
RCLK4
RPOS4
RNEG4
LOS1
LOS2
LOS3
LOS4
RAVDD1
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
AVSS8
TTIP7
TVSS7
TVDD7
TRING7
AVSS7
TTIP6
TVSS6
TVDD6
TRING6
AVSS6
TTIP5
TVSS5
TVDD5
TRING5
AVSS5
TTIP4
TVSS4
TVDD4
TRING4
AVSS4
TTIP3
TVSS3
TVDD3
TRING3
AVSS3
TTIP2
TVSS2
TVDD2
TRING2
AVSS2
TTIP1
TVSS1
TVDD1
TRING1
AVSS1
R/W(WR)
AS(ALE)/SCLK
DS(RD)
/SDI
CS
INT
PVDD
MCLK
PVSS
RAVSS2
RAVDD2
RESET
RRING7
RTIP7
BTS
RRING6
RTIP6
TEST4
RRING5
RTIP5
TEST3
BVSS
BGREF
BVDD
TEST2
RRING4
RTIP4
P/S
RRING3
RTIP3
CLKSEL
RRING2
RTIP2
TEST1
RRING1
RTIP1
RAVSS1
(TOP VIEW)
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
3
PIN CONDITION
Pin No. Pin Name I/O Pin Type AC Load DC Load Comments
1TCLK7 ICMOS
2TPOS7 ICMOS
3TNEG7 ICMOS
4RCLK7 OCMOS ≤15pF
5RPOS7 O CMOS ≤15pF
6RNEG7 OCMOS ≤15pF
7TCLK6 ICMOS
8TPOS6 ICMOS
9TNEG6 ICMOS
10 RCLK6 OCMOS ≤15pF
11 RPOS6 O CMOS ≤15pF
12 RNEG6 OCMOS ≤15pF
13 IOVDD2 IPower
14 IOVSS2 IPower
15 TAVDD2 IPower
16 TAVSS2 IPower
17 TCLK5 ICMOS
18 TPOS5 ICMOS
19 TNEG5 ICMOS
20 RCLK5 OCMOS ≤15pF
21 RPOS5 O CMOS ≤15pF
22 RNEG5 OCMOS ≤15pF
23 DAVSS2 IPower
24 DVSS2 IPower
25 DVDD2 IPower
26 LOS7 OCMOS ≤15pF
27 LOS6 OCMOS ≤15pF
28 LOS5 OCMOS ≤15pF
29 AD0 I/O CMOS ≤50pF
30 AD1 I/O CMOS ≤50pF
31 AD2 I/O CMOS ≤50pF
32 AD3 I/O CMOS ≤50pF
33 AD4 I/O CMOS ≤50pF
34 AD5 I/O CMOS ≤50pF
35 AD6 I/O CMOS ≤50pF
36 AD7/SDO I/O CMOS ≤50pF
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
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Pin No. Pin Name I/O Pin Type AC Load DC Load Comments
37 R/W(WR) ICMOS
38 AS(ALE)
/SCLK
ICMOS
39 DS(RD)/SDI ICMOS
40 CS ICMOS
41 INT OOpen drain PMOS
open drain
42 PVDD IPower
43 MCLK ICMOS
44 PVSS IPower
45 RAVSS2 IPower
46 RAVDD2 IPower
47 RESET ICMOS
48 RRING7 IAnalog
49 RTIP7 IAnalog
50 BTS ICMOS
51 RRING6 IAnalog
52 RTIP6 IAnalog
53 TEST4 ICMOS Note 1
54 RRING5 IAnalog
55 RTIP5 IAnalog
56 TEST3 ICMOS Note 1
57 BVSS IPower
58 BGREF OAnalog 12kΩ
±
1% accuracy
59 BVDD IPower
60 TEST2 ICMOS Note 1
61 RRING4 IAnalog
62 RTIP4 IAnalog
63 P/S ICMOS
64 RRING3 IAnalog
65 RTIP3 IAnalog
66 CLKSEL ICMOS
67 RRING2 IAnalog
68 RTIP2 IAnalog
69 TEST1 ICMOS Note 1
70 RRING1 IAnalog
71 RTIP1 IAnalog
72 RAVSS1 IPower
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
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Pin No. Pin Name I/O Pin Type AC Load DC Load Comments
73 RAVDD1 IPower
74 LOS4 OCMOS ≤15pF
75 LOS3 OCMOS ≤15pF
76 LOS2 OCMOS ≤15pF
77 LOS1 OCMOS ≤15pF
78 RNEG4 OCMOS ≤15pF
79 RPOS4 O CMOS ≤15pF
80 RCLK4 OCMOS ≤15pF
81 TNEG4 ICMOS
82 TPOS4 ICMOS
83 TCLK4 ICMOS
84 DVDD1 IPower
85 DVSS1 IPower
86 DAVSS1 IPower
87 RNEG3 OCMOS ≤15pF
88 RPOS3 O CMOS ≤15pF
89 RCLK3 OCMOS ≤15pF
90 TNEG3 ICMOS
91 TPOS3 ICMOS
92 TCLK3 ICMOS
93 TAVSS1 IPower
94 TAVDD1 IPower
95 IOVSS1 IPower
96 IOVDD1 IPower
97 RNEG2 OCMOS ≤15pF
98 RPOS2 O CMOS ≤15pF
99 RCLK2 OCMOS ≤15pF
100 TNEG2 ICMOS
101 TPOS2 ICMOS
102 TCLK2 ICMOS
103 RNEG1 OCMOS ≤15pF
104 RPOS1 O CMOS ≤15pF
105 RCLK1 OCMOS ≤15pF
106 TNEG1 ICMOS
107 TPOS1 ICMOS
108 TCLK1 ICMOS
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
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Pin No. Pin Name I/O Pin Type AC Load DC Load Comments
109 AVSS1 IPower
110 TRING1 OAnalog driver output
111 TVDD1 IPower
112 TVSS1 IPower
113 TTIP1 OAnalog driver output
114 AVSS2 IPower
115 TRING1 OAnalog driver output
116 TVDD2 IPower
117 TVSS2 IPower
118 TTIP2 OAnalog driver output
119 AVSS3 IPower
120 TRING3 OAnalog driver output
121 TVDD3 IPower
122 TVSS3 IPower
123 TTIP3 OAnalog driver output
124 AVSS4 IPower
125 TRING4 OAnalog driver output
126 TVDD4 IPower
127 TVSS4 IPower
128 TTIP4 OAnalog driver output
129 AVSS5 IPower
130 TRING5 OAnalog driver output
131 TVDD5 IPower
132 TVSS5 IPower
133 TTIP5 OAnalog driver output
134 AVSS6 IPower
135 TRING6 OAnalog driver output
136 TVDD6 IPower
137 TVSS6 IPower
138 TTIP6 OAnalog driver output
139 AVSS7 IPower
140 TRING7 OAnalog driver output
141 TVDD7 IPower
142 TVSS7 IPower
143 TTIP7 OAnalog driver output
144 AVSS8 IPower
Note 1)Should be connected to VSS externally.
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
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PIN FUNCTION
Pin Name I/O Function Comment
E1 Transceiver
TTIP1-7
TRING1-7 O
OTransmit Tip/Ring Output
Bipolar output over transmit transformer
TPOS1-7
TNEG1-7 I
ITransmit Positive/Negative Data Input
Input on the falling edge of TCLK
TCLK1-7 ITransmit Clock Input
RTIP1-7
RRING1-7 I
IReceive Tip/Ring Input
Bipolar Input over receive transformer
RPOS1-7
RNEG1-7 O
OReceive Positive/Negative Data Output
Output on the falling edge of RCLK
RCLK1-7 OReceive Clock Output recovered from receive data input
LOS1-7 OLoss of signal output
Output “high” when detect loss of signal
LOSx output is not masked by MLOSx register.
TVDD1-7 Positive Power Supply for the Transmit Driver
TVSS1-7 Negative Power Supply for the Transmit Driver
AVSS1-8 Analog ground .
Common Block
MCLK I2.048/32.768MHz External Reference Clock Input
AS(ALE) IAddress Select(Address Latch Enable) Input
INT OInterrupt Output(PMOS open drain, should be tied to GND through
a resistor), Active High, INT output goes “high” when the alarm is
reported to any one of LOSx, LOTCx or LOMC registers. This pin can
be masked by MLOSx, MLOTCx or MLOMC registers.
DS(RD) IData Strobe(Read Enable) Input
R/W (WR) IRead/Write(Write Enable) Input
CS IChip Select Input
BTS IBus Type Select Input
BTS=“H” : Motorola Mode
BTS=“L” : Intel Mode
SCLK ISerial Clock Input
SDI ISerial Data Input
SDO OSerial Data Output
AD0-AD7 I/O Address/Data Input/Output
Used for read/write internal registers.
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
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Pin Name I/O Function Comment
Common Block
CLKSEL IMCLK Select Input
CLKSEL=“H”:2.048MHz
CLKSEL=“L”:34.768MHz
P/S IParallel/Serial Port Select
P/S=“H”: Serial Port is selected
P/S=“L”: Parallel Port is selected
RESET IReset Input
Active “Low” input pulse over 200ns initializes the internal circuit
and forces RPOSx/RNEGx output “low” and LOSx output “high”.
TEST1,2,3,4
IFactory Use. Should be connected to VSS externally.
TAVDD1,2 Positive Power Supply for the analog circuitry in the transmitters
TAVSS1,2 Negative Power Supply for the analog circuitry in the transmitters
RAVDD1,2 Positive Power Supply for the analog circuitry in the receivers
RAVSS1,2 Negative Power Supply for the analog circuitry in the receivers
DVDD1,2 Positive Power Supply for Digital
DVSS1,2 Negative Power Supply for Digital
DAVSS1,2 Ground for Digital
IOVDD1,2 Positive Power Supply for I/O
IOVSS1,2 Negative Power Supply for I/O
BVDD Positive Power Supply for Reference Circuit
BVSS Negative Power Supply for Reference Circuit
PVDD Positive Power Supply for PLL
PVSS Negative Power Supply for PLL
BGREF Bandgap Reference Output.
12kΩ±1% exeternal register should be connected across this pin and
VSS.
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
9
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Typ Max Units Condition
DC Supply VDD -0.3 6.5 V
VIN1-0.3 VDD+0.3 VApply to except for RTIPx,
RRINGx
Input Voltage
VIN2 -3 VDD+0.3 VApply to RTIPx, RRINGx
Input Current IIN 10 mA
Storage Temperature Tstg -55 130 ºC
Note) All voltages with respect to ground.
All negative voltage pins=0V. VDD apply to all positive voltage pins.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol min typ max Units Condition
DC Supply V+ 3.135 3.3 3.465 V3.3V±5%
Ambient Operating Temperature Ta -40 25 +85 ºC
Note) All voltages with respect to ground.
All negative voltage pins=0V. VDD apply to all positive voltage pins.
ELECTORICAL CHARACTERISTICS
DC CHARACTERISTICS
Parameter Symbol min typ max Units Condition
Power Consumption(/ch) 75Ω
120Ω
PD 75
70
160
147
mW
mW
Note1
Digital High-Level Output Voltage VOH 0.9VDD VIOH=-40µA
Digital Low-Level Output Voltage VOL 0.4 VIOL=500µA
Digital High-Level Input Voltage VIH 0.7VDD V
Digital Low-Level Input Voltage VIL 0.3VDD V
Input Leak Current Ii 10 µA
Output Current IOH1.0 mA INT pin
Note1: typ: 50% mark, Room temp., VDD 3.3V
max: 100% mark, Temp./VDD in all range
Not include any other load(ex. External pull up register) except lines.
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
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RECEIVER
Receiver characteristics are guaranteed on the conditions as shown below.
VDD=3.3V±5%, VSS, GND=0V,Ta=-40~85ºC,
MCLK frequency: 2.048MHz±100ppm, 32.768MHz±100ppm.
Bipolar input frequency:2.048MHz±50ppm(reference input level: 2.37V0p±10%@75Ωsystem,
3V0p±10%@120Ωsystem)
Parameter Symbol Min Typ Max Units Condition
Input Impedance 5kΩ
Sensitivity -6 dB Note1
Loss of Signal Threshold 75Ω
120Ω
0.28
0.35
0.4
0.5
0.55
0.7
V
V
Note2
Allowable Consecutive Zeros before LOS 170 175 180 bits
S/X tolerance 12 dB Note3
Generated Jitter 16 nspp Note4
Low pulse density immunity 1/16 Mark
Jitter Tolerance ITU-T G.823
Note1: Relative value to the reference level. Compare at 1.024MHz with All mark pattern.
Note2: Level at the line side of transformer. Loss of signal is logical OR between an analog loss of signal
monitors input level and a digital loss of signal check recovered data stream.
Note3: PN15 and AMI 1/4 Mark pattern input. Noise frequency is 1MHz.
Note4: PN15 pattern input.
Jitter Tolerance(G.823)
20Hz
2.4kHz
18kHz 100kHz
1.2×10
-5
Hz
36.9
1.5
0.2
Jitter Frequency
Jitter Amplitude(UIpp)
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
11
TRANSMITTER
Transmitter characteristics are guaranteed on the conditions as shown below.
VDD=3.3V±5%,VSS,GND=0V,Ta=-40~85ºC, MCLK frequency:2.048MHz±100ppm, 32.768MHz±100ppm
Parameter Symbol Min Typ Max Units Condition
Output Pulse Shape G.703
Output Pulse Amplitude 75Ω
120Ω
2.14
2.7
2. 37
3.0
2.60
3.3
V0p
V0p
Note 1
Pulse Amplitude for a
space 75Ω
120Ω
-0.237
-0.30. 237
0.3V0p
V0p
Note 1
Output Pulse Imbalance amplitudes
widths -4
-4 4
4%
%
Output Jitter 20Hz-100kHz 0.05 UIpp
Return Loss
51kHz-102kHz
102kHz-2.048MHz
2.048MHz-3.072MHz
9
15
11
dB
dB
dB
Note1: Turns Ratio, DCR and external resistors are recommended value. (P27)
Pulse Mask Template (G.703)
269 ns
(244 + 25)
194 ns
(244 – 50)
244 ns
219 ns
(244 – 25)
488 ns
(244 + 244)
10%10%
10%10%
0%
50%
10%10%
20%20%
V = 100%
20%
Nominal pulse
Note
– V corresponds to the nominal peak value.
Mask of the pulse at the 2048 kbit/s interface
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
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AC CHARACTERISTICS(Clock/Data)
Parameter Symbol Min Typ Max Units Condition
Clock Frequency MCLK fci 2. 047795
32.76472
2. 048000
32.76800
2.048204
32.77127
MHz
MHz
±100ppm
Clock Pulse Width TCLK tpwhi
tpwli
244 ns Refer to Fig.2
Clock Pulse Width RCLK tpwho
tpwlo
244 ns Refer to Fig.1
Duty Cycle RCLK
TCLK
50 %Note1
Setup/Hold Time RCLK
RPOS
RNEG
tsu1
th1
150 ns Refer to Fig.1
Setup/Hold Time TCLK
TPOS
TNEG
tsu2
th2
50 ns Refer to Fig.2
Rise Time tr100 ns Refer to Fig.3
Note2
Fall Time
RCLK
RPOS
RNEG
TCLK
TPOS
TNEG
tf40 ns Refer to Fig.3
Note2
Note1) Duty Cycle:(tpwho/( tpwho+tpwlo))×100%
Note2) Drive 15pF Load Capacitance
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
13
Figure 1. Receiver Timing
Figure 2. Transmitter Timing
Figure 3. Rise and Fall Times
(RCLK,RPOS,RNEG,TCLK,TPOS,TNEG)
tpwho tpwlo
tsur thr
RCLK
RPOS/RNEG
50%
50% 50%
50%
trtf
10% 10%
90% 90%
tsut tht
tpwhi tpwli
50% 50%
50%
50%
TCLK
TPOS/TNEG
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
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AC CHARACTERISTICS(Parallel Port)
Parameter Symbol Min Typ Max Units Condition
Read/Write Cycle tcyc 250 ns
Motorola Mode
Address Setup Time t1 10 — — ns
Address Hold Time t2 10 — — ns
AS to DS Delay Time t3 20 — — ns
DS to AS Delay Time t4 20 — — ns
Read Data Delay Time t5 — — 40 ns
Read Data Hold Time t6 — — 20 ns
R/W Setup Time t7 10 — — ns
R/W Hold Time t8 10 — — ns
CS Setup Time t9 10 — — ns
CS Hold Time t10 15 — — ns
DS to Write Data Setup Time t11 40 — — ns
DS to Write Data Hold Time t12 20 — — ns
DS Pulse Width t13 100 — — ns
AS Pulse Width t14 20 — — ns
Address Invalid to DS Delay Time t15 0— — ns
Intel Mode
Address Setup Time t21 10 — — ns
Address Hold Time t22 10 — — ns
ALE to WR Delay Time t23 20 — — ns
WR to ALE Delay Time t24 20 — — ns
RD to ALE Delay Time t25 20 — — ns
Read Data Delay Time t26 — — 40 ns
Read Data Hold Time t27 — — 20 ns
CS Setup Time t28 10 — — ns
CS Hold Time t29 15 — — ns
DS to Write Data Setup Time t30 40 — — ns
DS to Write Data Hold Time t31 20 — — ns
RD Pulse Width t32 100 — — ns
WR Pulse Width t33 100 — — ns
ALE Pulse Width t34 20 — — ns
Address Invalid to RD Delay Time t35 0— — ns
Notes) CL= 50pF on AD0-AD7. All of the timing is specified at 50%VDD.
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
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Motorola Mode(READ)
CS
DS
AS
AD7-0
R/W
Address
Data
t1
t2
t13
t8
t6
t7
t9
t10
CS
DS
AS
AD7-0
R/W
Address
Data
t1
t2
t3
t13
t12
t7
t9
t10
t8
Motorola Mode(WRITE)
t14
t11
t14
t5
t4
t4
t15
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
16
Intel Mode(READ)
CS
WR
ALE
AD7-0
RD
Address
Data
t21
t22
t34
t26
t27
t28
t29
CS
WR
ALE
AD7-0
RD
Address
Data
t21
t22
t31
t28
t29
t30
Intel Mode(WRITE)
t33
t24
t32
t25
t34
t23
t35
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
17
AC CHARACTERISTICS(Serial Port)
Parameter Symbol min typ max Units Condition
SDI Setup Time tp1 25 — — ns
SDI Hold Time tp2 25 — — ns
SCLK Low Time tp3 100 — — ns
SCLK High Time tp4 100 — — ns
SCLK Rise Time tp5 — — 15 ns
SCLK Fall Time tp6 — — 15 ns
CS Setup Time tp7 20 — — ns
CS Hold Time Tp8 20 — — ns
CS Inactive Time tp9 100 — — ns
SCLK to SDO Valid tp10 — — 40 ns
CS to SDO High Z tp11 — — 40 Ns
Notes) CL= 50pF. All of the timing is specified at 50%VDD.
Serial Port Input Timing
Serial Port Output Timing
CS
SCLK
SDI
tp4
tp7 tp3
tp1 tp2
tp9
tp8
LSB MSB
1
2
3
8
9
10
16
15
14
1
2
7
8
CS
SCLK
SDO
tp10
tp8
tp11
SCLK
tp5 tp6
High-Z High-Z
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
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REGISTER DESCRIPTION
REGISTER MAP
*A7-A4=“0”
Address Function
A3 A2 A1 A0 Bit7
<AD7>
Bit6
<AD6>
Bit5
<AD5>
Bit4
<AD4>
Bit3
<AD3>
Bit2
<AD2>
Bit1
<AD1>
Bit0
<AD0>
Status Register (READ ONLY)
0 0 0 0 LOS7
(1)
LOS6
(1)
LOS5
(1)
LOS4
(1)
LOS3
(1)
LOS2
(1)
LOS1
(1)
0
0 0 0 1 LOTC7
(1)
LOTC6
(1)
LOTC5
(1)
LOTC4
(1)
LOTC3
(1)
LOTC2
(1)
LOTC1
(1)
LOMC
(1)
Mask Control Register (WRITE/READ)
0 0 1 0 MLOS7
(1)
MLOS6
(1)
MLOS5
(1)
MLOS4
(1)
MLOS3
(1)
MLOS2
(1)
MLOS1
(1)
RDEN
(0)
0 0 1 1 MLOTC7
(1)
MLOTC6
(1)
MLOTC5
(1)
MLOTC4
(1)
MLOTC3
(1)
MLOTC2
(1)
MLOTC1
(1)
MLOMC
(1)
Channel Control Register (WRITE/READ)
0 1 1 0 Reserved TAOS1
(0)
EC1
(0)
RLOOP1
(0)
LLOOP1
(0)
POLN1
(1)
MSK1
(1)
PD1
(1)
0 1 1 1 Reserved TAOS2
(0)
EC2
(0)
RLOOP2
(0)
LLOOP2
(0)
POLN2
(1)
MSK2
(1)
PD2
(1)
1 0 0 0 Reserved TAOS3
(0)
EC3
(0)
RLOOP3
(0)
LLOOP3
(0)
POLN3
(1)
MSK3
(1)
PD3
(1)
1 0 0 1 Reserved TAOS4
(0)
EC4
(0)
RLOOP4
(0)
LLOOP4
(0)
POLN4
(1)
MSK4
(1)
PD4
(1)
1 0 1 0 Reserved TAOS5
(0)
EC5
(0)
RLOOP5
(0)
LLOOP5
(0)
POLN5
(1)
MSK5
(1)
PD5
(1)
1 0 1 1 Reserved TAOS6
(0)
EC6
(0)
RLOOP6
(0)
LLOOP6
(0)
POLN6
(1)
MSK6
(1)
PD6
(1)
1 1 0 0 Reserved TAOS7
(0)
EC7
(0)
RLOOP7
(0)
LLOOP7
(0)
POLN7
(1)
MSK7
(1)
PD7
(1)
*Other address is reserved.
* Initial value is in ( ).
* “<>” show I/O pin name. Address A0-A3 should be input via AD0-AD3 pins.
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
19
STATUS REGISTER
Symbol Description
LOSx
(x=1 to 7)
Loss of signal alarm for channel x. Read only register.
When the loss of signal or the loss of MCLK are detected, LOSx goes High.
LOTCx
(x=1 to 7)
Loss of TCLK alarm for channel x. Read only register.
When the loss of TCLKx is detected, LOTCx goes High.
LOMC Loss of MCLK alarm. Read only register.
When the loss of MCLK is detected, LOMC and LOSx go High.
MASK CONTROL REGISTER
Symbol Description
MLOSx
(x=1 to 7)
Mask loss of signal alarm for channel x.
MLOSx is active-high to prevent LOSx from setting INT output “high” .
It is possible to read LOSx register regardless of the status of MLOSx.
Initial value is “high”.
MLOTCx
(x=1 to 7)
Mask loss of TCLK alarm for channel x .
MLOTCx is active-high to prevent LOTCx from setting INT output “high” .
It is possible to read LOTCx register regardless of the status of MLOTCx.
Initial value is “high”.
MLOMC Mask loss of MCLK alarm.
MLOMC is active-high to prevent LOMC from setting INT output “high” .
It is possible to read LOMC register regardless of the status of MLOMC.
Initial value is “high”.
Note) Please refer to “Loss of MCLK theory of operation”. (P25)
CHANNEL CONTROL REGISTER
Symbol Description
RLOOPx/
LLOOPx
Loopback mode of channel x is activated through the setting of these register
as shown below in Table 1.
POLNx TIPx/RINGx output polarity is controlled by this register as shown below in
Table 2. Initial value is “high”.
PDx PDx is active-high to set the corresponding transceiver in power down mode.
TTIPx and TRINGx go “low”. LOSx goes “high” in power down mode.
Initial value is “high”.
MSKx MSKx is active-high to prevent LOSx or LOTCx from setting INT output
“high”. Initial value is “high”.
RDEN RDEN is active-high to prevent RCLK, RPOS, and RNEG output from
forcing to “low” or “high” by the detection of Loss of signal. Initial value is
“low”.
TAOSx TAOS is active-high to output all one’s signal from TTIPx and TRINGx.
All one’s signal synchronized with TCLK. When TCLK is lost, the signal
synchronized with MCLK.
ECx Application is selected by this register in Table 3. Initial value is low.
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
20
Table 1. Loopback mode Select
RLOOPx LLOOPx Function
0 0 Normal (Initial value)
0 1 Local Loop back
1 0 Remote Loop back
1 1 Inhibited
Table 2. TIPx/RINGx Polarity Control
POLNx POSx/NEGx TIPx/RINGx
0space1
1mark
0mark0
1space
Table 3 Equalizer Control
ECx Application
0E1-Coax(75Ω) (Initial value)
1E1-Twisted Pair(120Ω)
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
21
OUTPUT CONTROL
* : don’t care
LOS: LOSx output and LOSx register
Reset, Loss of MCLK, Power down
LoopbackRESET MCLK PD TAOS
Local Remote
POLN RDEN TCLK Receive
Signal
TTIP
TRING
RCLK RPOS
RNEG
LOS
0* * * * * * * * * 0 0 0 1
1loss * * * * 1* * * 0 0 0 1
1loss * * * * 0* * * 0 0 1 1
1clocked 1***1* * * 0 0 0 1
1clocked 1***0* * * 0 0 1 1
Normal Operation(RESET=1, MCLK:clocked, PD=0)
LoopbackTAOS
Local Remote
POLN RDEN TCLK Receive
signal
TTIP
TRING
RCLK RPOS
RNEG
LOS
0001*Clocked in TPOS
TNEG
RCLK RTIP
RRING
0
00010Clocked loss TPOS
TNEG
0 0 1
0001*Loss in 0RCLK RTIP
RRING
0
00010Loss loss 0 0 0 1
00011Clocked loss TPOS
TNEG
RCLK RTIP
RRING
1
00011Loss loss 0RCLK RTIP
RRING
1
0000*Clocked in TPOS
TNEG
RCLK RTIP
RRING
0
00000Clocked loss TPOS
TNEG
0 1 1
0000*Loss in 0 0RCLK RTIP
RRING
0
00000Loss loss 0 0 1 1
00001clocked loss TPOS
TNEG
RCLK RTIP
RRING
1
00001loss loss 0RCLK RTIP
RRING
1
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
22
Normal Operation(RESET=1, MCLK:clocked, PD=0)
LoopbackTAOS
Local Remote
POLN RDEN TCLK Receive
signal
TTIP
TRING
RCLK RPOS
RNEG
LOS
1001*clocked in All Mark RCLK RTIP
RRING
0
10010clocked loss All Mark 0 0 1
1001*loss in All Mark RCLK RTIP
RRING
0
10010loss loss All Mark 0 0 1
10011clocked loss All Mark RCLK RTIP
RRING
1
10011loss loss All Mark RCLK RTIP
RRING
1
1000*clocked in All Mark RCLK RTIP
RRING
0
10000clocked loss All Mark 0 1 1
1000*loss in All Mark RCLK RTIP
RRING
0
10000loss loss All Mark 0 1 1
10001clocked loss All Mark RCLK RTIP
RRING
1
10001loss loss All Mark RCLK RTIP
RRING
1
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
23
Remote Loopback(RESET=1, MCLK:clocked, PD=0)
LoopbackTAOS
Local Remote
POLN RDEN TCLK Receive
signal
TTIP
TRING
RCLK RPOS
RNEG
LOS
0011* * in RTIP
RRING
RCLK RTIP
RRING
0
00110 *loss RTIP
RRING
0 0 1
00111 *loss RTIP
RRING
RCLK RTIP
RRING
1
0010* * in RTIP
RRING
RCLK RTIP
RRING
0
00100 *loss RTIIP
RRING
0 1 1
00101 *loss RTIP
RRING
RCLK RTIP
RRING
1
Remote Loopback(RESET=1, MCLK:clocked, PD=0)
LoopbackTAOS
Local Remote
POLN RDEN TCLK Receive
signal
TTIP
TRING
RCLK RPOS
RNEG
LOS
1011* * in All Mark RCLK RTIP
RRING
0
10110 *loss All Mark 0 0 1
10111 *loss All Mark RCLK RTIP
RRING
1
1010* * in All Mark RCLK RTIP
RRING
0
10100 *loss All Mark 0 1 1
10101 *loss All Mark RCLK RTIP
RRING
1
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
24
Local Loopback(RESET=1, MCLK:clocked, PD=0)
LoopbackTAOS
Local Remote
POLN RDEN TCLK Receive
signal
TTIP
TRING
RCLK RPOS
RNEG
LOS
0101*clocked in TPOS
TNEG
TCLK
(Note)
TPOS
TNEG
0
0101*clocked loss TPOS
TNEG
TCLK
(Note)
TPOS
TNEG
1
0101*loss in 0 0 0 0
0101*loss loss 0 0 0 1
0100*clocked in TPOS
TNEG
TCLK
(Note)
TPOS
TNEG
0
0100*clocked loss TPOS
TNEG
TCLK
(Note)
TPOS
TNEG
1
0100*loss in 0 0 1 0
0100*loss loss 0 0 1 1
Note) The phase satisfy receive output timing.
Local Loopback(RESET=1, MCLK:clocked, PD=0)
LoopbackTAOS
Local Remote
POLN RDEN TCLK Receive
signal
TTIP
TRING
RCLK RPOS
RNEG
LOS
1101*clocked in All Mark TCLK
(Note)
TPOS
TNEG
0
1101*clocked loss All Mark TCLK
(Note)
TPOS
TNEG
1
1101*loss in All Mark 0 0 0
1101*loss loss All Mark 0 0 1
1100*clocked in All Mark TCLK
(Note)
TPOS
TNEG
0
1100*clocked loss All Mark TCLK
(Note)
TPOS
TNEG
1
1100*loss in All Mark 0 1 0
1100*loss loss All Mark 0 1 1
Note) The phase satisfy receive output timing.
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
25
THEORY OF OPERATION
Loss of signal
Loss of signal in channel x is reported by setting LOSx register “high”.
The receiver will indicate loss of signal upon receiving 175 consecutive zeros or detecting input
level being below the threshold(ALOS).
LOSx returns to “low” when the received signal returns to 12.5% ones density and not include
100 consecutive zeros.
When Loss of Signal is detected in channel x, LOSx register is set “high” and LOSx pin becomes
“high”. When LOSx is set “high”, interrupt will be issued on INT pin if MLOSx is “low”. LOSx
pin becomes high regardless of MLOSx status. MLOSx is active-high and masks LOSx interrupt.
LOSx register represents the current status of received signal regardless of the status of the
MLOSx status.
Loss of TCLK
Loss of TCLKx is reported by setting LOTCx “high”. When LOTCx is set “high”, INT output
becomes “high” if MLOTCx is “low”. Even if TCLK return to normal quickly, LOTCx remain
“high” for 126us. MLOTCx is active-high and masks LOTCx interrupt. LOTCx represents the
current status of TCLKx and can be read regardless of the status of the MLOTCx status.
When Loss of TCLKx is detected, TTIPx/TRINGx will be forced to “0”.
Loss of MCLK
Loss of MCLK is reported by setting LOMC “high”. When LOMC goes “high”, INT output
becomes “high” if MLOMC is “low”. Even if MCLK return to normal quickly, LOMC remain
“high” for 126us. MLOMC is active-high and masks LOMC interrupt. LOMC represents the
current status of MCLK and can be read regardless of MLOMC status. When the loss of MCLK
is detected, LOSx register and LOSx pin goes “high” at the same time. Therefore all MLOSx
register must be set to “high” to prevent loss of MCLK from setting INT output.
INT output
INT output goes “high” when the alarm is reported to any one of LOSx, LOTCx or LOMC
registers. This pin can be masked by MLOSx, MLOTCx or MLOMC registers.
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
26
Local Loopback
In Local Loopback mode, TPOSx,TNEGx,TCLKx signals are looped back to RPOSx, RNEGx,
RCLKx output. RTIPx,RRINGx inputs are ignored but loss of signal detection is active.
The transmitter in channel x outputs TTIPx,TRINGx normally.
Remote Loopback
In Remote Loopback mode, RTIPx/RRINGx signals are looped back to TTIPx/TRINGx output.
The receiver in channel x output RPOSx,RNEGx,RCLKx normally and detect loss of signal.
TPOSx,TNEGx,TCLKx inputs are ignored. When TAOSx is “high”, all mark signal is output to
TTIPx/TRINGx.
Interface
Interface to control/status register is selected by P/S pin. When P/S is set to “low”, parallel
interface is selected. When P/S is set to “high”, serial interface is selected.
Parallel Interface
Bus type(Intel/Motorola) is selected by BTS pin.
When BTS is set to “high”, Motorola mode is selected. When BTS is set to “low”, Intel mode is
selected.
Serial Interface
The timing of serial interface is shown below.
R/W=1: read
R/W=0: write
R/W A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
CS
SCLK
SDI
SDO High-Z
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
27
RECOMMENDED EXTERNAL CIRCUIT
Transmit Circuit
75Ω120Ω
Trans Rate 1:2 1:2.2
R1.R2 8.2Ω±1% 9.1Ω±1%
C1 1uF 1uF
C2 470pF 470pF
Received Circuit
75Ω120Ω
R1,R2 20Ω82Ω
R3,R4 130Ω160Ω
Rp100Ω
*Rp is protection resistance against surge.
Rp is used for surge current limiting. (ITU-T K.41)
Recommended Transformer Specification DCR
(Max)
Turns
Ratio
(Typ)
Primary
Inductance
(Min)
Leakage
Inductance
(Max)
Interwinding
Capacitance
(Max) pri sec
1:2 720uH0.3uH 30pF 0.6Ω1.2ΩTx 75Ω
120Ω1:2.2 720uH0.3uH 30pF 0.6Ω1.3Ω
Rx 1:2 1.2mH0.3uH 30pF 0.6Ω1.2Ω
AK2548
TTIPx
TRINGx
C1 1:N
R1
R2
C2
AK2548
RTIPx
RRINGx
R1
R3
R2
2:1
R4
Rp
Rp
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
28
Reference current circuit
To determine input reference current, connect 12kΩ±1% resistor.
Power Supply
To attenuate the power supply noise, connect capacitors between VDD and VSS respectively.
The value of the capacitance AK2548 need depend on the condition of the power supply line.
Please decide the value of the capacitance after your evaluation.
Pin name C1
RAVDD1-RAVSS1, RAVDD2-RAVSS2, BVDD-BVSS,
TAVDD1-TAVSS1, TAVDD2-TAVSS2
1uF
TVDD1-TVSS1, TVDD2-TVSS2, TVDD3-TVSS3, TVDD4-TVSS4,
TVDD5-TVSS5, TVDD6-TVSS6, TVDD7-TVSS7, IOVDD1-
IOVSS1, IOVDD2-IOVSS2, DVDD1-DVSS1, DVDD2-DVSS2,
PVDD-PVSS
0.01uF
BGREF
AK2548 R1
R1=12kΩ±1%
VDD
AK2548
C1
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
29
PACKAGE
144pin LQFP
OUTPUT DIMENSIONS
22.0
136
37
72
73108
109
144
20.0
0.50 0.20
0~10°
0.17±0.040.07
22.0
20.0
1.70 Max
1.40
0.50±0.1
0.10
0.10
0.10 M
AK2548
XXXXXXX
JAPAN
ASAHI KASEI [AK2548]
C0028-E-00 1999/9
30
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export
license or other official approval under the law and regulations of the country of export pertaining
to customs and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which
its failure to function or perform may reasonably be expected to result in loss of life or in
significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected
to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device
or system containing it, and which must therefore meet very high standards of performance
and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and
liability for and hold AKM harmless from any and all claims arising from the use of said product in
the absence of such notification.