DS90C402M/NOPB - NATIONAL SEMICONDUCTOR

DS90C402

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SNLS001C –JUNE 1998–REVISED APRIL 2013

DS90C402 Dual Low Voltage Differential Signaling (LVDS) Receiver

Check for Samples: DS90C402

1FEATURES DESCRIPTION

The DS90C402 is a dual receiver device optimized

2• Ultra Low Power Dissipation for high data rate and low power applications. This

• Operates above 155.5 Mbps device along with the DS90C401 provides a pair chip

• Standard TIA/EIA-644 solution for a dual high speed point-to-point interface.

The device is in a PCB space saving 8 lead small

• 8 Lead SOIC Package saves PCB space outline package. The receiver offers ±100 mV

• VCM ±1V center around 1.2V threshold sensitivity, in addition to common-mode

• ±100 mV Receiver Sensitivity noise protection.

Connection Diagram

See Package Number D (SOIC)

Functional Diagram

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

DS90C402

SNLS001C –JUNE 1998–REVISED APRIL 2013

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Absolute Maximum Ratings(1)(2)

Supply Voltage (VCC)−0.3V to +6V

Input Voltage (RIN+, RIN−)−0.3V to (VCC + 0.3V)

Output Voltage (ROUT)−0.3V to (VCC + 0.3V)

D Package 1025 mW

Maximum Package Power Dissipation @ +25°C Derate D Package 8.2 mW/°C above +25°C

Storage Temperature Range −65°C to +150°C

Lead Temperature Range

Soldering (4 sec.) +260°C

Maximum Junction Temperature +150°C

ESD Rating(3) (HBM, 1.5 kΩ, 100 pF) ≥3,500V

(EIAJ, 0 Ω, 200 pF) ≥250V

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply

that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) ESD Rating: HBM (1.5 kΩ, 100 pF) ≥3,500V EIAJ (0Ω, 200 pF) ≥250V

Recommended Operating Conditions Min Typ Max Units

Supply Voltage (VCC) +4.5 +5.0 +5.5 V

Receiver Input Voltage GND 2.4 V

Operating Free Air Temperature (TA)−40 +25 +85 °C

Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)

Symbol Parameter Conditions Pin Min Typ Max Units

VTH Differential Input High Threshold VCM = + 1.2V RIN+, +100 mV

RIN−

VTL Differential Input Low Threshold −100 mV

IIN Input Current VIN = +2.4V VCC = 5.5V −10 ±1 +10 μA

VIN = 0V −10 ± 1 +10 µA

VOH Output High Voltage IOH =−0.4 mA, VID = +200 mV ROUT 3.8 4.9 V

IOH =−0.4mA, Inputs terminated 3.8 4.9 V

IOH =−0.4mA, Inputs Open 3.8 4.9 V

IOH =−0.4mA, Inputs Shorted 4.9 V

VOL Output Low Voltage IOL = 2 mA, VID =−200 mV 0.07 0.3 V

IOS Output Short Circuit Current VOUT = 0V(3) −15 −60 −100 mA

ICC No Load Supply Current Inputs Open VCC 3.5 10 mA

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground

unless otherwise specified.

(2) All typicals are given for: VCC = +5.0V, TA= +25°C.

(3) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted

at a time, do not exceed maximum junction temperature specification.

Product Folder Links: DS90C402

DS90C402

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SNLS001C –JUNE 1998–REVISED APRIL 2013

Switching Characteristics

VCC = +5.0V ± 10%, TA=−40°C to +85°C(1)(2)(3)(4)(5)

Symbol Parameter Conditions Min Typ Max Units

tPHLD Differential Propagation Delay High to Low CL= 5 pF, 1.0 3.40 6.0 ns

VID = 200 mV

tPLHD Differential Propagation Delay Low to High 1.0 3.48 6.0 ns

(Figure 1 and Figure 2)

tSKD Differential Skew |tPHLD −tPLHD| 0 0.08 1.2 ns

tSK1 Channel-to-Channel Skew(3) 0 0.6 1.5 ns

tSK2 Chip to Chip Skew(4) 5.0 ns

tTLH Rise Time 0.5 2.5 ns

tTHL Fall Time 0.5 2.5 ns

(1) All typicals are given for: VCC = +5.0V, TA= +25°C.

(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, trand tf(0%–100%) ≤1 ns for RIN.

(3) Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same

chip with an event on the inputs.

(4) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.

(5) CLincludes probe and jig capacitance.

Parameter Measurement Information

Figure 1. Receiver Propagation Delay and Transition Time Test Circuit

Figure 2. Receiver Propagation Delay and Transition Time Waveforms

Product Folder Links: DS90C402

DS90C402

SNLS001C –JUNE 1998–REVISED APRIL 2013

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TYPICAL APPLICATION

Figure 3. Point-to-Point Application

Applications Information

LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as

is shown in Figure 3. This configuration provides a clean signaling environment for the quick edge rates of the

drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair

cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the

range of 100Ω. A termination resistor of 100Ωshould be selected to match the media, and is located as close to

the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a

voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,

but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as

ground shifting, noise margin limits, and total termination loading must be taken into account.

The DS90C402 differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V common-

mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The

driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be

the result of a ground potential difference between the driver's ground reference and the receiver's ground

reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins

should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground),

exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages.

Fail-Safe Feature:

The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS

logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from

appearing as a valid signal.

The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe

protection (a stable known state HIGH output voltage) for floating, terminated or shorted receiver inputs.

1. Open Input Pins. The DS90C402 is a dual receiver device, and if an application requires only one receiver,

the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other

voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a

HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs.

2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a power-off condition,

the receiver output will again be in a HIGH state, even with the end of cable 100Ωtermination resistor across

the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable

picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch.

To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be

used. Twisted pair cable will offer better balance than flat ribbon cable

3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V

differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not

supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs

shorted and no external common-mode voltage applied.

Product Folder Links: DS90C402

DS90C402

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SNLS001C –JUNE 1998–REVISED APRIL 2013

PIN DESCRIPTIONS

Pin No. Name Description

2, 6 ROUT Receiver output pin

3, 7 RIN+ Positive receiver input pin

4, 8 RIN- Negative receiver input pin

5 GND Ground pin

1 VCC Positive power supply pin, +5V ± 10%

Product Folder Links: DS90C402

DS90C402

SNLS001C –JUNE 1998–REVISED APRIL 2013

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Typical Performance Characteristics

Output High Voltage vs Output High Voltage vs

Power Supply Voltage Ambient Temperature

Figure 4. Figure 5.

Output Low Voltage vs Output Low Voltage vs

Power Supply Voltage Ambient Temperature

Figure 6. Figure 7.

Output Short Circuit Current Output Short Circuit Current

vs Power Supply Voltage vs Ambient Temperature

Figure 8. Figure 9.

Product Folder Links: DS90C402

DS90C402

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SNLS001C –JUNE 1998–REVISED APRIL 2013

Typical Performance Characteristics (continued)

Differential Propagation Delay

vs Differential Propagation Delay

Power Supply Voltage vs Ambient Temperature

Figure 10. Figure 11.

Differential Skew vs Differential Skew vs

Power Supply Voltage Ambient Temperature

Figure 12. Figure 13.

Transition Time vs Transition Time vs

Power Supply Voltage Ambient Temperature

Figure 14. Figure 15.

Product Folder Links: DS90C402

DS90C402

SNLS001C –JUNE 1998–REVISED APRIL 2013

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REVISION HISTORY

Changes from Revision B (April 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format ............................................................................................................ 7

Product Folder Links: DS90C402

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

DS90C402M NRND SOIC D 8 95 Non-RoHS

& Green Call TI Call TI -40 to 85 DS90C

402M

DS90C402M/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90C

402M

DS90C402MX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS90C

402M

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DS90C402MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DS90C402MX/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2017

Pack Materials-Page 2

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PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

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EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

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EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

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