1
Rad Hard and SEE Hard 6A Synchronous Buck Regulator
ISL70001SEH
The ISL70001SEH is a radiation hardened and SEE hardened
high efficiency monolithic synchronous buck regulator with
integrated MOSFETs. This single chip power solution operates
over an input voltage range of 3V to 5.5V and provides a tightly
regulated output voltage that is externally adjustable from 0.8V
to ~85% of the input voltage. Output load current capacity is 6A
for TJ < +145°C.
High integration and class leading radiation tolerance makes
the ISL70001SEH an ideal choice to power many of today’s
small form factor applications. Two devices can be
synchronized to provide a complete power solution for large
scale digital ICs, like field programmable gate arrays (FPGAs)
that require separate core and I/O voltages.
Applications
• FPGA, CPLD, DSP, CPU Core or I/O Voltages
• Low-Voltage, High-Density Distributed Power Systems
Related Literature
• ISL70001SRHEVAL1Z Evaluation Board, AN1518
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed in the Ordering Information table on Page 2 must
be used when ordering.
Detailed Electrical Specifications for these devices are contained
in SMD 5962-09225. This link is also available on the
ISL70001SEH product information page on the Intersil web site.
Features
• ±1% reference voltage over line, load, temperature and
radiation
• Current mode control for excellent dynamic response
• Full Mil-temp range operation (TA = -55°C to +125°C)
• High efficiency > 90%
• Fixed 1MHz operating frequency
• Available in a thermally enhanced heatsink package - R48.B
• Operates from 3V to 5.5V supply
• Adjustable output voltage
- Two external resistors set VOUT from 0.8V to ~85% of VIN
• Bi-directional SYNC pin allows two devices to be synchronized
180°C out-of-phase
• Device enable with comparator type input
• Power-good output voltage monitor
• Adjustable analog soft-start
• Input undervoltage, output undervoltage and output
overcurrent protection
• Starts into pre-biased load
• Electrically screened to DLA SMD 5962-09225
• QML qualified per MIL-PRF-38535 requirements
•Radiation hardness
- Total dose [50-300rad(Si)/s] . . . . . . . . . 100krad(Si) (min)
- Total dose [<10mrad(Si)/s]. . . . . . . . . . . . 50krad(Si) (min)
• SEE hardness
- SEL and SEB LETeff . . . . . . . . . . . 86.4MeV/mg/cm2 (min)
-SEFI X-section (LET
eff = 86.4MeV/mg/cm2) 1.4 x 10-6 cm2
(max)
-SET LET
eff (< 1 Pulse Perturbation) 86.4MeV/mg/cm2 (min)
FIGURE 1. TYPICAL APPLICATION FIGURE 2. EFFICIENCY 5V INPUT TO 3.3V OUTPUT, TA = +25°C
ISL70001SEH
ISL75051SEH
ISL70001SEH
5V SUPPLY CORE
AUX
I/O
RAD TOLERANT
FPGA
SYNCH
SYNCH
LOAD CURRENT (A)
EFFICIENCY (%)
70
75
80
85
90
95
0123456
June 27, 2013
FN7956.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2011, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL70001SEH
2FN7956.1
June 27, 2013
Functional Block Diagram
POWER-ON
RESET (POR)
PWM
REFERENCE
0.6V
SOFT
START
COMPENSATION
EA GM
SLOPE
COMPENSATION
GATE
DRIVE
CURRENT
SENSE
LXx
PVINx
CONTROL
LOGIC
PWM
FB
UV
PGOOD POWER-GOOD
PGNDx
AVDD
SS
M/S
SYNC
PORSEL
REF TDI
TDO
BIT
ZAP
TRIM
AGND
DVDD
DGND
EN
TRIM
Ordering Information
ORDERING NUMBER
PART NUMBER
(Note 2)
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
5962R0922502VXC ISL70001SEHVF (Note 1) -55 to +125 48 Ld CQFP R48.A
5962R0922502VYC ISL70001SEHVFE (Note 1) -55 to +125 48 Ld CQFP With Heatsink R48.B
5962R0922502V9A ISL70001SEHVX -55 to +125 Die
5962R0922501VXC ISL70001SRHVF (Note 1) -55 to +125 48 Ld CQFP R48.A
ISL70001SRHF/PROTO ISL70001SRHF/PROTO (Note 1) -55 to +125 48 Ld CQFP R48.A
ISL70001SEHFE/PROTO ISL70001SEHFE/PROTO (Note 1) -55 to +125 48 Ld CQFP With Heatsink R48.B
ISL70001SRHX/SAMPLE ISL70001SRHX/SAMPLE -55 to +125 Die
ISL70001SRHEVAL1Z Evaluation Board
ISL70001ASEHEV1Z Evaluation Board
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70001SEH. For more information on MSL, please see Tech Brief
TB363.
ISL70001SEH
3FN7956.1
June 27, 2013
Pin Configuration
ISL70001SEH
(48 LD CQFP)
TOP VIEW
7
8
9
10
11
12
13
14
38
37
36
35
34
33
32
31
3029282726252423
15
16
17
1819 20 21 22
39
40
41
42
434445464748123456
PVIN3
LX3
PGND3
PGND3
PGND4
PGND4
LX4
PVIN4
PVIN4
PVIN5
PVIN5
LX5
M/S
ZAP
TDI
TDO
PGOOD
DVDD
DGND
DGND
AGND
AGND
SS
DVDD
SYNC
PVIN1
PVIN1
LX1
PGND1
PGND2
PGND2
LX2
PVIN2
PVIN2
PVIN3
PGND1
AVDD
REF
FB
EN
PORSEL
PVIN6
PVIN6
LX6
PGND6
PGND6
PGND5
PGND5
* HEATSINK
* Heatsink available in R48.B package
Pin Descriptions
PIN NUMBER PIN NAME DESCRIPTION
1, 2, 27, 28, 29, 30,
37, 38, 39, 40, 47,
48
PGNDx These pins are the power grounds associated with the corresponding internal power blocks. Connect these pins
directly to the ground plane. These pins should also connect to the negative terminals of the input and output
capacitors. Locate the input and output capacitors as close as possible to the IC.
3, 26, 31, 36, 41,
46
LXx These pins are the outputs of the corresponding internal power blocks and should be connected to the output
filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches. To minimize
voltage undershoot, it is recommended that a Schottky diode be connected from these pins to PGNDx. The
Schottky diode should be located as close as possible to the IC.
4, 5, 24, 25, 32, 33,
34, 35, 42, 43, 44,
45
PVINx These pins are the power supply inputs to the corresponding internal power blocks. These pins must be
connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly
to PGNDx with ceramic capacitors located as close as possible to the IC.
6 SYNC This pin is the synchronization I/O for the IC. When configured as an output (Master Mode), this pin drives the
SYNC input of another ISL70001SEH. When configured as an input (Slave Mode), this pin accepts the SYNC
output from another ISL70001SEH or an external clock. Synchronization of the slave unit is 180° out-of-phase
with respect to the master unit. If synchronizing to an external clock, the clock must be SEE hardened and the
frequency must be within the range of 1MHz ±20%.
7 M/S This pin is the Master/Slave input for selecting the direction of the bi-directional SYNC pin. For SYNC = Output
(Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to DGND.
8 ZAP This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to DGND.
9 TDI This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND.
10 TDO This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND.
11 PGOOD This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the output
voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V,
independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin
to DGND with a 10nF ceramic capacitor to mitigate SEE.
ISL70001SEH
4FN7956.1
June 27, 2013
12 SS This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output
ramp time in accordance with Equation 1:
where:
tSS = Soft-start output ramp time
CSS = Soft-start capacitor
VREF = Reference voltage (0.6V typical)
ISS = Soft-start charging current (23µA typical)
Soft-start time is adjustable from approximately 2ms to 200ms.
The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.
13, 14 DVDD These pins are the bias supply inputs to the internal digital control circuitry. Connect these pins together at the
IC and locally filter them to DGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter
components as close as possible to the IC.
15, 16 DGND These pins are the digital ground associated with the internal digital control circuitry. Connect these pins
directly to the ground plane.
17, 18 AGND These pins are the analog ground associated with the internal analog control circuitry. Connect these pins
directly to the ground plane.
19 AVDD This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω
resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC.
20 REF This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic capacitor
located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current (sourcing or
sinking) is available from this pin.
21 FB This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and
from FB to AGND to adjust the output voltage in accordance with Equation 2:
where:
VOUT = Output voltage
VREF = Reference voltage (0.6V typical)
RT = Top divider resistor (Must be 1kΩ)
RB = Bottom divider resistor
The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across RT to mitigate SEE
and to improve stability margins.
22 EN This pin is the enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and
programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND with a 10nF
ceramic capacitor to mitigate SEE.
23 PORSEL This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V
supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply
voltages between 5V and 3.3V, connect this pin to DGND.
Heatsink The heatsink is electrically isolated and should be connected to a thermal chassis of any potential which offers
optimal thermal relief.
Pin Descriptions (Continued)
PIN NUMBER PIN NAME DESCRIPTION
tSS CSS VREF
⋅ISS
⁄=(EQ. 1)
VOUT VREF 1R
TRB
⁄()+[]⋅=(EQ. 2)
ISL70001SEH
5FN7956.1
June 27, 2013
Typical Application Schematic
FIGURE 3. 5V INPUT SUPPLY VOLTAGE WITH MASTER MODE SYNCHRONIZATION
PGOOD
FB
470µF
1µH
5V
1µF
PVIN1
PVIN2
ISL70001SEH
3A
PVIN3
1Ω1kΩ
499Ω
PVIN4
PVIN5
PVIN6
EN
M/S
PORSEL
SYNC
DVDD
DGND
TDO
ZAP
TDI
0V TO 5.5V
VSENSE
10nF
1µF
AVDD
AGND
LX1
LX2
LX3
LX4
LX5
LX6
PGND1
PGND2
PGND3
PGND4
PGND5
PGND6
REF
220nF
SS
100nF
10nF
1µF
100µF
20V
1µF
1Ω
1.8V
6A
ISL70001SEH
6FN7956.1
June 27, 2013
FIGURE 4. 3.3V INPUT SUPPLY VOLTAGE WITH SLAVE MODE SYNCHRONIZATION
Typical Application Schematic (Continued)
PGOOD
FB
470µF
1µH 1.8V
3.3V
1µF
PVIN1
PVIN2
ISL70001SEH
3A
PVIN3
1Ω1kΩ
499Ω
PVIN4
PVIN5
PVIN6
EN
M/S
PORSEL
SYNC
AVDD
AGND
TDO
ZAP
TDI
0V TO 5.5V
VSENSE
10nF
1µF
DVDD
DGND
LX1
LX2
LX3
LX4
LX5
LX6
PGND1
PGND2
PGND3
PGND4
PGND5
PGND6
REF
220nF
SS
100nF
10nF
1µF
100µF
4.7nF
20V
6A
1µF
1Ω
ISL70001SEH
7FN7956.1
June 27, 2013
Absolute Maximum Ratings Thermal Information
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND - 0.3V to AGND + 6.5V
DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND - 0.3V to DGND +6.5V
LXx, PVINx . . . . . . . . . . . . . . . . . . . . . . . . . . . PGNDx - 0.3V to PGNDx + 6.5V
AVDD - AGND, DVDD - DGND . . . . . . . . . . . . . . . . . . . . PVINx - PGNDx ± 0.3V
Signal Pins (Note 7) . . . . . . . . . . . . . . . . . . . . . AGND - 0.3V to AVDD + 0.3V
Digital Control Pins (Note 8) . . . . . . . . . . . . . . DGND - 0.3V to DVDD + 0.3V
PGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND - 0.3V to DGND + 6.5V
SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND - 0.3V to DGND + 2.5V
Absolute Maximum Ratings (Note 9)
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND - 0.3V to AGND + 5.7V
DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND - 0.3V to DGND + 5.7V
LXx, PVINx . . . . . . . . . . . . . . . . . . . . . . . . . . . PGNDx - 0.3V to PGNDx + 5.7V
AVDD - AGND, DVDD - DGND . . . . . . . . . . . . . . . . . . . . PVINx - PGNDx ± 0.3V
Signal Pins (Note 7) . . . . . . . . . . . . . . . . . . . . . AGND - 0.3V to AVDD + 0.3V
Digital Control Pins (Note 8) . . . . . . . . . . . . . . DGND - 0.3V to DVDD + 0.3V
PGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND - 0.3V to DGND + 5.7V
SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND - 0.3V to DGND + 2.5V
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
48 Ld CQFP R48.A (Notes 3,5) . . . . . . . . . . 36.5 3
48 Ld CQFP R48.B (Notes 4,6) . . . . . . . . . . 19 1.3
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+145°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND + 3V to 5.5V
DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND + 3V to 5.5V
PVINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGNDx + 3V to 5.5V
AVDD - AGND, DVDD - DGND . . . . . . . . . . . . . . . . . . . . PVINx - PGNDx ± 0.1V
Signal Pins (Note 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVDD
Digital Control Pins (Note 9) . . . . . . . . . . . . . . . . . . . . . . . . . .DGND to DVDD
REF, SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Set
GND, TDI, TDO, TPGM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND
ILXx (TJ ≤ +145°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.0A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the package underside.
6. For θJC, the “case temp” location is the center of the exposed metal heatsink on the package underside.
7. EN, FB, PORSEL and REF pins.
8. M/S, SYNC, TDI, TDO and ZAP pins.
9. For Operation in a heavy ion environment tested at LET = 86.4 MeV•cm2/mg with +125°C (TC).
Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V;
GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V,
SYNC = LXx = Open Circuit; PGOOD is pulled up to VIN with a 1kΩ resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a
100nF capacitor; IOUT = 0A; TA= TJ = +25°C. (Note 10). Boldface limits apply over the operating temperature range, -55°C to +125°C; over a total iodizing
dose of 100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total iodizing dose of 50krad(Si) with exposure at a low dose rate
of <10mrad(Si)/s.
PARAMETER TEST CONDITIONS
MIN
(Note 11) TYP
MAX
(Note 11) UNITS
POWER SUPPLY
Operating Supply Current VIN = 5.5V 40 65 mA
VIN = 3.6V 25 45 mA
Shutdown Supply Current VIN = 5.5V, EN = GND 6 12 mA
VIN = 3.6V, EN = GND 3 6mA
OUTPUT VOLTAGE
Reference Voltage Tolerance 0.594 0.6 0.606 V
Output Voltage Tolerance VOUT = 0.8V to 2.5V for VIN = 4.5V to 5.5V,
VOUT = 0.8V to 2.5V for VIN = 3V to 3.6V,
IOUT = 0A to 6A (Notes 12, 13)
-2 02%
Feedback (FB) Input Leakage Current VIN = 5.5V, VFB = 0.6V -1 01µA
PWM CONTROL LOGIC
Oscillator Accuracy 0.85 11.15 MHz
ISL70001SEH
8FN7956.1
June 27, 2013
External Oscillator Range .8 11.2 MHz
Minimum LXx On Time VIN = 5.5V, Test Mode 110 150 ns
Minimum LXx Off Time VIN = 5.5V, Test Mode 40 100 ns
Minimum LXx On Time VIN = 3V, Test Mode 150 210 ns
Minimum LXx Off Time VIN = 3V, Test Mode 50 100 ns
Master/Slave (M/S) Input Voltage Input High Threshold VIN - 0.5 1.3 V
Input Low Threshold 1.2 0.5 V
Master/Slave (M/S) Input Leakage Current VIN = 5.5V, M/S = GND or VIN -1 01µA
Synchronization (SYNC) Input Voltage Input High Threshold, M/S = GND 2.3 1.7 V
Input Low Threshold, M/S = GND 1.5 1V
Synchronization (SYNC) Input Leakage
Current
VIN = 5.5V, M/S = GND, SYNC = GND or VIN -1 01µA
Synchronization (SYNC) Output Voltage VIN - VOH @ IOH = -1mA 0.15 0.4 V
VOL@ IOL = 1mA 0.15 0.4 V
POWER BLOCKS
Upper Device rDS(ON) VIN = 3V, 0.4A Per Power Block, Test Mode (Note 13) 122 215 346 mΩ
Lower Device rDS(ON) VIN = 3V, 0.4A Per Power Block, Test Mode (Note 13) 77 146 236 mΩ
LXx Output Leakage VIN = 5.5V, EN = LXx = GND, Single LXx Output -1 0µA
VIN = 5.5V, EN = GND, LXx = VIN, Single LXx Output 0 15 µA
Deadtime Within a Single Power Block or between Power
Blocks (Note 13)
1.7 5ns
Efficiency VIN = 3.3V, VOUT = 1.8V, IOUT = 3A 90 %
VIN = 5V, VOUT = 2.5V, IOUT = 3A 92 %
POWER-ON RESET
POR Select (PORSEL) Input High Threshold VIN - 0.5 1.4 V
Input Low Threshold 1.2 0.5 V
POR Select (PORSEL) Input Leakage
Current
VIN = 5.5V, PORSEL = GND or VIN -1 01µA
VIN POR Rising Threshold, PORSEL = VIN 4.1 4.25 4.45 V
Hysteresis, PORSEL = VIN 225 325 425 mV
Rising Threshold, PORSEL = GND 2.65 2.8 2.95 V
Hysteresis, PORSEL = GND 90 175 260 mV
Enable (EN) Input Voltage Rising/Falling Threshold 0.56 0.6 0.64 V
Enable (EN) Input Leakage Current VIN = 5.5V, EN = GND or VIN -3 03µA
Enable (EN) Sink Current EN = 0.3V 6.4 11 16.6 µA
SOFT-START
Soft-Start Source Current SS = GND 20 23 27 µA
Soft-Start Discharge ON-Resistance 2.2 4.7 Ω
Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V;
GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V,
SYNC = LXx = Open Circuit; PGOOD is pulled up to VIN with a 1kΩ resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a
100nF capacitor; IOUT = 0A; TA= TJ = +25°C. (Note 10). Boldface limits apply over the operating temperature range, -55°C to +125°C; over a total iodizing
dose of 100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total iodizing dose of 50krad(Si) with exposure at a low dose rate
of <10mrad(Si)/s. (Continued)
PARAMETER TEST CONDITIONS
MIN
(Note 11) TYP
MAX
(Note 11) UNITS
ISL70001SEH
9FN7956.1
June 27, 2013
Soft-Start Discharge Time 256 Clock Cycles
POWER-GOOD SIGNAL
Rising Threshold VFB as a% of VREF, Test Mode 107 111 115 %
Rising Hysteresis VFB as a% of VREF, Test Mode 23.5 5%
Falling Threshold VFB as a% of VREF, Test Mode 85 89 93 %
Falling Hysteresis VFB as a% of VREF, Test Mode 23.5 5%
Power-Good Drive VIN = 3V, PGOOD = 0.4V, EN = GND 7.3 8.2 mA
Power-Good Leakage VIN = PGOOD = 5.5V 0.001 1µA
PROTECTION FEATURES
Undervoltage Monitor
Undervoltage Trip Threshold VIN = 3V, VFB as a% of VREF, Test mode 71 75 79 %
Undervoltage Recovery Threshold VIN = 3V, VFB as a% of VREF, Test mode 84 88 92 %
Overcurrent Monitor
Overcurrent Trip Level LX4 Power Block, Test Mode, (Note 14) 1.3 1.9 2.5 A
Overcurrent or Short-Circuit Duty-Cycle VIN = 3V, SS Interval = 200µs, Test Mode, Fault
Interval Divided by Hiccup Interval
0.8 5%
NOTES:
10. Typical values shown are not guaranteed. Guaranteed min/max values are provided in the SMD.
11. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
12. Limits do not include tolerance of external feedback resistors. The 0A to 6A output current range may be reduced by Minimum LXx On Time and
Minimum LXx Off Time specifications.
13. Limits established by characterization or analysis and are not production tested.
14. During an output short-circuit, peak current through the power block(s) can continue to build beyond the overcurrent trip level by up to 3A. With all
six power blocks connected, peak current through the power blocks and output inductor could reach (6 x 2.5A) + 3A = 18A. The output inductor must
support this peak current without saturating.
Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V;
GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤ VIN ≤ 5.5V and GND for VIN < 4.5V,
SYNC = LXx = Open Circuit; PGOOD is pulled up to VIN with a 1kΩ resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a
100nF capacitor; IOUT = 0A; TA= TJ = +25°C. (Note 10). Boldface limits apply over the operating temperature range, -55°C to +125°C; over a total iodizing
dose of 100krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total iodizing dose of 50krad(Si) with exposure at a low dose rate
of <10mrad(Si)/s. (Continued)
PARAMETER TEST CONDITIONS
MIN
(Note 11) TYP
MAX
(Note 11) UNITS
ISL70001SEH
10 FN7956.1
June 27, 2013
Functional Description
The ISL70001SEH is a monolithic, fixed frequency, current-mode
synchronous buck regulator with user configurable power blocks.
Two ISL70001SEH devices can be used to provide a total DC/DC
solution for FPGAs, CPLDs, DSPs and CPUs.
The ISL70001SEH utilizes peak current-mode control with
integrated compensation and switches at a fixed frequency of
1MHz. Two ISL70001SEH devices can be synchronized 180°C
out-of-phase to reduce input RMS ripple current. These attributes
reduce the number and size of external components required,
while providing excellent output transient response. The
internal synchronous power switches are optimized for high
efficiency and good thermal performance.
The chip features a comparator type enable input that provides
flexibility. It can be used for simple digital on/off control or,
alternately, can provide undervoltage lockout capability by
using two external resistors to precisely sense the level of an
external supply voltage. A power-good signal indicates when the
output voltage is within ±11% typical of the nominal output
voltage.
Regulator start-up is controlled by an analog soft-start circuit,
which can be adjusted from approximately 2ms to 200ms by
using an external capacitor.
The ISL70001SEH incorporates fault protection for the
regulator. The protection circuits include input undervoltage,
output undervoltage, and output overcurrent.
Power Blocks
The power output stage of the regulator consists of six 1A
capable power blocks that are paralleled to provide full 6A
output current capability. The block diagram in Figure 5 shows a
top level view of the individual power blocks.
Each power block has a power supply input pin, PVINx, a phase
output pin, LXx, and a power supply ground pin, PGNDx. All PVINx
pins must be connected to a common power supply rail and all
PGNDx pins must be connected to a common ground. LXx pins
should be connected to the output inductor based on the
required load current, but must include the LX4 pin. For example,
if 3A of output current is needed, any three LXx pins can be
connected to the inductor as long as one of them is the LX4 pin.
The unused LXx pins should be left unconnected. Connecting all
six LXx pins to the output inductor provides a maximum 6A of
output current. See the “Typical Application Schematic” on
page 5 for pin connection guidance.
A scaled pilot device associated with each power block provides
current feedback. Power block 4 contains the master pilot device
and this is why it must be connected to the output inductor.
Main Control Loop
During normal operation, the internal top power switch is turned
on at the beginning of each clock cycle. Current in the output
inductor ramps up until the current comparator trips and turns
off the top power MOSFET. The bottom power MOSFET turns on
and the inductor current ramps down for the rest of the cycle.
The current comparator compares the output current at the
ripple current peak to a current pilot. The error amplifier monitors
VOUT and compares it with an internal reference voltage. The
output voltage of the error amplifier drives a proportional current
to the pilot. If VOUT is low, the current level of the pilot is
increased and the trip off current level of the output is increased.
The increased output current raises VOUT until it is in agreement
with the reference voltage.
Output Voltage Selection
The output voltage of the ISL70001SEH can be adjusted using an
external resistor divider as shown in Figure 6.
RT should be selected as 1kΩ to mitigate SEE. RT should be
shunted by a 4.7nF ceramic capacitor, CC, to mitigate SEE and to
improve loop stability margins. The REF pin should be bypassed
to AGND with a 220nF ceramic capacitor to mitigate SEE. It
should be noted that no current (sourcing or sinking) is available
from the REF pin. RB can be determined from Equation 3. The
designer can configure the output voltage from 0.8V to 85% of
the input voltage.
Switching Frequency/Synchronization
The ISL70001SEH features an internal oscillator running at a
fixed frequency of 1MHz ±15% over recommended operating
conditions. The regulator can be configured to run from the
internal oscillator or can be synchronized to another
ISL70001SEH or an SEE hardened external clock with a
frequency range of 1MHz ±20%.
POWER BLOCK 6
PGND6
POWER BLOCK 5
POWER BLOCK 4
POWER BLOCK 1
POWER BLOCK 2
POWER BLOCK 3
PVIN6
PGND5
PVIN5
PGND4
PVIN4
PGND1
PVIN1
PGND2
PVIN2
PGND3
PVIN3
FIGURE 5. POWER BLOCK DIAGRAM
LX2
LX1
LX3
LX6
LX5
LX4
FIGURE 6. OUTPUT VOLTAGE SELECTION
FB
COUT
LOUT VOUT
LXx
RT
RB
VREF
ERROR
AMPLIFIER
REF
CREF
-
+
CC
VREF = 0.6V
CREF = 220nF
RT = 1k
CC = 4.7nF
RBRT
VREF
VOUT VREF
–
--------------------------------
⋅=(EQ. 3)
ISL70001SEH
11 FN7956.1
June 27, 2013
To run the regulator from the internal oscillator, connect the M/S
pin to DVDD. In this case, the output of the internal oscillator
appears on the SYNC pin. To synchronize the regulator to the
SYNC output of another ISL70001SEH regulator or to an SEE
hardened external clock, connect the M/S pin to DGND. In this
case, the SYNC pin is an input that accepts an external
synchronizing signal. When synchronizing multiple devices, Slave
regulators are synchronized 180° out-of-phase with respect to
the SYNC output of a Master regulator or to an external clock.
Operation Initialization
The ISL70001SEH initializes based on the state of the power-on
reset (POR) monitor of the PVINx inputs and the state of the EN
input. Successful initialization prompts a soft-start interval, and
the regulator begins slowly ramping the output voltage. Once the
commanded output voltage is within the proper window of
operation, the power-good signal changes state from low to high,
indicating proper regulator operation.
Power-On Reset
The POR circuitry prevents the controller from attempting to
soft-start before sufficient bias is present at the PVINx pins.
The POR threshold of the PVINx pins is controlled by the PORSEL
pin. For a nominal 5V supply voltage, PORSEL should be
connected to DVDD. For a nominal 3.3V supply voltage, PORSEL
should be connected to DGND. For nominal supply voltages
between 5V and 3.3V, PORSEL should be connected to DGND.
The POR rising and falling thresholds are shown in the “Electrical
Specifications” table on Page 8.
Hysteresis between the rising and falling thresholds ensures that
small perturbations on PVINx seen during turn-on/turn-off of the
regulator do not cause inadvertent turn-off/turn-on of the
regulator. When the PVINx pins are below the POR rising
threshold, the internal synchronous power MOSFET switches are
turned off, and the LXx pins are held in a high-impedance state.
Enable and Disable
After the POR input requirement is met, the ISL70001SEH
remains in shutdown until the voltage at the enable input rises
above the enable threshold. As shown in Figure 7, the enable
circuit features a comparator type input. In addition to simple
logic on/off control, the enable circuit allows the level of an
external voltage to precisely gate the turn-on/turn-off of the
regulator. An internal IEN current sink with a typical value of
11µA is only active when the voltage on the EN pin is below the
enable threshold. The current sink pulls the EN pin low. As VIN2
rises, the enable level is not set exclusively by the resistor divider
from VIN2.
With the current sink active, the enable level is defined by
Equation 4. R1 is the resistor from the EN pin to VIN2 and R2 is
the resistor from the EN pin to the AGND pin.
Once the voltage at the EN pin reaches the enable threshold, the
IEN current sink turns off.
With the part enabled and the IEN current sink off, the disable
level is set by the resistor divider. The disable level is defined by
Equation 5.
The difference between the enable and disable levels provides
adjustable hysteresis so that noise on VIN2 does not interfere
with the enabling or disabling of the regulator.
To mitigate SEE, the EN pin should be bypassed to the AGND pin
with a 10nF ceramic capacitor.
Soft-Start
Once the POR and enable circuits are satisfied, the regulator
initiates a soft-start. Figure 8 shows that the soft-start circuit
clamps the error amplifier reference voltage to the voltage on an
external soft-start capacitor connected to the SS pin.
VENABLE VR1R1
R2
-------
+⋅IEN R1⋅+= (EQ. 4)
FIGURE 7. ENABLE CIRCUIT
-
+
VR
EN
PVINx
VIN1
POR
LOGIC
VIN2
R1
R2
IEN
ENABLE
COMPARATOR
CEN
VR = 0.6V
IEN = 11µA
CEN = 10nF
VDISABLE VR1R1
R2
-------
+⋅=(EQ. 5)
FIGURE 8. SOFT-START CIRCUIT
-
+VREF
FB
PWM
LOGIC
ISS
ERROR
AMPLIFIER
REF
CREF
VOUT
RT
RB
+
SS
CSS
VREF = 0.6V
ISS = 23µA
RD
RD = 2.2Ω
ISL70001SEH
12 FN7956.1
June 27, 2013
The soft-start capacitor is charged by an internal ISS current
source. As the soft-start capacitor is charged, the output voltage
slowly ramps to the set point determined by the reference
voltage and the feedback network. Once the voltage on the SS
pin is equal to the internal reference voltage, the soft-start
interval is complete. The controlled ramp of the output voltage
reduces the inrush current during start-up. The soft-start output
ramp interval is defined in Equation 6 and is adjustable from
approximately 2ms to 200ms. The value of the soft-start
capacitor, CSS, should range from 8.2nF to 8.2µF, inclusive. The
peak in-rush current can be computed from Equation 7. The
soft-start interval should be long enough to ensure that the peak
in-rush current plus the peak output load current does not exceed
the overcurrent trip level of the regulator.
The soft-start capacitor is immediately discharged by a 2.2Ω
resistor whenever POR conditions are not met or EN is pulled low.
The soft-start discharge time is equal to 256 clock cycles.
Power-Good
The power-good (PGOOD) pin is an open-drain logic output that
indicates when the output voltage of the regulator is within
regulation limits. The power-good pin pulls low during shutdown
and remains low when the controller is enabled. After a
successful soft-start, the PGOOD pin releases, and the voltage
rises with an external pull-up resistor. The power-good signal
transitions low immediately when the EN pin is pulled low.
The power-good circuitry monitors the FB pin and compares it to
the rising and falling thresholds shown in the “Electrical
Specifications” table on Page 9. If the feedback voltage exceeds
the typical rising limit of 111% of the reference voltage, the
PGOOD pin pulls low. The PGOOD pin continues to pull low until
the feedback voltage falls to a typical of 107.5% of the reference
voltage. If the feedback voltage drops below a typical of 89% of
the reference voltage, the PGOOD pin pulls low. The PGOOD pin
continues to pull low until the feedback voltage rises to a typical
92.5% of the reference voltage. The PGOOD pin then releases
and signals the return of the output voltage to within the
power-good window.
The PGOOD pin can be pulled up to any voltage from 0V to 5.5V,
independently from the supply voltage. The pull-up resistor
should have a nominal value from 1kΩ to 10kΩ. The PGOOD pin
should be bypassed to DGND, with a 10nF ceramic capacitor to
mitigate SEE.
Fault Monitoring and Protection
The ISL70001SEH actively monitors output voltage and current
to detect fault conditions. Fault conditions trigger protective
measures to prevent damage to the regulator and external load
device.
Undervoltage Protection
A hysteretic comparator monitors the FB pin of the regulator. The
feedback voltage is compared to an undervoltage threshold that
is a fixed percentage of the reference voltage. Once the
comparator trips, indicating a valid undervoltage condition, a
3-bit undervoltage counter increments. The counter is reset if the
feedback voltage rises back above the undervoltage threshold,
plus a specified amount of hysteresis outlined in the “Electrical
Specifications” table on Page 9. If the 3-bit counter overflows,
the undervoltage protection logic shuts down the regulator.
After the regulator shuts down, it enters a delay interval
equivalent to the soft-start interval, which allows the device to
cool. The undervoltage counter is reset when the device enters
the delay interval. The protection logic initiates a normal
soft-start once the delay interval ends. If the output successfully
soft-starts, the power-good signal goes high, and normal
operation continues. If undervoltage conditions continue to exist
during the soft-start interval, the undervoltage counter must
overflow before the regulator shuts down again. This hiccup
mode continues indefinitely until the output soft-starts
successfully.
Overcurrent Protection
A pilot device integrated into the PMOS transistor of Power Block 4
samples current each cycle. This current feedback is scaled and
compared to an overcurrent threshold based on the number of
power blocks connected. Each additional power block connected
beyond Power Block 4 increases the overcurrent limit by 2A. For
example, if three power blocks are connected, the typical current
limit threshold would be 3 x 2A = 6A.
If the sampled current exceeds the overcurrent threshold, a 3-bit
overcurrent counter increments by one LSB. If the sampled current
falls below the threshold before the counter overflows, the counter
is reset. Once the overcurrent counter reaches 111, the regulator
shuts down.
After the regulator shuts down, it enters a delay interval,
equivalent to the soft-start interval, which allows the device to
cool. The overcurrent counter is reset when the device enters the
delay interval. The protection logic initiates a normal soft-start
once the delay interval ends. If the output successfully
soft-starts, the power-good signal goes high, and normal
operation continues. If overcurrent conditions continue to exist
during the soft-start interval, the overcurrent counter must
overflow before the regulator shut downs the output again. This
hiccup mode continues indefinitely until the output soft-starts
successfully.
Note: To prevent severe negative ringing that can disturb the
overcurrent counter, it is recommended that a Schottky diode of
appropriate rating be added from the LXx pins to the PGNDx pins.
Feedback Loop Compensation
To reduce the number of external components and to simplify
the process of determining compensation components, the
ISL70001SEH buck regulator has an internally compensated
error amplifier.
Due to the current loop feedback in peak current mode control, the
modulator has a single pole response with -20dB slope at a
frequency determined by the load (Equation 8):
tSS CSS
VREF
ISS
-------------
⋅=(EQ. 6)
IINRUSH COUT
VOUT
tSS
-------------
⋅=(EQ. 7)
FPO
1
2πROCOUT
⋅⋅
------------------------------------- =(EQ. 8)
ISL70001SEH
13 FN7956.1
June 27, 2013
where RO is load resistance and COUT is the output load
capacitance. For this type of modulator, a Type 2 compensation
circuit is usually sufficient.
Figure 9 shows a Type 2 amplifier and its response, along with
the responses of the current mode modulator and the converter.
The Type 2 amplifier, in addition to the pole at origin, has a
zero-pole pair that causes a flat gain region at frequencies
between the zero and the pole (Equations 9 and 10).
Zero frequency and amplifier high-frequency gain were chosen to
satisfy typical applications. The crossover frequency will appear
at the point where the modulator attenuation equals the
amplifier high frequency gain. The only task that the system
designer has to complete is to specify the output filter capacitors
to position the load main pole somewhere within one decade
lower than the amplifier zero frequency. Equation 13 on Page 13
approximates the amount of capacitance needed to achieve an
optimal pole location depending on the number of LXx pins
connected. With this type of compensation, plenty of phase
margin is easily achieved due to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load pole is
positioned too much to the left side on the frequency axis due to
excessive output filter capacitance. In this case, the ESR zero
placed within the 1.2kHz to 30kHz range gives some additional
phase ‘boost’. Some phase boost is also be achieved by
connecting the recommended capacitor CC in parallel with the
upper resistor RT of the divider that sets the output voltage value,
as demonstrated in Figure 6.
Component Selection Guide
This design guide is intended to provide a high-level explanation
of the steps necessary to create a power converter. It is assumed
the reader is familiar with many of the basic skills and
techniques referenced below. In addition to this guide, Intersil
provides a complete evaluation board that includes schematic,
BOM, and an example PCB layout (see Ordering Information
table on Page 2).
Output Filter Design
The output inductor and the output capacitor bank together form
a low-pass filter responsible for smoothing the pulsating voltage
at the phase node. The filter must also provide the transient
energy until the regulator can respond. Since the filter has low
bandwidth relative to the switching frequency, it limits the
system transient response. The output capacitors must supply or
sink current while the current in the output inductor increases or
decreases to meet the load demand.
OUTPUT CAPACITOR SELECTION
The critical load parameters in choosing the output capacitors are
the maximum size of the load step (ΔISTEP), the load-current slew
rate (di/dt), and the maximum allowable output voltage deviation
under transient loading (ΔVMAX). Capacitors are characterized
according to their capacitance, ESR (Equivalent Series Resistance)
and ESL (Equivalent Series Inductance).
At the beginning of a load transient, the output capacitors supply all
of the transient current. The output voltage initially deviates by an
amount approximated by the voltage drop across the ESL. As the
load current increases, the voltage drop across the ESR increases
linearly until the load current reaches its final value. Neglecting the
contribution of inductor current and regulator response, the output
voltage initially deviates by an amount shown in Equation 11.
The filter capacitors selected must have sufficiently low ESL and
ESR such that the total output voltage deviation is less than the
maximum allowable ripple.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination with
bulk capacitors having high capacitance but larger ESR.
Minimizing the ESL of the high-frequency capacitors allows them
to support the output voltage as the current increases.
Minimizing the ESR of the bulk capacitors allows them to supply
the increased current with less output voltage deviation.
Ceramic capacitors with X7R dielectric are recommended.
Alternately, a combination of low ESR solid tantalum capacitors
and ceramic capacitors with X7R dielectric may be used.
The ESR of the bulk capacitors is responsible for most of the
output voltage ripple. As the bulk capacitors sink and source the
inductor AC ripple current, a voltage, VP-P(MAX), develops across
the bulk capacitor according to Equation 12.
Another consideration in selecting the output capacitors is loop
stability. The total output capacitance sets the dominant pole of
the PWM. Because the ISL70001SEH uses integrated
compensation techniques, it is necessary to restrict the output
capacitance in order to optimize loop stability. The
recommended load capacitance can be estimated using
Equation 13.
FIGURE 9. FEEDBACK LOOP COMPENSATION
R1
R2 C1
C2
FPO
FZFP
FC
MODULATOR
EA
CONVERTER
TYPE 2 EA
GEA = 25.1dB
FZ
1
2πR2C1
⋅⋅
------------------------------8.6kHz== (EQ. 9)
FP
1
2πR1C2
⋅⋅
------------------------------546kHz== (EQ. 10)
ΔVMAX ESL di
dt
-----
×ESR ΔISTEP
×[]+≈(EQ. 11)
VP-P(MAX) ESR
VIN VOUT
–()VOUT
LOUT fs
×VIN
×
----------------------------------------------
×=(EQ. 12)
COUT 75μF NumberofLXxPinsConnected 1.8V
VOUT
-------------
××=
(EQ. 13)
ISL70001SEH
14 FN7956.1
June 27, 2013
Another stability requirement on the selection of the output
capacitor is that the ‘ESR zero’ (fZESR) be placed at 60kHz to
90kHz. This range is set by an internal, single compensation zero
at 8.6kHz. This ESR zero location contributes to increased phase
margin of the control loop; therefore (Equation 14):
In conclusion, the output capacitors must meet three criteria:
1. They must have sufficient bulk capacitance to sustain the
output voltage during a load transient while the output
inductor current is slewing to the value of the load transient.
2. The ESR must be sufficiently low to meet the desired output
voltage ripple due to the output inductor current.
3. The ESR zero should be placed, in a rather large range, to
provide additional phase margin.
OUTPUT INDUCTOR SELECTION
Once the output capacitors are selected, the maximum allowable
ripple voltage, VP-P(MAX), determines the lower limit on the
inductance as shown in Equation 15.
Since the output capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the transient,
the capacitor voltage becomes slightly depleted. The output
inductor must be capable of assuming the entire load current
before the output voltage decreases more than ΔVMAX. This
places an upper limit on inductance.
Equation 16 gives the upper limit on output inductance for the
case when the trailing edge of the current transient causes a
greater output voltage deviation than the leading edge.
Equation 17 addresses the leading edge. Normally, the trailing
edge dictates the inductance selection because duty cycles are
usually <50%. Nevertheless, both inequalities should be
evaluated, and inductance should be governed based on the
lower of the two results. In each equation, LOUT is the output
inductance, COUT is the total output capacitance, and ΔIL(P-P) is
the peak-to-peak ripple current in the output inductor.
The other concern when selecting an output inductor is to ensure
there is adequate slope compensation when the regulator is
operated above 50% duty cycle. Since the internal slope
compensation is fixed, output inductance should satisfy
Equation 18 to ensure this requirement is met.
Input Capacitor Selection
Input capacitors are responsible for sourcing the AC component
of the input current flowing into the switching power devices.
Their RMS current capacity must be sufficient to handle the AC
component of the current drawn by the switching power devices,
which is related to duty cycle. The maximum RMS current
required by the regulator is closely approximated by Equation 19.
The important parameters to consider when selecting an input
capacitor are the voltage rating and the RMS ripple current
rating. For reliable operation, select capacitors with voltage
ratings at least 1.5x greater than the maximum input voltage.
The capacitor RMS ripple current rating should be higher than
the largest RMS ripple current required by the circuit.
Ceramic capacitors with X7R dielectric are recommended.
Alternately, a combination of low ESR solid tantalum capacitors
and ceramic capacitors with X7R dielectric may be used. The
ISL70001SEH requires a minimum effective input capacitance of
100µF for stable operation.
Derating Current Capability
Most space programs issue specific derating guidelines for parts,
but these guidelines take the pedigree of the part into account.
For instance, a device built to MIL-PRF-38535, such as the
ISL70001, is already heavily derated from a current density
standpoint. However, a mil-temp or commercial IC that is
up-screened for use in space applications may need additional
current derating to ensure reliable operation because it was not
built to the same standards as the ISL70001.
Figure 10 shows the maximum average output current of the
ISL70001 with respect to junction temperature. These plots take
into account the worst-case current share mismatch in the power
blocks and the current density requirement of MIL-PRF-38535
(< 2 x 105 A/cm2). The plot clearly shows that the ISL70001 can
handle 12.1A at +125°C from a worst-case current density
standpoint, but the part is limited to 7.8A because that is the
lower limit of the current limit threshold with all six power blocks
connected.
ESR 1
2πfZESR
()COUT
()
----------------------------------------------
=(EQ. 14)
OUT ESR
VIN VOUT
–()VOUT
fsVIN
×VP-P(MAX)
×
--------------------------------------------------
×≥ (EQ. 15
LOUT
2COUT VOUT
⋅⋅
ΔISTEP
()
2
--------------------------------------- ΔVMAX ΔIL(P-P) ESR⋅()–≤(EQ. 16)
LOUT
2C
OUT
⋅
ΔISTEP
()
2
-------------------------- ΔVMAX ΔIL(P-P) ESR⋅()–VIN VOUT
–
⎝⎠
⎛⎞
≤(EQ. 17)
LOUT
4.32μH
NumberofLXxPinsConnected
-----------------------------------------------------------------------------------
≥(EQ. 18)
IRMSMAX
VOUT
VIN
----------------- IOUTMAX
21
12
------ VIN VOUT
–
LOUT fs
×
---------------------------------- VOUT
VIN
-----------------
×
⎝⎠
⎜⎟
⎛⎞
2
×+
⎝⎠
⎜⎟
⎛⎞
×=
(EQ. 19)
12.14
10.18
8.57
7.25
6.16
5.3
4
5
6
7
8
9
10
11
12
13
120 125 130 135 140 145 150 155
JUNCTION TEMPERATURE (°C)
MINIMUM OCP
LEVEL = 7.8A
6A @ +146°C
MAXIMUM AVERAGE CURRENT FOR
0.1% FAILURES AT 100,000 HOURS (A)
FIGURE 10. CURRENT vs TEMPERATURE
ISL70001SEH
15 FN7956.1
June 27, 2013
PCB Design
PCB design is critical to high-frequency switching regulator
performance. Careful component placement and trace routing
are necessary to reduce voltage spikes and minimize
undesirable voltage drops. Selection of a suitable thermal
interface material is also required for optimum heat dissipation
and to provide lead strain relief. See Table 1 on Page 17 for
layout x-y coordinates.
PCB Plane Allocation
Four layers of 2-ounce copper are recommended. Layer 2 should
be a dedicated ground plane with all critical component ground
connections made with vias to this layer. Layer 3 should be a
dedicated power plane split between the input and output power
rails. Layers 1 and 4 should be used primarily for signals but can
also provide additional power and ground islands, as required.
PCB Component Placement
Components should be placed as close as possible to the IC to
minimize stray inductance and resistance. Prioritize the
placement of bypass capacitors on the pins of the IC in the order
shown: REF, SS, AVDD, DVDD, PVINx (high frequency capacitors),
EN, PGOOD, PVINx (bulk capacitors).
Locate the output voltage resistive divider as close as possible to
the FB pin of the IC. The top leg of the divider should connect
directly to the POL (Point of Load), and the bottom leg of the
divider should connect directly to AGND. The junction of the
resistive divider should connect directly to the FB pin.
Locate a Schottky clamp diode as close as possible to the LXx
and PGNDx pins of the IC. A small series R-C snubber connected
from the LXx pins to the PGNDx pins may be used to damp high
frequency ringing on the LXx pins, if desired, see Figure 11.
PCB Layout
Use a small island of copper to connect the LXx pins of the IC to
the output inductor on Layers 1 and 4. To minimize capacitive
coupling to the power and ground planes, void the copper on
Layers 2 and 3 adjacent to the island. Place most of the island of
Layer 4 to minimize the amount of copper that must be voided
from the ground plane (Layer 2).
Keep all other signal traces as short as possible.
For an example layout, see AN1518.
Thermal Management for Ceramic Package
For optimum thermal performance, place a pattern of vias and a
thermal land on the top layer of the PCB directly underneath the
IC. Connect the vias to the plane which serves as a heatsink. To
ensure good thermal contact, thermal interface material such as
a Sil-Pad or thermally conductive epoxy should be used to fill the
gap between the vias and the bottom of the ceramic package.
Lead Strain Relief
The package leads protrude from the bottom of the package and
the leads need forming to provide strain relief. On the ceramic
bottom package R48.A, the Sil-pad or epoxy maybe be used to
fill the gap left between the PCB board and the bottom of the
package when lead forming is completed. On the heat sink
option of the package, R48.B, the lead forming should be made
so that the bottom of the heat sink and the formed leads are
flush.
Heat Sink Mounting Guidelines
The R48.B package option has a heat sink mounted on the
underside of the package. The following JESD51-5 guidelines
may be used to mount the package:
1. Place a thermal land on the PCB under the heat sink.
2. The land should be approximately the same size as to 1mm
larger than the 9x9mm heat sink.
3. Place an array of thermal vias below the thermal land.
- Via array size: ~8x8=64 thermal vias
- Via diameter: ~0.3mm drill diameter with plated copper on
the inside of each via.
- Via pitch: ~1.2mm.
- Vias should drop to and contact as much buried metal area
as feasible to provide the best thermal relief.
Heat Sink Electrical Potential
The heat sink is electrically isolated and unbiased. The heatsink
may be electrically connected to any potential which offers the
best thermal relief through conductive mounting materials
(conductive epoxy, solder, etc.) or may be left unbiased through
the use of electrically non-conductive mounting materials (non-
conductive epoxy, Sil-pad, kapton film, etc.).
FIGURE 11. SCHOTTKY DIODE AND R-C SNUBBER
FB
COUT
LOUT VOUT
LXx
RT
RB
VREF
ERROR
AMPLIFIER
REF
CREF
-
+
CC
3A RS
CS
PGNDx
ISL70001SEH
16 FN7956.1
June 27, 2013
Weight Characteristics
Weight of Packaged Device
1.602 Grams typical - R48.A Package
2.440 Grams typical - R48.B Package
Die Characteristics
Die Dimensions
5720µm x 5830µm (225.2 mils x 229.5 mils)
Thickness: 483µm ± 25.4µm (19.0 mils ± 1 mil)
Interface Materials
GLASSIVATION
Type: Silicon Oxide and Silicon Nitride
Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm
TOP METALLIZATION
Type: AlCu (0.5%)
Thickness: 2.7µm ±0.4µm
SUBSTRATE
Type: Silicon
Isolation: Junction
BACKSIDE FINISH
Silicon
ASSEMBLY RELATED INFORMATION
Substrate Potential - Package R48.A and R48.B: PGND
Metal Lid Potential
Electrically Isolated -Package R48.A
PGND - Package R48.B
ADDITIONAL INFORMATION
Worst Case Current Density
< 2 x 105 A/cm2
Transistor Count
25030
Layout Characteristics
Step and Repeat
5720µm x 5830µm
Connect PGND to PGNDx
Metallization Mask Layout ISL70001SEH
ISL70001SEH
17 FN7956.1
June 27, 2013
TABLE 1. LAYOUT X-Y COORDINATES
PAD NAME PAD NUMBER
X
(µm)
Y
(µm)
dX
(µm)
dY
(µm)
BOND WIRES
PER PAD
AVDD 15 478 263 135 135 1
REF 16 865 263 135 135 1
FB 17 1295 263 135 135 1
EN 18 1751 263 135 135 1
PORSEL 19 2151 263 135 135 1
PVIN6 20 2838 188 521 135 3
LX6 21 3449 188 521 135 3
PGND6 22 4060 188 521 135 3
PGND5 23 4845 188 521 135 3
LX5 24 5449 925 135 521 3
PVIN5 25 5449 1651 135 521 3
PVIN4 26 5449 2263 135 521 3
LX4 27 5449 2874 135 521 3
PGND4 28 5449 3485 135 521 3
PGND3 29 5449 4096 135 521 3
LX3 30 5449 4745 135 521 3
PVIN3 31 4941 5559 521 135 3
PVIN2 32 4137 5559 521 135 3
LX2 33 3449 5559 521 135 3
PGND2 34 2838 5559 521 135 3
PGND1 1 2227 5559 521 135 3
LX1 2 1578 5559 521 135 3
PVIN1 3 962 5559 521 135 3
SYNC 4 544 5559 135 135 1
M/S 5 226 5280 135 135 1
ZAP 6 226 4910 135 135 1
TDI 7 226 4540 135 135 1
TDO 8 226 4170 135 135 1
PGOOD 9 226 3777 135 135 1
SS 10 226 3425 135 135 1
DVDD 11 226 2566 135 333 2
DGND 12 226 1538 135 333 2
PGND 13 226 1018 135 135 1
AGND 14 226 654 135 135 1
ISL70001SEH
18
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7956.1
June 27, 2013
For additional products, see www.intersil.com/product_tree
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE REVISION CHANGE
May 20, 2013 FN7956.1 Added heat sink mounting guidelines on Page 15.
Added “Weight Characteristics” on Page 16.
Added label “Origin” to Metallization Mask Layout on Page 16.
May 6, 2013 Page 2, ordering information table: Removed the word "(HEATSINK)" under the first column, and added to
rows 2 & 6 in the fourth column "48 ld CQFP with Heatsink”.
Page 7, thermal information table: Changed note 6, from removed exposed metal pad to exposed metal
Heatsink.
May 3, 2013 Updated ordering information table on Page 2 as follow: Added ISL7000SRHVF. Added “Heatsink” to help
distinguish between the two package types. Thermal Resistance on Page 7 as follow: changed note 3 from
“low” to “high” effective” thermal conductivity test board type and added note 4 “direct attach”.
May 2, 2013 Page 2: Added ISL70001SEHVFE, ISL70001SEHFE/PROTO parts to ordering information table and added
Package DWG# column to table.
Added POD: R48.A and R48.
November 30, 2011 FN7956.0 Initial Release
ISL70001SEH
19 FN7956.1
June 27, 2013
Package Outline Drawing
R48.A
48 CERAMIC QUAD FLATPACK PACKAGE (CQFP)
Rev 3, 10/12
TOP VIEW
SIDE VIEW
NOTE:
1. All dimensions are in inches (millimeters).
0.015 (0.38)
1.118 (28.40)
0.015 (0.38) MIN
1.080 (27.43)
0.572 (14.53)
0.555 (14.10)
PIN 1
INDEX AREA
0.008 (0.20)
1.118 (28.40)
1.080 (27.43)
0.040 (1.02) BSC
0.572 (14.53)
0.555 (14.10)
0.287 (7.29)
0.253 (6.43)
0.016 (0.41)
0.009 (0.23)
0.099 (2.51)
0.076 (1.93)
0.007 (0.18) MIN
#48#1
ISL70001SEH
20 FN7956.1
June 27, 2013
Package Outline Drawing
R48.B
48 CERAMIC QUAD FLATPACK PACKAGE (CQFP) WITH BOTTOM HEATSINK
Rev 0, 10/12
1.080 (27.43)
0.555 (14.10)
INDEX AREA
PIN 1
1.118 (28.40)
0.572 (14.53)
0.253 (6.43)
0.287 (7.29)
1.118 (28.40)
1.080 (27.43)
0.040 (1.016) BSC
0.012 (0.30)
0.008 (0.20)
0.572 (14.53)
0.555 (14.10)
#48#1
TOP VIEW
0.013 (0.33)
0.131 (3.33)
0.042 (1.067) REF
SIDE VIEW
0.009 (0.23)
0.105 (2.67)
HEATSINK
0.026 (0.66) MIN. 2
PIN 1
INDEX AREA
BOTTOM VIEW
#1 #48
0.359 (9.12)
HEATSINK
0.349 (8.87)
0.349 (8.87)
0.359 (9.12)
NOTES:
1. All dimensions are in inches (millimeters)
2. Dimension shall be measured at point of exit
(beyond the meniscus) of the lead from the body.