SLUS473A - NOVEMBER 1999 - REVISED MARCH 2001 D Greater Than 4-MHz Operation D Integrated Oscillator / Voltage Feed Forward D D D D D D D Compensation >4:1 Input Voltage Range 25-ns Current Limit Delay Programmable Maximum Duty Cycle Clamp Optocoupler Interface 50-A Start-Up Current 4.2-mA Operating Current @ 1 MHz Smallest Footprint of the 8-pin MSOP Package Minimizes Board Area and Height D, OR P PACKAGE (TOP VIEW) ILIM FB VFF DISCH DGK PACKAGE (TOP VIEW) 1 ILIM VDD 8 2 FB OUT 7 3 VFF GND 6 4 DISCH RC 5 1 8 2 7 3 6 4 5 VDD OUT GND RC description The UCC35705 and UCC35706 devices are 8-pin voltage mode primary side controllers with fast over-current protection. These devices are used as core high-speed building blocks in high performance isolated and non-isolated power converters. UCC35705/UCC35706 devices feature a high speed oscillator with integrated feed-forward compensation for improved converter performance. A typical current sense to output delay time of 25 ns provides fast response to overload conditions. The IC also provides an accurate programmable maximum duty cycle clamp for increased protection which can also be disabled for the oscillator to run at maximum possible duty cycle. Two UVLO options are offered. The UCC35705 with lower turn-on voltage is intended for dc-to-dc converters while the higher turn-on voltage and the wider UVLO range of the UCC35706 is better suited for offline applications. The UCC35705/UCC35706 family is offered in 8-pin MSOP (DGK), SOIC (D) and PDIP (P) packages. typical application schematic + + VOUT - VIN - 4 DISCH VDD 8 FB 2 TPS2829 5 RC 3 VFF 6 GND OUT 7 FET DRIVER ILIM SOFT START CIRCUIT 1 UCC35705/6 MODE = 1 UDG-99181 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(! ,'&$% & !" $ %)(&&#$ % )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- ! ,'&$ )! &(%%2 , (% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- www.ti.com 1 SLUS473A - NOVEMBER 1999 - REVISED MARCH 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Input voltage (VFF,RC,ILIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Input current (DISCH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA Output current (OUT) dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Power Supply Control Data Book (TI Literature Number SLUD003) for thermal limitations and considerations of packages. AVAILABLE OPTIONS Packaged Devices TA = TJ -40C to 85C 0C to 70C UVLO Option SOIC-8 Small Outline (D) PDIP-8 Plastic Dip (P) MSOP-8 Small Outline (DGK) 8.8V/8V UCC25705D UCC25705P UCC25705DGK 12V/8V UCC25706D UCC25706P UCC25706DGK 8.8V/8V UCC35705D UCC35705P UCC35705DGK 12V/8V UCC35706D UCC35706P UCC35706DGK D (SOIC-8) and DGK (MSOP-8) packages are available taped and reeled. Add R suffix to device type (e.g. UCC35705DR) to order quantities of 2500 devices per reel for SOIC-8 and 2000 devices per reel for the MSOP-8. electrical characteristics, VDD = 11 V, VIN = 30 V, RT = 47 k, RDISCH = 400 k, RFF = 14 k, CT = 220 pF, CVDD = 0.1 F, and no load on the outputs, 0C TA 70C for the UCC3570x and -40C TA 85C for the UCC2570x, TA = TJ, (unless otherwise specified) UVLO section (UCCx5705) TYP MAX Start threshold PARAMETER TEST CONDITIONS MIN 8.0 8.8 9.6 UNITS V Stop threshold 7.4 8.2 9.0 V Hysteresis 0.3 0.6 1.0 V UVLO section (UCCx5706) TYP MAX Start threshold PARAMETER TEST CONDITIONS MIN 11.2 12.0 12.8 UNITS V Stop threshold 7.2 8.0 8.8 V Hysteresis 3.5 4.0 4.5 V MIN TYP MAX 30 90 A 4.2 5.0 mA supply current section PARAMETER Start-up current IDD active 2 TEST CONDITIONS VDD = UVLO start - 1 V, VDD comparator off VDD comparator on, oscillator running at 1 MHz www.ti.com UNITS SLUS473A - NOVEMBER 1999 - REVISED MARCH 2001 electrical characteristics, VDD = 11 V, VIN = 30 V, RT = 47 k, RDISCH = 400 k, RFF = 14 k, CT = 220 pF, CVDD = 0.1 F, and no load on the outputs, 0C TA 70C for the UCC3570x and -40C TA 85C for the UCC2570x, TA = TJ, (unless otherwise specified) line sense section PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Low line comparator threshold 0.95 1.00 1.05 V Input bias current (VFF) -100 100 nA oscillator section PARAMETER Frequency TEST CONDITIONS VFF = 1.2 V to 4.8 V CT peak voltage oltage CT valley voltage MIN 0.9 TYP MAX 1.0 1.1 UNITS MHz VFF = 1.2 V, See Note 1 1.2 V VFF = 4.8 V, See Note 1 4.8 V 0 V See Note 1 NOTE 1: Ensured by design. Not production tested. current limit section PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input bias current 0.2 -0.2 -1 A Current limit threshold 180 200 220 mV 25 35 ns TYP MAX 50 90 k 0 % 80 % Propagation delay, ILIM to OUT 50 mV overdrive pulse width modulator section PARAMETER FB input impedance Minimum duty cycle TEST CONDITIONS VFB = 3 V VFB < 2 V Ma im m duty Maximum d t cycle c cle VFB = VDD, VDISCH = 0 V, PWM gain VFF = 2.5 V, MIN 30 FOSC = 1 MHz FOSC = 1 MHz MODE = 1 70 Propagation delay, PWM to OUT 75 UNITS 93 % 12 %/V 65 120 TYP MAX 0.3 0.6 ns output section PARAMETER VOH TEST CONDITIONS VDD - output MIN UNITS VOL IOUT = -5 mA, IOUT = 5 mA 0.15 0.4 V Rise time CLOAD = 50 pF 10 25 ns Fall time CLOAD = 50 pF 10 25 ns www.ti.com V 3 SLUS473A - NOVEMBER 1999 - REVISED MARCH 2001 pin descriptions DISCH: A resistor to VIN sets the oscillator discharge current programming a maximum duty cycle. When grounded, an internal comparator switches the oscillator to a quick discharge mode. A small 100-pF capacitor between DISCH and GND may reduce oscillator jitter without impacting feed-forward performance. IDISCH must be between 25 A and 250 A over the entire VIN range. FB: Input to the PWM comparator. This pin is intended to interface with an optocoupler. Input impedance is 50-k typical. GND: Ground return pin. ILIM: Provides a pulse-by-pulse current limit by terminating the PWM pulse when the input is above 200 mV. This provides a high speed (25 ns typical) path to reset the PWM latch, allowing for a pulse-by-pulse current limit. OUT: The output is intended to drive an external FET driver or other high impedance circuits, but is not intended to directly drive a power MOSFET. This improves the controller's noise immunity. The output resistance of the PWM controller, typically 60 pull-up and 30 pull-down, will result in excessive rise and fall times if a power MOSFET is directly driven at the speeds for which the UCC35705/6 is optimized. RC: The oscillator can be configured to provide a maximum duty cycle clamp. In this mode the on-time is set by RT and CT, while the off-time is set by RDISCH and CT. Since the voltage ramp on CT is proportional to VIN, feed-forward action is obtained. Since the peak oscillator voltage is also proportional to VIN, constant frequency operation is maintained over the full power supply input range. When the DISCH pin is grounded, the duty cycle clamp is disabled. The RC pin then provides a low impedance path to ground CT during the off time. VDD: Power supply pin. This pin should be bypassed with a 0.1-F capacitor for proper operation. The undervoltage lockout function of the UCC35705/6 allows for a low current startup mode and ensures that all circuits become active in a known state. The UVLO thresholds on the UCC35705 are appropriate for a dc-to-dc converter application. The wider UVLO hysteresis of the UCC35706 (typically 4 V) is optimized for a bootstrap startup mode from a high impedance source. VFF: The feed-forward pin provides the controller with a voltage proportional to the power supply input voltage. When the oscillator is providing a duty cycle clamp, a current of 2 x IDISCH is sourced from the VFF pin. A single resistor RFF between VFF and GND then set VFF to: VFF [ VIN 2 2 R FF R FF ) R DISCH When the DISCH pin is grounded and the duty cycle clamp is not used, the internal current source is disabled and a resistor divider from VIN is used to set VFF. In either case, when the voltage on VFF is less than 1.0 V, both the output and oscillator are disabled. 4 www.ti.com SLUS473A - NOVEMBER 1999 - REVISED MARCH 2001 pin descriptions (continued) 50 mV DISCH 4 - + MODE 1.0 V VDD I LOW LINE 2 * I (MODE=1) 0 (MODE = 0) CLK + VFF 3 RC 5 S Q RD RD RD Q - PWM LATCH 7 OUT 8 VDD 6 GND 1 ILIM - 30 * I (MODE=1) 80 (MODE = 0) Q + S + RD Q UVLO UCC35705 (8.8 V/8 V) UCC35706 (12 V/8 V) - 100 mV 0.7 V PWM - + FB 2 + 30 k 20 k 200 mV CURRENT LIMIT 1 pF + - Figure 1. Block Diagram FUNCTIONAL DESCRIPTION oscillator and PWM The oscillator can be programmed to provide a duty cycle clamp or be configured to run at the maximum possible duty cycle. The PWM latch is set during the oscillator discharge and is reset by the PWM comparator when the CT waveform is greater than the feedback voltage. The voltage at the FB pin is attenuated before it is applied to the PWM comparator. The oscillator ramp is shifted by approximately 0.65-V at room temperature at the PWM comparator. The offset has a temperature coefficient of approximately -2 mV/C. The ILIM comparator adds a pulse by pulse current limit by resetting the PWM latch when VILIM > 200 mV. The PWM latch is also reset by a low line condition (VFF <1.0 V). All reset conditions are dominant; asserting any output will force a zero duty cycle output. oscillator with duty cycle clamp (MODE = 1) The timing capacitor CT is charged from ground to VFF through RT. The discharge path is through an on-chip current sink that has a value of 30 x IDISCH, where IDISCH is the current through the external resistor RDISCH. Since the charge and discharge currents are both proportional to VIN, their ratio, and the maximum duty cycle remains constant as VIN varies. www.ti.com 5 SLUS473A - NOVEMBER 1999 - REVISED MARCH 2001 FUNCTIONAL DESCRIPTION V IN R T R DISCH RC 5 DISCH 4 VDD CT I DISCH 30 * I DISCH 2 * IDISCH VFF 3 R Figure 2. Duty Cycle Clamp (MODE = 1) The on-time is approximately: T ON +T RT CT where T+ V FF 2 R FF [ V IN R DISCH The off-time is: T OFF +T RT RDISCH RT * RDISCH CT 30 The frequency is: f+ T 1 RT CT 1) 1 RDISCH 30 RT*RDISCH The maximum duty cycle is: Duty Cycle + 6 T ON R + 1 * DISCH T ON ) T OFF 30 R T www.ti.com FF SLUS473A - NOVEMBER 1999 - REVISED MARCH 2001 FUNCTIONAL DESCRIPTION component selection for oscillator with duty cycle clamp (MODE = 1) For a power converter with the following specifications: D D D D D VIN(min) = 18 V VIN(max) = 75 V VIN(shutdown) = 15 V FOSC = 1 MHz DMAX = 0.78 at VIN(min) In this mode, the on-time is approximately: D TON(max) = 780 ns D TOFF(min) = 220 ns D VFF(min) = 18 = 1.20 V 15 (1) Pick CT = 220 pF. (2) Calculate RT. RT + T ON(max) V INmin V FFmin CT RT = 51.1 k (3) RDISCH R DISCH + 30 1 ) VFF(min) VIN(min) RT RT CT TOFF(min) RDISCH = 383 k. IDISCH must be between 25 A and 250 A over the entire VIN range. With the calculated values, IDISCH ranges from 44 A to 193 A, within the allowable range. If IDISCH is too high, CT must be decreased. (4) RFF R FF + V FF(min) 2 R DISCH VIN(min) * 1 The nearest 1% standard value to the calculated value is 13.7 k. www.ti.com 7 SLUS473A - NOVEMBER 1999 - REVISED MARCH 2001 FUNCTIONAL DESCRIPTION oscillator without duty cycle clamp (MODE = 0) In this mode, the timing capacitor is discharged through a low impedance directly to ground. The DISCH pin is externally grounded. A comparator connected to DISCH senses the ground connection and disables both the discharge current source and VFF current source. A resistor divider is now required to set VFF. V IN RT RC 5 DISCH 4 CT VFF 3 Figure 3. Ocsillator Without Clamp (MODE = 0) In this mode, the on-time is approximately: T ON +T RT CT where T+ V FF V IN The off-time is: T OFF [ 75 ns The frequency is: f+ 8 T RT 1 C T ) 75 ns www.ti.com SLUS473A - NOVEMBER 1999 - REVISED MARCH 2001 FUNCTIONAL DESCRIPTION component selection for oscillator without duty cycle clamp (MODE = 0) For a power converter with the following specifications: D D D D VIN(min) = 18 V VIN(max) = 75 V VIN(shutdown) = 15 V FOSC = 1 MHz With these specifications, V FF(min) + 18 + 1.2 V 15 (1) Pick CT = 220 pF (2) Calculate RT. VIN(min) RT + VFF(min) 1 * 75 ns FOSC CT TYPICAL CHARACTERISTICS UCC35706 UVLO THRESHOLDS vs TEMPERATURE UCC35705 UVLO THRESHOLDS vs TEMPERATURE 8.9 13 8.8 12 UVLO - Thresholds - V UVLO - Thresholds - V 8.7 8.6 8.5 8.4 8.3 11 10 9 8.2 8 8.1 7 8.0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 Temperature Temperature C Figure 4 50 75 100 125 C Figure 5 www.ti.com 9 SLUS473A - NOVEMBER 1999 - REVISED MARCH 2001 TYPICAL CHARACTERISTICS OPERATING CURRENT (AT 1mHz) vs TEMPERATURE LOW-LINE THRESHOLD vs. TEMPERATURE 1.05 4.7 1.04 4.6 1.03 Low-Line Threshold - V 4.8 IDD - mA 4.5 4.4 4.3 4.2 1.02 1.01 1.00 0.99 4.1 0.98 4.0 0.97 3.9 0.96 3.8 0.65 -50 -25 0 25 50 75 100 -50 125 -25 50 75 Figure 6 Figure 7 OSCILLATOR FREQUENCY vs TEMPERATURE PROGRAMMABLE MAXIMUM DUTY CYCLE vs TEMPERATURE 100 125 100 125 82 Programmable Maximum Duty Cycle -% 1.10 Oscillator Frequency - MHz 25 Temperature C Temperature C 1.05 1.00 0.95 0.90 80 78 76 74 72 70 68 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 Temperature C Temperature C Figure 9 Figure 8 10 0 www.ti.com 75 SLUS473A - NOVEMBER 1999 - REVISED MARCH 2001 TYPICAL CHARACTERISTICS CURRENT-LIMIT THRESHOLD vs TEMPERATURE CURRENT-LIMIT PROP DELAY vs TEMPERATURE 35 220 33 215 Current-Limit Prop Delay -ns Current-Limit Threshold -mV 31 210 205 200 195 190 29 27 25 23 21 19 185 17 180 15 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature C Temperature C Figure 11 Figure 10 www.ti.com 11 SLUS473A - NOVEMBER 1999 - REVISED MARCH 2001 MECHANICAL DATA Detailed package drawing for MSOP-8 (DGK) is shown below. For SOIC-8 (D) and PDIP-8 (P) package drawings, consult Packaging Section of the Power Supply Control Data Book (TI Literature Number SLUD003). DGK (MSOP-8) MINI SMALL OUTLINE PACKAGE 0,38 0,25 0,65 8 0,25 M 5 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0-6 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073329/B 04/98 NOTES: A. B. C. D. 12 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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