TPS65320QPWPRQ1 - Texas Instruments

GND

BOOT

VIN

RT/CLK

Supply

nRST

FB1

EN2

COMP

TPS65320-Q1

EN1

PowerPAD

VI = 3.6 V to 40 V

LDO_OUT

VIN_LDO

FB2

LDO Input

Auto Source

Regulator

Control

1.1 V to 20 V, 3.2 A

1.1 V to 7 V, 280 mA

100

0.0 1.0 2.0 3.0 4.0

Efficiency (%)

Output Current (A)

fsw = 300kHz

fsw = 2MHz

C001

VI= 14 V

VO= 5 V

fS= 300 kHz

fS= 2 MHz

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Folder

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Buy

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Design

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS65320-Q1

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

TPS65320-Q1 40-V Step-Down Converter With Eco-mode™ and LDO Regulator

1 Features

1• Qualified for Automotive Applications

• AEC-Q100 Qualified With the Following Results:

– Device Temperature Grade 1: –40°C to

+125°C Ambient Operating Temperature

– Device HBM ESD Classification Level 2

– Device CDM ESD Classification Level C4B

• One High-VIN Step-Down Converter

– 3.6- to 40-V Input Range

– 250-mΩHigh-Side MOSFET

– 3.2-A Maximum Load Current, 1.1- to 20-V

Output Adjustable

– 100-kHz to 2.5-MHz Adjustable Switch-Mode

Frequency

– Less Than 140-µA Operating Quiescent

Current

• One Low-Dropout Voltage Regulator (LDO)

– 280-mA Current Capability With 28-μA

(Typical) Operating Quiescent Current in No-

Load Condition

– Input Supply Auto-Source to Balance

Efficiency and Low Standby Current

– Power-Good Output (Push-Pull)

– Low-Dropout Voltage of 300 mV at IOUT = 200

mA (Typical)

• Overcurrent Protection for Both Regulators

• Overtemperature Protection

• 14-Pin HTSSOP Package With PowerPAD™

Package

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

2 Applications

• Automotive Infotainment and Cluster

• Advanced Driver Assistance System (ADAS)

• Telematics

3 Description

The TPS65320-Q1 device is a combination of a 40-V,

3.2-A, DC-DC step-down converter and a low-dropout

(LDO) regulator. The DC-DC step-down converter,

referred to as the buck regulator, has an integrated

high-side MOSFET. The LDO regulator also has an

integrated MOSFET and a low-input supply current of

28-μA (typical) in a no-load condition. Furthermore,

the LDO regulator has an active-low, push-pull reset

output pin. To reduce heat, the input supply of the

LDO regulator can auto-source from the input voltage

to the output of the buck regulator. The low-voltage

tracking feature can eliminate the need to use a boost

converter during cold-crank conditions.

The buck regulator has a switching frequency range

from 100 kHz to 2.5 MHz that provides a flexible

design to fix system requirements. The external loop

compensation allows for optimization of the converter

response for the appropriate operating conditions. A

low-ripple pulse-skip mode reduces the no-load input

supply current to less than 140 μA.

The device has built-in protection features such as

soft start, current limit, thermal sensing, and

shutdown because of excessive power dissipation.

Furthermore, the device has an internal undervoltage-

lockout (UVLO) function that turns off the device at a

too-low supply voltage.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS65320-Q1 HTSSOP (14) 5.00 mm × 4.40 mm

Typical Application Schematic Buck Efficiency Versus Output Current

TPS65320-Q1

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 4

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 Timing Requirements................................................ 8

6.7 Switching Characteristics.......................................... 8

6.8 Typical Characteristics.............................................. 8

7 Detailed Description............................................ 10

7.1 Overview................................................................. 10

7.2 Functional Block Diagram....................................... 11

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 21

8 Application and Implementation ........................ 22

8.1 Application Information............................................ 22

8.2 Typical Applications ................................................ 22

9 Power Supply Recommendations...................... 33

10 Layout................................................................... 34

10.1 Layout Guidelines ................................................. 34

10.2 Layout Example .................................................... 35

11 Device and Documentation Support................. 36

11.1 Device Support...................................................... 36

11.2 Documentation Support ........................................ 36

11.3 Community Resource............................................ 37

11.4 Trademarks........................................................... 37

11.5 Electrostatic Discharge Caution............................ 37

11.6 Glossary................................................................ 37

12 Mechanical, Packaging, and Orderable

Information........................................................... 37

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (December 2015) to Revision F Page

• Added the VIN – VIN_LDO supply input parameter back to the Absolute Maximum Ratings table...................................... 5

• Changed the Buck-Regulator Output Voltage,Buck-Regulator Feedback-Voltage Reference (V(FB1)) vs Junction

Temperature,LDO-Regulator Load Regulation,LDO-Regulator Dropout Voltage vs Load Current, and LDO-

Regulator Feedback-Voltage Reference (V(FB2)) vs Junction Temperature graphs in the Typical Characteristics

section ................................................................................................................................................................................... 8

• Updated the LDO Regulator section ................................................................................................................................... 19

Changes from Revision D (June 2015) to Revision E Page

• Updated the function of the BOOT pin .................................................................................................................................. 4

• Deleted the VIN – VIN_LDO supply input parameter from the Absolute Maximum Ratings table......................................... 5

Changes from Revision C (March 2015) to Revision D Page

• Changed nRST pin description from open-drain to push-pull in the Pin Functions table ..................................................... 4

• Changed the TJ value in the condition statement of the Electrical Characteristics from –150°C to –40°C to 150°C ........... 6

Changes from Revision B (September 2013) to Revision C Page

• Changed the ESD Ratings table, Feature Description section, Device Functional Modes section, Application and

Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation

Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1

• Updated the Applications section........................................................................................................................................... 1

• Updated Features and Description sections ......................................................................................................................... 1

• Changed the MIN value for the VIN_LDO supply input from 3.6 to 3 in the Recommended Operating Conditions

table ....................................................................................................................................................................................... 5

• Changed the MAX value for the shutdown supply current from 5 to 7 ................................................................................. 6

TPS65320-Q1

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• Added the Initial start-up voltage parameter ......................................................................................................................... 6

• Changed the MIN value of the Internal UVLO rising threshold parameter from 2.5 to 2.2 ................................................... 6

• Changed the MIN value of the Operating input voltage (VIN_LDO) from 4 to 3 ................................................................... 7

• Updated the FB2 voltage reference test condition ................................................................................................................ 7

• Changed the MAX value of the Quiescent current parameter from 40 to 75 and add TJto test condition ........................... 7

• Added the V(LDO_OUT) value to the Output capacitor parameter test conditions...................................................................... 7

• Changed the TYP value for the Thermal-shutdown trip point from 170 to 155 ..................................................................... 7

• Changed the minimum value of the soft-start capacitor from 0.47 nF to 1 nF in the Soft-Start and Tracking Pin

(SS/TR) section ................................................................................................................................................................... 13

• Changed the 300-kHz switching frequency application to 500-kHz switching frequency Design Example With 300-

kHz Switching Frequency section ........................................................................................................................................ 31

Changes from Revision A (April 2013) to Revision B Page

• Deleted the word, Codec, from document title....................................................................................................................... 1

• Changed first bullet item in APPLICATIONS from Qualified for Automotive Applications to Automotive.............................. 1

• Added min value for ISS parameter in ELECTRICAL CHARACTERISTICS table.................................................................. 7

• Added test condition to Output high parameter under RESET (nRST PIN) in ELECTRICAL CHARACTERISTICS table.... 7

• Added push-pull stage and nRS release text to Power-Good Output, nRST section.......................................................... 20

Thermal

Pad

1BOOT 14 SW

2VIN 13 GND

3VIN_LDO 12 COMP

4LDO_OUT 11 FB1

5FB2 10 SS

6nRST 9 RT/CLK

7EN2 8 EN1

TPS65320-Q1

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

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5 Pin Configuration and Functions

PWP Package

14-Pin HTSSOP With PowerPAD

Top View

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

BOOT 1 O A bootstrap capacitor is required between the BOOT and SW pins to supply the bias voltage for the

integrated high-side MOSFET.

COMP 12 O Error-amplifier output of the buck regulator, and input to the output-switch current comparator of the

buck regulator. Connect frequency-compensation components to the COMP pin.

EN1 8 I Enable and disable input for the buck regulator (high-voltage tolerant) internally pulls to ground. Pull this

pin up externally to enable the buck regulator.

EN2 7 I Enable and disable input for the LDO regulator (high-voltage tolerant) internally pulls to ground. Pull this

pin up externally to enable the LDO regulator.

FB1 11 I Feedback pin of the buck regulator. Connect an external resistive divider between the buck regulator

output, FB2, and GND to set the desired output voltage of the buck regulator.

FB2 5 I Feedback pin of the LDO regulator. Connect an external resistive divider between LDO_OUT, FB2, and

GND for setting the desired output voltage of the LDO regulator

GND 13 — Ground

LDO_OUT 4 O LDO regulator output

nRST 6 O Active-low, push-pull reset output of the LDO regulator. Connect this pin with an external bias voltage

through an external resistor. This pin is asserted high after the LDO regulator begins regulating.

RT/CLK 9 I External resistor connected to ground to program the switching frequency of the buck regulator. An

alternative option is to feed an external clock to provide a reference for the switching frequency of the

buck regulator.

SS 10 I External capacitor to ground that sets the soft-start time of the buck regulator

SW 14 I Source node of the internal high-side MOSFET of the buck regulator

VIN 2 — Input supply pin for the internal biasing and high-side MOSFET of the buck regulator

VIN_LDO 3 — Input supply pin for the LDO regulator

Exposed PowerPAD — Electrically connect the PowerPAD to ground. Solder the PowerPAD to the ground plane of the PCB for

thermal performance.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Supply inputs VIN –0.3 45 V

VIN_LDO –0.3 20

VIN – VIN_LDO –0.3 45

Control EN1, EN2 –0.3 45 V

EN1-VIN, EN2-VIN 1

Buck converter

FB1 –0.3 3.6

SW –0.3

–2 V for 30 ns 40

BOOT –0.3 46

BOOT-SW 8

COMP –0.3 3.6

SS –0.3 3.6

RT/CLK, SS –0.3 3.6

LDO regulator LDO_OUT –0.3 7 VFB2 –0.3 7

nRST –0.3 7

Operating ambient temperature, TA–40 125 °C

Operating junction temperature, TJ–40 150

Storage temperature, Tstg –55 165 °C

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic

discharge

Human-body model (HBM), per AEC Q100-002(1) ±2000 V

Charged-device model (CDM), per AEC Q100-011 All pins ±500

Corner pins (1, 7, 8, and 14) ±750

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

Supply inputs VIN 3.6 40 V

VIN_LDO 3 20

Buck regulator

BOOT1 3.6 46

SW1 –1 40

VFB1 0 3

SS 0 3

COMP 0 3

RT/CLK 0 3

LDO regulator LDO_OUT 1.1 5.5 VVFB2 0 5.25

nRST 0 5.25

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Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

Control EN1 0 40 V

EN2 0 40

Operating junction temperature, TJ–40 150 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRS953.

6.4 Thermal Information

THERMAL METRIC(1) TPS65320-Q1

UNITPWP (HTSSOP)

14 PINS

RθJA Junction-to-ambient thermal resistance 49.9 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 31 °C/W

RθJB Junction-to-board thermal resistance 26.6 °C/W

ψJT Junction-to-top characterization parameter 1 °C/W

ψJB Junction-to-board characterization parameter 26.4 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 3.7 °C/W

6.5 Electrical Characteristics

VI= 6 V to 27 V, EN1 = EN2 = VI, over-operating free-air temperature range TA= –40°C to +125°C and maximum operating

junction temperature TJ= –40°C to +150°C, unless otherwise noted. VIis the voltage on the battery-supply pins, VIN and

VIN_LDO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIN (INPUT POWER SUPPLY)

Operating input voltage Normal mode, after initial start-up 3.6 14 40 V

Shutdown supply current V(EN1) = V(EN2) = 0 V, 25°C 2 7 μA

Initial start-up voltage 6 40 V

ENABLE AND UVLO (EN1 AND EN2 PINS)

Enable low level 0.7 V

Enable high level 2.5 V

V(VIN)(f) Internal UVLO falling threshold Ramp V(VIN) down until output turns OFF 2 2.6 3 V

V(VIN)(r) Internal UVLO rising threshold Ramp V(VIN) up until output turns ON 2.2 2.8 3.2 V

BUCK REGULATOR

Operating: non-switching supply V(FB1) = 0.83 V, V(VIN) = 12 V, 25°C 110 140 μA

Output capacitor ESR = 0.001 Ωto 0.1 Ω, large output

capacitance may be required for load

transient 10 μF

BUCK REGULATOR: HIGH-SIDE MOSFET

On-resistance V(VIN) = 12 V, V(SW) = 6 V 127 250 mΩ

BUCK REGULATOR: ERROR AMPLIFIER

Input current 50 nA

Error-amplifier transconductance

(gm) –2 µA < I(COMP) < 2 µA, V(COMP) = 1 V 310 µS

Error-amplifier transconductance

(gm) during soft start –2 µA < I(COMP) < 2 µA, V(COMP) = 1 V

V(FB1) = 0.4 V 70 µS

Error-amplifier dc gain V(FB1) = 0.8 V 100 dB

Error-amplifier bandwidth 6000 kHz

Error-amplifier source or sink V(COMP) = 1 V, 100-mV overdrive ±27 μA

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Electrical Characteristics (continued)

VI= 6 V to 27 V, EN1 = EN2 = VI, over-operating free-air temperature range TA= –40°C to +125°C and maximum operating

junction temperature TJ= –40°C to +150°C, unless otherwise noted. VIis the voltage on the battery-supply pins, VIN and

VIN_LDO. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

COMP to switch-current

transconductance 10.5 S

Vref1 Voltage reference for FB1 pin Buck regulator output: 3.6 V to 10 V 0.788 0.8 0.812 V

BUCK REGULATOR: CURRENT-LIMIT

Current-limit threshold V(VIN) = 12 V, TJ= 25°C 4 6 A

BUCK REGULATOR: TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)

RT/CLK High threshold 1.9 2.2 V

RT/CLK Low threshold 0.5 0.7 V

BUCK REGULATOR: INTERNAL SOFT START TIMER

IS(SS) Soft-start source current V(SS) = 0 V 1 2 4 μA

LDO REGULATOR

ΔVO(ΔVI) Line regulation V(VIN) = 6 V to 30 V, I(LDO_OUT) = 10 mA,

V(LDO_OUT) = 3.3 V 20 mV

ΔVO(ΔIL) Load regulation I(LDO_OUT) = 10 mA to 200 mA, V(VIN_LDO) = 14

V, V(LDO_OUT) = 3.3 V 35 mV

VDROPOUT

(V(VIN_LDO)

–

V(LDO_OUT))

Dropout voltage I(LDO_OUT) = 200 mA 300 450 mV

I(LDO_OUT) Output current V(LDO_OUT) in regulation 0 280 mA

Error-amplifier dc gain 800 V/V

V(VIN_LDO) Operating input voltage on

VIN_LDO pin Buck regulator is in regulation and supplying

at least LDO output plus dropout voltage

VDROPOUT 3 20 V

Vref2 Voltage reference for FB2 pin V(LDO_OUT) = 1.2 V to 5 V 0.788 0.8 0.812 V

ICL(LDO_OUT) Output current limit V(LDO_OUT) = 0 V (LDO_OUT pin is shorted to

ground.) 280 1000 mA

IQ(LDO) Quiescent current V(VIN) > 9 V, V(EN1) = 0 V, V(EN2) = 5 V,

I(LDO_OUT) = 0.01 mA to 0.75 mA, TJ= 25°C 28 75 μA

PSRR Power supply ripple rejection V(VIN_LDO)(rip) = 0.5 VPP, I(LDO_OUT) = 200 mA,

frequency = 100 Hz, V(LDO_OUT) = 5 V and

V(LDO_OUT) = 3.3 V 60 dB

PSRR Power supply ripple rejection VVIN_LDO(rip) = 0.5 VPP, I(LDO_OUT) = 200 mA,

frequency = 150 kHz, V(LDO_OUT) = 5 V and

V(LDO_OUT) = 3.3 V 30 dB

Output capacitor

ESR = 0.001 Ωto 100 mΩ, large output

capacitance may be required for load

transient, V(LDO_OUT) ≥3.3 V 1 40 μF

ESR = 0.001 Ωto 100 mΩ, large output

capacitance may be required for load

transient, 1.2 V ≤V(LDO_OUT) < 3.3 V 20 40 μF

LDO REGULATOR: RESET (nRST PIN)

RESET threshold V(LDO_OUT) decreasing 88% 92% 95%

VOH Output high Reset released due to rising LDO_OUT,

V(LDO_OUT) ≥3.3 V, IOH = 100 µA –5% ×

V(LDO_OUT) V

VOL Output low Reset asserted due to falling LDO_OUT, IOL =

1 mA 0 0.045 0.4 V

OVERTEMPERATURE PROTECTION

TSD Thermal-shutdown trip point 155 ºC

Thys Hysteresis 10 ºC

100

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

% of Nominal ƒ

F 1 Voltage (V)B C004

Input Voltage (V)

Output Voltage (V)

3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 5.75

1.5

2.5

3.5

4.5

5.5

No Load

100-mA Load

1-A Load

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6.6 Timing Requirements

VI= 6 V to 27 V, EN1 = EN2 = VI, over-operating free-air temperature range TA= –40°C to +125°C and maximum operating

junction temperature TJ= –40°C to +150°C, unless otherwise noted MIN TYP MAX UNIT

BUCK REGULATOR: TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)

Minimum CLK input pulse width 40 ns

6.7 Switching Characteristics

VI= 6 V to 27 V, EN1 = EN2 = VI, over-operating free-air temperature range TA= –40°C to +125°C and maximum operating

junction temperature TJ= –40°C to +150°C, unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

BUCK REGULATOR: HIGH-SIDE MOSFET

tonmin Minimum on-time ƒS= 2.5 MHz 100 ns

BUCK REGULATOR: TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)

ƒSSwitching-frequency range using

RT mode 100 2500 kHz

ƒSSwitching frequency 200 kΩconnected between pin RT/CLK

and GND 450 581 720 kHz

ƒSSwitching-frequency range using

CLK mode 300 2200 kHz

RT/CLK Falling edge to SW rising edge

delay Measured at 500 kHz with 200-kΩseries

resistor connected to RT/CLK pin 60 ns

PLL Lock-in time Measured at 500 kHz 100 μs

LDO REGULATOR: RESET (nRST PIN)

Filter time Delay before asserting nRST low 6 10 15 μs

6.8 Typical Characteristics

ƒS= 2 MHz

Figure 1. Buck-Regulator Output Voltage

V(VIN) = 12 V

Figure 2. Buck-Regulator Switching Frequency vs V(FB1)

Feedback Voltage

0.790

0.792

0.794

0.796

–50 –25 0 25 50 75 100 125 150

LDO-Regulator Feedback-Voltage Reference (V)

Junction Temperature (°C) C010

3.292

3.294

3.296

3.298

3.300

3.302

3.304

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

Output Voltage (V)

LDO Load Current (A) C008

100

150

200

250

300

350

400

450

500

0 50 100 150 200 250 300 350 400

Dropout Voltage (mV)

LDO Load Current (mA) C009

500

1000

1500

2000

2500

3000

0 200 400 600 800 1000 1200 1400 1600

Switching Frequency (kHz)

RT/CLK Resistance (kΩ) C003

0.790

0.792

0.794

0.796

0.798

–50 –25 0 25 50 75 100 125 150

Buck-Regulator Feedback-Voltage Reference (V)

Junction Temperature (°C) C007

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Typical Characteristics (continued)

V(VIN) = 12 V TJ= 25°C

Figure 3. Buck-Regulator Switching Frequency vs RT_CLK

Resistance

No Load V(VIN) = 12 V

Figure 4. Buck-Regulator Feedback-Voltage Reference

(V(FB1)) vs Junction Temperature

V(VIN_LDO) = 5 V V(LDO_OUT) = 3.3 V

Figure 5. LDO-Regulator Load Regulation Figure 6. LDO-Regulator Dropout Voltage vs Load Current

I(LDO_OUT) = 100 mA V(VIN_LDO) = 12 V

Figure 7. LDO-Regulator Feedback-Voltage Reference (V(FB2)) vs Junction Temperature

TPS65320-Q1

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

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7 Detailed Description

7.1 Overview

The TPS65320-Q1 buck regulator is a 40-V, 3.2-A, step-down (buck) converter with a 280-mA LDO linear

regulator. Both regulators have low quiescent consumption during a light loads to prolong the battery life.

The buck converter improves performance during line and load transients by implementing a constant-frequency

and current-mode control that reduces output capacitance, simplifying external frequency-compensation design.

The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting

the output-filter components. The switching frequency can be adjusted by using a resistor to ground on the

RT/CLK pin. The buck converter has an internal phase-locked loop (PLL) on the RT/CLK pin that synchronizes

the power switch turnon to the falling edge of an external system clock.

The TPS65320-Q1 buck regulator reduces the external component count by integrating the boot recharge diode.

A capacitor between the BOOT and SW pins supplies the bias voltage for the integrated high-side MOSFET. The

output voltage can be stepped down to as low as the 0.8-V reference. The soft-start feature minimizes inrush

currents and provides power-supply sequencing during power up. Connect a small-value capacitor to the SS pin

to adjust the soft-start time. Couple a resistor divider to the pin for critical power-supply sequencing

requirements.

The LDO regulator only consumes about 40-µA current in light loads. The LDO regulator can also track the

battery when battery voltage is low (in a cold-crank condition). The input of the LDO regulator has a unique auto-

source feature which sources the input supply from either the buck output or the battery. If both the buck and

LDO regulators are enabled, the buck regulator switches the input of the LDO regulator to the output of the buck

to reduce heat. With the buck disabled or the buck output voltage out of regulation (VFB1 less than 91% of Vref),

the buck regulator switches the LDO input automatically to the input voltage.

The LDO regulator of the TPS65320-Q1 device has a power-good comparator (nRST) that asserts when the

regulated output voltage is less than 91% of the nominal output voltage.

ERROR

AMPLIFIER

Boot

Charge

Current

Sense

Logic

Slope

Compensation

PWM

Latch

PWM

Comparator

Minimum

Clamp

Pulse

Skip

Maximum

Clamp

Voltage

Reference

Overload

Recovery

FB1

SS/TR

COMP

RT/CLK

BOOT

VIN

GND

EN1

Shutdown

Enable

Threshold



Logic

Shutdown PWRGD

PowerPAD

Shutdown

OVTO

EN2

LDO_OUT

FB2

Linear Regulator

Control

0.8 V

Voltage

Supervisor

VIN_LDO

LDO Input

Selection

VIN

Shutdown

Logic

Oscillator

with PLL

Thermal

Shutdown UVLO

Boot

UVLO

nRST

Frequency

Shift

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7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Buck Regulator

7.3.1.1 Fixed-Frequency PWM Control

The TPS65320-Q1 buck regulator uses an adjustable, fixed-frequency peak-current mode control. An internal

voltage reference compares the output voltage through external resistors on the FB1 pin to an error amplifier

which drives the COMP pin. An internal oscillator initiates the turnon of the high-side power switch. The buck

regulator compares the error amplifier output to the high-side power-switch current. When the power-switch

current reaches the level set by the COMP voltage, the power switch turns off. The COMP pin voltage increases

and decreases as the output current increases and decreases. The buck regulator implements a current limit by

clamping the COMP pin voltage to a maximum level.

7.3.1.2 Slope Compensation Output

The TPS65320-Q1 buck regulator adds a compensating ramp to the switch current signal. This slope

compensation prevents sub-harmonic oscillations. The available peak-inductor current remains constant over the

full duty-cycle range.

TPS65320-Q1

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

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Product Folder Links: TPS65320-Q1

Feature Description (continued)

7.3.1.3 Pulse-Skip Eco-mode™ Control Scheme

The TPS65320-Q1 buck regulator operates in a pulse-skip mode at light load currents to improve efficiency by

reducing switching and gate-drive losses. The design of the TPS65320-Q1 buck regulator is such that if the

output voltage is within regulation and the peak switch current at the end of any switching cycle is below the

pulse-skipping-current threshold, the buck regulator enters pulse-skip mode. This current threshold is the current

level corresponding to a nominal COMP voltage, or 720 mV. The current at which entry to the pulse-skip mode

occurs depends on switching frequency, inductor selection, output-capacitor selection, and compensation

network.

In pulse-skip mode, the buck regulator clamps the COMP pin voltage at 720 mV, inhibiting the high-side

MOSFET. Further decreases in load current or in output voltage cannot drive the COMP pin below this clamp-

voltage level. Because the buck regulator is not switching, the output voltage begins to decay. As the voltage-

control loop compensates for the falling output voltage, the COMP pin voltage begins to rise. At this time, the

high-side MOSFET turns on and a switching pulse initiates on the next switching cycle. The peak current is set

by the COMP pin voltage. The output current recharges the output capacitor to the nominal voltage, then the

peak switch current begins to decrease, and eventually falls below the pulse-skip-mode threshold, at which time

the buck regulator enters Eco-mode again.

For pulse-skip-mode operation, the TPS65320-Q1 buck regulator senses the peak current, not the average or

load current. Therefore, the load current where the buck regulator enters pulse-skip mode is dependent on the

output inductor value. When the load current is low and the output voltage is within regulation, the buck regulator

enters a sleep mode and draws only 140-µA input quiescent current. The internal PLL remains operating when

the buck regulator is in sleep mode.

7.3.1.4 Dropout Operation and Bootstrap Voltage (BOOT)

The TPS65320-Q1 buck regulator has an integrated boot regulator and requires a small ceramic capacitor

between the BOOT and SW pins to provide the gate-drive voltage for the high-side MOSFET. The BOOT

capacitor recharges when the high-side MOSFET is off and the low-side diode conducts. The value of this

ceramic capacitor should be 0.1 µF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric

and a voltage rating of 10 V or higher because of the stable characteristics over temperature and voltage.

To improve drop out, the high-side MOSFET of the TPS65320-Q1 buck regulator remains on for 7 consecutive

switching cycles, and is forced off during the 8th switching cycle to allow the low-side diode to conduct and

refresh the charge on the BOOT capacitor. Because the current supplied by the BOOT capacitor is low, the high-

side of the MOSFET can remain on longer before it is required to refresh the BOOT capacitor.

Voltage drops across the power MOSFET, inductor resistance, low-side diode, and printed circuit board

resistance are the main influence on the effective duty cycle during dropout of the regulator. During operating

conditions in which the input voltage drops and the regulator is operating in continuous-conduction mode (CCM),

the high-side MOSFET can remain on for 100% of the duty cycle to maintain output regulation until the BOOT to

SW voltage falls below 2.1 V.

Careful attention must be given to maximum duty cycle applications that experience extended time periods with

light loads or no load. When the voltage across the BOOT capacitor falls below the 2.1-V UVLO threshold, the

high-side MOSFET turns off, however not-enough inductor current exists to pull the SW pin down to recharge the

BOOT capacitor. The high-side MOSFET of the regulator stops switching because the voltage across the BOOT

capacitor is less than 2.1 V. The output capacitor then decays until the difference in the input voltage and output

voltage is greater than 2.1 V, which exceeds the BOOT UVLO threshold, and the buck regulator begins switching

again until reaching the desired output voltage. This operating condition persists until the input voltage, the load

current, or both increase.

7.3.1.5 Error Amplifier

The buck converter of the TPS65320-Q1 buck regulator has a transconductance amplifier acting as the error

amplifier. The error amplifier compares the FB1 voltage to the lower of the internal soft-start (SS) voltage or the

internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 310 µS during normal

operation. During the soft-start operation, the transconductance is a fraction of the normal operating gm. When

the voltage of the voltage on the FB1 pin is below 0.8 V and the buck regulator is regulating using an internal SS

voltage, the gm is 70 µS. For frequency compensation, external compensation components (capacitor with series

resistor and an optional parallel capacitor) must be connected between the COMP pin and the GND pin.

T1.0888

206033

R (k ) ƒ (kHz)

W =

SS SS

ref

t (ms) I (µA)

C (nF) V (V) 0.8

V 0.8 (V)

R1 R2 0.8 (V)

= ´

TPS65320-Q1

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Product Folder Links: TPS65320-Q1

Feature Description (continued)

7.3.1.6 Voltage Reference

The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output

of a temperature-stable bandgap circuit.

7.3.1.7 Adjusting the Output Voltage

A resistor divider from the output node to the FB1 pin sets the output voltage. Using a divider resistor with a

tolerance of 1% or better is recommended. Begin with a value of 10 kΩfor the R2 resistor and use Equation 1 to

calculate the value of R1. To improve efficiency at light loads, consider using larger-value resistors. If the values

are too high, the regulator is more susceptible to noise and voltage errors from the FB1 input current are

noticeable.

where

• VOis the buck regulator output voltage (1)

7.3.1.8 Soft-Start and Tracking Pin (SS/TR)

The TPS65320-Q1 buck regulator effectively uses the lower voltage of the internal voltage reference or the

SS/TR pin voltage as the reference voltage of the power supply and regulates the output accordingly. A capacitor

on the SS/TR pin to ground implements a soft-start time. The TPS65320-Q1 buck regulator has an internal

pullup-current source of 2 µA that charges the external soft-start capacitor. Use Equation 2 to calculate to

calculate the value of the soft-start capacitor, CSS, which sets the soft-start time, tSS (10% to 90%). The soft-start

capacitor should remain lower than 0.47 μF and greater than 1 nF.

where

• The voltage reference (Vref) is 0.8 V.

• The soft-start current (ISS) is 2 µA (2)

At power up with the EN1 pin or after recovering from a UVLO event or from a thermal shutdown event, the

TPS65320-Q1 buck regulator does not begin switching until the soft-start pin, SS/TR, discharges to less than 40

mV to ensure a proper power up.

7.3.1.9 Overload Recovery Circuit

The TPS65320-Q1 buck regulator has an overload recovery (OLR) circuit. The OLR circuit soft-starts the output

from the overload voltage to the nominal regulation voltage on removal of the fault condition. The OLR circuit

discharges the SS/TR pin to a voltage slightly greater than the FB1 pin voltage using an internal pulldown of 382

µA when the error amplifier changes to a high voltage from a fault condition. On removal of the fault condition,

the output soft-starts from the fault voltage to the nominal output voltage.

7.3.1.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)

The switching frequency of the TPS65320-Q1 buck regulator is adjustable over a wide range from approximately

100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and

must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given

switching frequency, use Equation 3 or the curves in Figure 2. To reduce the solution size, the user typically sets

the switching frequency as high as possible, but consider tradeoffs of the supply efficiency, maximum input

voltage, and minimum controllable on-time. The minimum controllable on-time is typically 100 ns and limits the

maximum operating input voltage. The frequency-shift circuit also limits the maximum switching frequency. The

following sections discuss the maximum switching frequency in detail.

(3)

L DC O(SC) d

div

ON I L HS d

(I R V V )

ƒ (shift) t (V I R V )

´ + +

æ ö

= ´ ç ÷

ç ÷ ç ÷

- ´ +

è ø è ø

L DC O d

ON I L HS d

(I R V V )

ƒ (max skip) t (V I R V )

æ ö æ ö

´ + +

= ´

ç ÷ ç ÷

- ´ +

è ø è ø

TPS65320-Q1

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

www.ti.com

Product Folder Links: TPS65320-Q1

Feature Description (continued)

7.3.1.11 Overcurrent Protection and Frequency Shift

The TPS65320-Q1 buck regulator implements current mode control, which uses the COMP pin voltage to turn off

the high-side MOSFET on a cycle-by-cycle basis. During each cycle, the switch current and COMP pin voltage

are compared. When the peak switch current intersects the COMP voltage, the high-side switch turns off. During

overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high,

increasing the switch current. Internal clamping of the error-amplifier output functions as a switch-current limit.

The TPS65320-Q1 buck regulator implements a frequency shift. The switching frequency is divided by 8, 4, 2,

and 1 as the voltage ramps from 0 to 0.8 V on the FB1 pin. During short-circuit events (particularly with high-

input-voltage applications), the control loop has a finite minimum controllable on-time, and the output has a low

voltage. During the switch on-time, the inductor current ramps to the peak current limit because of the high input

voltage and minimum on-time. During the switch off-time, the inductor would normally not have enough off time

and output voltage for the inductor to ramp down by the ramp up amount. The frequency shift effectively

increases the off-time, allowing the current to ramp down.

7.3.1.12 Selecting the Switching Frequency

The switching frequency that is selected should be the lower value of the two equations, Equation 4 and

Equation 5. Use Equation 4 to calculate the maximum switching frequency limitation set by the minimum

controllable on-time. Setting the switching frequency above this value causes the regulator to skip switching

pulses. The buck regulator maintains regulation, but pulse-skipping leads to high inductor current and a

significant increase in output ripple voltage.

Use Equation 5 to calculate the maximum switching frequency limit set by the frequency-shift protection. For

adequate output short-circuit protection at high input voltages, set the switching frequency to a value less than

the ƒS(maxshift) frequency. In Equation 5, to calculate the maximum switching frequency one must take into

account that the output voltage decreases from the nominal voltage to 0 volts, and the ƒdiv integer increases from

1 to 8 corresponding to the frequency shift.

In Figure 8, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the

output voltage is zero volts, the resistance of the inductor is 0.130 Ω, the FET on-resistance is 0.127 Ω, and the

diode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping.

where

• tON = controllable on-time (typ. 100 ns)

• IL= inductor current

• RDC = inductor resistance

• VO= output voltage

• Vd= diode voltage drop

• VI= maximum input voltage

• RHS = FET on resistance (127 mΩtypical) (4)

where

• ƒdiv = frequency divide factor (equals 8, 4, 2 or 1)

• VO(SC) = output voltage during short (5)

RT/CLK

Rfset

10 pF 4 k

50 Ext Clock Source

PLL

TPS65320-Q1

500

1000

1500

2000

2500

10 20 30 40 50 60

Switchin Frequency (kHz)

Input Voltage (V)

fsw (Max Skip)

fsw (Shift)

C012

S(maxskip)

S(shift)

TPS65320-Q1

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Product Folder Links: TPS65320-Q1

Feature Description (continued)

IL= 1 A VO= 3.3 V

Figure 8. Maximum Switching Frequency versus Input Voltage

7.3.1.13 How to Interface to RT/CLK Pin

The RT/CLK pin synchronizes the buck regulator to an external system clock. To implement the synchronization

feature, connect a square wave to the RT/CLK pin through the circuit network shown in Figure 9. The square-

wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on-time

greater than 40 ns and an off-time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200

kHz. The rising edge of SW is synchronizes with the falling edge of RT/CLK pin signal. Design the external

synchronization circuit in such a way that the buck regulator has the default frequency-set resistor connected

from the RT/CLK pin to ground should the synchronization signal turn off. Using a frequency-set resistor

connected as shown in Figure 9 through a 50-Ωresistor to ground is recommended. The resistor should set the

switching frequency close to the external CLK frequency. TI also recommends AC-coupling the synchronization

signal through a 10-pF ceramic capacitor to the RT/CLK pin and a 4-kΩseries resistor. The series resistor

reduces SW jitter in heavy-load applications when synchronizing to an external clock, and in applications which

transition from synchronizing to RT mode. The first time CLK is pulled above the CLK threshold, the buck

regulator switches from the RT resistor frequency to PLL mode. Along with the resulting removal of the internal

0.5-V voltage source, the CLK pin becomes high-impedance as the PLL begins to lock onto the external signal.

Because regulator has a PLL, the switching frequency can be higher or lower than the frequency set with the

external resistor. The buck regulator transitions from the resistor mode to the PLL mode and then increases or

decreases the switching frequency until the PLL locks onto the CLK frequency within 100 ms.

When the buck regulator transitions from the PLL mode to the resistor mode, the switching frequency slows

down from the CLK frequency to 150 kHz, then reapplies the 0.5-V voltage. the resistor then sets the switching

frequency. The switching-frequency divisor changes to 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on the

FB1 pin. The buck regulator implements a digital frequency shift to enable synchronizing to an external clock

during normal startup and fault conditions.

Figure 9. Synchronizing to a System Clock

gmea = 310 A/V

Power Stage

gmps = 10.5 A/V a

RESR

Vref = 0.8 V

COMP

FB1

Error

Amplifier

Inside

TPS65320-Q1

Co_ea

TPS65320-Q1

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

www.ti.com

Product Folder Links: TPS65320-Q1

Feature Description (continued)

7.3.1.14 Overvoltage Transient Protection

The TPS65320-Q1 buck regulator incorporates an overvoltage transient-protection (OVTP) circuit to minimize

voltage overshoot when recovering from output fault conditions or strong unload transients on power-supply

designs with low-value output capacitance. For example, with the power-supply output overloaded, the error

amplifier compares the actual output voltage to the internal reference voltage. If the FB1 pin voltage is lower than

the internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the

error amplifier output to a high voltage, thus requesting the maximum output current. On removal of the condition,

the regulator output rises and the error-amplifier output transitions to the steady-state duty cycle. In some

applications, the power-supply output voltage can respond faster than the error-amplifier output can respond

which actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot

when using a low-value output capacitor by implementing a circuit to compare the FB1 pin voltage to the OVTP

threshold (which is 109% of the internal voltage reference). The FB1 pin voltage going higher than the OVTP

threshold disables the high-side MOSFET, preventing current from flowing to the output and minimizing output

overshoot. The FB1 voltage dropping lower than the OVTP threshold allows the high-side MOSFET to turn on at

the next clock cycle.

7.3.1.15 Thermal Shutdown

The buck regulator implements an internal thermal shutdown to protect the regulator if the junction temperature

exceeds 155°C (typical). The thermal shutdown forces the buck regulator to stop switching when the junction

temperature exceeds the thermal trip threshold. When the junction temperature decreases below 145°C (typical),

the buck regulator reinitiates the power-up sequence.

7.3.1.16 Small-Signal Model for Loop Response

Figure 10 shows an equivalent model for the TPS65320-Q1 control loop which can be modeled in a circuit-

simulation program to check frequency response and dynamic load response. The error amplifier is a

transconductance amplifier with a gmea of μA/V. One can model the error amplifier using an ideal voltage-

controlled current source. Resistor Roand capacitor Comodel the open-loop gain and frequency response of the

amplifier. The 1-mV AC voltage source between nodes aand beffectively breaks the control loop for the

frequency-response measurements. Plotting cversus ashows the small signal response of the frequency

compensation. Plotting aversus bshows the small signal response of the overall loop. Check the dynamic loop

response by replacing RLwith a current source that has the appropriate load-step amplitude and step rate in a

time-domain analysis. This equivalent model is only valid for continuous-conduction-mode designs.

Figure 10. Small-Signal Model for Loop Response

Z _ mod

ESR OUT

f2 R C

p ´ ´

P _ mod

L OUT

f2 R C

p ´ ´

dc ps L

A gm R= ´

2 f

æ ö

ç ÷

p ´

è ø

= ´ æ ö

ç ÷

p ´

è ø

gmps = 10.5 A/V

RESR

VcAdc

TPS65320-Q1

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Feature Description (continued)

7.3.1.17 Simple Small-Signal Model for Peak-Current Mode Control

Figure 11 shows a simple small-signal model that can be used to understand how to design the frequency

compensation. A voltage-controlled current source (duty cycle modulator) supplying current to the output

capacitor and load resistor can approximate the buck-regulator power stage. Equation 6 shows the control-to-

output transfer function, which consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the

change in switch current divided by the change in COMP pin voltage (node cin Figure 10) is the power-stage

transconductance. The gmPS for the buck-regulator power stage buck regulator is 10.5 A/V. Use Equation 7 to

calculate the low-frequency gain of the power stage which is the product of the transconductance and the load

resistance.

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This

variation with the load may seem problematic at first, but the dominant pole moves with the load current (see

Equation 8). The dashed line in the right half of Figure 11 highlights the combined effect. As the load current

decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same

for the varying load conditions, which makes designing the frequency compensation easier. The type of selected

output capacitor determines whether the ESR zero has a profound effect on the frequency compensation design.

Using high-ESR aluminum electrolytic capacitors can reduce the number of frequency-compensation

components required to stabilize the overall loop because the phase margin increases from the ESR zero at the

lower frequencies (see Equation 9).

Figure 11. Simple Small-Signal Model and Frequency Response for Peak-Current Mode

(6)

(7)

(8)

(9)

7.3.1.18 Small-Signal Model for Frequency Compensation

The buck regulator of the TPS65320-Q1 device uses a transconductance amplifier for the error amplifier.

Figure 12 shows compensation circuits. Implementation of Type 2 circuits is most likely in high-bandwidth power-

supply designs. The purpose of loop compensation is to ensure stable operation while maximizing dynamic

performance. Use of the Type 1 circuit is with power-supply designs that have high-ESR aluminum electrolytic or

tantalum capacitors. Equation 10 and Equation 11 show how to relate the frequency response of the amplifier to

o _ ea o _ ea

P0 2 R C

p ´ ´

o _ ea

C2 BW (Hz)

p ´

o _ ea

A (V/V)

Rgm

Aol

Vref = 0.8 V

COMP

R2 R3

Ro_ea C1 C2

FB1

Error

Amp

Inside

TPS65320-Q1

Type 2A

gmea

Co_ea

Type 2B Type 1

± C2

TPS65320-Q1

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

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Product Folder Links: TPS65320-Q1

Feature Description (continued)

the small-signal model in Figure 12. Modeling of the open-loop gain and bandwidth uses the Roand Coshown in

Figure 12. See the Typical Applications section for a design example with a Type 2A network that has a low-ESR

output capacitor. For stability purposes, the target is to have a loop-gain slope that is –20 dB/decade at the

crossover frequency. Also, the crossover frequency should not exceed one-fifth of the switching frequency (120

kHz in the case of a 600-kHz switching frequency).

For dynamic purposes, the higher the bandwidth, the faster the load-transient response. A large DC gain means

high DC regulation accuracy (DC voltage changes little with load or line variations). To achieve this loop gain, set

the compensation components according to the shape of the control-output bode plot.

Equation 10 through Equation 20 serve as a reference to calculate the compensation components. Roand C1

form the dominant pole (P1). A resistor (R3) and a capacitor (C1) in series to ground work as zero (Z1). In

addition, for an optional pole, add a lower-value capacitor (C2) in parallel with R3 to. This capacitor can be used

to filter noise at switching frequency, and it is also needed if the output capacitor has high ESR.

Figure 12. Types of Frequency Compensation

Figure 13. Frequency Response of the Type 2 Frequency Compensation

(10)

(11)

(12)

VIN (V)

Hysteresis

OFF

8.5 9

o _ ea

P2 Type 1

2 R C2

p ´ ´

o _ ea

P2 Type 2B

2 R3 C

p ´ ´

P2 Type 2A

2 R3 C2

2 R3 C1

p ´ ´

o _ ea

P1 2 R C1

p ´ ´

ea o _ ea

A1 gm R || R3 R1 R2

= ´ ´

ea o _ ea

A0 gm R R1 R2

= ´ ´

P1 P2

2 f

EA A0

2 2

1 1

2 f 2 f

æ ö

ç ÷

p ´

è ø

= ´ æ ö æ ö

+ ´ +

ç ÷ ç ÷

p ´ p ´

è ø è ø

TPS65320-Q1

www.ti.com

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

Product Folder Links: TPS65320-Q1

Feature Description (continued)

(13)

(14)

(15)

(16)

(17)

(18)

(19)

(20)

7.3.2 LDO Regulator

For the TPS65320-Q1 device, the design of the linear regulator is for low-power consumption and a quiescent

current of about 40 µA in light-load applications.

The LDO regulator requires both supplies from VIN and VIN_LDO to function. At all times the voltage level of VIN

must be higher or equal to the voltage level of VIN_LIN for the the LDO regulator to function properly. The

current capability of the LDO regulator is 280 mA under the full VIN_LDO input range, while VIN ≥4 V. When

VIN becomes less than 4 V, the current capability of the LDO regulator decreases.

7.3.2.1 Charge-Pump Operation

The LDO regulator has an internal charge pump which turns on or off depending on the input voltage. The

charge-pump switching circuitry does not cause conducted emissions to exceed required thresholds on the input

voltage line. The charge-pump switching thresholds are hysteretic. Figure 14 shows the typical switching

thresholds for the charge pump.

Figure 14. Charge-Pump Switching Thresholds

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Feature Description (continued)

Table 1. Typical Quiescent Current Consumption

CHARGE PUMP ON CHARGE PUMP OFF

LDO Iq300 µA 40 µA

7.3.2.2 Low-Voltage Tracking

At low input voltages, the regulator drops out of regulation, and the output voltage tracks input minus a dropout

voltage (VDROPOUT). This feature allows for a smaller input capacitor and can possibly eliminate the requirement

for a boost convertor during cold-crank conditions.

7.3.2.3 Power-Good Output, nRST

The nRST pin is a push-pull output formed by a push-pull stage between LDO_OUT and GND pins. The power-

on-reset output asserts low until the output voltage on LDO_OUT exceeds the setting thresholds (91%) and the

deglitch timer has expired. Additionally, whenever the EN2 pin is low or open, the nRST pin immediately asserts

low regardless of the output voltage. If a thermal shutdown occurs because of excessive thermal conditions, this

pin also asserts low. When the nRST is released (not asserted low), it can only be pulled-up to the specified VOH

voltage when the LDO_OUT voltage is equal to or higher than 3.3 V.

7.3.3 Enable and Undervoltage Lockout

The TPS65320-Q1 device enable pins (EN1 and EN2) are high-voltage-tolerant input pins with an internal

pulldown circuit. A high input activates the buck regulator and turns the regulators ON.

The TPS65320-Q1 device has an internal UVLO circuit to shut down the output if the input voltage falls below an

internally fixed UVLO threshold level. This UVLO circuit ensures that both regulators are not latched into an

unknown state during low-input-voltage conditions. The regulators power up when the input voltage exceeds the

voltage level.

Full-Running Mode

GND

BOOT

VIN

FB1

EN2

Standby Mode

EN1

Automotive Battery

LDO_OUT

VIN_LDO

FB2

KL15 OFF

KL30 Always ON

5-V Preregulator

3.3-V Standby MCU

LDO Input

MUX

Regulator

Control GND

BOOT

VIN

FB1

EN2

EN1

Automotive Battery

LDO_OUT

VIN_LDO

FB2

KL15 ON

KL30 Always ON

5-V Preregulator

3.3-V Standby MCU

LDO Input

MUX

Regulator

Control

TPS65320-Q1

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Product Folder Links: TPS65320-Q1

7.4 Device Functional Modes

7.4.1 Modes of Operation

The buck regulator has two hardware enable pins, and one can turn off either the buck or the LDO by pulling the

enable pin low, as listed in Table 2. One unique feature of the TPS65320-Q1 buck regulator is the input auto

source of the LDO. With both the buck and the LDO enabled, the LDO receives input from the output of the buck

through the VIN_LDO pin. In this mode, the buck output voltage must be higher than the LDO output voltage.

With the buck disabled and the LDO still enabled, the input of the LDO changes automatically from VIN_LDO to

VIN which is useful for standby operations which need a very low standby current, such as automotive

infotainment, telematics, and other operations. The LDO changes the input when the buck output voltage is out

of regulation (V(FB1) is less than 91% of Vref1).

Table 2. Device Operation Modes

BUCK LDO DESCRIPTION

EN1 EN2

0 0 Both buck and LDO disabled

0 1 Buck disabled. LDO enabled and LDO input source is from the battery.

1 0 Buck enabled and LDO disabled

1 1 Both buck and LDO enabled and LDO input source is from buck output. Buck output voltage must

be higher than LDO output voltage.

Figure 15. Example of LDO Auto Source in Standby Condition

GND

BOOT

VIN

RT/CLK

Supply

nRST

FB1

EN2

3.3 V

COMP

TPS65320-Q1

EN1

PowerPAD

VI = 9 V to 16 V

LDO_OUT

VIN_LDO

FB2

4.7 F

47 k

3.3 nF

27 k

62 k

20 k

2.7 nF

10 F

C2 (Optional)

5.4 pF

5 V

10 k

53.6 k

0.1 F

2.2 H

22 FC5

22 F

TPS65320-Q1

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

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Product Folder Links: TPS65320-Q1

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS65320-Q1 buck regulator operates with a supply voltage VIof 3.6 V to 40 V. The TPS65320-Q1 LDO

regulator operates with a supply voltage VIN_LDO of 3 V to 40 V. For reducing power dissipation, TI strongly

recommends to use the output voltage of the buck regulator as the input supply for the LDO regulator. To use

the output voltage of the buck regulator this way, the selected buck-regulator output voltage must be higher than

the selected LDO-regulator output voltage.

For optimized switching performance (such as low jitter) in automotive applications with input voltages that have

wide ranges, TI recommends to operate the device at higher frequencies, such as 2 MHz, which also helps

achieve AM-band compliance requirements (that extends until 1.7 MHz).

8.2 Typical Applications

8.2.1 2.2-MHz Switching Frequency, 9-V to 16-V Input, 5-V Output Buck Regulator, 3.3-V Output LDO

Regulator

This example application details the design of a high-frequency switching regulator and linear regulator using

ceramic output capacitors (see the Detailed Design Procedure section for the design procedure).

Figure 16. TPS65320-Q1 Design Example With 2.2-MHz Switching Frequency

I O O

O IND I S

V max V V

L min I K V max ƒ

= ´

´ ´

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Typical Applications (continued)

8.2.1.1 Design Requirements

A few parameters must be known to begin the design process. Determination of these parameters is typically at

the system level. This example begins with the parameters listed in Table 3.

Table 3. Design Requirements

DESIGN PARAMETER EXAMPLE VALUE

Input voltage, VIN1 9 V to 16 V, typical 12 V

Output voltage, VREG1 (buck regulator) 5 V ± 2%

Maximum output current IO_max1 3 A

Minimum output current IO_min1 0.01 A

Transient response 0.01 A to 0.8 A 3%

Output ripple voltage 1%

Switching frequency ƒSW 2.2 MHz

Output voltage, VREG2 (LDO regulator) 3.3 V ± 2%

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Switching Frequency Selection for the Buck Regulator

The first step is to decide on a switching frequency for the regulator. Typically, the user selects the highest

switching frequency possible because this produces the smallest solution size. The high switching frequency

allows for lower-valued inductors and smaller output capacitors compared to a power supply that switches at a

lower frequency. The selectable switching frequency is limited by the minimum on-time of the internal power

switch, the input voltage, the output voltage, and the frequency-shift limitation.

Consider minimum on-time and frequency-shift protection as calculated with Equation 4 and Equation 5. To find

the maximum switching frequency for the regulator, select the lower value of the two results. Switching

frequencies higher than these values result in pulse skipping or the lack of overcurrent protection during a short

circuit. The typical minimum on-time, tON-min, is 100 ns for the TPS65320-Q1 device. For this example, where the

output voltage is 5 V and the maximum input voltage is 16 V, use a switching frequency of 2200 kHz. Use

Equation 3 to calculate the timing resistance for a given switching frequency. The R4 resistor sets the switching

frequency. A 2.2-MHz switching frequency requires a 47-kΩresistor (see R4 in Figure 16).

8.2.1.2.2 Output Inductor Selection for the Buck Regulator

Use Equation 21 to calculate the minimum value of the output inductor. The output capacitor filters the inductor

ripple current. Therefore, selecting high inductor-ripple currents impacts the selection of the output capacitor

because the output capacitor must have a ripple-current rating equal to or greater than the inductor ripple

current. In general, the inductor ripple value is at the discretion of the designer; however, the following guidelines

can be used to select this value. KIND is a coefficient that represents the amount of inductor ripple current relative

to the maximum output current.

(21)

For designs using low-ESR output capacitors such as ceramics, use a value as high as KIND = 0.3. When using

higher-ESR output capacitors, KIND = 0.2 yields better results. In a wide-input voltage regulator, selecting an

inductor ripple current on the larger side is best because it allows the inductor to still have a measurable ripple

current with the input voltage at a minimum.

S O

2 I

Cƒ V

´ D

ripple

L peak O

I I 2

-= +

2 2

L RMS O ripple

I I I

-= +

( )

O I O

ripple

I o S

V V max V

IV max L ƒ

´ -

=´ ´

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For this design example, use KIND = 0.3 and the minimum inductor value which is calculated as 1.73 µH. For this

design, select the nearest standard value which is 2.2 µH (see L1 in Figure 16). Use Equation 22 to calculate the

inductor ripple current (Iripple). For the output filter inductor, do not to exceed the RMS-current and saturation-

current ratings. Use Equation 23 and Equation 24 to calculate the RMS current (IL-RMS) and the peak inductor (IL-

peak).

(22)

(23)

(24)

For this design, the RMS inductor current is 3.01 A, the peak inductor current is 3.36 A, and the inductor ripple

current is 0.71 A. The selected inductor is a Coilcraft MSS1038-103NLB and has a saturation-current rating of

4.52 A and an RMS-current rating of 4.05 A. As the equation set demonstrates, lower ripple current reduces the

output ripple voltage of the buck regulator but requires a larger value of inductance. Selecting higher ripple

currents increases the output ripple voltage of the buck regulator but allows for a lower inductance value.

8.2.1.2.3 Output Capacitor Selection for the Buck Regulator

Consider three primary factors when selecting the value of the output capacitor. The output capacitor determines

the modulator pole, the output ripple voltage, and how the buck regulator responds to a large change in load

current. Select the output capacitance based on the most stringent of these three criteria. The desired response

to a large change in the load current is the first criterion. The output capacitor must supply the load with current

when the regulator cannot. This situation occurs if the desired hold-up times are present for the buck regulator. In

this case, the output capacitor must hold the output voltage above a certain level for a specified amount of time

after the input power is removed. The regulator is also temporarily unable to supply sufficient output current if a

large, fast increase occurs affecting the current requirements of the load, such as a transition from no load to full

load. The buck regulator usually requires two or more clock cycles for the control loop to notice the change in

load current and output voltage, and to adjust the duty cycle to react to the change. Size the output capacitor to

supply the extra current to the load until the control loop responds to the load change. The output capacitance

must be large enough to supply the difference in current for two clock cycles while only allowing a tolerable

amount of droop in the output voltage. Use Equation 25 to calculate the minimum output capacitance required to

supply the difference in current.

where

•ΔIOis the change in the buck-regulator output current

• ƒSis the switching frequency of the buck regulator

•ΔVOis the allowable change in the buck-regulator output voltage (25)

For this example, the specified transient load response is a 3% change in VOfor a load step from 0.01 A to 0.8 A

(full load). For this example, ΔIO= 0.8 – 0.01 = 0.79 A and ΔVO= 0.03 × 5 = 0.15 V. Using these numbers

results in a minimum capacitance of 4.7 µF. This value does not consider the ESR of the output capacitor in the

output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.

Aluminum electrolytic and tantalum capacitors have higher ESR that must be take into consideration.

The catch diode of the regulator cannot sink current. Therefore any stored energy in the inductor produces an

output-voltage overshoot when the load current rapidly decreases. Also, size the output capacitor to absorb the

energy stored in the inductor when transitioning from a high load current to a lower load current. The excess

energy that is stored in the output capacitor increases the voltage on the capacitor. Size the capacitor to maintain

the desired output voltage during these transient periods.

O I O

CO(RMS)

I O S

V (V max V )

I12 V max L ƒ

´ -

´ ´ ´

O ripple

ESR

L ripple

OO ripple

L ripple

1 1

8 ƒ

> ´

2 2

OH OL

O O 2 2

f i

(I I )

C L (V V )

> ´

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Use Equation 26 to calculate the minimum capacitance to keep the output voltage overshoot to a desired value.

where

• LOis the output inductance of the buck regulator

• IOH is the output current of the buck regulator under heavy load

• IOL is the output current of the buck regulator under light load

• Vfis the final peak output voltage of the buck regulator

• Viis the initial capacitor voltage of the buck regulator (26)

For this example, the worst-case load step is from 3 A to 0.01 A. The output voltage increases during this load

transition, and the stated maximum in the specification is 3% of the output voltage (see the Electrical

Characteristics table). This makes Vf= 1.03 × 5 = 5.15. Viis the initial capacitor voltage, which is the nominal

output voltage of 5 V. Using these numbers in Equation 26 yields a minimum capacitance of 13 µF.

Equation 27 calculates the minimum output capacitance needed to meet the output ripple-voltage specification.

Equation 27 yields 0.8 µF.

where

• VO-ripple is the maximum allowable output ripple voltage of the buck regulator

• IL-ripple is the inductor ripple current of the buck regulator (27)

Use Equation 28 to calculate the maximum ESR required for the output capacitor to meet the output voltage

ripple specification. As a result of Equation 28, the ESR should be less than 70 mΩ.

(28)

The most stringent criterion for the output capacitor is 13 µF of capacitance to keep the output voltage in

regulation during a load transient.

Factor in additional capacitance deratings for aging, temperature, and DC bias which increase this minimum

value. For this example, two 22-µF, 10-V ceramic capacitors with 3 mΩof ESR are used (see C4 and C5 in

Figure 16). Capacitors generally have limits to the amount of ripple current they can handle without failing or

producing excess heat. Specify an output capacitor that can support the inductor ripple current. Some capacitor

data sheets specify the root-mean-square (RMS) value of the maximum ripple current.

Use Equation 29 to calculate the RMS ripple current that the output capacitor must support. For this application,

Equation 29 yields 205 mA.

(29)

8.2.1.2.4 Catch Diode Selection for the Buck Regulator

The TPS65320-Q1 device requires an external catch diode between the SW pin and GND (see D1 in Figure 16).

The selected diode must have a reverse voltage rating equal to or greater than VImax. The peak current rating of

the diode must be greater than the maximum inductor current. The diode should also have a low forward voltage.

Schottky diodes are typically a good choice for the catch diode because of low forward voltage of these diodes.

The lower the forward voltage of the diode, the higher the efficiency of the regulator.

Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage is. Although the

design example has an input voltage up to 16 V, select a diode with a minimum of 40-V reverse voltage to allow

input voltage transients up to the rated voltage of the TPS65320-Q1 device.

I S

I max 0.25

VC ƒ

D =

O I O

CI(RMS) O

I I

V (V min V )

I I max V min V min

= ´ ´

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For the example design, the selection of a Schottky diode is B540C-13-F based on the lower forward voltage of

this diode. This diode is also available in a larger package size, which has good thermal characteristics over

small buck regulators. The typical forward voltage of the B540C-13-F is 0.55 V.

Also, select a diode with an appropriate power rating. The diode conducts the output current during the off-time

of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the

output voltage, and the switching frequency. The output current during the off-time, multiplied by the forward

voltage of the diode, equals the conduction losses of the diode. At higher switching frequencies, consider the AC

losses of the diode. The AC losses of the diode are because the charging and discharging of the junction

capacitance and reverse recovery.

8.2.1.2.5 Input Capacitor Selection for the Buck Regulator

The TPS65320-Q1 device requires a high-quality ceramic input decoupling capacitor (type X5R or X7R) of at

least 3 µF of effective capacitance, and in some applications a bulk capacitance. The effective capacitance

includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input

voltage. The capacitor must also have a ripple-current rating greater than the maximum input-current ripple of the

TPS65320-Q1 device. Use Equation 30 to calculate the input ripple current (ICI(RMS)).

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the

capacitor. Minimize the capacitance variations because of temperature by selecting a dielectric material that is

stable over temperature. Designers usually select X5R and X7R ceramic dielectrics for power regulator

capacitors because these capacitors have a high capacitance-to-volume ratio and are fairly stable over

temperature. Also, select the output capacitor with the DC bias taken into consideration. The capacitance value

of a capacitor decreases as the DC bias across a capacitor increases.

This design requires a ceramic capacitor with at least a 40-V voltage rating to support the maximum input

voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V, or 100

V. For this design example. The selection for this example is a 4.7-µF, 50-V capacitor (see C8 in Figure 16).

(30)

Table 4 lists a selection of high-voltage capacitors. The input-capacitance value determines the input ripple

voltage of the regulator. Use Equation 31 to calculate the input ripple voltage (ΔVI).

(31)

Using the design example values, IOmax =3A,CI= 4.7 µF, ƒS= 2200 kHz, yields an input ripple voltage of 72.5

mV and an RMS input ripple current of 1.49 A.

Table 4. Capacitor Types

VENDOR VALUE (μF) EIA Size VOLTAGE DIALECTRIC COMMENTS

Murata

1 to 2.2 1210 100 V

X7R

GRM32 series

1 to 4.7 50 V

11206 100 V GRM31 series

1 to 2.2 50 V

AVX

1 to 4.7 1210 50 V

X7R dielectric series

1 100 V

1 to 4.7 1812 50 V

1 to 2.2 100 V

8.2.1.2.6 Soft-Start Capacitor Selection for the Buck Regulator

The soft-start capacitor determines the minimum amount of time required for the output voltage to reach the

nominal programmed value during power up which is useful if a load requires a controlled-voltage slew rate. This

feature is also useful if the output capacitance is large and requires large amounts of current to charge the

capacitor quickly to the output voltage level. The large currents required to charge the capacitor may make the

TPS65320-Q1 device reach the current limit, or excessive current draw from the input power supply may cause

the input voltage rail to sag. Limiting the output voltage-slew rate solves both of these problems.

CO P _ mod

ƒ ƒ 2

= ´

CO P _ mod Z _ mod

ƒ ƒ ƒ= ´

Z _ mod

ESR O

ƒ2π R C

´ ´

max

P _ mod

L O O O

ƒ2π R C 2π V C

= =

´ ´ ´ ´

O O

ss(avg)

C V 0.8

´ ´

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The soft-start time must be long enough to allow the regulator to charge the output capacitor up to the output

voltage without drawing excessive current. Use Equation 32 to calculate the minimum soft-start time, tss, required

to charge the output capacitor, CO, from 10% to 90% of the output voltage, VO, with an average soft-start current

of Iss(avg).

(32)

In the example, to charge the effective output capacitance of 44 µF up to 5 V while only allowing the average

output current to be 3 A requires a 0.088-ms soft-start time.

When the soft-start time is known, use Equation 2 to calculate the soft-start capacitor. For the example circuit,

the soft-start time is not too critical because the output-capacitor value is 2 × 22 µF, which does not require much

current to charge to 5 V. The example circuit has the soft-start time set to an arbitrary value of 1 ms, which

requires a 3.125-nF soft-start capacitor. This design uses the next-larger standard value of 3.3 nF.

8.2.1.2.7 Bootstrap Capacitor Selection for the Buck Regulator

Connect a 0.1-µF ceramic capacitor between the BOOT and SW pins for proper operation. TI recommends using

a ceramic capacitor with X5R or better-grade dielectric. The capacitor should have a 10-V or higher voltage

rating.

8.2.1.2.8 Output Voltage and Feedback Resistor Selection for the Buck Regulator

The voltage divider of R1 and R2 sets the output voltage. For the design example, the selected value of R2 is 10

kΩ, and the calculated value of R1 is 53.6 kΩ. Because of current leakage of the FB1 pin, the current flowing

through the feedback network should be greater than 1 μA to maintain the output-voltage accuracy. Selecting

higher resistor values decreases the quiescent current and improves efficiency at low output currents, but can

introduce noise immunity problems.

8.2.1.2.9 Frequency Compensation Selection for the Buck Regulator

Several possible methods exist to design closed loop compensation for DC-DC converters. The method

presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the buck

regulator. Ignoring the slope compensation usually causes the actual crossover frequency to be lower than the

crossover frequency used in the calculations. This method assumes the crossover frequency is between the

modulator pole and the ESR zero, and that the ESR zero is at least 10 times greater than the modulator pole.

To begin, use Equation 33 to calculate the modulator pole, ƒP_mod, and Equation 34 to calculate the ESR zero,

ƒz_mod. For COUT, use a derated value of 40 μF.

(33)

(34)

Use Equation 35 and Equation 36 to calculate an estimate starting point for the crossover frequency, ƒCO, to

design the compensation.

(35)

(36)

For the example design, ƒP_mod is 2.39 kHz and ƒZ_mod is 1.33 MHz. Equation 35 is the geometric mean of the

modulator pole and the ESR zero and Equation 36 is the mean of the modulator pole and the switching

frequency. Equation 35 yields 56.4 kHz and Equation 36 results 51.3 kHz. Use the lower value of Equation 35 or

Equation 36 for an initial crossover frequency.

For this example, the target value of ƒCO is 51.3 kHz. Next, calculate the compensation components. Use a

resistor in series with a capacitor to create a compensating zero. A capacitor in parallel to these two components

forms the compensating pole.

C2 π R3 ƒ

´ ´

O ESR

C R

P _ mod

C1 2π R3 ƒ

´ ´

CO O O

ps ref ea

2π ƒ C V

R3 gm V gm

æ ö æ ö

´ ´

= ´

ç ÷ ç ÷

ç ÷ ´

è ø

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The total loop gain, which consists of the product of the modulator gain, the feedback voltage-divider gain, and

the error amplifier gain at ƒCO equal to 1. Use Equation 37 to calculate the compensation resistor, R3 (see the

schematic in Figure 16).

(37)

Assume the power-stage transconductance, gmps, is 10.5 S. The output voltage (VO), reference voltage (Vref),

and amplifier transconductance, (gmea) are 5 V, 0.8 V, and 310 μS, respectively. The calculated value for R3 is

24.74 kΩ. For this design, use a value of 27 kΩfor R3. Use Equation 38 to set the compensation zero to the

modulator pole frequency.

(38)

Equation 36 yields 2468 pF for compensating capacitor C1 (see the schematic in Figure 16). For this design,

select a value of 2700 pF for C1.

To implement a compensation pole as needed, use an additional capacitor, C2, in parallel with the series

combination of R3 and C1. Use Equation 39 and Equation 40 to calculate the value of C2 and select the larger

resulting value to set the compensation pole. Type 2B compensation does not use C2 because it would demand

a low ESR of the output capacitor.

(39)

(40)

8.2.1.2.10 LDO Regulator

Depending on the end application, use different values of external components can be used. To program the

output voltage, carefully select the feedback resistors, R5 and R6 (see the schematic in Figure 16). Using smaller

resistors results in higher current consumption, whereas using very large resistors impacts the sensitivity of the

regulator. Therefore selecting feedback resistors such that the sum of R5 and R6 is between 20 kΩand 200 kΩ

is recommended.

If the desired regulated output voltage is 3.3 V on selecting R6, the value of R5 can be calculated. With Vref = 0.8

V (typical), VO= 3.3 V, and selecting R6 = 20 kΩ, the calculated value of R5 is 62 kΩ.

Depending on application requirements, a larger output capacitor for the LDO regulator may be required (see C7

in Figure 16) to prevent the output from temporarily dropping down during fast load steps. TI recommends a low-

ESR ceramic capacitor with dielectric of type X5R or X7R. Additionally, a bypass capacitor can be connected at

the output to decouple high-frequency noise based on the requirements of the end application.

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8.2.1.2.11 Power Dissipation

8.2.1.2.11.1 Power Dissipation Losses of the Buck Regulator

Use the following equations to calculate the power dissipation losses for the buck regulator. These losses are

applicable for continuous-conduction-mode (CCM) operation.

1. Conduction loss:

PCON = IO2× rDS(on) × (VO/ VI)

where

• IOis the buck regulator output current

• VOis the buck regulator output voltage

• VIis the input voltage (41)

2. Switching loss:

PSW = ½ × VI× IO× (tr+ tf) × fS

where

• tris the FET switching rise time (trmaximum = 20 ns)

• tfis the FET switching fall time (tfmaximum = 20 ns)

• ƒSis the switching frequency of the buck regulator (42)

3. Gate drive loss:

PGate = Vdrive × Qg× ƒsw

where

• Vdrive is the FET gate-drive voltage (typically Vdrive = 6 V)

• Qg= 1 × 10–9 (nC, typical) (43)

8.2.1.2.12 Power Dissipation Losses of the LDO Regulator

PLDO = (VVIN_LDO – V(LDO_OUT)) × I(LDO_OUT) (44)

8.2.1.2.13 Total Device Power Dissipation Losses and Junction Temperature

1. Supply loss:

PIC = VI× IQ-normal (45)

2. Total power loss:

PTotal = PCON + PSW + PGate + PLDO + PIC (46)

For a given operating ambient temperature TA:

TJ= TA+ Rth × PTotal

where

• TJis the junction temperature in °C

• TAis the ambient temperature in °C

• Rth is the thermal resistance of package in (°C/W)

• PTotal is the total power dissipation (W) (47)

For a given maximum junction temperature TJ-max = 150°C, the allowed Total power dissipation is given as:

TA-max = TJ-max -Rth × PTotal (48)

where

• TA-max is the maximum ambient temperature in °C

• TJ-max is the maximum junction temperature in °C (49)

Additional power losses occur in the regulator circuit because of the inductor AC and DC losses, the Schottky

diode, and trace resistance that impact the overall efficiency of the regulator.

2 V/div

1 V/div

2 V/div

100 mA/div

EN2

nRST

LDO_out

I_load

50 mV/div

100 mA/div

LDO_out

I_load

200 mV/div

1 A/div

Buck_out

I_load

1 V/div

EN1

1 V/div

1 A/div

Buck_out

I_load

Power Dissipation (W)

Ambient Temperature (qC)

0.5

125 150

100

1.5

2.5

25 50

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Figure 17. Thermal Derating

8.2.1.3 Application Curves

Figure 18. Buck Regulator Output at Load Transient (200

mA to 3 A, Buck Output Voltage = 5 V, ƒS= 2 MHz) Figure 19. Buck-Regulator Startup Operation

Figure 20. LDO Regulator Startup Operation Figure 21. LDO-Regulator Output at Load Transient (50 mA

to 300 mA)

Fsw 500kHz

BOOT

VIN

VIN_LDO

LDO_OUT

FB2

NRST

EN2

7EN1 8

RT/CLK 9

SS 10

FB1 11

COMP 12

GND 13

SW 14

PWPD

U01

TPS65320QPWPRQ1

10µF

C48

L03

74408943010

10µF

C49

10µF

C50

0.1µF

GND

1uH

+9V to +18V (40Vpk)

0.1µFC51

3.32

TP_nRST

10µF

C61

GND

240k

R62

10.0k

R56

49.9

R55 22µF

C58

22µF

C59

22µF

C62

22µF

C63

D800

B340A-13-F

L04

MSS1048-103MLB

10uH

TP_SW

1µF

C60

GND

6V5

TP_PM1

Gnd1

Gnd

+6.5V at 1A

4700pF

C52

FB1

100pF

C53

Vin

Fco 10kHz

PM >60degs

GM<-15db

Vfb 800mV

0.01µF

C54

10.0k

R53

71.5k

R54

10.0k

R50

31.6k

R48

+3.3V at 250mA

3V3

Gnd2

10.0

R57

220pF

C57

+Vbatt

Gnd

+Vcam

Gnd

COC60

100

0.0 1.0 2.0 3.0 4.0

Efficiency (%)

Output Current (A)

fsw = 300kHz

fsw = 2MHz

C001

fS= 300 kHz

fS= 2 MHz

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VI= 14 V VO= 5 V

Figure 22. Buck Efficiency Versus Output Current

8.2.2 Design Example With 500-kHz Switching Frequency

R55 is for test purposes only.

Figure 23. TPS65320-Q1 Design Example With 500-kHz Switching Frequency

8.2.2.1 Design Requirements

This example begins with the parameters listed in Table 5.

Table 5. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE

Input voltage, VIN1 9 V to 18 V, typical 12 V

Output voltage, VREG1 (buck regulator) 6.5 V ± 2%

Maximum output current, IO_max1 1 A

Minimum output current, IO_min1 0.01 A

Transient response, 0.01 A to 1 A 3%

Output ripple voltage 1%

Switching frequency, ƒSW 500 kHz

Output voltage, VREG2 (LDO regulator) 3.3 V ± 2%

Overvoltage threshold 106% of output voltage

Undervoltage threshold 91% of output voltage

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8.2.2.2 Detailed Design Procedure

For the 500-kHz switching-frequency design, make the adjustments as outlined in the following sections. For

sections such as LDO-component calculations, bootstrap-capacitor selection, and others that are not listed in this

section, see the 2.2-MHz Switching Frequency, 9-V to 16-V Input, 5-V Output Buck Regulator, 3.3-V Output LDO

Regulator section.

8.2.2.2.1 Selecting the Switching Frequency

For 500-kHz operation, use a 240-kΩresistor which is calculated using Equation 3. The R62 resistor sets this

switching frequency.

8.2.2.2.2 Output Inductor Selection

Using Equation 21, the inductor value is calculated as 10.39 μH with KIND = 0.8. This design example can allow

for a higher ripple current, therefore, select the nearest standard value of 10 µH. The RMS and peak inductor-

current ratings are calculated using Equation 23 and Equation 24 which result in 1.03 A and 1.42 A, respectively.

The value of the output-filter inductor must not exceed the RMS-current and saturation-current ratings.

8.2.2.2.3 Output Capacitor

For this example, the specified transient load response is a 3% change in VOfor a load step from 0.01 A to 1 A

(full load). For this example, ΔIO= 1 – 0.01 = 0.99 A and ΔVO= 0.03 × 6.5 = 0.195 V. Using these numbers

results in a minimum capacitance of 20.31 μF. This value does not consider the ESR of the output capacitor in

the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.

Aluminum electrolytic and tantalum capacitors have higher ESR that should be considered. The catch diode of

the regulator cannot sink current, so any stored energy in the inductor produces an output-voltage overshoot

when the load current rapidly decreases. Also, size the output capacitor to absorb the energy stored in the

inductor when transitioning from a high load current to a lower load current. The excess energy that is stored in

the output capacitor increases the voltage on the capacitor. Size the capacitor to maintain the desired output

voltage during these transient periods. Use Equation 26 to calculate the minimum capacitance to keep the output

voltage overshoot to a desired value.

For this example, the worst-case load step is from 1 A to 0.01 A. The output voltage increases during this load

transition, and the stated maximum in our specification is 3% of the output voltage resulting in Vf= 1.03 × 6.5 =

6.7. Viis the initial capacitor voltage, which is the nominal output voltage of 5 V. Using these values, Equation 26

yields a minimum capacitance of 3.88 μF. Equation 27 calculates the minimum output capacitance required to

meet the output ripple-voltage specification. Equation 27 yields 10.6 μF. Equation 28 calculates the maximum

ESR an output capacitor can have to meet the output ripple-voltage specification. Equation 28 indicates the ESR

should be less than 60.2 mΩ.

The most stringent criterion for the output capacitor is 20.31 μF of capacitance to keep the output voltage in

regulation during a load transient.

Factor in additional capacitance deratings for aging, temperature, and DC bias which increase this minimum

value. For this example, four 22-μF, 25-V and one 1-µF, 25-V ceramic capacitors with 10 mΩof ESR are used.

Specify an output capacitor that can support the inductor ripple current. Some capacitor data sheets specify the

RMS value of the maximum ripple current. Use Equation 29 to calculate the RMS ripple current that the output

capacitor must support. For this design example, Equation 29 yields 240 mA.

8.2.2.2.4 Compensation

This design example use a different approach for calculating compensation values, beginning with the desired

crossover frequency. Ensure that the crossover frequency is maintained at 10 kHz to provide reasonable phase

margin (PM). To achieve circuit stability, a phase margin greater than 60 degrees and a gain margin less than 15

dB is required. Next, place the zero close to the load pole. The zero is determined using C52 and R56. For this

example, select a value of 10 kΩfor R56 which results in a value of approximately 4.7 nF for C52. The pole,

resulting from C53 and R56, can be placed between 10 times the crossover frequency and 1/3 of the switching

frequency. The gain is adjusted to be maintained over 60 degrees of phase margin and –15 dB of gain margin.

The resulting value of C53 is approximately 100 pF for a pole frequency of 159 kHz.

Use the following component values:

R56 = 10 kΩ

Output Current (A)

Efficiency (%)

0 0.2 0.4 0.6 0.8 1

D001

VIN = 9 V

VIN = 13.8 V

VIN = 18 V

TPS65320-Q1

www.ti.com

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

Product Folder Links: TPS65320-Q1

C53 = 100 pF

C52 = 4700 pF

8.2.2.3 Application Curve

Figure 24. Efficiency vs Output Current

9 Power Supply Recommendations

The TPS65320-Q1 buck regulator is designed to operate from an input voltage up to 40 V. Ensure that the input

supply is well regulated. Furthermore, if the supply voltage in the application is likely to reach negative voltage

(for example, reverse battery) a forward diode must be placed at the input of the supply. For the VIN pin, a small

ceramic capacitor with a typical value of 4.7 µF is recommended. Capacitance derating for aging, temperature,

and DC bias must be taken into account while determining the capacitor value. Connect a local decoupling

capacitor close to the VIN_LDO pin for proper filtering.

TPS65320-Q1

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

www.ti.com

Product Folder Links: TPS65320-Q1

10 Layout

10.1 Layout Guidelines

TI recommends the following guidelines for PCB layout of the TPS65320-Q1 buck regulator. This layout example

is based on TPS65320EVM (SLVU691).

10.1.1 Inductor (L)

Use a low-EMI inductor with a ferrite-type shielded core. Other types of inductors can be used; however, these

inductors must have low-EMI characteristics and be located away from the low-power traces and components in

the circuit.

10.1.2 Input Filter Capacitors (CI)

Locate input ceramic filter capacitors in close proximity to the VIN pin. TI recommends surface-mount (SM)

capacitors to minimize lead length and reduce noise coupling.

10.1.3 Resistive Feedback Networks

Route the feedback trace so that it has minimum interaction with any noise sources associated with the switching

components. The recommended practice is to ensure the inductor is placed away from the feedback trace to

prevent creating an EMI noise source.

10.1.4 Traces and Ground Plane

All power (high-current) traces should be as thick and short as possible. The inductor and output capacitor of the

buck regulator should be as close to each other as possible which reduces EMI radiated by the power traces

because of high switching currents. In a two-sided PCB, TI recommends having ground planes on both sides of

the PCB to help reduce noise and ground loop errors. The ground connection for the input and output capacitors

and IC ground should connect to this ground plane. In a multi-layer PCB, the ground plane separates the power

plane (where high switching currents and components are) from the signal plane (where the feedback trace and

components are) for improved performance. Also, arrange the components such that the switching-current loops

curl in the same direction. Place the high-current components such that during conduction the current path is in

the same direction which prevents magnetic field reversal caused by the traces between the two half-cycles, and

helps reduce radiated EMI.

Place the input

capacitors (C49, C50,

C1) close to VIN

(to minimize lead

length and reduce

noise coupling)

Switching Components

Minimize this loop area to reduce ringing

Place feedback

components away

from the power

path

(to avoid noise

coupling)

411

BOOT

VIN

VIN_LDO

LDO_OUT

FB2

nRST

EN2

GND

COMP

FB1

RT/CLK

EN1

Buck Regulator

Catch Diode

Buck Regulator

Output Inductor

Buck Regulator

Output Capacitor VO(BUCK)

Buck

Regulator

BOOT

Capacitor

Input Capacitors

Power

Ground

LDO Regulator

Output Capacitor

VO(LDO)

Buck Regulator

Compensation Components

Buck Regulator

Soft-Start Capacitor

Buck Regulator Switching

Frequency Resistor

Buck

Regulator

Resistor

Feedback

Network

LDO

Regulator

Resistor

Feedback

Network

Analog Ground Trace

Exposed

Thermal Pad

Area

TPS65320-Q1

www.ti.com

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

Product Folder Links: TPS65320-Q1

10.2 Layout Example

Figure 25. TPS65320-Q1 Layout Example

Figure 26. TPS65320-Q1 Layout Example — Top Side

Multiple vias connect the input, output

and IC ground to the ground plane.

Ensure the ground plane is large to

reduce noise and ground-loop errors

TPS65320-Q1

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

www.ti.com

Product Folder Links: TPS65320-Q1

Layout Example (continued)

Figure 27. TPS65320-Q1 Layout Example — Bottom Side

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

•TPS65320-Q1 Design Checklist,SLVA593

•CISPR25 Radiated Emissions Using TPS65320-Q1,SLVA702

• User's guide, TPS65320EVM,SLVU691

TPS65320-Q1

www.ti.com

SLVSAY9F –DECEMBER 2012–REVISED MARCH 2016

Product Folder Links: TPS65320-Q1

11.3 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.4 Trademarks

Eco-mode, PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 15-Jun-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TPS65320BQPWPRQ1 NRND HTSSOP PWP 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 T65320B

TPS65320QPWPRQ1 NRND HTSSOP PWP 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS65320

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 15-Jun-2016

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS65320BQPWPRQ1 HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TPS65320QPWPRQ1 HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Feb-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS65320BQPWPRQ1 HTSSOP PWP 14 2000 367.0 367.0 38.0

TPS65320QPWPRQ1 HTSSOP PWP 14 2000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Feb-2016

Pack Materials-Page 2

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