SiI9573 and SiI9575 Port Processor
Data Sheet
SiI-DS-1089-G
April 2017
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 SiI-DS-1089-G
Contents
1. General Description ...................................................................................................................................................... 7
1.1. HDMI Inputs and Outputs ..................................................................................................................................... 7
1.2. Performance Improvement Features .................................................................................................................... 8
1.3. Audio Inputs and Outputs ..................................................................................................................................... 8
1.4. Control Capability ................................................................................................................................................. 8
1.5. Packaging .............................................................................................................................................................. 8
2. Functional Description .................................................................................................................................................. 9
2.1. Always-on Section ................................................................................................................................................. 9
2.1.1. Serial Ports Block ......................................................................................................................................... 10
2.1.2. Static RAM Block ......................................................................................................................................... 10
2.1.3. NVRAM Block .............................................................................................................................................. 10
2.1.4. HDCP Registers Block .................................................................................................................................. 10
2.1.5. OTP ROM Block ........................................................................................................................................... 10
2.1.6. Booting Sequencer ...................................................................................................................................... 10
2.1.7. Configuration, Status, and Interrupt Control Block ..................................................................................... 11
2.1.8. Mobile HD Control Block ............................................................................................................................. 11
2.1.9. CEC Interface Controller .............................................................................................................................. 11
2.1.10. Power Block................................................................................................................................................. 11
2.2. Power-down Section ........................................................................................................................................... 11
2.2.1. TMDS Receiver Blocks ................................................................................................................................. 11
2.2.2. 6:1 Input Multiplexer Blocks A and B and 4:1 Input Multiplexer Blocks C and D ........................................ 11
2.2.3. HDMI, MHL, and InstaPort Receiver Blocks ................................................................................................ 12
2.2.4. Video/Audio Splitter Block .......................................................................................................................... 12
2.2.5. InstaPrevue Block ........................................................................................................................................ 12
2.2.6. Stream Mixer Block ..................................................................................................................................... 12
2.2.7. 2:1 Input Multiplexer Blocks E and F and Main and Subaudio Formatting Blocks ...................................... 12
2.2.8. Parallel Video Input Block ........................................................................................................................... 12
2.2.9. Video Pattern Generator Block ................................................................................................................... 13
2.2.10. Audio Sampling Rate Converter Block ......................................................................................................... 13
2.2.11. On-screen Display Controller ...................................................................................................................... 14
2.2.12. Audio Input Block ........................................................................................................................................ 14
2.2.13. Audio Output Block ..................................................................................................................................... 15
2.2.14. Audio Return Channel (ARC) Input and Output .......................................................................................... 15
2.2.15. TMDS Transmitter Block .............................................................................................................................. 16
3. Electrical Specifications............................................................................................................................................... 17
3.1. Absolute Maximum Conditions ........................................................................................................................... 17
3.2. Normal Operating Conditions ............................................................................................................................. 18
3.3. DC Specifications ................................................................................................................................................. 19
3.4. AC Specifications ................................................................................................................................................. 21
3.4.1. Control Signal Timing Specifications ........................................................................................................... 23
3.4.2. Audio Input Timing ..................................................................................................................................... 24
3.4.3. Audio Output Timing .................................................................................................................................. 24
3.5. Serial Flash SPI Interface AC Specifications ......................................................................................................... 25
4. Timing Diagrams ......................................................................................................................................................... 26
4.1. Video Input Timing Diagrams ............................................................................................................................. 26
4.2. Reset Timing Diagrams ....................................................................................................................................... 27
4.3. I2C Timing Diagrams ............................................................................................................................................ 28
4.4. Digital Audio Input Timing .................................................................................................................................. 28
4.5. Digital Audio Output Timing ............................................................................................................................... 29
5. Pin Diagram and Pin Descriptions ............................................................................................................................... 31
5.1. Pin Diagram ......................................................................................................................................................... 31
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 3
5.2. Pin Descriptions .................................................................................................................................................. 32
5.2.1. HDMI Receiver and MHL Port Pins .............................................................................................................. 32
5.2.2. HDMI Receiver and MHL Port Pins (continued) .......................................................................................... 33
5.2.3. HDMI Transmitter Port Pins ........................................................................................................................ 33
5.2.4. Audio Return Channel Pins ......................................................................................................................... 33
5.2.5. Audio Pins ................................................................................................................................................... 34
5.2.6. Crystal Pins .................................................................................................................................................. 34
5.2.7. SPI Interface Pins ........................................................................................................................................ 35
5.2.8. Parallel Video Bus ....................................................................................................................................... 35
5.2.9. DDC I2C Pins ................................................................................................................................................ 36
5.2.10. Control Pins ................................................................................................................................................. 37
5.2.11. System Switching Pins ................................................................................................................................. 37
5.2.12. Configuration Pins ....................................................................................................................................... 38
5.2.13. CEC Pins....................................................................................................................................................... 38
5.2.14. Power and Ground Pins .............................................................................................................................. 39
5.2.15. Reserved Pin ............................................................................................................................................... 39
6. Feature Information .................................................................................................................................................... 40
6.1. Standby and HDMI Port Power Supplies ............................................................................................................. 40
6.2. InstaPort.............................................................................................................................................................. 41
6.3. InstaPrevue ......................................................................................................................................................... 41
6.4. Support for UltraHD resolution at 50P/60P frames per second .......................................................................... 42
6.5. ViaPort Matrix Switch ......................................................................................................................................... 42
6.6. MHL Receiver ...................................................................................................................................................... 42
6.7. 3D Video Formats on Main Display .................................................................................................................... 43
6.8. VS Insertion ......................................................................................................................................................... 43
6.9. 3D L/R and Active Space Indicators Output on GPIO Pins ................................................................................... 44
6.10. Parallel Video Input Data Bus Mapping .......................................................................................................... 45
6.10.1. Common Video Input Formats ................................................................................................................... 45
6.10.2. RGB and YCbCr 4:4:4 Formats Dual Clock Edge .......................................................................................... 46
6.10.3. YC 4:2:2 Separate Sync Formats .................................................................................................................. 48
6.10.4. YC 4:2:2 Embedded Syncs Formats ............................................................................................................. 49
6.10.5. YC Mux 4:2:2 Separate Sync Formats Single Clock Edge ............................................................................. 52
6.10.6. YC Mux 4:2:2 Embedded Sync Formats Single Clock Edge .......................................................................... 56
6.10.7. YC Mux 4:2:2 Separate Sync Formats Dual Clock Edge ............................................................................... 59
6.10.8. YC Mux 4:2:2 Embedded Sync Formats Dual Clock Edge ............................................................................ 64
7. Design Recommendations .......................................................................................................................................... 69
7.1. Power Supply Decoupling ................................................................................................................................... 69
7.2. Power Supply Control Timing and Sequencing ................................................................................................... 69
8. Package Information ................................................................................................................................................... 70
8.1. ePad Requirements ............................................................................................................................................. 70
8.2. Package Dimensions ........................................................................................................................................... 71
8.3. Marking Specification ......................................................................................................................................... 72
8.4. Ordering Information .......................................................................................................................................... 72
References .......................................................................................................................................................................... 73
Standards Documents ..................................................................................................................................................... 73
Standards Groups ........................................................................................................................................................... 73
Lattice Semiconductor Documents ................................................................................................................................. 73
Technical Support ........................................................................................................................................................... 73
Revision History .................................................................................................................................................................. 74
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 SiI-DS-1089-G
Figures
Figure 1.1. Port Processor Application ............................................................................................................................ 7
Figure 2.1. Functional Block Diagram ............................................................................................................................. 9
Figure 2.2. I2C Control Configuration ............................................................................................................................ 10
Figure 3.1. Test Point SBVCC5TP for SBVCC5 Measurement ......................................................................................... 18
Figure 3.2. Audio Crystal Schematic ............................................................................................................................. 23
Figure 4.1. IDCK Clock Duty Cycle ................................................................................................................................. 26
Figure 4.2. Control and Data Single-Edge Setup and Hold Times—EDGE = 1 ............................................................... 26
Figure 4.3. Control and Data Single-Edge Setup and Hold Times—EDGE = 0 ............................................................... 26
Figure 4.4. Control and Data Dual-Edge Setup and Hold Times ....................................................................................27
Figure 4.5. Conditions for Use of RESET# .......................................................................................................................27
Figure 4.6. RESET# Minimum Timing .............................................................................................................................27
Figure 4.7. I2C Data Valid Delay (Driving Read Cycle Data) ........................................................................................... 28
Figure 4.8. I2C Data Setup Time .................................................................................................................................... 28
Figure 4.9. I2S Input Timing .......................................................................................................................................... 28
Figure 4.10. S/PDIF Input Timing .................................................................................................................................. 28
Figure 4.11. I2S Output Timing ...................................................................................................................................... 29
Figure 4.12. S/PDIF Output Timing ............................................................................................................................... 29
Figure 4.13. MCLK Timing ............................................................................................................................................. 29
Figure 4.14. SPI Flash Memory Timing ......................................................................................................................... 30
Figure 5.1. Pin Diagram (Top View)............................................................................................................................... 31
Figure 6.1. Standby Power Supply Diagram .................................................................................................................. 40
Figure 6.2. VS Insertion in Active Space ........................................................................................................................ 44
Figure 6.3. L/R and Active Space Indicators Output on GPIO Pins ................................................................................ 45
Figure 6.4. 8-bit Color Depth RGB/YCbCr 4:4:4 Dual Edge Timing (DRA = 0) .................................................................47
Figure 6.5. 8-bit Color Depth RGB/YCbCr 4:4:4 Dual Edge Timing (DRA = 1) .................................................................47
Figure 6.6. 8-bit Color Depth YC 4:2:2 Timing (YCSWAP = 0) ........................................................................................ 48
Figure 6.7. 8-bit Color Depth YC 4:2:2 Timing (YCSWAP = 1) ........................................................................................ 49
Figure 6.8. 10-bit Color Depth YC 4:2:2 Timing (YCSWAP = 0) ...................................................................................... 49
Figure 6.9. 10-bit Color Depth YC 4:2:2 Timing (YCSWAP = 1) ...................................................................................... 49
Figure 6.10. 8-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 0) ........................................................... 50
Figure 6.11. 8-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 1) ........................................................... 51
Figure 6.12. 10-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 0) ......................................................... 51
Figure 6.13. 10-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 1) ......................................................... 51
Figure 6.14. 8-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0) .................................................................................... 52
Figure 6.15. 8-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1) .................................................................................... 53
Figure 6.16. 10-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0) .................................................................................. 54
Figure 6.17. 10-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1) .................................................................................. 54
Figure 6.18. 12-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0) .................................................................................. 55
Figure 6.19. 12-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1) .................................................................................. 56
Figure 6.20. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0) ...........................................................57
Figure 6.21. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1) ...........................................................57
Figure 6.22. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0) ........................................................ 58
Figure 6.23. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1) ........................................................ 58
Figure 6.24. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0) ........................................................ 59
Figure 6.25. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1) ........................................................ 59
Figure 6.26. 8-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0) .............................................. 60
Figure 6.27. 8-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 1) .............................................. 61
Figure 6.28. 10-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0) ............................................ 62
Figure 6.29. 10-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 0) ............................................ 62
Figure 6.30. 12-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0) ............................................ 63
Figure 6.31. 12-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 0) ............................................ 64
Figure 6.32. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0) .................... 65
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 5
Figure 6.33. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 1) ..................... 65
Figure 6.34. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0) ................... 66
Figure 6.35. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 0) ................... 67
Figure 6.36. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0) ................... 68
Figure 6.37. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 0) ................... 68
Figure 7.1. Decoupling and Bypass Schematic ............................................................................................................... 69
Figure 7.2. Decoupling and Bypass Capacitor Placement .............................................................................................. 69
Figure 8.1. Package Diagram ..........................................................................................................................................71
Figure 8.2. SiI957n Marking Diagram ............................................................................................................................. 72
Figure 8.3. Alternate SiI9573 Marking Diagram ............................................................................................................. 72
Figure 8.4. Alternate SiI9575 Marking Diagram ............................................................................................................. 72
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 SiI-DS-1089-G
Tables
Table 2.1. Pixel Clock Source and Frequency ................................................................................................................ 13
Table 3.1. Absolute Maximum Conditions .................................................................................................................... 17
Table 3.2. Normal Operating Conditions ....................................................................................................................... 18
Table 3.3. Digital I/O DC Specifications ......................................................................................................................... 19
Table 3.4. TMDS Input DC Specifications – HDMI Mode ............................................................................................... 19
Table 3.5. TMDS Input DC Specifications – MHL Mode................................................................................................. 19
Table 3.6. TMDS Output DC Specifications ................................................................................................................... 20
Table 3.7. Single Mode Audio Return Channel DC Specifications ................................................................................. 20
Table 3.8. S/PDIF Input Port DC Specifications.............................................................................................................. 20
Table 3.9. CEC DC Specifications ................................................................................................................................... 20
Table 3.10. CBUS DC Specifications ............................................................................................................................... 20
Table 3.11. Power .......................................................................................................................................................... 21
Table 3.12. TMDS Input Timing AC Specifications – HDMI Mode ................................................................................. 21
Table 3.13. TMDS Input Timing AC Specifications – MHL Mode ................................................................................... 21
Table 3.14. TMDS Output Timing AC Specifications...................................................................................................... 21
Table 3.15. Single Mode Audio Return Channel AC Specifications ............................................................................... 22
Table 3.16. CEC AC Specifications ................................................................................................................................. 22
Table 3.17. CBUS AC Specifications ............................................................................................................................... 22
Table 3.18. Video Input Timing AC Specifications ........................................................................................................ 22
Table 3.19. Control Signal Timing Specifications .......................................................................................................... 23
Table 3.20. Audio Crystal Frequency ............................................................................................................................. 23
Table 3.21. S/PDIF Input Port AC Specifications ............................................................................................................ 24
Table 3.22. I2S Input Port AC Specifications .................................................................................................................. 24
Table 3.23. I2S Output Port AC Specifications ............................................................................................................... 24
Table 3.24. S/PDIF Output Port AC Specifications ......................................................................................................... 24
Table 3.25. Serial Flash AC Specifications ..................................................................................................................... 25
Table 6.1. Description of Power Modes ........................................................................................................................ 40
Table 6.2. Supported InstaPrevue Window Formats .................................................................................................... 42
Table 6.3. Supported 3D Video Formats ....................................................................................................................... 43
Table 6.4. L/R and Active Space Indicator Mapping to GPIO Pins ................................................................................. 44
Table 6.5. Video Input Formats ..................................................................................................................................... 45
Table 6.6. RGB/YCbCr 4:4:4 Separate Sync Dual Clock Edge Data Mapping .................................................................. 46
Table 6.7. YC 4:2:2 Separate Sync Data Mapping .......................................................................................................... 48
Table 6.8. YC 4:2:2 Embedded Sync Data Mapping ....................................................................................................... 50
Table 6.9. YC Mux 4:2:2 8-bit Color Depth Separate Sync Data Mapping ..................................................................... 52
Table 6.10. YC Mux 4:2:2 10-bit Color Depth Separate Sync Data Mapping ................................................................. 53
Table 6.11. YC Mux 4:2:2 12-bit Color Depth Separate Sync Data Mapping ................................................................. 55
Table 6.12. YC Mux 4:2:2 8-bit Color Depth Embedded Sync Data Mapping ................................................................ 56
Table 6.13. YC Mux 4:2:2 10-bit Color Depth Embedded Sync Data Mapping ...............................................................57
Table 6.14. YC Mux 4:2:2 12-bit Color Depth Embedded Sync Data Mapping .............................................................. 58
Table 6.15. YC Mux 4:2:2 8-bit Color Depth Separate Sync Dual Clock Edge Data Mapping ......................................... 60
Table 6.16. YC Mux 4:2:2 10-bit Color Depth Separate Sync Dual Clock Edge Data Mapping ....................................... 61
Table 6.17. YC Mux 4:2:2 12-bit Color Depth Separate Sync Dual Clock Edge Data Mapping ....................................... 63
Table 6.18. YC Mux 4:2:2 8-bit Color Depth Embedded Sync Dual Clock Edge Data Mapping ...................................... 64
Table 6.19. YC Mux 4:2:2 10-bit Color Depth Embedded Sync Dual Clock Edge Data Mapping.................................... 66
Table 6.20. YC Mux 4:2:2 12-bit Color Depth Embedded Sync Dual Clock Edge Data Mapping.................................... 67
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 7
1. General Description
The Lattice Semiconductor SiI9573 and SiI9575 Port
Processor is the latest generation HDMI® port
processor targeted at audio video receivers (AVR),
Home Theater in a Box (HTiB), and Digital TVs (DTVs).
The port processor has many innovative features such
as InstaPort®, InstaPrevue, Mobile High-Definition Link
(MHL®), ViaPort Matrix Switch (the SiI9575 device only),
and Audio Return Channel (ARC) technology.
The two devices are the same except where noted.
SiI957n is used throughout this document to refer to
both devices.
The SiI957n port processor offers an extensive set of
audio features including audio extraction and insertion.
Audio from the active HDMI input is sent to the main
or subaudio output port. High-Bitrate (HBR) audio is
supported on the main audio output port. Additionally,
a 2-channel I2S or an S/PDIF input receives PCM or bit
stream audio from an audio DSP or a DTV SoC, and
output to either the main or sub-HDMI output, or
both.
The SiI957n port processor supports two independent
ARC transceivers. Each ARC transceiver is configurable
as an ARC receiver or transmitter. As an ARC receiver in
an AVR or HTiB design, either the Tx0 or Tx1 HDMI
output can receive an ARC signal from a DTV. As an ARC
transmitter in a DTV design, the ARC signal can be
transmitted out of the two of the six Rx HDMI inputs,
which are designated as ARC-capable, to an AVR or
soundbar.
The MHL to HDMI bridge function is available on two
input ports; this allows consumers to attach their
mobile devices to the AVR or DTV and view high
definition content while the AVR or DTV charges the
mobile device battery.
The SiI9575 device supports ViaPort Matrix Switch.
While the main HDMI output selects one of the HDMI
inputs, the second HDMI output can select another
HDMI input or parallel video input. This is ideal for AVR
Zone 2 support or PIP/POP function in DTV.
1.1. HDMI Inputs and Outputs
Six HDMI input ports support 300 MHz
simultaneously
Two HDMI output ports that support 300 MHz
simultaneously
TMDS™ cores run up to 3.0 Gb/s
HDMI, MHL, HDCP, and DVI compatible
Supports video resolutions up to 4K × 2K @ 30 Hz,
8-bit, 1080p @ 60 Hz, 12-bit or 720p/1080i @ 120
Hz, 12-bit
Supports 4K × 2K 50P/60P FPS when pixel format is
YCb Cr 4:2:0.
Supports all the mandatory and some optional 3D
formats up to 300 MHz
MHL support up to1080p @ 24 Hz on two input
ports
Pre-programmed with HDCP keys
Repeater function supports up to 127 devices
Figure 1.1. Port Processor Application
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 SiI-DS-1089-G
1.2. Performance Improvement
Features
InstaPort™ viewing technology reduces port
switching time to less than one second
InstaPrevue technology provides a picture-in-
picture preview of connected source devices
AVI, Audio InfoFrame, and video input resolution
detection for all input ports, accessible port-by-
port
Hardware-based HDCP error detection and
recovery minimizes firmware intervention
Automatic output mute and unmute based on link
stability, such as cable connect/detach
1.3. Audio Inputs and Outputs
Two S/PDIF inputs and two S/PDIF outputs
supporting PCM and compressed audio formats up
to 192 kHz such as Dolby Digital, DTS, and AC-3
DSD output supports Super Audio CD applications,
up to 6 channels
I2S outputs support PCM, DVD-Audio output, up to
8-channel 192 kHz
I2S inputs support PCM, DVD-Audio input, up to 2-
channel 192 kHz
High-Bitrate audio output support such as
DTS-HD MA and Dolby® TrueHD
Sample Rate Converter (SRC) supports down
sampling 2:1 and 4:1
Two HDMI ARC inputs or outputs support
1.4. Control Capability
Two independent Consumer Electronics Control
(CEC) interfaces with HDMI-compliant CEC I/O to
support two sink devices
Integrated EDID in non-volatile memory and DDC
support for the HDMI ports using separate
256-byte SRAM for the HDMI ports and 128-byte
SRAM for VGA EDID
Individual control of Hot Plug Detect (HPD) for
each of the input ports
Controllable by the local I2C bus
1.5. Packaging
176-pin, 20 mm × 20 mm, 0.4 mm pitch TQFP package
with an exposed pad (ePad)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 9
2. Functional Description
Figure 2.1 shows the block diagram of the SiI957n port processor.
Power-Down
Section
R0X
R1X
R2X
R3X
R4X
R5X
D[19..0]
Audio Input
Audio Output
Multi-Channel
Parallel
Video
Input
ARC0/1 Rx
I2S/SPDIF/
DSD
I2S/SPDIF
ARC
Input
and
Output
HDCP
Decryption
T1X
Audio Input
I2S/SPDIF
OSD SPI
T0X
TMDS Tx
(Port 0)
HDCP Encryption
Main
Sub
Main
Sub
Mobile HD
Control
HDCP
Registers OTP
EDID SRAM NVRAM Booting
Sequencer
Configuration, Status,
and Interrupt-Control
Registers
DDC0
DDC1
DDC2
DDC3
DDC4
DDC5
Local
I2C
Always-On
Section
CEC A0
DDC
I2C
INT
CBUS/
HPD
Serial Ports
CEC A1
CBUS0
CBUS1
CEC Interface
Controller 1
TPI HW
DDC TX
ARC0/1 Tx
Power
RnPWR5V,
SBVCC5V
HDMI/
MHL
Receiver
InstaPort
HDMI/
MHL
Receiver
InstaPort
TMDS Rx
(Port 0)
TMDS Rx
(Port 1)
TMDS Rx
(Port 2)
TMDS Rx
(Port 3)
TMDS Rx
(Port 4)
TMDS Rx
(Port 5)
M
U
X
M
U
X
M
U
X
M
U
X
M
U
X
M
U
XTMDS Tx
(Port 1)
HDCP Encryption
Audio Output
2 Channel
CEC Interface
Controller 0
SRC
M
U
X
DDC6
Video
Pattern
Generator
InstaPrevue
Stream
Mixer
Video/
Audio
Splitter
A
B
C
D
E
F
G
ENB
Figure 2.1. Functional Block Diagram
2.1. Always-on Section
The Always-on section contains the low speed control circuits of the HDMI connection, and includes the I2C interfaces,
internal memory blocks, and the registers that control the blocks of the Power-down section.
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 SiI-DS-1089-G
2.1.1. Serial Ports Block
The Serial Ports Block provides eight I2C serial interfaces: six DDC ports to communicate with the HDMI or DVI hosts,
one VGA DDC port, and one local I2C port for initialization and control by a local microcontroller in the display or AVR.
Each interface is 5 V tolerant. Figure 2.2 shows the connection of the local I2C port to the system microcontroller.
Port Processor System
Microcontroller
INT
VDD33 Standby Power
SiI957nCSDA
CSCL
Figure 2.2. I2C Control Configuration
The seven DDC interfaces (DDC 0–6) on the SiI957n port processor are slave interfaces that can run up to 400 kHz. Each
interface connects to one E-DDC bus and is used to read the integrated EDID and HDCP authentication information. The
port is accessible on the E-DDC bus at device addresses 0xA0 for the EDID and 0x74 for HDCP control. The transmitter
DDC master controller supports accessing HDCP and EDID up to 100 kHz. Local I2C can also access the transmitter DDC
bus; in this case, an internal oscillator provides the clock source.
2.1.2. Static RAM Block
The Static RAM (SRAM) Block contains 2,560 bytes of RAM. Each port is allocated a 256-byte block for DDC; this allows all
ports to be read simultaneously from six different sources connected to the SiI957n device. A 128-byte block is available
for VGA DDC, 768 bytes are available for Key Selection Vectors (KSV), 64 bytes are used for the auto-boot feature, and 64
bytes are reserved. Every EDID and SHA KSV has an offset location. The SRAM can be written to and read from using the
local I2C interface and it can be read through the DDC interface. The memory can be read through the DDC interface
without main TV power, using only 5 V power from the HDMI connector.
2.1.3. NVRAM Block
The port processor contains 512 bytes of NVRAM, 256 of which is used to store common EDID data used by each of the
ports, 128 of which is used for VGA DDC, and 64 of which is used by the auto boot feature. 64 bytes are unused. Both
the NVRAM EDID data and NVRAM auto-boot data should be initialized by software using the local I2C bus at least once
during the time of manufacture.
2.1.4. HDCP Registers Block
The HDCP Registers Block controls the necessary logic to decrypt the incoming audio and video data. The decryption
process is controlled entirely by the host-side microcontroller using a set sequence of register reads and writes through
the DDC channel. The decryption process uses preprogrammed HDCP keys and Key Selection Vector (KSV) stored in the
on-chip nonvolatile memory.
2.1.5. OTP ROM Block
The Receiver One-Time Programmable (OTP) ROM Block is preprogrammed at the factory with HDCP keys. System
manufacturers do not need to purchase key sets from Digital Content Protection, LLC. Lattice Semiconductor handles all
purchasing, programming, and security for the HDCP keys. The preprogrammed HDCP keys provide the highest level of
security possible, as it is not possible to read out the keys after they are programmed.
2.1.6. Booting Sequencer
The Booting Sequencer boots up the required data, such as EDID, initial HPD status, and MHL port selection from
NVRAM during power on.
SiI9573 and SiI9575 Port Processor
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 11
2.1.7. Configuration, Status, and Interrupt Control Block
The Configuration, Status, and Interrupt Control Registers Block incorporate the registers required for configuring and
managing the features of the SiI957n port processor. These registers are grouped by functions such as RPI, TPI, CPI,
MHL, and miscellaneous and are used to perform audio, video, and auxiliary format processing, HDMI 1.4a InfoFrame
Packet format, and power-down control. The registers are accessible from the local I2C port. This block also handles
interrupt operation.
2.1.8. Mobile HD Control Block
The Mobile HD Control Block handles MHL DDC control. This block handles CBUS conversion to DDC signals for
accessing the EDID and HDCP interface blocks.
2.1.9. CEC Interface Controller
Two independent Consumer Electronics Control (CEC) interface controllers are available in the SiI957n port processor.
This gives the system designer the option to design a system that supports both primary CEC line and a secondary CEC
line that are not physically connected to each other. For example, using an AVR featuring two DTV connections from the
SiI957n device, the primary CEC line (CEC_A0 pin) can be connected to the CEC signal of all HDMI input ports of the AVR
while the secondary CEC line (CEC_A1 pin) connects to the CEC signal of the second DTV.
Each CEC interface controller provides a CEC-compliant signal and has a high-level register interface accessible through
the I2C interface. Programming is done through the Lattice Semiconductor CEC Programming Interface (CPI). This
controller makes CEC control easy and straightforward by removing the burden of requiring that the host processor
perform these low-level transactions on the CEC bus. As a result, CEC pass-through mode is neither required nor
supported.
The CEC controllers (CEC_A0 and CEC_A1) are identical except for the device address used to access them.
2.1.10. Power Block
The Power Block features an analog power multiplexer with inputs from the +5 V power from the R[0–5]PWR5V and the
SBVCC5V sources. The output of the analog power multiplexer supplies power to the Always-On Section.
2.2. Power-down Section
The Power-down Section contains the HDMI high-speed data paths, including the analog TMDS input and output blocks
and the digital logic for HDMI data and HDCP processing.
2.2.1. TMDS Receiver Blocks
The TMDS Receiver Blocks, defined as Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5, are terminated separately,
equalized under the control of the receiver digital block, and controlled by the local I2C bus. Input data is over-sampled
by five to enable the downstream DPLL block to capture the most stable signal at any given time.
2.2.2. 6:1 Input Multiplexer Blocks A and B and 4:1 Input Multiplexer Blocks C and D
6:1 Input Multiplexer Block A selects one of the six TMDS inputs and sends it to the main pipe. 6:1 Input Multiplexer
Block B selects one of the six TMDS inputs and sends it to the subpipe. 4:1 Input Multiplexer Block C selects among
main pipe, subpipe, parallel video, and video pattern generator sources and sends it to HDMI output Tx0. 4:1 Input
Multiplexer Block D selects among main pipe, subpipe, parallel video, and video pattern generator sources and sends it
to HDMI output Tx1. The specific function of the multiplexers is determined by whether InstaPort, InstaPrevue, or
matrix switch mode is enabled.
In InstaPort or InstaPrevue modes, Multiplexer Block A selects the active input and sends it to the main pipe for
processing. The subpipe functions as a roving pipe whereby Multiplexer Block B sequentially selects one of the five
inactive inputs and sends it to the InstaPort or InstaPrevue blocks for processing. Multiplexer Blocks C and D can each
independently select among main pipe, parallel video, and video pattern generator sources to send to HDMI output Tx0
and Tx1 respectively.
SiI9573 and SiI9575 Port Processor
Data Sheet
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12 SiI-DS-1089-G
In matrix switch mode, Multiplexer Block A selects one active input and sends it to the main pipe for processing. roving
is disabled and the subpipe functions as a second processing pipe for another active input selected by Multiplexer Block
B. Multiplexer Blocks C and D can each independently select between main pipe and subpipe sources to send to HDMI
output Tx0 and Tx1, respectively. Matrix Switch mode is supported on the SiI9575 device only.
2.2.3. HDMI, MHL, and InstaPort Receiver Blocks
The HDMI, MHL, and InstaPort Receiver blocks perform functions including deskewing, analyzing packets, processing
the main pipe and roving pipe, multiplexing, demultiplexing, repeater functions, and HDCP authentication. The SiI957n
device supports six HDMI input ports. MHL can be enabled on any two input ports selected at the time of manufacture
by programming a register in the NVRAM.
2.2.4. Video/Audio Splitter Block
The Video/Audio Splitter Block separates the video and audio data from the TMDS stream for the roving pipe. The video
is sent to the InstaPrevue block and the audio is sent to Multiplexer Blocks C and D. This can be used in the InstaPrevue
Picture-In-Picture (PIP) mode in which a single sub-window is displayed on the main video. The audio from the sub-
window can replace the audio from the main video before being sent to Tx0 and Tx1.
2.2.5. InstaPrevue Block
The InstaPrevue Block captures and processes all of the preauthenticated HDMI/DVI/MHL subframe images from the
roving pipe. The operating preview mode is configured in this block.
2.2.6. Stream Mixer Block
The Stream Mixer Block replaces a region of the main port video with a sub-frame image from the InstaPrevue block. It
merges sub-frames with the main video input at the proper screen locations specified by external software register
settings.
2.2.7. 2:1 Input Multiplexer Blocks E and F and Main and Subaudio Formatting Blocks
2:1 Input Multiplexer Block E selects either the decoded audio stream from the TMDS input to main pipe or the subpipe
and sends it to the main audio block to be processed as I2S and S/PDIF. The main audio block supports 8-channel PCM
and 6-channel DSD for I2S and 2-channel PCM and compressed audio formats for S/PDIF. 2:1 Input Multiplexer Block F
selects either the decoded audio stream from the TMDS input to main pipe or the subpipe and sends it to the subaudio
block to be sent out as I2S and S/PDIF. The subaudio block supports 2-channel PCM for I2S and 2-channel PCM and
compressed audio formats for S/PDIF.
2.2.8. Parallel Video Input Block
The Parallel Video Input Block features a 20-bit parallel video input interface which supports input clocks up to 165 MHz
in dual edge and single edge modes. In dual edge mode, incoming data is latched on both edges of the clock for double
data rate (DDR) to support up to 720p/1080i @ 60 Hz for RGB/YCbCr 4:4:4 formats. In single edge mode, incoming data
is latched on one edge of the clock for single data rate (SDR) to support up to 1080p @ 60 Hz and UXGA @ 60 Hz for
YCbCr 4:2:2 formats.
Video processing features support color space conversion, 4:2:2 to 4:4:4 up- and 4:4:4 to 4:2:2 down-sampling, RGB
range expansion, RGB/YCbCr range compression, clipping, and dithering functions. All of these functions can be
bypassed through register settings.
The color space conversion feature performs color conversion from YCbCr to RGB and RGB to YCbCr according to the
selected color space standard ITU-R BT.601 for standard-definition DTV and ITU-R BT.709 for high-definition DTV.
Chrominance up-sampling increases the number of chrominance samples in each line of video. Up-sampling doubles
the number of chrominance samples in each line, converting 4:2:2 sampled video to 4:4:4 sampled video.
Chrominance down-sampling decreases the number of chrominance samples in each line of video. Down-sampling
halves the number of chrominance samples in each line, converting 4:4:4 sampled video to 4:2:2 sampled video.
SiI9573 and SiI9575 Port Processor
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SiI-DS-1089-G 13
The SiI957n port processor can scale the input color range from limited-range into full range using the range expansion
block. When enabled by itself, the range expansion block expands 16–235 limited-range data into 0–255 full-range data
for each video channel. When range expansion and the YCbCr to RGB color space converter are both enabled, the input
conversion range for the Cb and Cr channels is 16–240.
When enabled by itself, the range compression block compresses 0–255 full range data into 16–235 limited range data
for each video channel. When enabled with the RGB to YCbCr converter, this block compresses to 16–240 for the Cb and
Cr channels. The color range scaling is linear.
When enabled, the clipping block clips the values of the output video to 16–235 for RGB video for the Y channel, and to
16–240 for the Cb and Cr channels.
The SiI957n port processor can dither the video by adding a pseudorandom number to every value. The 18-bit dithering
result can be truncated or rounded. Additionally, dithering can be enabled or disabled by video component (R, G, B, Y,
Cb, or Cr).
2.2.9. Video Pattern Generator Block
The Video Pattern Generator (VPG) Block supplies one of eight predefined video patterns to the HDMI transmitters. The
predefined video patterns are solid red, solid green, solid blue, solid black, solid white, ramp, 8 × 6 chessboard, and
color bars. The video patterns have an RGB color space at 480p, 576p, and 720p video resolutions.
An example use for the VPG is to combine the predefined video pattern with an external audio input to create a
complete HDMI stream which can then be sent out of the HDMI transmitter to a sound bar. The VPG can also be used
for test purposes during product development.
The VPG requires a pixel clock for its operation. One of several clock sources, including the crystal oscillator (xclk), audio
VCO clock 0, or audio VCO clock 1, can be used to generate the pixel clock for the VPG. If the crystal oscillator (xclk),
audio VCO clock 0, or audio VCO clock 1 is used as the clock source for the VPG, then the frequency of the external
audio crystal must be 27 MHz to generate the correct pixel clock frequencies for the VPG. Incorrect pixel clock
frequencies will be generated if the external audio crystal used is not 27 MHz; the range specified in Table 3.20 on page
23 will not work for this function. The xclk is generated from the external audio crystal. The audio VCO clock 0 is an
output of a PLL which uses the xclk as the input. The audio VCO clock 1 is an output of another PLL which also uses the
xclk as the input. Table 2.1 shows the pixel clock source and frequency for the VPG at 480p, 576p and 720p video
resolutions. Refer to the Programmer’s Reference for details on configuring the VPG.
Table 2.1. Pixel Clock Source and Frequency
Video Resolution
Pixel Clock Source
Pixel Clock Frequency
480p, 576p
xclk
27 MHz
720p
audio VCO clock 0 or audio VCO clock 1
(27 MHz) • (11/4) = 74.25 MHz
The audio VCO clock 0 and VCO clock 1 PLLs are shared with the audio extraction logic. Therefore, if audio VCO clock 0
or VCO clock 1 is used for the VPG, the respective main or subport audio extraction mode needs to be disabled.
2.2.10. Audio Sampling Rate Converter Block
The audio Sampling Rate Converter (SRC) Block allows the inserted 2-channel PCM audio from either the main- or sub-
audio ports to be down-sampled before combining with the HDMI stream from the main pipe and sending to Tx0. The
audio data can be down-sampled by a factor of 2 or 4 by register control. Conversions from: 192 kHz to 48 kHz,
176.4 kHz to 44.1 kHz, 96 kHz to 48 kHz, and 88.2 kHz to 44.1 kHz are supported.
SiI9573 and SiI9575 Port Processor
Data Sheet
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14 SiI-DS-1089-G
2.2.11. On-screen Display Controller
The On-screen Display Controller (OSD) Block supports a text-based onscreen display that allows for up to four
character-based windows to be overlaid onto the video displayed from the Tx0 HDMI output. The OSD supports three
font sizes: 12×16, 16 × 24 and 24 × 32 pixels, to provide flexibility for choosing the character and icon size in the OSD
windows.
OSD supports 480p, 576p, 720p, 1080p, and 1080iHDMI 2D video formats. OSD is supported on SiI957n Tx0 HDMI
output only. OSD may be combined on the displayed video along with InstaPrevue windows to form a complete menu
system.
A 12 kB on-chip RAM memory stores the OSD font bit maps and window index information. The OSD memory can be
loaded by the host microcontroller through the I2C bus or from an external flash memory though the Serial Peripheral
Interface (SPI). The SPI supports clock frequencies of 1.6875 MHz, 3.375 MHz, 13.5 MHz, and 27 MHz. This interface is
used to read and write the external flash memory. In addition, the host microcontroller can program the external flash
memory using I2C through the SPI interface.
2.2.12. Audio Input Block
The Audio Input Block supports external audio insertion into the transmitted HDMI streams. There are two audio input
blocks: the main audio port and the subaudio port. The inserted audio to the main audio port is two-channel I2S or a
single S/PDIF. Similarly, the inserted audio to the subaudio port is two-channel I2S or a single S/PDIF.
Both main audio port and subaudio port insertion support the following audio formats:
I2S: 2 channels
PCM: 2 channels
S/PDIF: IEC 60958 and IEC 61937
PCM: 2channels
Compressed bit-stream: Dolby® Digital, Dolby Digital Plus, Dolby Digital EX, Dolby Digital Surround EX DTS, DTS
ES
Each of the SiI957n I2S main and subaudio port insertion requires SCK, WS, and SD0 signals for two channel I2S. For both
the main and subaudio ports, the SiI957n device supports CTS and N value generation without requiring an MCLK input.
The SiI957n main audio port S/PDIF insertion shares the same pin with SD0 of the I2S insertion. The function of this pin
is configured by software.
The SiI957n subaudio port S/PDIF insertion shares the same pin with SD0 of the I2S insertion. The function of this pin is
configured by software. In addition, the subaudio port I2S and S/PDIF insertion pins are multiplexed with the subaudio
port I2S and S/PDIF extraction pins. The functions of these pins are configured by software.
The audio inserted into the main audio port can be combined with the HDMI stream from the main pipe and sent to Tx0
or combined with the HDMI stream from the subpipe and sent to Tx1. Similarly, the audio inserted to the subaudio port
can be combined with the HDMI stream from the main pipe and sent to Tx0 or combined with the HDMI stream from
the subpipe and sent to Tx1. The audio sampling rate converter block selects between inserted audio from the main
audio port and the subaudio port to send to Tx0. Input Multiplexer G selects between inserted audio from the main
audio port and the subaudio port to send to Tx1.
SiI9573 and SiI9575 Port Processor
Data Sheet
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 15
2.2.13. Audio Output Block
The Audio Output Block supports audio extraction from the received HDMI/MHL streams. There are two audio output
blocks, the main audio port and the subaudio port. The extracted audio from the main audio port is eight-channel I2S,
six-channel DSD, or a single S/PDIF audio. The extracted audio from the subaudio port is either two-channel I2S or
single S/PDIF audio.
Main Audio Port Extraction
I2S: 8 channels
PCM: up to 8 channels
HBR: Dolby TrueHD, DTS-HD Master Audio
DSD: 6 channels
S/PDIF: IEC 60958 and IEC 61937
PCM: 2 channels
Compressed bit-stream: Dolby Digital, Dolby Digital Plus, Dolby Digital EX, Dolby Digital Surround EX, DTS,
DTS-ES
Subaudio Port Extraction
I2S: 2 channels
PCM: 2 channels
S/PDIF: IEC 60958 and IEC 61937
PCM: 2 channels
Compressed bit-stream: Dolby Digital, Dolby Digital Plus, Dolby Digital EX, Dolby Digital Surround EX, DTS,
DTS-ES
By default, the main audio port is configured for eight-channel I2S audio extraction from the main pipe and the
subaudio port is configured for two-channel I2S audio extraction from the subpipe. The SiI957n device allows swapping
the main and subaudio ports to provide two-channel I2S audio extraction from the main pipe and eight-channel I2S
audio extraction from the subpipe.
The SiI957n I2S audio extraction provides the MCLK, SCK, WS, SD0, SD1, SD2, and SD3 signals for eight-channel I2S from
the main audio port and SCK, WS, and SD0 for two-channel I2S for the subaudio port. To generate the MCLK for the
subaudio port, an external PLL clock generator can be used.
The SiI957n main audio port I2S, DSD, and S/PDIF audio extraction pins are shared. The functions of these pins are
configured by software.
The SiI957n subaudio port S/PDIF audio extraction shares the same pin with SD0 of the I2S audio extraction. The
function of this pin is configured by software. In addition, the subaudio port I2S and S/PDIF audio extraction pins are
multiplexed with the subaudio port I2S and S/PDIF audio insertion pins. The functions of these pins are configured by
software.
2.2.14. Audio Return Channel (ARC) Input and Output
The Audio Return Channel (ARC) feature eliminates an extra cable when sending audio from an HDMI sink device to an
adjacent HDMI source or repeater device. This is done by allowing a single IEC60958-1 or IEC61937 audio stream to
travel in the opposite direction of the TMDS signal on its own conductor in the HDMI cable, after negotiation using CEC
Audio Return Channel Control. The HDMI sink device implements the ARC transmitter and the HDMI source or repeater
device implements the ARC receiver.
The SiI957n device provides two ARC transceiver channels. Each pin can be independently configured to operate as an
ARC transmitter or an ARC receiver. For example, the SiI957n device designed into a DTV can use the ARC transmitter
feature while the SiI957n device designed into an AVR can use the ARC receiver feature. For an ARC transmitter, the
ARC transceiver pin is connected to the ARC pin of the connector for the HDMI Rx port that is designated as ARC-
capable. For an ARC receiver, the ARC transceiver pin is connected to the ARC pin of the HDMI connector for the
transmitter port that is designated as ARC-capable.
SiI9573 and SiI9575 Port Processor
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16 SiI-DS-1089-G
ARC transceivers can share pins with the HDMI Ethernet Channel (HEC) signals. The SiI957n device does not support
HEC and therefore cannot use HEC and ARC simultaneously on the same receiver port.
The SiI957n device supports only single mode ARC. The SiI957n ARC receiver can be made compatible for common
mode ARC by using an AC-coupling network between the HPD and NC pins of the HDMI connector of the transmitter
port and the SiI957n ARC receiver pin.
2.2.15. TMDS Transmitter Block
The TMDS Transmitter Blocks perform HDCP encryption and 8-to-10-bit TMDS encoding on the data to be transmitted
over the HDMI link. The encoded data is sent to the three TMDS differential data lines, along with a TMDS differential
clock line. Internal source termination eliminates the need to use external R-C components for signal shaping. The
internal source termination can be disabled by registers settings. The SiI957n port processor integrates two HDMI
output ports, which enables zone-2 support by using the ViaPort Matrix Switch feature of the device. Both transmitter
ports support up to 300 MHz.
SiI9573 and SiI9575 Port Processor
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 17
3. Electrical Specifications
3.1. Absolute Maximum Conditions
Table 3.1. Absolute Maximum Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Notes
AVDD33
TMDS core supply voltage
−0.3
—
4.0
V
1, 2
IOVCC33
I/O supply voltage
−0.3
—
4.0
V
1, 2
SBVCC5
5 V standby power supply voltage
−0.3
—
5.7
V
1, 2
R[0–5]PWR5V
5 V input from power pin of HDMI connector
−0.3
—
5.7
V
1, 2
XTALVCC33
PLL crystal oscillator power
−0.3
—
4.0
V
1, 2
AVDD13
TMDS receiver core supply voltage
−0.3
—
1.5
V
1, 2
APLL13
PLL Analog VCC
−0.3
—
1.5
V
1, 2
CVCC13
Digital core supply voltage
−0.3
—
1.5
V
1, 2
TDVDD13
TMDS transmitter core supply voltage
−0.3
—
1.5
V
1, 2
TPVDD13
TMDS transmitter core supply voltage
−0.3
—
1.5
V
1, 2
VI
Input voltage
−0.3
—
IOVCC33 + 0.3
V
1, 2
VO
Output voltage
−0.3
—
IOVCC33 + 0.3
V
1, 2
TJ
Junction temperature
0
—
125
C
—
TSTG
Storage temperature
−65
—
150
C
—
Notes:
1. Permanent damage can occur to the device if absolute maximum conditions are exceeded.
2. Functional operation should be restricted to the conditions described in the Normal Operating Conditions section below.
SiI9573 and SiI9575 Port Processor
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 SiI-DS-1089-G
3.2. Normal Operating Conditions
Table 3.2. Normal Operating Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Notes
AVDD33
TMDS core supply voltage
3.14
3.3
3.46
V
—
IOVCC33
I/O supply voltage
3.14
3.3
3.46
V
—
SBVCC5
5 V standby power supply voltage
4.5
5.0
5.5
V
1
R[0–5]PWR5V
5 V input from power pin of HDMI connector
4.5
5.0
5.5
V
—
XTALVCC33
PLL crystal oscillator power
3.14
3.3
3.46
V
—
AVDD13
TMDS receiver core supply voltage
1.25
1.3
1.35
V
2
APLL13
PLL Analog VCC
1.25
1.3
1.35
V
2
CVCC13
Digital core supply voltage
1.25
1.3
1.35
V
2
TDVDD13
TMDS transmitter core supply voltage
1.25
1.3
1.35
V
2
TPVDD13
TMDS transmitter core supply voltage
1.25
1.3
1.35
V
2
AVDD13
TMDS receiver core supply voltage
1.27
1.3
1.35
V
3
APLL13
PLL Analog VCC
1.27
1.3
1.35
V
3
CVCC13
Digital core supply voltage
1.27
1.3
1.35
V
3
TDVDD13
TMDS transmitter core supply voltage
1.27
1.3
1.35
V
3
TPVDD13
TMDS transmitter core supply voltage
1.27
1.3
1.35
V
3
TA
Ambient temperature (with power applied)
0
+25
+70
C
—
ja
Ambient thermal resistance (Theta JA)
—
22.0
—
C/W
—
jc
Junction to case resistance (Theta JC)
—
—
6.0
C/W
—
Notes:
1. SBVCC5 voltage is measured at SBVCC5TP as shown in Figure 3.1.
2. For 4 HDMI Inputs and 2 HDMI output running simultaneously at 300MHz
3. For 5 or 6 HDMI Inputs and 2 HDMI Outputs running simultaneously at 300MHz
SBVCC5
GND
SiI957n
SBVCC5TP
10Ω
0.1 F
10 F
Figure 3.1. Test Point SBVCC5TP for SBVCC5 Measurement
SiI9573 and SiI9575 Port Processor
Data Sheet
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 19
3.3. DC Specifications
Table 3.3. Digital I/O DC Specifications
Symbol
Parameter
Pin Type
Conditions
Min
Typ
Max
Unit
VIH
HIGH-level Input Voltage
LVTTL
—
2.0
—
—
V
VIL
LOW-level Input Voltage
LVTTL
—
—
—
0.8
V
VTH+DDC
LOW-to-HIGH Threshold,
DDC Buses
Schmitt
—
3.0
—
—
V
VTH-DDC
HIGH-to-LOW Threshold,
DDC Buses
Schmitt
—
—
—
1.5
V
VTH+I2C
LOW-to-HIGH Threshold,
I2C Buses
Schmitt
—
2.0
—
—
V
VTH-I2C
HIGH-to-LOW Threshold,
I2C Buses
Schmitt
—
—
—
0.8
V
VOH
HIGH-level Output Voltage
LVTTL
—
2.4
—
—
V
VOL
LOW-level Output Voltage
LVTTL
—
—
—
0.4
V
IOL
Output Leakage Current
—
High Impedance
−10
—
10
A
IOD4
4 mA Digital Output Drive
LVTTL
VOUT = 2.4 V
4
—
—
mA
VOUT = 0.4 V
4
—
—
mA
VTH+RESET
LOW-to-HIGH Threshold,
Reset
Schmitt
—
2.0
—
—
V
VTH-RESET
HIGH-to-LOW Threshold,
Reset
Schmitt
—
—
—
0.8
V
VCINL
Input Clamp Voltage
All
—
—
—
GND –0.3
V
VCIPL
Input Clamp Voltage
All
—
—
—
IOVCC33
+0.3
V
Table 3.4. TMDS Input DC Specifications – HDMI Mode
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VID
Differential Mode Input Voltage
—
150
—
1200
mV
VICM
Common Mode Input Voltage
—
AVDD33
–400
—
AVDD33
–37.5
mV
Table 3.5. TMDS Input DC Specifications – MHL Mode
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIDC
Single-ended Input DC Voltage
—
AVDD33
–1200
—
AVDD33
–300
mV
VIDF
Differential Mode Input Swing Voltage
—
200
—
1000
mV
VICM
Common Mode Input Swing Voltage
—
170
—
Min (720,
0.85 VIDF)
mV
SiI9573 and SiI9575 Port Processor
Data Sheet
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20 SiI-DS-1089-G
Table 3.6. TMDS Output DC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Notes
VSWING
Single-ended Output Swing Voltage
RLOAD = 50 Ω
400
—
600
mV
—
VH
Single-ended High-level Output Voltage
—
AVDD33
–200
—
AVDD33
+10
mV
—
VL
Single-ended Low-level Output Voltage
—
AVDD33
–700
—
AVDD33
–400
mV
—
VTH+RSEN
LOW-to-HIGH Threshold, RSEN
—
0.8
—
1.1
V
1
VTH-RSEN
HIGH-to-LOW Threshold, RSEN
—
0.3
—
0.5
V
2
Notes:
4. RSEN deasserted state to asserted state threshold voltage when sink Rx termination transitions from disabled to enabled.
5. RSEN asserted state to deasserted state threshold voltage when sink Rx termination transitions from enabled to disabled.
Table 3.7. Single Mode Audio Return Channel DC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Vel
Operating DC Voltage
—
0
—
5
V
Vel swing
Swing Amplitude
—
400
—
600
mV
Table 3.8. S/PDIF Input Port DC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Notes
ZI_SPDIF
Termination Impedance
—
—
75
—
Ω
1
—
—
4
—
kΩ
2
VI_SPDIF
Input Voltage
75 Ω
termination,
AC-coupled
400
—
600
mVPP
3
Notes:
1. This impedance is implemented with an external 75 Ω resistor to ground and is used when the interconnection is over a 75
Ω COAX cable.
2. This is the internal impedance of the S/PDIF input.
3. The S/PDIF input can also be safely driven at LVTTL voltage levels without AC coupling. The 75 Ω termination is not
required in this case.
Table 3.9. CEC DC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VTH+CEC
LOW to HIGH Threshold
—
2.0
—
—
V
VTH-CEC
HIGH to LOW Threshold
—
—
—
0.8
V
VOH_CEC
HIGH-level Output Voltage
—
2.5
—
—
V
VOL_CEC
LOW-level Output Voltage
—
—
—
0.6
V
IIL_CEC
Input Leakage Current
Power Off;
RnPWR5V = 0 V
—
—
1.8
A
Table 3.10. CBUS DC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIH_CBUS
High-level Input Voltage
—
1.0
—
—
V
VIL_CBUS
Low-level Input Voltage
—
—
—
0.6
V
VOH_CBUS
High-level Output Voltage
IOH = 100 A
1.5
—
1.9
V
VOL_CBUS
Low-level Output Voltage
IOL = –100 A
—
—
0.2
V
ZDSC_CBUS
Pull-down Resistance – Discovery
—
800
1000
1200
Ω
ZON_CBUS
Pull-down Resistance – Active
—
90
100
110
kΩ
IIL_CBUS
Input Leakage Current
High Impedance
—
—
1
A
CCBUS
Capacitance
Power On
—
—
80
pF
SiI9573 and SiI9575 Port Processor
Data Sheet
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 21
Table 3.11. Power
Symbol
Parameter
Min
Typ
Max
Unit
Notes
IAPLL13
Supply Current for APLL13
—
—
3
mA
1
IAVDD13
Supply Current for AVDD13
—
—
250
mA
1
IAVDD33
Supply Current for AVDD33
—
—
345
mA
1
IIOVCC33
Supply Current for IOVCC33
—
—
2
mA
1
IXTALVCC33
Supply Current for XTALVCC33
—
—
<1
mA
1
ICVCC13
Supply Current for CVCC13
—
—
680
mA
1
ISBVCC5STBY
Supply Current for SBVCC5 in Standby mode
—
—
8
mA
2
ISBVCC5ACT
Supply Current for SBVCC5 in Active mode
—
—
30
mA
1
ITDVDD13
Supply Current for TDVDD13
—
—
60
mA
1
ITPVDD13
Supply Current for TPVDD13
—
—
30
mA
1
Total
Total Power
—
—
2.6
W
1
Notes:
1. With six 300 MHz HDMI receiver inputs with InstaPort, InstaPrevue, audio outputs, and OSD on and two 300 MHz transmitter
outputs.
2. With no active AV sources connected to the HDMI Rx inputs.
3.4. AC Specifications
Table 3.12. TMDS Input Timing AC Specifications – HDMI Mode
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TRXDPS
Intrapair Differential Input Skew
—
—
—
0.4
TBIT
TRXCCS
Channel-to-Channel Differential Input Skew
—
—
—
0.2TPIXEL
+ 1.78
ns
FRXC
Differential Input Clock Frequency
—
25
—
300
MHz
TRXC
Differential Input Clock Period
—
3.33
—
40
ns
TIJIT
Differential Input Clock Jitter Tolerance (0.3Tbit)
300 MHz
—
—
100
ps
Table 3.13. TMDS Input Timing AC Specifications – MHL Mode
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TSKEW_DF
Input Differential Intrapair Skew
—
—
—
93
ps
TSKEW_CM
Input Common-mode Intrapair Skew
—
—
—
93
ps
FRXC
Differential Input Clock Frequency
—
25
—
75
MHz
TRXC
Differential Input Clock Period
—
13.33
—
40
ns
TCLOCK_JIT
Common Mode Clock Jitter Tolerance
—
—
—
0.3TBIT
+ 266.7
ps
TDATA_JIT
Differential Data Jitter Tolerance
—
—
—
0.4TBIT +
88.88
ps
Table 3.14. TMDS Output Timing AC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TTXDPS
Intrapair Differential Output Skew
—
—
—
0.15
TBIT
TTXRT
Data/Clock Rise Time
20%–80%
75
—
—
ps
TTXFT
Data/Clock Fall Time
80%–20%
75
—
—
ps
FTXC
Differential Output Clock Frequency
—
25
—
300
MHz
TTXC
Differential Output Clock Period
—
3.33
—
40
ns
TDUTY
Differential Output Clock Duty Cycle
—
40%
—
60%
TTXC
TOJIT
Differential Output Clock Jitter
—
—
—
0.25
TBIT
SiI9573 and SiI9575 Port Processor
Data Sheet
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22 SiI-DS-1089-G
Table 3.15. Single Mode Audio Return Channel AC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TASMRT
Rise Time
10%–90%
—
—
60
ns
TASMFT
Fall Time
90%–10%
—
—
60
ns
TASMJIT
Jitter Max
—
—
—
0.05
UI*
FASMDEV
Clock Frequency Deviation
—
–1000
—
1000
ppm
*Note: Proportional to unit time (UI), according to sample rate. Refer to the S/PDIF specification.
Table 3.16. CEC AC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TR_CEC
Rise Time
10%–90%
—
—
250
s
TF_CEC
Fall Time
90%–10%
—
—
50
s
Table 3.17. CBUS AC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TBIT_CBUS
Bit Time
1 MHz clock
0.8
—
1.2
s
TBJIT_CBUS
Bit-to-Bit Jitter
—
–1%
—
+1%
TBIT_CBUS
TDUTY_CBUS
Duty Cycle of 1 Bit
—
40%
—
60%
TBIT_CBUS
TR_CBUS
Rise Time
0.2 V–1.5 V
5
—
200
ns
TF_CBUS
Fall Time
0.2 V–1.5 V
5
—
200
ns
ΔTRF
Rise-to-Fall Time Difference
—
—
—
100
ns
Table 3.18. Video Input Timing AC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
TCIP
IDCK Period, One Pixel per Clock
—
6.06
—
40
ns
—
1
FCIP
IDCK Frequency, One Pixel per Clock
—
25
—
165
MHz
—
1
TCIP12
IDCK Period, Dual-edge Clock
—
12.12
—
40
ns
—
2
FCIP12
IDCK Frequency, Dual-edge Clock
—
25
—
82.5
MHz
—
2
TDUTY
IDCK Duty cycle, One Pixel per Clock
—
40%
—
60%
TCIP
Figure 4.1
—
TDUTY12
IDCK Duty Cycle, Dual-edge Clock
—
45%
—
55%
TCIP12
Figure 4.1
—
TIJIT
Worst Case IDCK Clock Jitter
—
—
—
1.0
ns
—
3, 4
TSIDF
Setup Time to IDCK Falling Edge
EDGE = 0
1.0
—
—
ns
Figure 4.3
5
THIDF
Hold Time to IDCK Falling Edge
2.2
—
—
ns
TSIDR
Setup Time to IDCK Rising Edge
EDGE = 1
1.0
—
—
ns
Figure 4.2
5
THIDR
Hold Time to IDCK Rising Edge
2.2
—
—
ns
TSIDD
Setup Time to IDCK Rising or Falling Edge
Dual-edge
Clocking
1.0
—
—
ns
Figure 4.4
6
THIDD
Hold Time to IDCK Rising or Falling Edge
2.2
—
—
ns
Notes:
1. TCIP and FCIP apply in single-edge clocking modes. TCIP is the inverse of FCIP and is not a controlling specification.
2. TCIP12 and FCIP12 apply in dual-edge mode. TCIP12 is the inverse of FCIP12 and is not a controlling specification.
3. Input clock jitter is estimated by triggering a digital scope at the rising edge of the input clock, and measuring peak-to-peak time
spread of the rising edge of the input clock 1 microsecond after the triggering.
4. Actual jitter tolerance can be higher depending on the frequency of the jitter.
5. Setup and hold time specifications apply to Data, DE, VSYNC, and HSYNC input pins, relative to IDCK input clock.
6. Setup and hold limits are not affected by the setting of the EDGE bit for 8/10/12-bit dual-edge clocking mode.
SiI9573 and SiI9575 Port Processor
Data Sheet
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 23
3.4.1. Control Signal Timing Specifications
Under normal operating conditions unless otherwise specified.
Table 3.19. Control Signal Timing Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Notes
TRESET
RESET# signal LOW time required for reset
—
50
—
—
µs
1, 5
TI2CDVD
SDA Data Valid Delay from SCL falling edge on
READ command
CL = 400pF
—
—
700
ns
2, 6
tSU;DAT
I2C data setup time
—
210
—
—
ns
7
THDDAT
I2C data hold time
0–400 kHz
2.0
—
—
ns
3, 6
TINT
Response time for INT output pin from change in
input condition (HPD, Receiver Sense, VSYNC
change, etc.).
RESET# =
HIGH
—
—
100
µs
—
FSCL
Frequency on master DDC SCL signal
—
40
70
100
kHz
4
FCSCL
Frequency on master CSCL signal
—
40
—
400
kHz
—
Notes:
1. Reset on RESET# signal can be LOW as the supply becomes stable (shown in Figure 4.5), or pulled LOW for at least TRESET (shown
in Figure 4.6).
2. All standard-mode (100 kHz) I2C timing requirements are guaranteed by design. These timings apply to the slave I2C port (pins
CSDA and CSCL) and to the master I2C port (pins DSDA and DSCL).
3. This minimum hold time is required by CSCL and CSDA signals as an I2C slave. The device does not include the 300 ns internal
delay required by the I2C Specification (Version 2.1, Table 5, note 2).
4. The master DDC block provides an SCL signal for the E-DDC bus. The HDMI Specification limits this to I2C Standard Mode or 100
kHz. Use of the Master DDC block does not require an active IDCK.
5. Not a Schmitt trigger.
6. Operation of I2C pins above 100 kHz is defined by LVTTL levels VIH, VIL, VOH, and VOL. For these levels, I2C speeds up to 400 kHz
(fast mode) are supported.
7. In default configuration, operation at 400 kHz does not meet the tSU;DAT data setup time required by the I2C Specification. For
advanced configuration information, refer to SiI-PR-1054 revision D or later.
Table 3.20. Audio Crystal Frequency
Symbol
Parameter
Conditions
Min
Typ
Max
Units
FXTAL
External Crystal Frequency
—
26
27
28.5
MHz
Note: Fxtal must be 27 MHz if the crystal oscillator (xclk) is used as the clock source for the Video Pattern Generator.
R
XTALVCC33
XTALIN
XTALOUT
27MHz
C2
3.3 V
C1
XTALGND
The values of C1, C2, and R
depend upon the
characteristics of the crystal.
Figure 3.2. Audio Crystal Schematic
Note: The XTALIN/XTALOUT pin pair must be driven with a clock in all applications.
SiI9573 and SiI9575 Port Processor
Data Sheet
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24 SiI-DS-1089-G
3.4.2. Audio Input Timing
Table 3.21. S/PDIF Input Port AC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
FS_SPDIF
Sample Rate
2 Channel
32
—
192
kHz
—
—
TSPCYC
S/PDIF Cycle Time
CL = 10 pF
—
—
1.0
UI
Figure 4.10
1
TSPDUTY
S/PDIF Duty Cycle
CL = 10 pF
90%
—
110%
UI
Figure 4.10
1
Note: Refer to the notes for Table 3.22.
Table 3.22. I2S Input Port AC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
FS_I2S
Sample Rate
—
32
—
192
kHz
—
—
TSCKCYC
I2S Cycle Time
CL = 10 pF
—
—
1.0
UI
Figure 4.9
1
TSCKDUTY
I2S Duty Cycle
CL = 10 pF
90%
—
110%
UI
Figure 4.9
—
TI2SSU
I2S Setup Time
CL = 10 pF
15
—
—
ns
Figure 4.9
2
TI2SHD
I2S Hold Time
CL = 10 pF
0
—
—
ns
Figure 4.9
2
Notes:
1. Proportional to unit time (UI) according to sample rate. Refer to the I2S or S/PDIF specifications.
2. Setup and hold minimum times are based on 13.388 MHz sampling, which is adapted from Figure 3 of the Philips I2S
Specification.
3.4.3. Audio Output Timing
Table 3.23. I2S Output Port AC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TTR
SCK Clock Period (TX)
CL = 10 pF
1.0
—
—
TTR
THC
SCK Clock HIGH Time
CL = 10 pF
0.35
—
—
TTR
TLC
SCK Clock LOW Time
CL = 10 pF
0.35
—
—
TTR
TSU
Setup Time, SCK to SD/WS
CL = 10 pF
0.4TTR – 5
—
—
ns
THD
Hold Time, SCK to SD/WS
CL = 10 pF
0.4TTR – 5
—
—
ns
TSCKDUTY
SCK Duty Cycle
CL = 10 pF
40
—
60
% TTR
TSCK2SD
SCK to SD or WS Delay
CL = 10 pF
–5.0
—
5.0
ns
Note: Refer to Figure 4.11 on page 29.
Table 3.24. S/PDIF Output Port AC Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TSPCYC
SPDIF Cycle Time
CL = 10 pF
—
1.0
—
UI1
FSPDIF
SPDIF Frequency
—
4.0
—
24.0
MHz
TSPDUTY
SPDIF Duty Cycle
CL = 10 pF
90.0
—
110.0
% TSPCYC
TMCLKCYC
MCLK Cycle Time
CL = 10 pF
20.0
—
250
ns
FMCLK
MCLK Frequency
CL = 10 pF
4.0
—
50.0
MHz
TMCLKDUTY
MCLK Duty Cycle
CL = 10 pF
45
—
65
% TMCLKCYC
Notes:
1. Proportional to unit time (UI), according to sample rate. Refer to the S/PDIF specification.
2. Refer to Figure 4.12 on page 29 and Figure 4.13 on page 29.
SiI9573 and SiI9575 Port Processor
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 25
3.5. Serial Flash SPI Interface AC Specifications
Table 3.25. Serial Flash AC Specifications
Symbol
Parameter
Min
Typ
Max
Unit
FSCLK
Clock Frequency
1.6875
—
27
MHz
TSCLKH
Clock HIGH Time
16
—
—
ns
TSCLKL
Clock LOW Time
16
—
—
ns
TSLCH
SS Active Setup Time
11
—
—
ns
TCHSH
SS Not Active Hold Time
11
—
—
ns
TDVCH
SDI Data Out Setup Time
6
—
—
ns
TCHDX
SDI Data Out Hold Time
6
—
—
ns
TCLQV
Clock LOW-to-SDO Data In Valid
—
—
16
ns
Note: Refer to Figure 4.14 on page 30.
SiI9573 and SiI9575 Port Processor
Data Sheet
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26 SiI-DS-1089-G
4. Timing Diagrams
4.1. Video Input Timing Diagrams
TCIP/TCIP12
50% 50% 50%
TDUTY /TDUTY12
Figure 4.1. IDCK Clock Duty Cycle
D[19:0], DE,
HSYNC, VSYNC 50 % 50 %
IDCK
TSIDR THIDR
50 % 50 %
Signals may change only in the unshaded portion of the waveform, to meet both the
minimum setup and minimum hold time specifications.
no change allowed
TCIP
Figure 4.2. Control and Data Single-Edge Setup and Hold Times—EDGE = 1
D[19:0], DE,
HSYNC, VSYNC 50 % 50 %
IDCK
TSIDF THIDF
50 % 50 %
Signals may change only in the unshaded portion of the waveform, to meet both the
minimum setup and minimum hold time specifications.
no change allowed
Figure 4.3. Control and Data Single-Edge Setup and Hold Times—EDGE = 0
SiI9573 and SiI9575 Port Processor
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 27
D[11:0], DE,
HSYNC,VSYNC 50 % 50 %
IDCK
TSIDD THIDD
50 % 50 %
TSIDD THIDD
50 %
no change
allowed no change
allowed
Signals may change only in the unshaded portion of the waveform, to meet both the
minimum setup and minimum hold time specifications.
TCIP12
Figure 4.4. Control and Data Dual-Edge Setup and Hold Times
4.2. Reset Timing Diagrams
VCC must be stable between the limits shown in the Normal Operating Conditions section on page 18 for TRESET before
RESET# goes HIGH, as shown in Figure 4.5. Before accessing registers, RESET# must be pulled LOW for TRESET. This can be
done by holding RESET# LOW until TRESET after stable power, or by pulling RESET# LOW from a HIGH state for at least
TRESET, as shown in Figure 4.6. Note: VCC can be one of RnPPWR5V or SBVCC5V.
RESET#
VCCmin
VCCmax
TRESET
VCC
Figure 4.5. Conditions for Use of RESET#
RESET#
TRESET
Figure 4.6. RESET# Minimum Timing
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28 SiI-DS-1089-G
4.3. I2C Timing Diagrams
CSCL, DSCL
TI2CDVD
CSDA, DSDA
Figure 4.7. I2C Data Valid Delay (Driving Read Cycle Data)
CSCL, DSCL tSU:DAT
CSDA, DSDA
Figure 4.8. I2C Data Setup Time
4.4. Digital Audio Input Timing
SD[0:3], WS 50 % 50 %
SCK
TI2SSU TI2SHD
50 % 50 %
no change allowed
TSCKDUTY
TSCKCYC
Figure 4.9. I2S Input Timing
SPDIF
TSPDUTY
50%
TSPCYC
Figure 4.10. S/PDIF Input Timing
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 29
4.5. Digital Audio Output Timing
WS
SD
SCK
TTR
TSCKDUTY
TSU THD
TSCK2SD {Max} TSCK2SD {Min}
Data ValidData Valid Data Valid
Figure 4.11. I2S Output Timing
SPDIF
TSPDUTY
50%
TSPCYC
Figure 4.12. S/PDIF Output Timing
MCLK
TMCLKCYC
TMCLKDUTY
50%50%
Figure 4.13. MCLK Timing
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30 SiI-DS-1089-G
TSLCH
TDVCH TCHDX
SS
SCLK
SDI
SS
SCLK
SDO
TCLQV
TCHSH
SS and SDI Timing
SDO Timing
TSCLKH
TSCLKL
Figure 4.14. SPI Flash Memory Timing
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 31
5. Pin Diagram and Pin Descriptions
5.1. Pin Diagram
Figure 5.1 shows the pin assignments of the SiI957n port processor. Individual pin functions are described in the Pin
Descriptions section on the next page. The package is a 20 × 20 × 0.4 mm 176-pin TQFP with an ePad, which must be
connected to ground.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
99
98
97
96
95
94
93
92
91
90
89
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
D15
D16
D17
D18
D19
DE
VSYNC
HSYNC
IDCK
R0XC–
R0XC+
R0X0–
R0X0+
R0X1–
R0X1+
R0X2–
R0X2+
R1XC–
R1XC+
R1X0–
R1X0+
R1X1–
R1X1+
R1X2–
R1X2+
R2XC–
R2XC+
R2X0–
R2X0+
R2X1–
DSCL3
CBUS_HPD3
R3PWR5V
DSCL4
DSCL5
SBVCC5
VCC33OUT
TX_HPD0
TXDSDA0
TXDSCL0
TXDSDA1
TXDSCL1
RSVDL
SS/GPIO2
SCLK/GPIO3
SDO/GPIO4
SDI/GPIO5
XTALIN
XTALOUT
XTALVCC33
XTALGND
APLL13
Top View
SiI957n
33
34
35
36
37
38
39
40
41
42
43
44
R2X1+
R2X2–
R2X2+
R4X0–
R4X0+
AVDD33
R3XC–
R3XC+
R3X0–
R3X0+
R4XC–
R4XC+
77 78 79 80 81 82 83 84 85 86 87 88
96
132
131
130
129
128
127
126
125
124
123
122
121
AVDD33
T1X2+
T1X2–
T1X1+
T1X1–
T1X0+
T1X0–
T1XC+
T1XC–
TPVDD13
CVCC13
TDVDD13
144 143 142 141 140 139 138 137 136 135 134 133
100
CBUS_HPD4
R4PWR5V
CBUS_HPD5
TX_HPD1
SD0_0/DL0
SD0_1/DR1/GPIO6
SD0_3/DR2/GPIO8
SD0_2/DL1/GPIO7
WS0_OUT/DR0
T0X2+
T0X2–
T0X1+
T0X1–
T0X0+
T0X0–
T0XC+
T0XC–
ARC0
ARC1
MCLK
SCK0/DDCK
SPDIF0_OUT/DL2
WS0_IN/GPIO11
SD0_IN/SPDIF0_IN
SCK1_IN/SCK1_OUT
WS1_IN/WS1_OUT
SD1_IN/SD1_OUT/SPDIF1_IN/SPDIF1_OUT
MUTEOUT/GPIO9
D14
D13
D12
D11
D10
D9
D1
D2
D3
D4
D5
D6
D7
D0
D8
R3X2–
R3X2+
R3X1–
R3X1+
DSDA0
DSDA1
DSDA2
DSDA3
DSDA4
DSDA5
DSDA6(VGA)
DSCL2
DSCL0
DSCL1
DSCL6(VGA)
R2PWR5V
R5PWR5V
R1PWR5V
R0PWR5V
CBUS_HPD0
CBUS_HPD1
CBUS_HPD2
CSCL
CSDA
RESET#
TPWR_CI2CA
INT
CEC_A0
CEC_A1
RSVDL
MHL_CD0/GPIO0
MHL_CD1/GPIO1
TDVDD13
TPVDD13
CVCC13
CVCC13
CVCC13
CVCC13
R4X1–
R4X1+
R4X2–
R4X2+
R5X0–
R5X0+
R5XC+
R5X1–
R5X1+
R5X2–
R5X2+
R5XC–
AVDD33
IOVCC33
IOVCC33
AVDD13
AVDD13
AVDD13
SCK0_IN/GPIO10
ePad (GND)
Figure 5.1. Pin Diagram (Top View)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32 SiI-DS-1089-G
5.2. Pin Descriptions
5.2.1. HDMI Receiver and MHL Port Pins
Name
Pin
Type
Dir
Description
R0X0+
13
TMDS
Input
HDMI Receiver Port 0 TMDS Input Data Pairs.
R0X0–
12
R0X1+
15
R0X1–
14
R0X2+
17
R0X2–
16
R0XC+
11
TMDS
Input
HDMI Receiver Port 0 TMDS Input Clock Pair.
R0XC–
10
R1X0+
23
TMDS
Input
HDMI Receiver Port 1TMDS Input Data Pairs.
R1X0–
22
R1X1+
25
R1X1–
24
R1X2+
27
R1X2–
26
R1XC+
21
TMDS
Input
HDMI Receiver Port 1 TMDS Input Clock Pair.
R1XC–
20
R2X0+
31
TMDS
Input
HDMI Receiver Port 2 TMDS Input Data Pairs.
R2X0–
30
R2X1+
33
R2X1–
32
R2X2+
35
R2X2–
34
R2XC+
29
TMDS
Input
HDMI Receiver Port 2 TMDS Input Clock Pair.
R2XC–
28
R3X0+
42
TMDS
Input
HDMI Receiver Port 3 TMDS Input Data Pairs.
R3X0–
41
R3X1+
44
R3X1–
43
R3X2+
46
R3X2–
45
R3XC+
40
TMDS
Input
HDMI Receiver Port 3 TMDS Input Clock Pair.
R3XC–
39
R4X0+
50
TMDS
Input
HDMI Receiver Port 4 TMDS Input Data Pairs.
R4X0–
49
R4X1+
52
R4X1–
51
R4X2+
54
R4X2–
53
R4XC+
48
TMDS
Input
HDMI Receiver Port 4 TMDS Input Clock Pair.
R4XC–
47
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 33
5.2.2. HDMI Receiver and MHL Port Pins (continued)
Name
Pin
Type
Dir
Description
R5X0+
60
TMDS
Input
HDMI Receiver Port 5 TMDS Input Data Pairs.
R5X0–
59
R5X1+
62
R5X1–
61
R5X2+
64
R5X2–
63
R5XC+
58
TMDS
Input
HDMI Receiver Port 5 TMDS Input Clock Pair.
R5XC–
57
Note: For Port n and Port m that have been configured as MHL inputs, the RnX0+ and RnX0– pin pair and RmX0+ and RmX0– pin pair
carry the respective MHL signals.
5.2.3. HDMI Transmitter Port Pins
Name
Pin
Type
Dir
Description
T0X0+
155
TMDS
Output
HDMI Transmitter Port 0 TMDS Output Data Pairs.
Main HDMI transmitter output port TMDS data pairs.
T0X0–
154
T0X1+
157
T0X1–
156
T0X2+
159
T0X2–
158
T0XC+
153
TMDS
Output
HDMI Transmitter Port 0 TMDS Output Clock Pair.
Main HDMI transmitter output port TMDS clock pair.
T0XC–
152
T1X0+
145
TMDS
Output
HDMI Transmitter Port 1 TMDS Output Data Pairs.
Sub-HDMI transmitter output port TMDS data pairs.
T1X0–
144
T1X1+
147
T1X1–
146
T1X2+
149
T1X2–
148
T1XC+
143
TMDS
Output
HDMI Transmitter Port 1 TMDS Output Clock Pair.
Sub-HDMI transmitter output port TMDS clock pair.
T1XC–
142
5.2.4. Audio Return Channel Pins
Name
Pin
Type
Dir
Description
ARC0
137
Analog
Input/
Output
Audio Return Channels 0 and 1.
These pins are used to transmit or receive an IEC60958-1 audio stream. In ARC
transmitter mode, received on the SPDIFn_IN input pin, this pin transmits an
S/PDIF signal to an ARC receiver-capable source (such as HTiB) or a repeater
(such as AVR) devices, using single-mode ARC.
In ARC receiver mode, transmitted through the SPDIFn_OUT pin, this pin
receives an S/PDIF signal from an ARC transmitter-capable sink (such as DTV)
device, using single-mode ARC. In combination with external components,
common-mode ARC can be received.
Each channel can either be an ARC input or an ARC output at one time.
ARC1
138
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34 SiI-DS-1089-G
5.2.5. Audio Pins
Name
Pin
Type
Dir
Description
MCLK
125
LVTTL
Output
Master Clock Output
SCK0/
DDCK
122
LVTTL
Output
Main Port I2S Serial Clock Output/DSD Clock Output.
WS0_OUT/
DR0
121
LVTTL
Output
Main Port I2S Word Select Output/DSD Data Right Bit 0.
SD0_0/
DL0
124
LVTTL
Output
Main Port I2S Serial Data 0 Output/DSD Data Left Bit 0 Output.
SD0_1/DR1/
GPIO6
126
LVTTL
Output
Main Port I2S Serial Data 1 Output/DSD Data Right Bit 1 Output/
Programmable GPIO 6.
SD0_2/DL1/
GPIO7
127
LVTTL
Output
Main Port I2S Serial Data 2 Output/DSD Data Left Bit 1 Output/ Programmable
GPIO 7.
SD0_3/DR2/
GPIO8
128
LVTTL
Output
Main Port I2S Serial Data 3 Output/DSD Data Right Bit 2/ Programmable GPIO
8.
SPDIF0_OUT/
DL2
130
Analog/
LVTTL
Output
Main Port S/PDIF Output/DSD Data Left Bit 2.
SCK0_IN/
GPIO10
132
LVTTL
Input/
Output
Main Port I2S Serial Clock Input/Programmable GPIO 10.
WS0_IN/
GPIO11
131
LVTTL
Input/
Output
Main Port I2S Word Select Input/Programmable GPIO 11.
SD0_IN/
SPDIF0_IN
133
Analog/
LVTTL
Input
Main Port I2S Serial Data Input/S/PDIF Input.
SCK1_IN/
SCK1_OUT
134
LVTTL
Input/
Output
Subport I2S Serial Clock1 Input/I2S Serial bit Clock Output.
WS1_IN/
WS1_OUT
135
LVTTL
Input/
Output
Subport I2S Word Select Input/I2S Word Select Output.
SD1_IN/
SD1_OUT/
SPDIF1_IN/
SPDIF1_OUT
136
LVTTL
Input/
Output
Subport I2S Serial Data Input/I2S Serial Data1 Output/ SPDIF Input//SPDIF
Output.
MUTEOUT/
GPIO9
129
LVTTL
Input/
Output
Mute Audio Output/Programmable GPIO 9.
5.2.6. Crystal Pins
Name
Pin
Type
Dir
Description
XTALOUT
113
LVTTL
5 V tolerant
Output
Crystal clock output.
XTALIN
114
LVTTL
5 V tolerant
Input
Crystal clock input.
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 35
5.2.7. SPI Interface Pins
Name
Pin
Type
Dir
Description
SS/
GPIO2
117
LVTTL
Input/
Output
SPI Slave Select/Programmable GPIO 2.
SCLK/
GPIO3
118
LVTTL
Schmitt
Open-drain\
Input/
Output
SPI Clock/Programmable GPIO 3.
SDO/
GPIO4
119
LVTTL
Schmitt
Open-drain
Input/
Output
SPI Slave Data Output/Master Data Input/Programmable GPIO 4.
SDI/
GPIO5
120
LVTTL
Schmitt
Open-drain
Input/
Output
SPI Slave Data Input/Master Data Output/Programmable GPIO 5.
5.2.8. Parallel Video Bus
Name
Pin
Type
Dir
Description
D0
161
LVTTL
Input
Video Data Inputs.
The video data inputs can be configured to support a wide variety of input
formats, including multiple RGB and YCbCr bus formats, using register
settings.
D1
162
D2
163
D3
164
D4
165
D5
166
D6
167
D7
168
D8
169
D9
170
D10
171
D11
174
D12
175
D13
176
D14
1
D15
2
D16
3
D17
4
D18
5
D19
6
DE
7
LVTTL
Input
Data Enable Input
HSYNC
9
LVTTL
Input
Horizontal Sync Input
VSYNC
8
LVTTL
Input
Vertical Sync Input
IDCK
172
LVTTL
Input
Input Data Clock
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36 SiI-DS-1089-G
5.2.9. DDC I2C Pins
Name
Pin
Type
Dir
Description
DSDA0
76
LVTTL
Schmitt
Open-drain
5 V tolerant
Input/
Output
DDC I2C Data for respective HDMI receiver port.
These signals are true open drain, and do not pull to ground when power is
not applied to the device. These pins require an external pull-up resistor.
DSDA1
80
DSDA2
84
DSDA3
88
DSDA4
92
DSDA5
97
DSDA6(VGA)
73
LVTTL
Schmitt
Open-drain
5 V tolerant
Input/
Output
DDC I2C data for VGA port.
This signal is true open drain, and does not pull to ground when power is not
applied to the device. This pin requires an external pull-up resistor.
DSCL0
77
LVTTL
Schmitt
Open-drain
5 V tolerant
Input
DDC I2C Clock for respective HDMI receiver port.
These signals are true open drain, and do not pull to ground when power is
not applied to the device. These pins require an external pull-up resistor.
DSCL1
81
DSCL2
85
DSCL3
89
DSCL4
93
DSCL5
98
DSCL6(VGA)
74
LVTTL
Schmitt
Open-drain
5 V tolerant
Input
DDC I2C Clock for VGA port.
This signal is true open drain, and does not pull to ground when power is not
applied to the device. This pin requires an external pull-up resistor.
TXDSDA0
106
LVTTL
Schmitt
Open-drain
5 V tolerant
Input/
Output
DDC Master I2C Data for HDMI transmitter Port 0.
This signal is true open drain, and does not pull to ground when power is not
applied to the device. This pin requires an external pull-up resistor.
TXDSDA1
109
LVTTL
Schmitt
Open-drain
5 V tolerant
Input/
Output
DDC Master I2C Data for HDMI transmitter Port 1.
This signal is true open drain, and does not pull to ground when power is not
applied to the device. This pin requires an external pull-up resistor.
TXDSCL0
107
LVTTL
Schmitt
Open-drain
5 V tolerant
Input/
Output
DDC Master I2C Clock for HDMI transmitter Port 0.
This signal is true open drain, and does not pull to ground when power is not
applied to the device. This pin requires an external pull-up resistor.
TXDSCL1
110
LVTTL
Schmitt
Open-drain
5 V tolerant
Input/
Output
DDC Master I2C Clock for HDMI transmitter Port 1
This signal is true open drain, and does not pull to ground when power is not
applied to the device. This pin requires an external pull-up resistor.
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 37
5.2.10. Control Pins
Name
Pin
Type
Dir
Description
CSCL
66
Schmitt
Open-drain
5 V tolerant
Input
Local Configuration/Status I2C Clock.
Chip configuration/status is accessed via this I2C port. This pin is true open
drain, so it does not pull to ground if power is not applied. See Figure 2.2 on
page 10.
CSDA
67
LVTTL
Schmitt
Open-drain
5 V tolerant
Input/
Output
Local Configuration/Status I2C Data.
Chip configuration/status is accessed via this I2C port. This pin is true open
drain, so it does not pull to ground if power is not applied. See Figure 2.2 on
page 10.
RESET#
69
Schmitt
Input
External reset.
Active LOW. Must be pulled up to VCC33OUT. When main power is not
provided to the system, the microcontroller must present a high impedance of
at least 100 kΩ to RESET#. If this condition is not met, a circuit to block the
leakage from VCC33OUT to the microcontroller GPIO may be required.
5.2.11. System Switching Pins
Name
Pin
Type
Dir
Description
R0PWR5V
79
Power
Input
5 V Port detection input for respective HDMI receiver port.
Connect to 5 V signal from HDMI input connector. These pins require a 10 Ω
series resistor, a 5.1 kΩ pull down resistor, and at least a 1 µF capacitor to
ground.
R1PWR5V
83
R2PWR5V
87
R3PWR5V
91
R4PWR5V
95
R5PWR5V
100
CBUS_HPD0
78
LVTTL
1.5 mA
5 V tolerant
Analog
Input/
Output
Hot Plug Detect output for the respective HDMI receiver port.
In MHL mode, these pins serve as the respective CTRL bus.
CBUS_HPD1
82
CBUS_HPD2
86
CBUS_HPD3
90
CBUS_HPD4
94
CBUS_HPD5
99
TX_HPD0
105
LVTTL
5 V tolerant
Input
Hot Plug Detect Input for HDMI transmitter Port 0.
TX_HPD1
108
LVTTL
5 V tolerant
Input
Hot Plug Detect Input for HDMI transmitter Port 1.
MHL_CD0/
GPIO0
103
LVTTL
Input/
Output
MHL Cable Detect 0/Programmable GPIO 0.
MHL_CD0 is 5 V tolerant if SBVCC5 or one of the R[0-5]PWR5V is applied to
the device. If none of these power supplies are applied, then MHL_CD0 is 3.3
V tolerant.
MHL_CD1/
GPIO1
104
LVTTL
Input/
Output
MHL Cable Detect 1/Programmable GPIO 1.
MHL_CD1 is 5 V tolerant if SBVCC5 or one of the R[0-5]PWR5V is applied to
the device. If none of these power supplies are applied, then MHL_CD1 is 3.3
V tolerant.
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38 SiI-DS-1089-G
5.2.12. Configuration Pins
Name
Pin
Type
Dir
Description
TPWR_CI2CA
70
LVTTL
Input/
Output
I2C Slave Address Input/Transmit Power Sense Output.
During power-on-reset (POR), this pin is used as an input to latch the I2C sub-
address. The level on this pin is latched when the POR transitions from the
asserted state to the de-asserted state.
After completion of POR, this pin is used as the TPWR output. A register
setting can change this pin to show if the active port is receiving a TMDS clock.
INT
68
Schmitt
Open-drain
8 mA
3.3 V tolerant
Output
Interrupt Output.
This is an open-drain output and requires an external pull-up resistor. This
output can be safely pulled up to 3.3 V with no power (no SBVCC5,
no R[0-5]PWR5V, no 3.3 V, and no 1.3 V) applied to the device.
5.2.13. CEC Pins
Name
Pin
Type
Dir
Description
CEC_A0
72
CEC
Compliant
5 V tolerant,
Schmitt
triggered,
LVTTL
Input/
Output
Primary CEC I/O used for interfacing to CEC devices This signal is electrically
compliant with the CEC specification.
As an input, this pin acts as an LVTTL Schmitt triggered input and is 5 V
tolerant. As an output, the pin acts as an NMOS driver with resistive pull-up.
This pin has an internal pull-up resistor.
This signal should be connected to the CEC signal of all HDMI input and output
ports if the system supports just one CEC line.
OR
In a system designed to have separate CEC connectivity for the HDMI input
and output ports, this signal should be connected to the CEC signal of all the
input ports supported in the system.
This signal and CEC_A0 each connect to a separate CEC controller within the
port processor and are independent of each other.
CEC_A1
71
CEC
Compliant
5 V tolerant,
Schmitt
triggered,
LVTTL
Input/
Output
Secondary CEC I/O used for interfacing to CEC devices.
This signal is electrically compliant with the CEC specification. As an input, this
pin acts as an LVTTL Schmitt triggered input and is 5 V tolerant. As an output,
the pin acts as an NMOS driver with resistive pull-up. This pin has an internal
pull-up resistor.
This is an optional CEC signal provided for system designers who want to
implement a system with two independent CEC lines, such as a system that
supports a separate CEC line for the HDMI input ports and the HDMI output
ports. In the example of a DTV that provides a second HDMI output using the
SiI957n port processor; this signal can be connected to the CEC signal of the
output port while the CEC_A1 signal is connected to the CEC signal of the
input ports.
This signal and CEC_A1 each connect to a separate CEC controller within the
port processor and are independent of each other.
SiI9573 and SiI9575 Port Processor
Data Sheet
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 39
5.2.14. Power and Ground Pins
Name
Pin
Type
Description
Supply
AVDD33
19, 38, 56
Power
TMDS Core VDD.
AVDD33 should be isolated from other system supplies to
prevent leakage from the source device through the TMDS
input pins. AVDD33 should not be used to power other system
components that can be adversely affected by such leakage.
3.3 V
IOVCC33
123, 173
Power
I/O VCC.
3.3 V
SBVCC5
101
Power
Local Power from system.
This pin requires a 10 Ω series resistor.
5.0 V
AVDD13
18, 36, 55
Power
TMDS Receiver Core VDD.
1.3 V
CVCC13
37, 65, 116, 139, 160
Power
Digital Core VCC.
1.3 V
APLL13
111
Power
PLL Analog VCC.
1.3 V
VCC33OUT
102
Power
Internal regulator 3.3 V output.
VCC33OUT should not be used as a power source to provide
power to other external circuits
3.3 V
TPVDD13
140, 150
Power
Analog Power for TMDS Tx core.
1.3 V
TDVDD13
141, 151
Power
Digital Power for TMDS Tx core.
1.3 V
XTALVCC33
112
Power
PLL crystal oscillator power.
3.3 V
XTALGND
115
Ground
PLL crystal oscillator ground.
GND
GND
ePad
Ground
The ePad must be soldered to ground, as this is the only
ground connection for the device.
GND
5.2.15. Reserved Pin
Name
Pin
Type
Description
RSVDL
75
Reserved
Reserved, must be tied to ground.
RSVDL
96
Reserved
Reserved, must be tied to ground through a 4.7 kΩ pull-down resistor.
SiI9573 and SiI9575 Port Processor
Data Sheet
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
40 SiI-DS-1089-G
6. Feature Information
6.1. Standby and HDMI Port Power Supplies
The port processor has a 5-volt standby power supply pin (SBVCC5V) that can be used to supply power to the EDID and
CEC portions of the device when all other power supplies are turned off. This arrangement results in a low-power mode,
but allows the EDID to be readable and the CEC controllers to be operational. Table 6.1 summarizes the power modes
available in the SiI957n port processor. Figure 6.1 shows a block diagram of the standby power supply sources and the
always-on power island.
Table 6.1. Description of Power Modes
Power Mode
Description
SBVCC5
RnPWR5V
AVDD33
AVDD13
Power-on Mode
All power supplies to the SiI957n chip are on. All
functions are available. The standby power
supply is 5 V.
5 V
NA
3.3 V
1.3 V
Standby Power mode
The always-on power domain is on, supplied
from the internal power MUX; all other supplies
are off. The standby power supply is 5 V. In this
mode, EDID and CEC are functional, but video
and audio processing is not performed and all
outputs are off.
5 V
NA
Off
Off
HDMI Port-only Power
Power is off to the device. HDMI +5 V from the
HDMI cable is the only power source. For
example, if the TV is unplugged from AC wall
outlet, the EDID and CEC are functional in this
mode.
Off
5 V on
any
input
Off
Off
Note: All other supplies are on in the power-on mode and off in all other modes.
RnPWR5V
CEC
EDID
RAM
SBVCC5
Always-on
Power Island
Power
Multiplexer Video and
Audio
Processing
Blocks
ARC
ARC Block
HDMI
Connectors
n = 0 to 5
AVDD33
CVCC13
AVDD13
TDVDD13
SiI957n
Port Processor
TPVDD13
Figure 6.1. Standby Power Supply Diagram
SiI9573 and SiI9575 Port Processor
Data Sheet
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 41
If all power is off to the device, such as if the AVR or TV is unplugged from the AC electrical outlet, the EDID can still be
read from the source by using power from the HDMI connector +5 V signal. In this case, the internal power MUX
automatically switches to the HDMI connector power for powering the always-on logic. In this mode, only the EDID and
CEC blocks are functional; all other functions of the device are in power-off mode. No damage will occur to the device
in this mode.
6.2. InstaPort
The SiI957n port processor supports the InstaPort™ HDCP preauthentication feature, which hides the HDCP
authentication time from the user. HDCP authentication is started on an upstream (input) port immediately after a
source device is connected, regardless of whether the port is currently selected for output to the downstream sink
device. All nonselected ports are HDCP authenticated in this manner and when HDCP is authenticated, it is maintained
in the background. When a nonselected port is then selected, the authenticated content is immediately available
because it does not have to reauthenticate HDCP. This InstaPort HDCP preauthentication feature reduces port switching
times to less than one second.
6.3. InstaPrevue
The SiI957n device incorporates the InstaPrevue feature, which provides periodically updated picture-in-picture
previews of each connected source device. The contents of each preauthenticated TMDS source device not being
viewed can be displayed as a small subwindow overlaid onto the main video currently being viewed. With this feature,
DTV and AVR manufacturers can provide the end-user with a content based, rather than a text based user interface for
changing or selecting among various Blu-ray disc players, set-top boxes, DVD players, game consoles, or other
HDMI/DVI/MHL connected sources.
InstaPrevue operates in one of three modes:
The All Preview mode displays one to five sub-windows, selected by the user, regardless of whether a source device
is connected or not. A subwindow with a manufacturer defined color is displayed for an unconnected source device.
The Active mode displays only the subwindows for which there is a connected, active, and authenticated source
device.
The Selected mode displays a single subwindow for a connected source device selected by the user and is intended
as a Picture-In-Picture (PIP) type preview.
InstaPrevue can be displayed on both Tx0 and Tx1 outputs of the SiI957n device. On the SiI9575 device, InstaPrevue
does not operate in ViaPort Matrix Switch mode.
The supported combinations of main video display and InstaPrevue window formats are shown in the following table.
InstaPrevue is compatible with RGB, YC4:4:4, and YC4:2:2 color formats.
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42 SiI-DS-1089-G
Table 6.2. Supported InstaPrevue Window Formats
Main Video Display Format
InstaPrevue Window Format
Supported?
All supported 2D Resolutions
All supported 2D Resolutions except 4K×2K
Yes
720p and 1080p 3D Frame Packing
Yes
480p and 1080i 3D Frame Packing
No
3D Side-by-Side (Half)
No
3D Side-by-Side (Full)
No
3D Top & Bottom
No
720p and 1080p 3D Frame Packing
All supported 2D Resolutions except 4K×2K
Yes
720p and 1080p 3D Frame Packing
Yes
480p and 1080i 3D Frame Packing
No
3D Side-by-Side (Half)
No
3D Top & Bottom
No
480p and 1080i 3D Frame Packing
All Formats
No
3D Top & Bottom
3D Side-by-Side (Half)
3D Side-by-Side (Full)
4K×2K
All Formats
No
6.4. Support for UltraHD resolution at 50P/60P frames per second
The SiI957n device support 4K × 2K 50P and 4K × 2K 60p frame per second when pixel format is YCbCr 4:2:0 with TMDS
clock frequency of 300 MHz. When configuring this mode, On-screen Display (OSD) and InstaPrevue must be disabled
by the Firmware.
6.5. ViaPort Matrix Switch
The ViaPort Matrix Switch feature is available only on the SiI9575 device. When enabled, a different input source is sent
to each of the two HDMI transmitter ports. The available input sources for the ViaPort Matrix Switch are any one of six
TMDS input ports, an external parallel video input port, and an internal video pattern generator. This feature allows the
system designer to implement a two zone system in an AVR or similar device.
6.6. MHL Receiver
The SiI957n port processor supports the Mobile High-definition Link (MHL) as a sink device on two of the six RX receiver
ports selected at the time of manufacture. MHL is a high-speed multimedia data transfer protocol intended for use
between mobile and display devices. The SiI957n device supports HDMI and MHL modes on the two selected RX
receiver ports simultaneously. When an HDMI source is connected, the receiver port is configured as an HDMI port.
When an MHL source is connected, an MHL cable detect sense signal from the cable is asserted and sent to the SiI957n
device and also to the host microcontroller as an interrupt to configure the receiver port as an MHL port and to initiate
the CBUS discovery process.
MHL carries video, audio, auxiliary, control data, and power across a cable consisting of five conductors. One connection
is for a dedicated ground which is used as the 0V reference for the signals on the remaining four connections. Two other
conductors form a single channel TMDS differential signal pair used to send video, audio and auxiliary data from the
source device to the sink device. On the SiI957n device, the MHL TMDS channel differential signal pair pins are shared
with the RX0+ and RX0– pins of the HDMI TMDS channel differential signal pair. Another connection is for the MHL
Control Bus (CBUS). The CBUS carries control information that provides configuration and status exchanges between the
source and the sink devices. CBUS is a software/hardware protocol that supports four types of packet transfers: Display
Data Control (DDC), Vendor Specific, MHL Sideband Channel (MSC), and a reserved type. EDID data can be transferred
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 43
between the source and sink devices using the CBUS. On the SiI957n device, the CBUS signal pin is shared with the HPD
signal pin. Another connection is used as the VBUS which provides +5V power to charge the connected MHL source
device. An external power switch is typically used on the system board to supply the +5 V power to the VBUS. Enabling
the switch provides the +5 V power on the VBUS when the MHL source is connected and the MHL cable detect signal is
asserted.
6.7. 3D Video Formats on Main Display
The SiI957n port processor supports the pass-through of 3D video modes described in the HDMI 1.4a Specification. All
modes support RGB 4:4:4, YCbCr 4:4:4, and YCbCr 4:2:2 color formats and 8-, 10-, and 12-bit data-width per color
component. Table 6.3 shows only the maximum possible resolution with a given frame rate; for example, Side-by-Side
(Half) mode is defined for 1080p @ 60 Hz, which implies that 720p, 60 Hz and 480p @ 60 Hz are also supported.
Furthermore, a frame rate of 24 Hz also means that a frame rate of 23.98 Hz is supported and a frame rate of 60 Hz also
means a frame rate of 59.94 Hz is supported. The input pixel clock changes accordingly.
The SiI957n device supports pass-through of the HDMI Vendor Specific InfoFrame, which carries 3D information to the
receiver. It also supports extraction of the HDMI Vendor Specific InfoFrame, which allows the 3D information contained
in the InfoFrame to be passed to the host system over the I2C port.
Table 6.3. Supported 3D Video Formats
3D Format
Extended Definition
Resolution
Frame Rate (Hz)
Input Pixel Clock (MHz)
Frame Packing
—
1080p
50/60
297
Side-by-Side
Full
Line Alternative
—
L + Depth
—
Frame Packing
—
1080p
24/30
148.5
720p/1080i
50/60
Side-by-Side
Full
1080p
24/30
720p/1080i
50/60
Half
1080p
50/60
Top & Bottom
—
1080p
50/60
1080p
24/30
74.25
720p/1080i
50/60
Line Alternative
—
1080p
24/30
148.5
720p/1080i
50/60
Field Alternative
—
1080i
50/60
L + Depth
—
1080p
24/30
6.8. VS Insertion
The SiI957n device features logic that can be used to assist the downstream SoC in processing 3D video for display. It
can monitor the 3D video stream and insert a VS pulse in the VS signal during the Active space period for demarcating
the L and R video frames. Figure 6.2 on the next page shows the VS insertion mode. The front porch, pulse width, back
porch, and polarity of the inserted VS signal can be individually set.
SiI9573 and SiI9575 Port Processor
Data Sheet
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44 SiI-DS-1089-G
VS
HS
Vact_video Vact_space Vact_video
Original 3D Stream
VS
HS
Vact_video Vsync Vact_video
Modified 3D Stream
Vfront Vback
Figure 6.2. VS Insertion in Active Space
6.9. 3D L/R and Active Space Indicators Output on GPIO Pins
The SiI957n device can also monitor the 3D video stream and output L, R and Active Space indicators on GPIO pins for
both the main pipe and the subpipe. The main pipe GPIO pins are shared with the main pipe I2S audio extraction pins
and the subpipe GPIO pins are shared with the SPI interface pins as shown in Table 6.4.
Table 6.4. L/R and Active Space Indicator Mapping to GPIO Pins
Pin
Name
Primary Function
Secondary Function
118
SCLK/GPIO3
SPI SCLK
SP_3D_R_FLAG
119
SDO/GPIO4
SPI SDO
SP_3D_V_FLAG
120
SDI/GPIO5
SPI SDI
SP_3D_L_FLAG
126
SD0_1/DR1/GPIO6
Audio Out I2S/DSD
MP_3D_R_FLAG
127
SD0_2/DL1/GPIO7
Audio Out I2S/DSD
MP_3D_V_FLAG
128
SD0_3/DR2/GPIO8
Audio Out I2S/DSD
MP_3D_L_FLAG
The main pipe I2S audio extraction must be disabled when the main pipe 3D indicators are output on the respective
GPIO pins. The SPI interface to the external Flash memory cannot be used when the subpipe 3D indicators are output
on the respective GPIO pins. Figure 6.3 shows the 3D L, R and Active Space indicators output on the respective GPIO
pins. 3D indicators are supported only for 720p frame-packed, and 1080p frame-packed video modes.
SiI9573 and SiI9575 Port Processor
Data Sheet
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 45
L
R
Active video
Active video
Active space
H
V
GPIO6/GPIO3
Delay
Delay
Delay
3D Frame Packing Video
Single register
controls delay for
all three markers
GPIO7/GPIO4
GPIO8/GPIO5
Figure 6.3. L/R and Active Space Indicators Output on GPIO Pins
6.10.Parallel Video Input Data Bus Mapping
6.10.1. Common Video Input Formats
Table 6.5. Video Input Formats
Color
Space
Video
Format
Clock
Mode
Bus
Width/
Color
Depth
SYNC4
Input Clock (MHz)
Notes
Page
480i 5
VGA/
480p
576i
576p
XGA
720p
1080i
SXGA
1080p
UXGA
RGB
4:4:4
1x, dual
12/8
Sep
27
25/27
27
27
65
74.25
74.25
—
—
—
1
46
YCbCr
4:4:4
1x, dual
12/8
Sep
27
25/27
27
27
65
74.25
74.25
—
—
—
1
46
4:2:2
1x, single
16/8
20/10
Sep
27
25/27
27
27
65
74.25
74.25
108
148.5
162
2
48
Emb
27
25/27
27
27
65
74.25
74.25
108
148.5
162
2, 3
49
2x, single/
YC Mux
8/8
10/10
12/12
Sep
—
50/54
54
54
130
148.5
148.5
—
—
—
2
52
Emb
—
50/54
54
54
130
148.5
148.5
—
—
—
2, 3
56
1x, dual/
YC Mux
8/8
10/10
12/12
Sep
27
25/27
27
27
65
74.25
74.25
108
148.5
162
1
—
Emb
27
25/27
27
27
65
74.25
74.25
108
148.5
162
1, 3
—
Notes:
1. Falling or rising edge latched first is programmable.
2. Latching on falling or rising edge is programmable.
3. If embedded syncs are provided, DE is generated internally from SAV/EAV sequences. Embedded syncs use
ITU-R BT 656 SAV/EAV sequences of FF, 00, 00, XY.
4. Sep = separate sync; Emb = embedded sync.
5. 480i must be provided at 27 MHz, using pixel replication, to be transmitted across the HDMI link.
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
46 SiI-DS-1089-G
6.10.2. RGB and YCbCr 4:4:4 Formats Dual Clock Edge
The input clock runs at the pixel rate and a complete definition of each pixel is received on each input clock cycle. One
clock edge latches in half the pixel data. The opposite clock edge latches in the remaining half of the pixel data on the
same pins. The same timing format is used for RGB and YCbCr 4:4:4. Each pair of columns in Table 6.6 shows the first
pixel of n + 1 pixels in the line of video. The figures below the table show RGB and YCbCr data; the YCbCr 4:4:4 data is
given in braces {}. Data and control signals (Dx, DE, HSYNC, and VSYNC) must change state to meet the setup and hold
times specified for the dual edge mode, with respect to the first edge of IDCK as defined by the setting of the Edge
Select bit (see the Programmer’s Reference). The figures show IDCK latching input data when the Edge Select bit is set
to 1 (first edge is the rising edge).
Table 6.6. RGB/YCbCr 4:4:4 Separate Sync Dual Clock Edge Data Mapping
Video Bus
Setting
12-bit Data Bus
8-bit Color Depth
12-bit Data Bus
8-bit Color Depth
12-bit Data Bus
8-bit Color Depth
12-bit Data Bus
8-bit Color Depth
YCSWAP
N/A
N/A
N/A
N/A
DRA
0
1
0
1
Pin Name
RGB
RGB
YCbCr
YCbCr
1st Clock
Edge
2nd Clock
Edge
1st Clock
Edge
2nd Clock
Edge
1st Clock
Edge
2nd Clock
Edge
1st Clock
Edge
2nd Clock
Edge
D0
LOW
LOW
B0[0]
G0[4]
LOW
LOW
Cb0[0]
Y0[4]
D1
LOW
LOW
B0[1]
G0[5]
LOW
LOW
Cb0[1]
Y0[5]
D2
LOW
LOW
B0[2]
G0[6]
LOW
LOW
Cb0[2]
Y0[6]
D3
LOW
LOW
B0[3]
G0[7]
LOW
LOW
Cb0[3]
Y0[7]
D4
LOW
LOW
B0[4]
R0[0]
LOW
LOW
Cb0[4]
Cr0[0]
D5
LOW
LOW
B0[5]
R0[1]
LOW
LOW
Cb0[5]
Cr0[1]
D6
LOW
LOW
B0[6]
R0[2]
LOW
LOW
Cb0[6]
Cr0[2]
D7
LOW
LOW
B0[7]
R0[3]
LOW
LOW
Cb0[7]
Cr0[3]
D8
B0[0]
G0[4]
G0[0]
R0[4]
Cb0[0]
Y0[4]
Y0[0]
Cr0[4]
D9
B0[1]
G0[5]
G0[1]
R0[5]
Cb0[1]
Y0[5]
Y0[1]
Cr0[5]
D10
B0[2]
G0[6]
G0[2]
R0[6]
Cb0[2]
Y0[6]
Y0[2]
Cr0[6]
D11
B0[3]
G0[7]
G0[3]
R0[7]
Cb0[3]
Y0[7]
Y0[3]
Cr0[7]
D12
B0[4]
R0[0]
LOW
LOW
Cb0[4]
Cr0[0]
LOW
LOW
D13
B0[5]
R0[1]
LOW
LOW
Cb0[5]
Cr0[1]
LOW
LOW
D14
B0[6]
R0[2]
LOW
LOW
Cb0[6]
Cr0[2]
LOW
LOW
D15
B0[7]
R0[3]
LOW
LOW
Cb0[7]
Cr0[3]
LOW
LOW
D16
G0[0]
R0[4]
LOW
LOW
Y0[0]
Cr0[4]
LOW
LOW
D17
G0[1]
R0[5]
LOW
LOW
Y0[1]
Cr0[5]
LOW
LOW
D18
G0[2]
R0[6]
LOW
LOW
Y0[2]
Cr0[6]
LOW
LOW
D19
G0[3]
R0[7]
LOW
LOW
Y0[3]
Cr0[7]
LOW
LOW
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
DE
DE
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 47
Pixel n - 1
blank Pixel 0 Pixel 1 Pixel 2
val
val
D[15:12]
D[11:8]
IDCK
DE
HSYNC,
VSYNC
val
val
val
D[19:16] val
val
val
val
val
val
val
val
val
val
blank blank
Pixel n
B0[7:4]
{Cb0[7:4]}
G0[3:0]
{Y0[3:0]}
B0[3:0]
{Cb0[3:0]}
R0[3:0]
{Cr0[3:0]}
R0[7:4]
{Cr0[7:4]}
G0[7:4]
{Y0[7:4]}
Bn-1[7:4]
{Cbn-1[7:4]}
Gn-1[3:0]
{Yn-1[3:0]}
Bn-1[3:0]
{Cbn-1[3:0]}
Rn-1[3:0]
{Crn-1[3:0]}
Rn-1[7:4]
{Crn-1[7:4]}
Gn-1[7:4]
{Yn-1[7:4]}
Bn[7:4]
{Cbn[7:4]}
Gn[3:0]
{Yn[3:0]}
Bn[3:0]
{Cbn[3:0}
Rn[3:0]
{Crn[3:0]}
Rn[7:4]
{Crn[7:4]}
Gn[7:4]
{Yn[7:4]}
B1[7:4]
{Cb1[7:4]}
G1[3:0]
{Y1[3:0]}
B1[3:0]
{Cb1[3:0]}
R1[3:0]
{Cr1[3:0]}
R1[7:4]
{Cr1[7:4]}
G1[7:4]
{Y1[7:4]}
B2[7:4]
{Cb2[7:4]}
G2[3:0]
{Y2[3:0]}
B2[3:0]
{Cb2[3:0]}
R2[3:0]
{Cr2[3:0]}
R2[7:4]
{Cr2[7:4]}
G2[7:4]
{Y2[7:4]}
Figure 6.4. 8-bit Color Depth RGB/YCbCr 4:4:4 Dual Edge Timing (DRA = 0)
Pixel n - 1
blank Pixel 0 Pixel 1 Pixel 2
val
val
D[7:4]
D[3:0]
IDCK
DE
HSYNC,
VSYNC
val
val
val
D[11:8] val
val
val
val
val
val
val
val
val
val
blank blank
Pixel n
B0[7:4]
{Cb0[7:4]}
G0[3:0]
{Y0[3:0]}
B0[3:0]
{Cb0[3:0]}
R0[3:0]
{Cr0[3:0]}
R0[7:4]
{Cr0[7:4]}
G0[7:4]
{Y0[7:4]}
Bn-1[7:4]
{Cbn-1[7:4]}
Gn-1[3:0]
{Yn-1[3:0]}
Bn-1[3:0]
{Cbn-1[3:0]}
Rn-1[3:0]
{Crn-1[3:0]}
Rn-1[7:4]
{Crn-1[7:4]}
Gn-1[7:4]
{Yn-1[7:4]}
Bn[7:4]
{Cbn[7:4]}
Gn[3:0]
{Yn[3:0]}
Bn[3:0]
{Cbn[3:0}
Rn[3:0]
{Crn[3:0]}
Rn[7:4]
{Crn[7:4]}
Gn[7:4]
{Yn[7:4]}
B1[7:4]
{Cb1[7:4]}
G1[3:0]
{Y1[3:0]}
B1[3:0]
{Cb1[3:0]}
R1[3:0]
{Cr1[3:0]}
R1[7:4]
{Cr1[7:4]}
G1[7:4]
{Y1[7:4]}
B2[7:4]
{Cb2[7:4]}
G2[3:0]
{Y2[3:0]}
B2[3:0]
{Cb2[3:0]}
R2[3:0]
{Cr2[3:0]}
R2[7:4]
{Cr2[7:4]}
G2[7:4]
{Y2[7:4]}
Figure 6.5. 8-bit Color Depth RGB/YCbCr 4:4:4 Dual Edge Timing (DRA = 1)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
48 SiI-DS-1089-G
6.10.3. YC 4:2:2 Separate Sync Formats
The input clock runs at the pixel rate and a complete definition of each pixel is received on each input clock cycle. A
luma (Y) value is carried for every pixel, but the chroma values (Cb and Cr) change only every second pixel. The data
bus can be 16 or 20 bits. HSYNC and VSYNC are driven explicitly on their own signals. Each pair of columns in Table
6.7 shows the first and second pixel of n + 1 pixels in the line of video. The DE HIGH time must contain an even
number of pixel clocks.
Table 6.7. YC 4:2:2 Separate Sync Data Mapping
Video Bus
Setting
16-bit Data Bus
8-bit Color Depth
16-bit Data Bus
8-bit Color Depth
20-bit Data Bus
10-bit Color Depth
20-bit Data Bus
10-bit Color Depth
YCSWAP
0
1
0
1
DRA
N/A
N/A
N/A
N/A
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
Pixel #0
Pixel #1
Pixel #0
Pixel #1
D0
LOW
LOW
LOW
LOW
Cb0[0]
Cr0[0]
Y0[0]
Y1[0]
D1
LOW
LOW
LOW
LOW
Cb0[1]
Cr0[1]
Y0[1]
Y1[1]
D2
Cb0[0]
Cr0[0]
Y0[0]
Y1[0]
Cb0[2]
Cr0[2]
Y0[2]
Y1[2]
D3
Cb0[1]
Cr0[1]
Y0[1]
Y1[1]
Cb0[3]
Cr0[3]
Y0[3]
Y1[3]
D4
Cb0[2]
Cr0[2]
Y0[2]
Y1[2]
Cb0[4]
Cr0[4]
Y0[4]
Y1[4]
D5
Cb0[3]
Cr0[3]
Y0[3]
Y1[3]
Cb0[5]
Cr0[5]
Y0[5]
Y1[5]
D6
Cb0[4]
Cr0[4]
Y0[4]
Y1[4]
Cb0[6]
Cr0[6]
Y0[6]
Y1[6]
D7
Cb0[5]
Cr0[5]
Y0[5]
Y1[5]
Cb0[7]
Cr0[7]
Y0[7]
Y1[7]
D8
Cb0[6]
Cr0[6]
Y0[6]
Y1[6]
Cb0[8]
Cr0[8]
Y0[8]
Y1[8]
D9
Cb0[7]
Cr0[7]
Y0[7]
Y1[7]
Cb0[9]
Cr0[9]
Y0[9]
Y1[9]
D10
LOW
LOW
LOW
LOW
Y0[0]
Y1[0]
Cb0[0]
Cr0[0]
D11
LOW
LOW
LOW
LOW
Y0[1]
Y1[1]
Cb0[1]
Cr0[1]
D12
Y0[0]
Y1[0]
Cb0[0]
Cr0[0]
Y0[2]
Y1[2]
Cb0[2]
Cr0[2]
D13
Y0[1]
Y1[1]
Cb0[1]
Cr0[1]
Y0[3]
Y1[3]
Cb0[3]
Cr0[3]
D14
Y0[2]
Y1[2]
Cb0[2]
Cr0[2]
Y0[4]
Y1[4]
Cb0[4]
Cr0[4]
D15
Y0[3]
Y1[3]
Cb0[3]
Cr0[3]
Y0[5]
Y1[5]
Cb0[5]
Cr0[5]
D16
Y0[4]
Y1[4]
Cb0[4]
Cr0[4]
Y0[6]
Y1[6]
Cb0[6]
Cr0[6]
D17
Y0[5]
Y1[5]
Cb0[5]
Cr0[5]
Y0[7]
Y1[7]
Cb0[7]
Cr0[7]
D18
Y0[6]
Y1[6]
Cb0[6]
Cr0[6]
Y0[8]
Y1[8]
Cb0[8]
Cr0[8]
D19
Y0[7]
Y1[7]
Cb0[7]
Cr0[7]
Y0[9]
Y1[9]
Cb0[9]
Cr0[9]
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
DE
DE
D[19:12]
blank Pixel 0 Pixel 1 Pixel 2 Pixel 3
val Y0[7:0] Y1[7:0] Y2[7:0] Y3[7:0]
D[9:2] val Cb0[7:0] Cr0[7:0] Cb2[7:0] Cr2[7:0]
IDCK
DE
HSYNC,
VSYNC
Pixeln - 1 blank blank blankPixel n
val val val
Yn-1[7:0]
val val val
Yn[7:0]
Cbn-1[7:0] Crn-1[7:0]
Figure 6.6. 8-bit Color Depth YC 4:2:2 Timing (YCSWAP = 0)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 49
D[19:12]
blank Pixel 0 Pixel 1 Pixel 2 Pixel 3
val Cb0[7:0] Cr0[7:0] Cb2[7:0] Cr2[7:0]
D[9:2] val Y0[7:0] Y1[7:0] Y2[7:0] Y3[7:0]
IDCK
DE
HSYNC,
VSYNC
Pixeln - 1 blank blank blankPixel n
val val val
Yn-1[7:0] val val val
Yn[7:0]
Cbn-1[7:0] Crn-1[7:0]
Figure 6.7. 8-bit Color Depth YC 4:2:2 Timing (YCSWAP = 1)
D[19:10]
blank Pixel 0 Pixel 1 Pixel 2 Pixel 3
val Y0[9:0] Y1[9:0] Y2[9:0] Y3[9:0]
D[9:0] val Cb0[9:0] Cr0[9:0] Cb2[9:0] Cr2[9:0]
IDCK
DE
HSYNC,
VSYNC
Pixeln - 1 blank blank blankPixel n
val val val
Yn-1[9:0]
val val val
Yn[9:0]
Cbn-1[9:0] Crn-1[9:0]
Figure 6.8. 10-bit Color Depth YC 4:2:2 Timing (YCSWAP = 0)
D[19:10]
blank Pixel 0 Pixel 1 Pixel 2 Pixel 3
val Cb0[9:0] Cr0[9:0] Cb2[9:0] Cr2[9:0]
D[9:0] val Y0[9:0] Y1[9:0] Y2[9:0] Y3[9:0]
IDCK
DE
HSYNC,
VSYNC
Pixeln - 1 blank blank blankPixel n
val val val
Yn-1[9:0] val val val
Yn[9:0]
Cbn-1[9:0] Crn-1[9:0]
Figure 6.9. 10-bit Color Depth YC 4:2:2 Timing (YCSWAP = 1)
6.10.4. YC 4:2:2 Embedded Syncs Formats
The Embedded Sync format is identical to the YC 4:2:2 formats with Separate Syncs, except that the syncs are
embedded and not explicit. The data bus is 16 bits. Each pair of columns in Table 6.8 shows the first and second pixel of
n + 1 pixels in the line of video.
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
50 SiI-DS-1089-G
Table 6.8. YC 4:2:2 Embedded Sync Data Mapping
Video Bus
Setting
16-bit Data Bus
8-bit Color Depth
16-bit Data Bus
8-bit Color Depth
20-bit Data Bus
10-bit Color Depth
20-bit Data Bus
10-bit Color Depth
YCSWAP
0
1
0
1
DRA
N/A
N/A
N/A
N/A
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
Pixel #0
Pixel #1
Pixel #0
Pixel #1
D0
LOW
LOW
LOW
LOW
Cb0[0]
Cr0[0]
Y0[0]
Y1[0]
D1
LOW
LOW
LOW
LOW
Cb0[1]
Cr0[1]
Y0[1]
Y1[1]
D2
Cb0[0]
Cr0[0]
Y0[0]
Y1[0]
Cb0[2]
Cr0[2]
Y0[2]
Y1[2]
D3
Cb0[1]
Cr0[1]
Y0[1]
Y1[1]
Cb0[3]
Cr0[3]
Y0[3]
Y1[3]
D4
Cb0[2]
Cr0[2]
Y0[2]
Y1[2]
Cb0[4]
Cr0[4]
Y0[4]
Y1[4]
D5
Cb0[3]
Cr0[3]
Y0[3]
Y1[3]
Cb0[5]
Cr0[5]
Y0[5]
Y1[5]
D6
Cb0[4]
Cr0[4]
Y0[4]
Y1[4]
Cb0[6]
Cr0[6]
Y0[6]
Y1[6]
D7
Cb0[5]
Cr0[5]
Y0[5]
Y1[5]
Cb0[7]
Cr0[7]
Y0[7]
Y1[7]
D8
Cb0[6]
Cr0[6]
Y0[6]
Y1[6]
Cb0[8]
Cr0[8]
Y0[8]
Y1[8]
D9
Cb0[7]
Cr0[7]
Y0[7]
Y1[7]
Cb0[9]
Cr0[9]
Y0[9]
Y1[9]
D10
LOW
LOW
LOW
LOW
Y0[0]
Y1[0]
Cb0[0]
Cr0[0]
D11
LOW
LOW
LOW
LOW
Y0[1]
Y1[1]
Cb0[1]
Cr0[1]
D12
Y0[0]
Y1[0]
Cb0[0]
Cr0[0]
Y0[2]
Y1[2]
Cb0[2]
Cr0[2]
D13
Y0[1]
Y1[1]
Cb0[1]
Cr0[1]
Y0[3]
Y1[3]
Cb0[3]
Cr0[3]
D14
Y0[2]
Y1[2]
Cb0[2]
Cr0[2]
Y0[4]
Y1[4]
Cb0[4]
Cr0[4]
D15
Y0[3]
Y1[3]
Cb0[3]
Cr0[3]
Y0[5]
Y1[5]
Cb0[5]
Cr0[5]
D16
Y0[4]
Y1[4]
Cb0[4]
Cr0[4]
Y0[6]
Y1[6]
Cb0[6]
Cr0[6]
D17
Y0[5]
Y1[5]
Cb0[5]
Cr0[5]
Y0[7]
Y1[7]
Cb0[7]
Cr0[7]
D18
Y0[6]
Y1[6]
Cb0[6]
Cr0[6]
Y0[8]
Y1[8]
Cb0[8]
Cr0[8]
D19
Y0[7]
Y1[7]
Cb0[7]
Cr0[7]
Y0[9]
Y1[9]
Cb0[9]
Cr0[9]
HSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
VSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D[19:12]
SAV Pixel 0 Pixel 1 Pixel 2 Pixel 3
Y0[7:0] Y1[7:0] Y2[7:0] Y3[7:0]
D[9:2] XY Cb0[7:0] Cr0[7:0] Cb2[7:0] Cr2[7:0]
IDCK
Active
video
EAV
Yn-1[7:0] Yn[7:0]
Cbn-1[7:0] Crn-1[7:0]
00
00FF XY
00
00FF
XY
00
00FF XY
00
00FF
Pixel n - 1 Pixel n
Figure 6.10. 8-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 0)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 51
D[19:12]
SAV Pixel 0 Pixel 1 Pixel 2 Pixel 3
Cb0[7:0] Cr0[7:0] Cb2[7:0] Cr2[7:0]
D[9:2] XY Y0[7:0] Y1[7:0] Y2[7:0] Y3[7:0]
IDCK
Active
video
EAV
Cbn-1[7:0] Crn-1[7:0]
Yn-1[7:0] Yn[7:0]
00
00FF XY
00
00FF
XY
00
00FF XY
00
00FF
Pixel n - 1 Pixel n
Figure 6.11. 8-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 1)
D[19:10]
SAV Pixel 0 Pixel 1 Pixel 2 Pixel 3
Y0[9:0] Y1[9:0] Y2[9:0] Y3[9:0]
D[9:0] XY Cb0[9:0] Cr0[9:0] Cb2[9:0] Cr2[9:0]
IDCK
Active
video
EAV
Yn-1[9:0] Yn[9:0]
Cbn-1[9:0] Crn-1[9:0]
00
00FF XY
00
00FF
XY
00
00FF XY
00
00FF
Pixel n - 1 Pixel n
Figure 6.12. 10-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 0)
D[19:10]
SAV Pixel 0 Pixel 1 Pixel 2 Pixel 3
Cb0[9:0] Cr0[9:0] Cb2[9:0] Cr2[9:0]
D[9:0] XY Y0[9:0] Y1[9:0] Y2[9:0] Y3[9:0]
IDCK
Active
video
EAV
Cbn-1[9:0] Crn-1[9:0]
Yn-1[9:0] Yn[9:0]
00
00FF XY
00
00FF
XY
00
00FF XY
00
00FF
Pixel n - 1 Pixel n
Figure 6.13. 10-bit Color Depth YC 4:2:2 Embedded Sync Timing (YCSWAP = 1)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
52 SiI-DS-1089-G
6.10.5. YC Mux 4:2:2 Separate Sync Formats Single Clock Edge
The video data is multiplexed onto fewer pins than the mapping described in the YC 4:2:2 Separate Sync Formats
section on page 48. The input clock runs at double the pixel rate so a chroma value is sent for each pixel, followed by a
corresponding luma value for the same pixel. Thus, a luma (Y) value is provided for each pixel, while the Cb and Cr
values alternate on successive pixels. Each group of four columns in Table 6.9 shows the four clock cycles for the first
two pixels of the line. Pixel values for Cb0 and Y0 values are sent with the first pixel (first two clock cycles). Then the Cr0
and Y1 values are sent with the second pixel (next two clock cycles). The figures below the table show how this pattern
is extended for the rest of the pixels in a video line of n + 1 pixels.
Table 6.9. YC Mux 4:2:2 8-bit Color Depth Separate Sync Data Mapping
Video Bus
Setting
8-bit Data Bus
8-bit Color Depth
8-bit Data Bus
8-bit Color Depth
YCSWAP
N/A
N/A
DRA
0
1
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
1st Clock
Cycle
2nd Clock
Cycle
3rd Clock
Cycle
4th Clock
Cycle
1st Clock
Cycle
2nd Clock
Cycle
3rd Clock
Cycle
4th Clock
Cycle
D0
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D1
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D2
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D3
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D4
LOW
LOW
LOW
LOW
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
D5
LOW
LOW
LOW
LOW
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
D6
LOW
LOW
LOW
LOW
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
D7
LOW
LOW
LOW
LOW
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
D8
LOW
LOW
LOW
LOW
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
D9
LOW
LOW
LOW
LOW
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
D10
LOW
LOW
LOW
LOW
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
D11
LOW
LOW
LOW
LOW
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
D12
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
LOW
LOW
LOW
LOW
D13
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
LOW
LOW
LOW
LOW
D14
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
LOW
LOW
LOW
LOW
D15
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
LOW
LOW
LOW
LOW
D16
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
LOW
LOW
LOW
LOW
D17
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
LOW
LOW
LOW
LOW
D18
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
LOW
LOW
LOW
LOW
D19
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
LOW
LOW
LOW
LOW
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
DE
DE
D[19:12] Y1[7:0] Cb2[7:0] Y2[7:0] Cr2[7:0]
IDCK
Yn-1[7:0] Yn[7:0]
DE
HSYNC
VSYNC
Cb0[7:0] Y0[7:0] Cr0[7:0] Y3[7:0] Cbn-1[7:0] Crn-1[7:0]
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n
val val
Figure 6.14. 8-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 53
D[11:4] Y1[7:0] Cb2[7:0] Y2[7:0] Cr2[7:0]
IDCK
Yn-1[7:0] Yn[7:0]
DE
HSYNC
VSYNC
Cb0[7:0] Y0[7:0] Cr0[7:0] Y3[7:0] Cbn-1[7:0] Crn-1[7:0]
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n
val val
Figure 6.15. 8-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1)
Table 6.10. YC Mux 4:2:2 10-bit Color Depth Separate Sync Data Mapping
Video Bus
Setting
10-bit Data Bus
10-bit Color Depth
10-bit Data Bus
10-bit Color Depth
YCSWAP
N/A
N/A
DRA
0
1
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
1st Clock
Cycle
2nd Clock
Cycle
3rd Clock
Cycle
4th Clock
Cycle
1st Clock
Cycle
2nd Clock
Cycle
3rd Clock
Cycle
4th Clock
Cycle
D0
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D1
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D2
LOW
LOW
LOW
LOW
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
D3
LOW
LOW
LOW
LOW
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
D4
LOW
LOW
LOW
LOW
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
D5
LOW
LOW
LOW
LOW
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
D6
LOW
LOW
LOW
LOW
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
D7
LOW
LOW
LOW
LOW
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
D8
LOW
LOW
LOW
LOW
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
D9
LOW
LOW
LOW
LOW
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
D10
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
D11
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
D12
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
LOW
LOW
LOW
LOW
D13
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
LOW
LOW
LOW
LOW
D14
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
LOW
LOW
LOW
LOW
D15
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
LOW
LOW
LOW
LOW
D16
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
LOW
LOW
LOW
LOW
D17
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
LOW
LOW
LOW
LOW
D18
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
LOW
LOW
LOW
LOW
D19
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
LOW
LOW
LOW
LOW
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
DE
DE
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
54 SiI-DS-1089-G
D[19:10] Y1[9:0] Cb2[9:0] Y2[9:0] Cr2[9:0]
IDCK
Yn-1[9:0] Yn[9:0]
DE
HSYNC
VSYNC
Cb0[9:0] Y0[9:0] Cr0[9:0] Y3[9:0] Cbn-1[9:0] Crn-1[9:0]
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n
val val
Figure 6.16. 10-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0)
D[11:2] Y1[9:0] Cb2[9:0] Y2[9:0] Cr2[9:0]
IDCK
Yn-1[9:0] Yn[9:0]
DE
HSYNC
VSYNC
Cb0[9:0] Y0[9:0] Cr0[9:0] Y3[9:0] Cbn-1[9:0] Crn-1[9:0]
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n
val val
Figure 6.17. 10-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 55
Table 6.11. YC Mux 4:2:2 12-bit Color Depth Separate Sync Data Mapping
Video Bus
Setting
12-bit Data Bus
12-bit Color Depth
12-bit Data Bus
12-bit Color Depth
YCSWAP
N/A
N/A
DRA
0
1
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
1st Clock
Cycle
2nd Clock
Cycle
3rd Clock
Cycle
4th Clock
Cycle
1st Clock
Cycle
2nd Clock
Cycle
3rd Clock
Cycle
4th Clock
Cycle
D0
LOW
LOW
LOW
LOW
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
D1
LOW
LOW
LOW
LOW
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
D2
LOW
LOW
LOW
LOW
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
D3
LOW
LOW
LOW
LOW
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
D4
LOW
LOW
LOW
LOW
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
D5
LOW
LOW
LOW
LOW
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
D6
LOW
LOW
LOW
LOW
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
D7
LOW
LOW
LOW
LOW
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
D8
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
D9
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
D10
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
Cb0[10]
Y0[10]
Cr0[10]
Y1[10]
D11
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
Cb0[11]
Y0[11]
Cr0[11]
Y1[11]
D12
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
LOW
LOW
LOW
LOW
D13
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
LOW
LOW
LOW
LOW
D14
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
LOW
LOW
LOW
LOW
D15
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
LOW
LOW
LOW
LOW
D16
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
LOW
LOW
LOW
LOW
D17
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
LOW
LOW
LOW
LOW
D18
Cb0[10]
Y0[10]
Cr0[10]
Y1[10]
LOW
LOW
LOW
LOW
D19
Cb0[11]
Y0[11]
Cr0[11]
Y1[11]
LOW
LOW
LOW
LOW
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
DE
DE
D[19:8] Y1[11:0] Cb2[11:0] Y2[11:0] Cr2[11:0]
IDCK
Yn-1[11:0] Yn[11:0]
DE
HSYNC
VSYNC
Cb0[11:0] Y0[11:0] Cr0[11:0] Y3[11:0] Cbn-1[11:0] Crn-1[11:0]
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n
val val
Figure 6.18. 12-bit Color Depth YC Mux 4:2:2 Timing (DRA = 0)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
56 SiI-DS-1089-G
D[11:0] Y1[11:0] Cb2[11:0] Y2[11:0] Cr2[11:0]
IDCK
Yn-1[11:0] Yn[11:0]
DE
HSYNC
VSYNC
Cb0[11:0] Y0[11:0] Cr0[11:0] Y3[11:0] Cbn-1[11:0] Crn-1[11:0]
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n
val val
Figure 6.19. 12-bit Color Depth YC Mux 4:2:2 Timing (DRA = 1)
6.10.6. YC Mux 4:2:2 Embedded Sync Formats Single Clock Edge
This format is identical to the one described in the YC Mux 4:2:2 Separate Sync Formats Single Clock Edge section on
page 52, except the syncs are embedded and not explicit. The figures following this table show only the first two pixels
and last pixel of the line and the SAV and EAV sequences, but the remaining pixels are similar to those shown in the
figures of the previous section.
Table 6.12. YC Mux 4:2:2 8-bit Color Depth Embedded Sync Data Mapping
Video Bus
Setting
8-bit Data Bus
8-bit Color Depth
8-bit Data Bus
8-bit Color Depth
YCSWAP
N/A
N/A
DRA
0
1
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
1st Clock
Cycle
2nd Clock
Cycle
3rd Clock
Cycle
4th Clock
Cycle
1st Clock
Cycle
2nd Clock
Cycle
3rd Clock
Cycle
4th Clock
Cycle
D0
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D1
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D2
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D3
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D4
LOW
LOW
LOW
LOW
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
D5
LOW
LOW
LOW
LOW
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
D6
LOW
LOW
LOW
LOW
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
D7
LOW
LOW
LOW
LOW
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
D8
LOW
LOW
LOW
LOW
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
D9
LOW
LOW
LOW
LOW
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
D10
LOW
LOW
LOW
LOW
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
D11
LOW
LOW
LOW
LOW
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
D12
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
LOW
LOW
LOW
LOW
D13
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
LOW
LOW
LOW
LOW
D14
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
LOW
LOW
LOW
LOW
D15
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
LOW
LOW
LOW
LOW
D16
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
LOW
LOW
LOW
LOW
D17
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
LOW
LOW
LOW
LOW
D18
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
LOW
LOW
LOW
LOW
D19
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
LOW
LOW
LOW
LOW
HSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
VSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 57
SAV Pixel 0 Pixel 1
D[19:12] XY Cb0[7:0]
IDCK
Active
video
EAV
Pixel n
00
00FF Y0[7:0] Cr0[7:0] Y1[7:0] Crn-1[7:0] Yn[7:0] XY
00
00FF
Figure 6.20. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0)
D[19:10]
SAV Pixel 0 Pixel 1 Pixel 2 Pixel 3
Cb0[9:0] Cr0[9:0] Cb2[9:0] Cr2[9:0]
D[9:0] XY Y0[9:0] Y1[9:0] Y2[9:0] Y3[9:0]
IDCK
Active
video
EAV
Cbn-1[9:0] Crn-1[9:0]
Yn-1[9:0] Yn[9:0]
00
00FF XY
00
00FF
XY
00
00FF XY
00
00FF
Pixel n - 1 Pixel n
Figure 6.21. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1)
Table 6.13. YC Mux 4:2:2 10-bit Color Depth Embedded Sync Data Mapping
Video Bus
Setting
10-bit Data Bus
10-bit Color Depth
10-bit Data Bus
10-bit Color Depth
YCSWAP
N/A
N/A
DRA
0
1
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
1st Clock
Cycle
2nd Clock
Cycle
3rd Clock
Cycle
4th Clock
Cycle
1st Clock
Cycle
2nd Clock
Cycle
3rd Clock
Cycle
4th Clock
Cycle
D0
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D1
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D2
LOW
LOW
LOW
LOW
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
D3
LOW
LOW
LOW
LOW
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
D4
LOW
LOW
LOW
LOW
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
D5
LOW
LOW
LOW
LOW
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
D6
LOW
LOW
LOW
LOW
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
D7
LOW
LOW
LOW
LOW
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
D8
LOW
LOW
LOW
LOW
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
D9
LOW
LOW
LOW
LOW
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
D10
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
D11
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
D12
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
LOW
LOW
LOW
LOW
D13
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
LOW
LOW
LOW
LOW
D14
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
LOW
LOW
LOW
LOW
D15
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
LOW
LOW
LOW
LOW
D16
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
LOW
LOW
LOW
LOW
D17
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
LOW
LOW
LOW
LOW
D18
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
LOW
LOW
LOW
LOW
D19
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
LOW
LOW
LOW
LOW
HSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
VSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
58 SiI-DS-1089-G
SAV Pixel 0 Pixel 1
D[19:10] XY Cb0[9:0]
IDCK
Active
video
EAV
Pixel n
00
00FF Y0[9:0] Cr0[9:0] Y1[9:0] Crn-1[9:0] Yn[9:0] XY
00
00FF
Figure 6.22. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0)
SAV Pixel 0 Pixel 1
D[11:2] XY Cb0[9:0]
IDCK
Active
video
EAV
Pixel n
00
00FF Y0[9:0] Cr0[9:0] Y1[9:0] Crn-1[9:0] Yn[9:0] XY
00
00FF
Figure 6.23. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1)
Table 6.14. YC Mux 4:2:2 12-bit Color Depth Embedded Sync Data Mapping
Video Bus
Setting
12-bit Data Bus
12-bit Color Depth
12-bit Data Bus
12-bit Color Depth
YCSWAP
N/A
N/A
DRA
0
1
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
1st Clock
Cycle
2nd Clock
Cycle
3rd Clock
Cycle
4th Clock
Cycle
1st Clock
Cycle
2nd Clock
Cycle
3rd Clock
Cycle
4th Clock
Cycle
D0
LOW
LOW
LOW
LOW
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
D1
LOW
LOW
LOW
LOW
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
D2
LOW
LOW
LOW
LOW
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
D3
LOW
LOW
LOW
LOW
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
D4
LOW
LOW
LOW
LOW
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
D5
LOW
LOW
LOW
LOW
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
D6
LOW
LOW
LOW
LOW
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
D7
LOW
LOW
LOW
LOW
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
D8
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
D9
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
D10
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
Cb0[10]
Y0[10]
Cr0[10]
Y1[10]
D11
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
Cb0[11]
Y0[11]
Cr0[11]
Y1[11]
D12
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
LOW
LOW
LOW
LOW
D13
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
LOW
LOW
LOW
LOW
D14
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
LOW
LOW
LOW
LOW
D15
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
LOW
LOW
LOW
LOW
D16
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
LOW
LOW
LOW
LOW
D17
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
LOW
LOW
LOW
LOW
D18
Cb0[10]
Y0[10]
Cr0[10]
Y1[10]
LOW
LOW
LOW
LOW
D19
Cb0[11]
Y0[11]
Cr0[11]
Y1[11]
LOW
LOW
LOW
LOW
HSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
VSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 59
SAV Pixel 0 Pixel 1
D[19:8] XY Cb0[11:0]
IDCK
Active
video
EAV
Pixel n
00
00FF Y0[11:0] Cr0[11:0] Y1[11:0] Crn-1[11:0] Yn[11:0] XY
00
00FF
Figure 6.24. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 0)
SAV Pixel 0 Pixel 1
D[11:0] XY Cb0[11:0]
IDCK
Active
video
EAV
Pixel n
00
00FF Y0[11:0] Cr0[11:0] Y1[11:0] Crn-1[11:0] Yn[11:0] XY
00
00FF
Figure 6.25. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Timing (DRA = 1)
6.10.7. YC Mux 4:2:2 Separate Sync Formats Dual Clock Edge
The video data is multiplexed onto fewer pins than the mapping described in the YC 4:2:2 Separate Sync Formats on
page 48. The input clock runs at the pixel rate and a complete definition of each pixel is received on each input clock
cycle. The chroma value is sent for each pixel, followed by a corresponding luma value for the same pixel. Thus, a luma
(Y) value is provided for each pixel, while the Cb and Cr values alternate on successive pixels. One clock edge latches in
half the pixel data. The opposite clock edge latches in the remaining half of the pixel data on the same pins.
Each group of four columns in Table 6.9 shows the two clock cycles for the first two pixels of the line. Pixel values for
Cb0 and Y0 values are sent with the first pixel (first and second clock edges of the first clock cycle). Then the Cr0 and Y1
values are sent with the second pixel (first and second clock edges of the second clock cycle). The figures below the
table show how this pattern is extended for the rest of the pixels in a video line of n + 1 pixels.
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
60 SiI-DS-1089-G
Table 6.15. YC Mux 4:2:2 8-bit Color Depth Separate Sync Dual Clock Edge Data Mapping
Video Bus
Setting
8-bit Data Bus
8-bit Color Depth
8-bit Data Bus
8-bit Color Depth
YCSWAP
0
1
DRA
0
1
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
1st Clock
2nd Clock
1st Clock
2nd Clock
1st Clock
Edge
2nd Clock
Edge
1st Clock
Edge
2nd Clock
Edge
1st Clock
Edge
2nd Clock
Edge
1st Clock
Edge
2nd Clock
Edge
D0
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D1
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D2
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D3
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D4
LOW
LOW
LOW
LOW
Y0[0]
Cb0[0]
Y1[0]
Cr0[0]
D5
LOW
LOW
LOW
LOW
Y0[1]
Cb0[1]
Y1[1]
Cr0[1]
D6
LOW
LOW
LOW
LOW
Y0[2]
Cb0[2]
Y1[2]
Cr0[2]
D7
LOW
LOW
LOW
LOW
Y0[3]
Cb0[3]
Y1[3]
Cr0[3]
D8
LOW
LOW
LOW
LOW
Y0[4]
Cb0[4]
Y1[4]
Cr0[4]
D9
LOW
LOW
LOW
LOW
Y0[5]
Cb0[5]
Y1[5]
Cr0[5]
D10
LOW
LOW
LOW
LOW
Y0[6]
Cb0[6]
Y1[6]
Cr0[6]
D11
LOW
LOW
LOW
LOW
Y0[7]
Cb0[7]
Y1[7]
Cr0[7]
D12
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
LOW
LOW
LOW
LOW
D13
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
LOW
LOW
LOW
LOW
D14
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
LOW
LOW
LOW
LOW
D15
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
LOW
LOW
LOW
LOW
D16
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
LOW
LOW
LOW
LOW
D17
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
LOW
LOW
LOW
LOW
D18
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
LOW
LOW
LOW
LOW
D19
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
LOW
LOW
LOW
LOW
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
DE
DE
D[19:12] Y1[7:0] Cb2[7:0] Y2[7:0] Cr2[7:0]
IDCK
Yn-1[7:0] Yn[7:0]
DE
HSYNC
VSYNC
Cb0[7:0] Y0[7:0] Cr0[7:0] Y3[7:0] Cbn-1[7:0] Crn-1[7:0]
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n
val val
Figure 6.26. 8-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 61
D[11:4] Cr0[7:0] Y2[7:0] Cb2[7:0] Y3[7:0]
IDCK
Cbn-1[7:0] Crn-1[7:0]
DE
HSYNC
VSYNC
Y0[7:0] Cb0[7:0] Y1[7:0] Cr2[7:0] Yn-1[7:0] Yn[7:0]
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n
val val
Figure 6.27. 8-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 1)
Table 6.16. YC Mux 4:2:2 10-bit Color Depth Separate Sync Dual Clock Edge Data Mapping
Video Bus
Setting
10-bit Data Bus
10-bit Color Depth
10-bit Data Bus
10-bit Color Depth
YCSWAP
0
0
DRA
0
1
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
1st Clock
2nd Clock
1st Clock
2nd Clock
1st Clock
Edge
2nd Clock
Edge
3rd Clock
Edge
4th Clock
Edge
1st Clock
Edge
2nd Clock
Edge
3rd Clock
Edge
4th Clock
Edge
D0
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D1
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D2
LOW
LOW
LOW
LOW
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
D3
LOW
LOW
LOW
LOW
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
D4
LOW
LOW
LOW
LOW
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
D5
LOW
LOW
LOW
LOW
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
D6
LOW
LOW
LOW
LOW
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
D7
LOW
LOW
LOW
LOW
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
D8
LOW
LOW
LOW
LOW
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
D9
LOW
LOW
LOW
LOW
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
D10
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
D11
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
D12
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
LOW
LOW
LOW
LOW
D13
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
LOW
LOW
LOW
LOW
D14
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
LOW
LOW
LOW
LOW
D15
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
LOW
LOW
LOW
LOW
D16
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
LOW
LOW
LOW
LOW
D17
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
LOW
LOW
LOW
LOW
D18
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
LOW
LOW
LOW
LOW
D19
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
LOW
LOW
LOW
LOW
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
DE
DE
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
62 SiI-DS-1089-G
D[19:10] Y1[9:0] Cb2[9:0] Y2[9:0] Cr2[9:0]
IDCK
Yn-1[9:0] Yn[9:0]
DE
HSYNC
VSYNC
Cb0[9:0] Y0[9:0] Cr0[9:0] Y3[9:0] Cbn-1[9:0] Crn-1[9:0]
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n
val val
Figure 6.28. 10-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0)
D[11:2] Y1[9:0] Cb2[9:0] Y2[9:0] Cr2[9:0]
IDCK
Yn-1[9:0] Yn[9:0]
DE
HSYNC
VSYNC
Cb0[9:0] Y0[9:0] Cr0[9:0] Y3[9:0] Cbn-1[9:0] Crn-1[9:0]
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n
val val
Figure 6.29. 10-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 0)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 63
Table 6.17. YC Mux 4:2:2 12-bit Color Depth Separate Sync Dual Clock Edge Data Mapping
Video Bus
Setting
12-bit Data Bus
12-bit Color Depth
12-bit Data Bus
12-bit Color Depth
YCSWAP
0
0
DRA
0
1
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
1st Clock
2nd Clock
1st Clock
2nd Clock
1st Clock
Edge
2nd Clock
Edge
3rd Clock
Edge
4th Clock
Edge
1st Clock
Edge
2nd Clock
Edge
3rd Clock
Edge
4th Clock
Edge
D0
LOW
LOW
LOW
LOW
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
D1
LOW
LOW
LOW
LOW
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
D2
LOW
LOW
LOW
LOW
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
D3
LOW
LOW
LOW
LOW
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
D4
LOW
LOW
LOW
LOW
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
D5
LOW
LOW
LOW
LOW
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
D6
LOW
LOW
LOW
LOW
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
D7
LOW
LOW
LOW
LOW
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
D8
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
D9
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
D10
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
Cb0[10]
Y0[10]
Cr0[10]
Y1[10]
D11
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
Cb0[11]
Y0[11]
Cr0[11]
Y1[11]
D12
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
LOW
LOW
LOW
LOW
D13
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
LOW
LOW
LOW
LOW
D14
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
LOW
LOW
LOW
LOW
D15
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
LOW
LOW
LOW
LOW
D16
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
LOW
LOW
LOW
LOW
D17
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
LOW
LOW
LOW
LOW
D18
Cb0[10]
Y0[10]
Cr0[10]
Y1[10]
LOW
LOW
LOW
LOW
D19
Cb0[11]
Y0[11]
Cr0[11]
Y1[11]
LOW
LOW
LOW
LOW
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
DE
DE
D[19:8] Y1[11:0] Cb2[11:0] Y2[11:0] Cr2[11:0]
IDCK
Yn-1[11:0] Yn[11:0]
DE
HSYNC
VSYNC
Cb0[11:0] Y0[11:0] Cr0[11:0] Y3[11:0] Cbn-1[11:0] Crn-1[11:0]
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n
val val
Figure 6.30. 12-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 0, YCSWAP = 0)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
64 SiI-DS-1089-G
D[11:0] Y1[11:0] Cb2[11:0] Y2[11:0] Cr2[11:0]
IDCK
Yn-1[11:0] Yn[11:0]
DE
HSYNC
VSYNC
Cb0[11:0] Y0[11:0] Cr0[11:0] Y3[11:0] Cbn-1[11:0] Crn-1[11:0]
Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel n - 1 Pixel n
val val
Figure 6.31. 12-bit Color Depth YC Mux 4:2:2 Dual Edge Timing (DRA = 1, YCSWAP = 0)
6.10.8. YC Mux 4:2:2 Embedded Sync Formats Dual Clock Edge
This format is identical to the one described in the YC Mux 4:2:2 Separate Sync Formats Dual Clock Edge section on page
59, except the syncs are embedded and not explicit. The figures following this table show only the first two pixels and
last pixel of the line and the SAV and EAV sequences, but the remaining pixels are similar to those shown in the figures
of the previous section.
Table 6.18. YC Mux 4:2:2 8-bit Color Depth Embedded Sync Dual Clock Edge Data Mapping
Video Bus
Setting
8-bit Data Bus
8-bit Color Depth
8-bit Data Bus
8-bit Color Depth
YCSWAP
0
1
DRA
0
1
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
1st Clock
2nd Clock
1st Clock
2nd Clock
1st Clock
Edge
2nd Clock
Edge
3rd Clock
Edge
4th Clock
Edge
1st Clock
Edge
2nd Clock
Edge
3rd Clock
Edge
4th Clock
Edge
D0
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D1
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D2
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D3
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D4
LOW
LOW
LOW
LOW
Y0[0]
Cb0[0]
Y1[0]
Cr0[0]
D5
LOW
LOW
LOW
LOW
Y0[1]
Cb0[1]
Y1[1]
Cr0[1]
D6
LOW
LOW
LOW
LOW
Y0[2]
Cb0[2]
Y1[2]
Cr0[2]
D7
LOW
LOW
LOW
LOW
Y0[3]
Cb0[3]
Y1[3]
Cr0[3]
D8
LOW
LOW
LOW
LOW
Y0[4]
Cb0[4]
Y1[4]
Cr0[4]
D9
LOW
LOW
LOW
LOW
Y0[5]
Cb0[5]
Y1[5]
Cr0[5]
D10
LOW
LOW
LOW
LOW
Y0[6]
Cb0[6]
Y1[6]
Cr0[6]
D11
LOW
LOW
LOW
LOW
Y0[7]
Cb0[7]
Y1[7]
Cr0[7]
D12
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
LOW
LOW
LOW
LOW
D13
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
LOW
LOW
LOW
LOW
D14
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
LOW
LOW
LOW
LOW
D15
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
LOW
LOW
LOW
LOW
D16
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
LOW
LOW
LOW
LOW
D17
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
LOW
LOW
LOW
LOW
D18
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
LOW
LOW
LOW
LOW
D19
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
LOW
LOW
LOW
LOW
HSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
VSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 65
SAV Pixel 0 Pixel 1
D[19:12] 00 Cb0[7:0]
IDCK
Active
video
EAV
Pixel n
00
FFFF Y0[7:0] Cr0[7:0] Y1[7:0]
Crn-1[7:0] Yn[7:0] 00
00
FFFF XY
XY
0000
XY
XY
0000
D[19:12]
IDCK
Active
video
Figure 6.32. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0)
SAV Pixel 0 Pixel 1
D[11:4] 00 Y0[7:0]
IDCK
Active
video
EAV
Pixel n
00
FFFF Cb0[7:0] Y1[7:0] Cr0[7:0]
Yn[7:0] Crn-1[7:0] 00
00
FFFF XY
XY
0000
XY
XY
0000
D[11:4]
IDCK
Active
video
Figure 6.33. 8-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 1)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
66 SiI-DS-1089-G
Table 6.19. YC Mux 4:2:2 10-bit Color Depth Embedded Sync Dual Clock Edge Data Mapping
Video Bus
Setting
10-bit Data Bus
10-bit Color Depth
10-bit Data Bus
10-bit Color Depth
YCSWAP
0
0
DRA
0
1
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
1st Clock
2nd Clock
1st Clock
2nd Clock
1st Clock
Edge
2nd Clock
Edge
3rd Clock
Edge
4th Clock
Edge
1st Clock
Edge
2nd Clock
Edge
3rd Clock
Edge
4th Clock
Edge
D0
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D1
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
D2
LOW
LOW
LOW
LOW
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
D3
LOW
LOW
LOW
LOW
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
D4
LOW
LOW
LOW
LOW
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
D5
LOW
LOW
LOW
LOW
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
D6
LOW
LOW
LOW
LOW
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
D7
LOW
LOW
LOW
LOW
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
D8
LOW
LOW
LOW
LOW
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
D9
LOW
LOW
LOW
LOW
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
D10
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
D11
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
D12
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
LOW
LOW
LOW
LOW
D13
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
LOW
LOW
LOW
LOW
D14
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
LOW
LOW
LOW
LOW
D15
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
LOW
LOW
LOW
LOW
D16
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
LOW
LOW
LOW
LOW
D17
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
LOW
LOW
LOW
LOW
D18
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
LOW
LOW
LOW
LOW
D19
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
LOW
LOW
LOW
LOW
HSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
VSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
SAV Pixel 0 Pixel 1
D[19:10] 00 Cb0[9:0]
IDCK
Active
video
EAV
Pixel n
00
FFFF Y0[9:0] Cr0[9:0] Y1[9:0]
Crn-1[9:0] Yn[9:0] 00
00
FFFF XY
XY
0000
XY
XY
0000
D[19:10]
IDCK
Active
video
Figure 6.34. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 67
SAV Pixel 0 Pixel 1
D[11:2] 00 Cb0[9:0]
IDCK
Active
video
EAV
Pixel n
00
FFFF Y0[9:0] Cr0[9:0] Y1[9:0]
Crn-1[9:0] Yn[9:0] 00
00
FFFF XY
XY
0000
XY
XY
0000
D[11:2]
IDCK
Active
video
Figure 6.35. 10-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 0)
Table 6.20. YC Mux 4:2:2 12-bit Color Depth Embedded Sync Dual Clock Edge Data Mapping
Video Bus
Setting
12-bit Data Bus
12-bit Color Depth
12-bit Data Bus
12-bit Color Depth
YCSWAP
0
0
DRA
0
1
Pin Name
Pixel #0
Pixel #1
Pixel #0
Pixel #1
1st Clock
2nd Clock
1st Clock
2nd Clock
1st Clock
Edge
2nd Clock
Edge
3rd Clock
Edge
4th Clock
Edge
1st Clock
Edge
2nd Clock
Edge
3rd Clock
Edge
4th Clock
Edge
D0
LOW
LOW
LOW
LOW
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
D1
LOW
LOW
LOW
LOW
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
D2
LOW
LOW
LOW
LOW
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
D3
LOW
LOW
LOW
LOW
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
D4
LOW
LOW
LOW
LOW
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
D5
LOW
LOW
LOW
LOW
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
D6
LOW
LOW
LOW
LOW
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
D7
LOW
LOW
LOW
LOW
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
D8
Cb0[0]
Y0[0]
Cr0[0]
Y1[0]
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
D9
Cb0[1]
Y0[1]
Cr0[1]
Y1[1]
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
D10
Cb0[2]
Y0[2]
Cr0[2]
Y1[2]
Cb0[10]
Y0[10]
Cr0[10]
Y1[10]
D11
Cb0[3]
Y0[3]
Cr0[3]
Y1[3]
Cb0[11]
Y0[11]
Cr0[11]
Y1[11]
D12
Cb0[4]
Y0[4]
Cr0[4]
Y1[4]
LOW
LOW
LOW
LOW
D13
Cb0[5]
Y0[5]
Cr0[5]
Y1[5]
LOW
LOW
LOW
LOW
D14
Cb0[6]
Y0[6]
Cr0[6]
Y1[6]
LOW
LOW
LOW
LOW
D15
Cb0[7]
Y0[7]
Cr0[7]
Y1[7]
LOW
LOW
LOW
LOW
D16
Cb0[8]
Y0[8]
Cr0[8]
Y1[8]
LOW
LOW
LOW
LOW
D17
Cb0[9]
Y0[9]
Cr0[9]
Y1[9]
LOW
LOW
LOW
LOW
D18
Cb0[10]
Y0[10]
Cr0[10]
Y1[10]
LOW
LOW
LOW
LOW
D19
Cb0[11]
Y0[11]
Cr0[11]
Y1[11]
LOW
LOW
LOW
LOW
HSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
VSYNC
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
DE
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
68 SiI-DS-1089-G
SAV Pixel 0 Pixel 1
D[19:8] 00 Cb0[11:0]
IDCK
Active
video
EAV
Pixel n
00
FFFF Y0[11:0] Cr0[11:0] Y1[11:0]
Crn-1[11:0] Yn[11:0] 00
00
FFFF XY
XY
0000
XY
XY
0000
D[19:8]
IDCK
Active
video
Figure 6.36. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 0, YCSWAP = 0)
SAV Pixel 0 Pixel 1
D[11:0] 00 Cb0[11:0]
IDCK
Active
video
EAV
Pixel n
00
FFFF Y0[11:0] Cr0[11:0] Y1[11:0]
Crn-1[11:0] Yn[11:0] 00
00
FFFF XY
XY
0000
XY
XY
0000
D[11:0]
IDCK
Active
video
Figure 6.37. 12-bit Color Depth YC Mux 4:2:2 Embedded Sync Dual Edge Timing (DRA = 1, YCSWAP = 0)
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 69
7. Design Recommendations
7.1. Power Supply Decoupling
Designers should include decoupling and bypass capacitors at each power signal in the layout. These are shown
schematically in Figure 7.1. Connections in one group (such as AVDD33) can share C2, C3, and the ferrite, with each pin
having a separate C1 placed as close to the pin as possible. Figure 7.2 is representative of the various types of power
connections on the port processor.
The recommended impedance of the ferrite is 10 or more in the frequency range of 1 to 2 MHz.
C2C1
L1
VDD Pin
GND
+3.3 V
C3
Figure 7.1. Decoupling and Bypass Schematic
C1
+3.3 V
Ferrite
Via to GND
VDD
C2
C3
L1
Figure 7.2. Decoupling and Bypass Capacitor Placement
7.2. Power Supply Control Timing and Sequencing
All power supplies in the SiI957n port processor are independent. However, identical supplies must be provided at the
same time. For example, all three AVDD33 supplies have to be turned on at the same time.
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
70 SiI-DS-1089-G
8. Package Information
8.1. ePad Requirements
The SiI957n device is packaged in a 176-pin, 20 mm × 20mm TQFP package with an exposed pad (ePad) that is used for
the electrical ground of the device and for improved thermal transfer characteristics. The ePad dimensions are
7.500 mm × 6.740 mm ±0.20 mm. Soldering the ePad to the ground plane of the PCB is required to meet package
power dissipation requirements at full speed operation, and to correctly connect the chip circuitry to electrical ground.
A clearance of at least 0.25 mm should be designed on the PCB between the edge of the ePad and the inner edges of
the lead pads to avoid the possibility of electrical short circuits.
The thermal land area on the PCB may use thermal vias to improve heat removal from the package. These thermal vias
also double as the ground connections of the chip and must attach internally in the PCB to the ground plane. An array
of vias should be designed into the PCB beneath the package. For optimum thermal performance, the via diameter
should be 12 mils to 13 mils (0.30 mm to 0.33 mm) and the via barrel should be plated with 1-ounce copper to plug the
via. This design helps to avoid any solder wicking inside the via during the soldering process, which may result in voids
in solder between the pad and the thermal land. If the copper plating does not plug the vias, the thermal vias can be
tented with solder mask on the top surface of the PCB to avoid solder wicking inside the via during assembly. The solder
mask diameter should be at least 4 mils (0.1 mm) larger than the via diameter.
Package stand-off when mounting the device also needs to be considered. For a nominal stand-off of approximately
0.1 mm, the stencil thickness of 5 mils to 8 mils should provide a good solder joint between the ePad and the thermal
land.
Figure 8.1 on the next page shows the package dimensions of the SiI957n port processor.
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 71
8.2. Package Dimensions
These drawings are not to scale. All dimensions are in millimeters.
TOP VIEW
176
44
133
b
e
Pin 1
Identifier
A A
D1
D
E1E
7.500 ± 0.20
6.740 ± 0.20
1
D2
89
132
E2
45
88
A
B
D
0.20 H A–B D
0.20 H A–B D
0.07 C A–B D
MS S
SECTION A-A
L
S
R1
R2
GAGE PLANE
0.25
4X
4X
H
SIDE VIEW
SEATING PLANE
C
0.08 C
A1
A2
A
0.05 S
L1
DETAIL A
DETAIL B
DETAIL A DETAIL B
C
JEDEC Package Code MS-026
Item
Description
Min
Typ
Max
Item
Description
Min
Typ
Max
A
Thickness
1.00
1.10
1.20
b
Lead width
—
0.16
—
A1
Stand-off
0.05
0.10
0.15
C
Lead thickness
0.09
—
0.20
A2
Body thickness
0.95
1.00
1.05
e
Lead pitch
0.40 BSC
D
Footprint
22.00 BSC
L
Lead foot length
0.45
0.60
0.75
E
Footprint
22.00 BSC
L1
Total lead length
1.00 REF
D1
Body size
20.00 BSC
R1
Lead radius, inside
0.08
—
—
E1
Body size
20.00 BSC
R2
Lead radius, outside
0.08
—
0.20
D2
—
—
17.20
—
S
Lead horizontal run
0.20
—
—
E2
—
—
17.20
—
Figure 8.1. Package Diagram
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
72 SiI-DS-1089-G
8.3. Marking Specification
Figure 8.2 through Figure 8.4 show the marking diagrams of SiI9573 and SiI9575. These drawings are not to scale.
SiI957
n
CTUC
LLLLLL.LL-L
YYWW
XXXXXXX
Logo
Silicon Image Part Number
Lot # (= Job#)
Date code
Trace code
Pin 1 location
Product
Designation
SiIxxxxrpppp-sXXXX
Package Type
Revision
Special
Designation
Speed
Figure 8.2. SiI957n Marking Diagram
Pin 1 Indicator
DATECODE
@
SiI9573CTUC
Region/Country
of Origin
Figure 8.3. Alternate SiI9573 Marking Diagram
Pin 1 Indicator
DATECODE
@
SiI9575CTUC
Region/Country
of Origin
Figure 8.4. Alternate SiI9575 Marking Diagram
8.4. Ordering Information
Production Part Numbers:
Device
Part Number
Standard
SiI9573CTUC
With ViaPort Matrix Switch
SiI9575CTUC
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1089-G 73
References
Standards Documents
This is a list of standards abbreviations appearing in this document, and references to their respective specifications
documents.
Abbreviation
Standards publication, organization, and date
HDMI
High Definition Multimedia Interface, Revision 1.4a, HDMI Licensing, LLC, March 2010
HCTS
HDMI Compliance Test Specification, Revision 1.4a, HDMI Licensing, LLC, March 2010
HDCP
High-bandwidth Digital Content Protection, Revision 1.4, Digital Content Protection, LLC; July 2009
DVI
Digital Visual Interface, Revision 1.0, Digital Display Working Group; April 1999
E-EDID
Enhanced Extended Display Identification Data Standard, Release A Revision 1, VESA; Feb. 2000
E-DID IG
VESA EDID Implementation Guide, VESA, June 2001
EDDC
Enhanced Display Data Channel Standard, Version 1.1, VESA; March 2004
MHL
MHL (Mobile High-Definition Link) Specification, Version 1.2, MHL, LLC, June 2010
Standards Groups
For information on the specifications that apply to this document, contact the responsible standards groups appearing
on this list.
Standards Group
Web URL
ANSI/EIA/CEA
http://global.ihs.com
VESA
http://www.vesa.org
HDCP
http://www.digital-cp.com
DVI
http://www.ddwg.org
HDMI
http://www.hdmi.org
MHL
http://www.mhlconsortium.org
Lattice Semiconductor Documents
This is a list of the related documents that are available from your Lattice Semiconductor sales representative. The
Programmer’s Reference requires an NDA with Lattice Semiconductor.
Document
Title
SiI-PR-1054
SiI9573, SiI9575, and SiI9523 Port Processor Programmer’s Reference
SiI-PR-0041
CEC Programming Interface (CPI) Programmer’s Reference
Technical Support
For assistance, submit a technical support case at www.latticesemi.com/techsupport.
SiI9573 and SiI9575 Port Processor
Data Sheet
© 2010-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
74 SiI-DS-1089-G
Revision History
Revision G, April 2017
Updated Marking Specification as per PCN13A16.
Revision F, March 2016
Updated to latest template.
Revision F, December 2013
Added 4K × 2K 50/60 FPS support.
Added new section on Support for UltraHD resolution at 50P/60P frames per second.
Revision E, September 2013
Removed statement of “only” on OSD resolution limitations in On-screen Display Controller section.
Added Note 2 and updated to Note 3 in Table 3.2. Updated current values in Table 3.11: IAVDDI13 from 240 to 250,
IAVDDI33 from 330 to 345, and ICVCC13 from 650 to 680 mA.
Updated Note 3 in Table 3.11 from “three 225 MHz” to “six 300 MHz.”
Revision D, May 2013
Added information about I2C setup time.
Revision C, January 2013
Updated OSD video support and SBVCC5 voltage measurement; added VS insertion description.
Revision B, August 2012
Updated 3D L/R section, and Table 7; global grammatical changes.
Revision A, January 2012
First production release.
