TECHNICAL DATA IN74HC10 Triple 3-Input NAND Gate High-Performance Silicon-Gate CMOS The IN74HC10 is identical in pinout to the LS/ALS10. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HC10N Plastic IN74HC10D SOIC TA = -55 to 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs PIN 14 =VCC PIN 7 = GND Output A B C Y L X X H X L X H X X L H H H H L X = don't care 43 IN74HC10 MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin 20 mA IOUT DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 C 260 C VOUT IIN Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC =4.5 V VCC =2.0 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 44 IN74HC10 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC V 25 C to -55C 85 C 125 C Unit VOUT=0.1 V or VCC-0.1 V IOUT 20 A 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V Maximum Low Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V Minimum High-Level Output Voltage VIN=VIH or VIL IOUT 20 A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN=VIH IOUT 4.0 mA IOUT 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 Symbol Parameter VIH Minimum High-Level Input Voltage VIL VOH Test Conditions VIN=VIH or VIL IOUT 4.0 mA IOUT 5.2 mA VOL Guaranteed Limit Maximum Low-Level Output Voltage VIN=VIH IOUT 20 A V IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 0.1 1.0 1.0 A ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0A 6.0 2.0 20 40 A 45 IN74HC10 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbol Parameter V 25 C to -55C 85C 125C Unit tPLH, tPHL Maximum Propagation Delay, Input A,B or C to Output Y (Figures 1 and 2) 2.0 4.5 6.0 95 19 16 120 24 20 145 29 25 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns - 10 10 10 pF CIN Maximum Input Capacitance Power Dissipation Capacitance (Per Gate) CPD Typical @25C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms 25 Figure 2. Test Circuit EXPANDED LOGIC DIAGRAM (1/3 of the Device) 46 pF