1
LTC1153
D
U
ESCRIPTIO
S
FEATURE
Auto-Reset
Electronic Circuit Breaker
Programmable Trip Delay: 15µs to >100ms
Programmable Trip Current: 1mA to >20A
Programmbale Auto-Reset Time: 1ms to >10 sec.
4.5V to 18V Supply Range
Drives Low R
DS(ON)
N-Channel MOSFETs
Status Output Indicates Fault Condition
Thermal Trip with PTC Thermistor
8µA I
Q
in Standby Mode
No External Charge Pump Capacitors
Available in 8-Pin SOIC
The LTC1153 electronic circuit breaker drives a low cost
N-channel MOSFET to interrupt power to a sensitive
electronic load in the event of an over-current condition.
The breaker remains tripped for a period of time set by an
external timing capacitor and then is automatically reset.
This cycle continues until the over-current condition is
removed, protecting both the sensitive load and the
MOSFET switch.
The trip current, trip delay time and auto-reset period are
programmable over a wide range to accommodate a
variety of load impedances. An active high shutdown input
is also provided and interfaces directly to a PTC thermistor
for thermal circuit breaking. An open-drain output is
provided to report breaker status to the µP.
The LTC1153 is available in both 8-pin DIP and 8-pin SOIC
packages.
U
S
A
O
PPLICATI
Power Bus Circuit Breaker
SCSI Termination Power Protection
Regulator Over-Current Protection
Battery Short-Circuit Protection
DC Motor Stall Protection
Sensitive System Power Interrupt
U
A
O
PPLICATITYPICAL
Trip Delay Time
5V/1A Electronic Circuit Breaker with 1ms Trip Delay,
200ms Auto-Reset Period and 70°C Thermal Shutdown
CIRCUIT BREAKER CURRENT (A)
1
0.01
TRIP DELAY (ms)
10
10 100
LTC1153 • TA02
1
0.1
R
SEN
= 0.1
R
D
= 100k
C
D
= 0.01µF
IN
C
T
STATUS
GND
VS
DS
G
SHUTDOWN
LTC1153
C
D
0.01µFR
D
100k *R
SEN
0.1
IRLR024
51k
SENSITIVE
5V LOAD
**70°C
PTC
51k
5V
TO µP
C
T
0.22µF
ON/OFF
ALL COMPONENTS SHOWN ARE SURFACE MOUNT.
IMS026 INTERNATIONAL MANUFACTURING SERVICE, INC. (401) 683-9700
RL2006-100-70-30-PT1 KEYSTONE CARBON COMPANY (814) 781-1591
*
**
LTC1153 • TA01
Z5U
2
LTC1153
LTC1153C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
S
Supply Voltage 4.5 18 V
I
Q
Quiescent Current OFF V
S
= 5V, V
IN
= 0V 8 20 µA
I
Q
Quiescent Current ON V
S
= 5V, V
IN
= 5V 85 120 µA
I
Q
Quiescent Current ON V
S
=12V, V
IN
= 5V 180 400 µA
V
INH
Input High Voltage 2V
V
INL
Input Low Voltage 0.8 V
I
IN
Input Current 0
V
< V
IN
< V
S
±1µA
C
IN
Input Capacitance 5pF
V
CT
Timing Capacitor Threshold Voltage V
S
= 5V 2.1 2.5 2.9 V
V
S
= 12V 2.0 2.6 3.2 V
I
CT
Timing Capacitor Current V
S
= 12V 3.0 4.2 6.0 µA
V
SDH
Shutdown Input High Voltage 2V
V
SDL
Shutdown Input Low Voltage 0.8 V
I
SD
Shutdown Input Current 0V < V
IN
< V
S
±1µA
V
SEN
Drain Sense Threshold Voltage 80 100 120 mV
75 100 125 mV
I
SEN
Drain Sense Input Current 0V < V
SEN
< V
S
±0.1 µA
A
U
G
W
A
W
U
W
ARBSOLUTEXI T
I
S
Supply Voltage ........................................................ 22V
Input Voltage ..................... (V
S
+ 0.3V) to (GND – 0.3V)
Timing Capacitor Voltage... (VS + 0.3V) to (GND – 0.3V)
Gate Voltage ....................... (VS + 24V) to (GND – 0.3V)
Status Output Voltage.............................................. 15V
Current (Any Pin).................................................. 50mA
Operating Temperature
LTC1153C .............................................. 0°C to 70°C
Storage Temperature Range ................. 65°c to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
ELECTRICAL CHARACTERISTICS VS = 4.5V to 18V, TA = 25°C, CT = 0.1µF, VSD = 0V unless otherwise noted.
WU
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
S8 PART MARKING
ORDER PART
NUMBER
LTC1153CN8
T
JMAX
= 100°C, θ
JA
= 150°C/W
LTC1153CS8
1153
T
JMAX
= 100°C, θ
JA
= 130°C/W (N8)
1
2
3
4
8
7
6
5
TOP VIEW
IN
TIMING CAP
STATUS
GND
V
S
DRAIN SENSE
GATE
SHUTDOWN
N8 PACKAGE
8-LEAD PLASTIC DIP
LTC1153 • PO01
1
2
3
4
8
7
6
5
TOP VIEW
V
S
DRAIN SENSE
GATE
SHUTDOWN
TIMING CAP
STATUS
GND
S8 PACKAGE
8-LEAD PLASTIC SOIC
IN
LTC1154 • PO02
3
LTC1153
LTC1153C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
GATE
– V
S
Gate Voltage Above Supply V
S
= 5V 6.0 7.0 9.0 V
V
S
= 6V 7.5 8.3 15.0 V
V
S
= 12V 15.0 18.0 25.0 V
V
STAT
Status Output Low Voltage I
STAT
= 400µA0.05 0.4 V
I
STAT
Status Output Leakage Current V
STAT
= 12V 1µA
t
ON
Turn-ON Time V
S
= 5V, C
GATE
= 1000pF
Time for V
GATE
> V
S
+ 2V 30 110 300 µs
Time for V
GATE
> V
S
+ 5V 100 450 1000 µs
V
S
= 12V, C
GATE
= 1000pF
Time for V
GATE
> V
S
+ 5V 20 80 200 µs
Time for V
GATE
> V
S
+ 10V 50 160 500 µs
t
OFF
Turn-OFF Time V
S
= 5V, C
GATE
= 1000pF
Time for V
GATE
< 1V 10 36 60 µs
V
S
= 12V, C
GATE
= 1000pF
Time for V
GATE
< 1V 10 28 60 µs
t
TD
Minimum Trip Delay V
S
= 5V, C
GATE
= 1000pF
Time for V
GATE
< 1V 5 25 40 µs
V
S
= 12V, C
GATE
= 1000pF
Time for V
GATE
< 1V 5 23 40 µs
t
SD
Shutdown Turn-OFF Time V
S
= 5V, C
GATE
= 1000pF
Time for V
GATE
< 1V 17 40 µs
V
S
= 12V, C
GATE
= 1000pF
Time for V
GATE
< 1V 13 35 µs
ELECTRICAL CHARACTERISTICS VS = 4.5V to 18V, TA = 25°C, CT = 0.1µF, VSD = 0V unless otherwise noted.
The denotes specifications which apply over the operating temperature range.
CCHARA TERISTICS
UW
AT
Y
P
I
CALPER
F
O
RC
E
SUPPLY VOLTAGE (V)
0
0
SUPPLY CURRENT (µA)
5
15
20
25
50
35
515
LTC1153 • TPC01
10
40
45
30
10 20
V
IN
= 0V
T
A
= 25°C
Standby Supply Current Supply Current ON
SUPPLY VOLTAGE (V)
0
4
VGATE – VS (V)
6
10
12
14
24
18
510
LTC1153 • TPC03
8
20
22
16
15 20
MOSFET Switch Gate Voltage
SUPPLY VOLTAGE (V)
0
0
SUPPLY CURRENT (µA)
100
300
400
500
1000
700
510
LTC1153 • TPC02
200
800
900
600
15 20
T
A
= 25°C
4
LTC1153
CCHARA TERISTICS
UW
AT
Y
P
I
CALPER
F
O
RC
E
Input Threshold Voltage Drain Sense Threshold Voltage Auto-Reset Period
Supply Current ON Input ON Threshold Voltage
SUPPLY VOLTAGE (V)
0
0.4
INPUT THRESHOLD VOLTAGE (V)
0.6
1.0
1.2
1.4
2.4
1.8
510
LTC1153 • TPC04
0.8
2.0
2.2
1.6
15 20
V
ON
V
OFF
MOSFET Gate Turn-OFF Time Built-In Trip Delay
Standby Supply Current
TEMPERATURE (°C)
–50
0
SUPPLY CURRENT (µA)
5
15
20
25
50
35
050 75
LTC1153 • TPC10
10
40
45
30
–25 25 100 125
V
IN
= 0V
V
S
= 18V
V
S
= 5V
TEMPERATURE (°C)
–50
0
SUPPLY CURRENT (µA)
100
300
400
500
1000
700
050 75
LTC1153 • TPC11
200
800
900
600
–25 25 100 125
V
IN
= 5V
V
S
= 12V
V
S
= 5V
TEMPERATURE (°C)
–50
0.4
INPUT THRESHOLD VOLTAGE (V)
0.6
1.O
1.2
1.4
2.4
1.8
050 75
LTC1153 • TPC12
0.8
2.0
2.2
1.6
–25 25 100 125
V
S
= 18V
V
S
= 5V
SUPPLY VOLTAGE (V)
0
50
DRAIN SENSE THRESHOLD VOLTAGE (mV)
60
80
90
100
150
120
510
LTC1153 • TPC05
70
130
140
110
15 20
SUPPLY VOLTAGE (V)
0
0.01
RESET PERIOD (SEC)
1
10
510 20
LTC1153 • TPC06
0.1
15
T
A
= 25°C
3.3µF
1µF
0.1µF
0.033µF
0.33µF
MOSFET Gate Turn-ON Time
SUPPLY VOLTAGE (V)
0
0
TURN ON TIME (µs)
100
300
400
500
1000
700
510
LTC1153 • TPC07
200
800
900
600
15 20
VGS = 5V
VGS = 2V
CGATE = 1000pF
SUPPLY VOLTAGE (V)
0
0
TRIP TIME (µs)
5
15
20
25
50
35
515
LTC1153 • TPC09
10
40
45
30
10 20
C
GATE
= 1000pF
TIME FOR V
GATE
< 1V
V
SEN
= V
S
– 1V
NO EXTERNAL DELAY
SUPPLY VOLTAGE (V)
0
0
TURN OFF TIME (µs)
5
15
20
25
50
35
515
LTC1153 • TPC08
10
40
45
30
10 20
C
GATE
= 1000pF
TIME FOR V
GATE
< 1V
5
LTC1153
Auto-Reset Time*Shutdown Threshold Voltage MOSFET Gate Drive Current
CCHARA TERISTICS
UW
AT
Y
P
I
CALPER
F
O
RC
E
TEMPERATURE (°C)
–50
0.4
SHUTDOWN THRESHOLD VOLTAGE (V)
0.6
1.O
1.2
1.4
2.4
1.8
050 75
LTC1153 • TPC13
0.8
2.0
2.2
1.6
–25 25 100 125
V
S
= 18V
V
S
= 5V
TEMPERATURE (°C)
–25
0.1
1
10
25
LTC1153 • TPC14
AUTO-RESET TIME (s/µF)
–50 1250 50 75 100
*SECONDS OF DELAY
PER µF C
T
V
S
= 5V
V
S
= 12V
V
S
= 18V
PI FU CTIO S
U
UU
Input and Shutdown Pins
The LTC1153 input pin is active high and activates all of the
protection and charge pump circuitry when switched ON.
The shutdown pin is designed to break the circuit if a
secondary fault condition (over temperature, etc.) is de-
tected. The LTC1153 logic and shutdown inputs are high
impedance CMOS gates with ESD protection diodes to
ground and supply and therefore should not be forced
beyond the power supply rails. The shutdown pin should
be connected to ground when not in use.
Timing Capacitor Pin (Auto-Reset Timer)
The small capacitor charging current (4.2µA) produces
large delays with relatively small valued capacitors, but
care must be taken to ensure that this current is not
shunted to ground through a leaky capacitor or printed
circuit board trace. The timing capacitor voltage is sensed
by a high impedance CMOS comparator input with ESD
clamp diodes to ground and supply and therefore should
not be forced beyond the power supply rails. This pin can
be grounded if the auto-reset function is not used.
MOSFET Gate Drive Pin
The MOSFET gate drive pin is either driven to ground when
the switch is turned OFF or driven above the supply rail
when the switch is turned ON. This pin is a relatively high
impedance when driven above the rail (the equivalent of a
few hundred k). Care should be taken to minimize any
loading of this pin by parasitic resistance to ground or
supply.
Supply Pin
The supply pin of the LTC1153 serves two vital purposes.
The first is obvious: it powers the input, gate drive, regu-
lation and protection circuitry. The second purpose is less
obvious: it provides a Kelvin connection to the top of the
drain sense resistor for the internal 100mV reference.
The LTC1153 is designed to be
continuously powered
so
that the gate of the MOSFET is actively driven at all times.
If it is necessary to remove power from the supply pin and
then re-apply it, the input pin (or enable pin) should be
cycled a few milliseconds
after
the power is re-applied to
reset the input latch and protection circuitry. Also, the
input and enable pins should be isolated with 10k resistors
to limit the current flowing through the ESD protection
diodes to the supply pin.
The supply pin of the LTC1153 should never be forced
below ground as this may result in permanent damage to
the device.
A 300 resistor should be inserted in series
with the ground pin if negative supply voltage transients
are anticipated.
GATE VOLTAGE ABOVE SUPPLY (V)
1
GATE DRIVE CURRENT (µA)
10
100
1000
0 8 12 16
0.1 420
LTC1153 • TPC15
V
S
= 18V
T
A
= 25°C
V
S
= 12V
V
S
= 5V
6
LTC1153
PI FU CTIO S
U
UU
Drain Sense Pin
The drain sense pin is compared against the supply pin
voltage.
If the voltage at this pin is more than 100mV
below
the supply pin, the input latch will trip and the
MOSFET switch will be turned off.
This pin is also a high impedance CMOS gate with ESD
protection and therefore should not be forced beyond the
power supply rails.
Some loads, such as large supply capacitor, lamps, or
motors require high inrush currents. An RC time is added
between the sense resistor and the drain sense pin to
ensure that the drain sense circuitry does not false trigger
during start-up. This trip delay can be set from a few
microseconds to many seconds. However, very long de-
lays may put the MOSFET switch in risk of being destroyed
by a short-circuit condition. (see Applications Information
Section).
Status Pin
The status pin is an open-drain output which is driven low
whenever the breaker is tripped. A 51k pull-up resistor
should be connected between this output and a logic
supply. The status pins of multiple LTC1153s can be OR’d
together if independent fault sensing is not required. No
connection is required to this pin when not in use.
W
IDAGRA
B
L
O
C
K
GATE CHARGE
AND DISCHARGE
CONTROL LOGIC
SHUTDOWN
TTL-TO-CMOS
CONVERTER
OSCILLATOR
AND CHARGE
PUMP
FAST/SLOW
GATE CHARGE
LOGIC
FAULT DETECTION
AND STATUS
OUTPUT DRIVER
100mV
REFERENCE
COMP
ANALOG SECTION
INPUT
LATCH
R
S
GATE
SHUTDOWN
DRAIN
SENSE
ONE
SHOT
TTL-TO-CMOS
CONVERTER VOLTAGE
REGULATORS
ANALOG DIGITAL
GND
LOW STANDBY
CURRENT
REGULATOR
AUTO-RESET
TIMER
INPUT
TIMER
CAP
STATUS
VS
10µs
DELAY
LTC1153 • BD01
7
LTC1153
TEST CIRCUIT
S
TI I G DIAGRA
WW
U
LTC1153 OPERATIO
U
The LTC1153 is an electronic circuit breaker with built-in
MOSFET gate charge pump, over-current detection and
auto-reset circuitry. The LTC1153 consists of the follow-
ing functional blocks:
TTL and CMOS Compatible Inputs
The LTC1153 input and shutdown input have been de-
signed to accommodate a wide range of logic families.
Both input thresholds are set at about 1.3V with approxi-
mately 100mV of hysteresis.
A low standby current voltage regulator provides continu-
ous bias for the TTL-to-CMOS converter. The TTL-to-
CMOS converter output enables the rest of the circuitry. In
this way the power consumption is kept to a minimum in
the standby mode.
Auto-Reset Timer
An external timing capacitor, C
T
, is ramped up by a small
current whenever a fault is detected, i.e., the switch
latched off. When the timing capacitor ramps up to ap-
proximately 2.5V, the switch is turned back on and the
timing capacitor discharged. If the circuit breaker output
is still in an overload state, the breaker will latch off and this
cycle will continue until the fault condition is removed.
Internal Voltage Regulation
The output of the TTL-to-CMOS converter drives two
regulated supplies which power the low voltage CMOS
logic and analog blocks. The regulator outputs are isolated
from each other so that the noise generated by the charge
pump logic is not coupled into the 100mV reference or the
analog comparator.
Gate Charge Pump
Gate drive for the MOSFET switch is produced by an
adaptive charge pump circuit which generates a gate
voltage substantially higher than the power supply volt-
age. The charge pump capacitors are included on-chip and
therefore no external components are required to generate
the gate drive.
Drain Current Sense
The LTC1153 is configured to sense the current flowing
into the drain of an N-channel MOSFET switch. An internal
100mV reference is compared to the drop across a sense
resistor (typically 0.002 to 0.10) in series with the
drain lead. If the drop across this resistor exceeds the
internal 100mV threshold, the input latch is reset and the
gate is quickly discharged via a relatively large N-channel
transistor.
OVER-CURRENT
(AUTO-CURRENT)NORMALOFF NOR-
MAL SHUT-
DOWN OFF
*90ms
*200µs
S1 CLOSED S1 OPEN
*TIMES FOR COMPONENTS SHOWN IN TEST CIRCUIT
LTC1153 • TD01
INPUT
OUTPUT
STATUS
TIMING
CAP
SHUT-
DOWN
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
SHUTDOWN
8
7
6
5
1
2
3
4
R
SEN
0.05
IRLZ24
OUTPUT
S1
110
C
P
0.01µF
R
D
100k
0.1µF
Z5U
51k
STATUS
INPUT
5V
LTC1153 • TC01
8
LTC1153
LTC1153 OPERATIO
U
Controlled Gate Rise and Fall Times
When the input is switched ON and OFF, the gate is
charged by the internal charge pump and discharged in a
controlled manner. The charge and discharge rates have
been set to minimize RFI and EMI emissions in normal
operation. If a short-circuit or current overload condition
is encountered, the gate is discharged very quickly (typi-
cally a few microseconds) by a large N-channel transistor.
Status Output Driver
The status circuitry continuously monitors the input and
the gate charge control logic. The open-drain output is
driven low when the input is turned ON and the breaker is
latched off. The status circuitry is reset along with the input
latch when the auto-reset circuitry retries the breaker or
the input is cycled low.
Figure 1. Protecting Resistive Loads
Figure 2. Protecting Inductive Loads
Large inductive loads (>0.1mH) may require diodes con-
nected directly across the inductor to safely divert the
stored energy to ground. Many inductive loads have these
diodes included. If not, a diode of the proper current rating
MOSFET and Load Protection
The LTC1153 protects the power MOSFET switch by
removing drive from the gate as soon as an over-current
condition is detected and breaking the circuit to the load.
Resistive and inductive loads can be protected with no
external time delay in series with the drain sense pin. High
inrush current loads, however, require that the trip delay
time be set long enough to start the load but short enough
to ensure the safety of the MOSFET.
Resistive Loads
Loads that are primarily resistive should be protected with
as short a delay as possible to minimize the amount of time
that the MOSFET switch or the load is subjected to an
overload condition. The drain sense circuitry has a built-
in trip delay of approximately 10µs to eliminate false
triggering by power supply or load transient conditions.
This delay is sufficient to “mask” short load current
transients and the starting of a small capacitor (<1µF) in
parallel with the load. The drain sense pin can therefore be
connected directly to the drain current sense resistor as
shown in Figure 1.
Inductive Loads
Loads that are primarily inductive, such as relays, sole-
noids and stepper motor windings should be protected
with as short a delay as possible to minimize the amount
of time that the MOSFET is subjected to an overload
condition. The built-in 10µs trip delay will ensure that the
breaker is not false-tripped by a supply or load transient.
No external delay components are required as shown in
Figure 2.
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
C
T
0.22µF
+
100µF
IRFZ24
15V
R
LOAD
12
12V
C
LOAD
1µF
0.036
LTC1153 • F01
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
C
T
0.22µF
+
100µF
IRFZ24
15V
12V, 1A
SOLENOID
12V
1N5400
0.036
LTC1153 • F02
9
LTC1153
should be connected across the load, as shown in Figure
2, to safely divert the stored energy.
Capacitive Loads
Large capacitive loads, such as complex electrical sys-
tems with large bypass capacitors, should be powered
using the circuit shown in Figure 3. The gate drive to the
power MOSFET switch is passed through an RC delay
network, R1 and C1, which greatly reduces the turn on
ramp rate of the switch. And since the MOSFET source
voltage follows the gate voltage, the load is powered
smoothly and slowly from ground. This dramatically re-
duces the start-up current flowing into the supply capaci-
tor/s which, in turn, reduces supply transients and allows
for slower activation of sensitive electrical loads. (Diode,
D1, provides a direct path for the LTC1153 protection
circuitry to quickly discharge the gate).
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Using the values shown in Figure 3, the start-up current is
less than 100mA and does not false-trip the breaker.
Lamp Loads
The inrush current created by a lamp during turn-on can be
10 to 20 times greater than the rated operating current.
The circuit shown in Figure 4 shifts the trip threshold up by
a factor of 11:1 (to 30A) for 100ms while the bulb is turned
on. The trip threshold then drops down to 2.7A after the
inrush current has subsided.
The RC network, R
D
and C
D
, in series with the drain sense
input should be set to trip based on the expected charac-
teristics of the load
after
start-up. With this circuit, it is
possible to power a large capacitive load and still react
quickly (10µs) to break the circuit if a short-circuit condi-
tion is encountered. The ramp rate at the output of the
switch as it lifts off ground is approximately:
dV/dt = (V
GATE
– V
TH
)/(R1 × C1)
And therefore the current flowing into the capacitor during
start-up is approximately:
I
START-UP
= C
LOAD
× dV/dt
BREAKER CURRENT (1 = SET CURRENT)
1
0.01
TRIP DELAY TIME (1 = RC)
10
10 100
LTC1153 • F05
1
0.1
Figure 5. Trip Delay Time vs Breaker Current
Selecting R
D
and C
D
Figure 5 is a graph of normalized breaker trip time versus
breaker current. This graph is used to select the two delay
components, R
D
and C
D
, which make up a simple RC delay
between the drain sense resistor and the drain sense input.
Figure 3. Powering Large Capacitive Loads
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
C
T
0.47µF
+
470µF
MTP3055E
15V
12V
0.036
LTC1153 • F03
C
D
0.01µF
R
D
1OOk
R1
1OOk
R2
1OOk
D1
1N4148
C1
0.33µF
+
C
LOAD
100µF
OUT
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
C
T
0.33µF
+
470µF
MTP3055EL
9.1V
12V
0.036
LTC1153 • F04
10k
1M 0.1µF
VN2222LL
100k
12V/1A
BULB
Figure 4. Lamp Driver with Delayed Protection
10
LTC1153
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
The Y axis of the graph is normalized to one RC time
constant. The X axis is normalized to the set current. (The
set current is defined as the current required to develop
100mV across the drain sense resistor).
Note that the trip delay time is shorter for increasing levels
of MOSFET current. This ensures that the total energy
dissipated by the MOSFET is always within the bounds
established by the manufacturer for safe operation. (See
MOSFET data sheet for further S.O.A. information).
Using a Speed-Up Diode
Another way to reduce the trip delay time is to “bypass”
the delay resistor with a small signal diode as shown in
Figure 6. The diode will engage when the drop across the
drain sense resistor exceeds about 0.7V, providing a direct
path to the sense pin and dramatically reducing the trip
delay time. The drain sense resistor value is selected to
limit the maximum DC breaker current to 4A.
Figure 7. Reverse Battery Protection
Current Limited Power Supplies
The LTC1153 requires at least 3.5V at the supply pin to
ensure proper operation. It is therefore necessary that the
supply to the LTC1153 be held higher than 3.5V at all
times, even when the output of the switch is short circuited
to ground. The output voltage of a current limited regulator
may drop very quickly during short-circuit and pull the
supply pin of the LTC1153 below 3.5V before the shut-
down circuitry has had time to respond and remove drive
from the gate of the power MOSFET. A supply filter should
be added as shown in Figure 8 which holds the supply pin
of the LTC1153 high long enough for the over-current
shutdown circuitry to respond and fully discharge the
gate, i.e., break the circuit.
Reverse Battery Protection
The LTC1153 can be protected against reverse battery
conditions by connecting a resistor in series with the
ground lead as shown in Figure 7. The resistor limits the
supply current to less than 50mA with –12V applied. Since
the LTC1153 draws very little current while in normal
operation, the drop across the ground resistor is minimal.
the 5V µP (or control logic) is protected by the 10k
resistors in series with the input and status pins. Figure 8. Supply Filter for Current Limited Supplies
Figure 6. Using a Speed-Up Diode
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
0.1
IRLR024
SHORT
CIRCUIT
0.1µF100k
1µF
LTC1153 • F08
*20
+
*47µF
+
10µF
1N4148
*SUPPLY FILTER COMPONENTS
+
100µF
5V/2A
REGULATOR
>7V
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
C
T
0.22µF
+
100µF
IRF530
15V
12V
0.036
LTC1153 • F06
0.01µF
1OOk
1N4148
LOAD
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
C
T
0.47µF
MTP12N06
15V
12V
0.05
LTC1153 • F07
LOAD
10k
300
5V
µP OR
CONTROL
LOGIC
+
10µF
10k
10k
120k
5V
11
LTC1153
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Five volt linear regulators with small output capacitors
are the most difficult to protect as they can “switch”
from a voltage mode to a current limited mode very
quickly. The large output capacitors on many switching
regulators, on the other hand, may be able to hold the
supply pin of the LTC1153 above 3.5V sufficiently long
that this extra filtering is not required.
TYPICAL APPLICATIO S
U
Over-Temperature Circuit Breaker
24V to 28V Over-Temperature Circuit Breaker
Over-Voltage Circuit Breaker
24V to 28V Over-Temperature Circuit Breaker
with Bootstrapped Supply
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
0.47µF
+
100µF
MTD3055E
12V
LTC1153 • TA03
12V
LOAD
51k
*RL3006-50-100-25-PT0 KEYSTONE
30k
5V
*PTC
THERMISTOR
(100°C)
5V
Because the LTC1153 is micropower in both the standby
and ON state, the voltage drop across the supply filter
is less than 2mV, and does not significantly alter the
accuracy of the 100mV drain sense threshold voltage.
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
0.47µF
+
100µF
MTP15N06E
24V TO 28V
LTC1153 • TA06
24V TO 28V
LOAD
5V
5V
30k
+
10µF
18V
100k
*PTC
THERMISTOR
(100°C)
6.2k
1N4148
KEYSTONE RL2006-100-100-30-PT.
MOUNT ON MOSFET OR LOAD HEAT SINK.
BOOTSTRAPPING REDUCES I
Q(OFF)
TO 60µA, I
Q(ON)
= 1mA.
*
**
51k
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
0.47µF
+
100µF
MTP12N06
24V TO 28V
LTC1153 • TA04
24V TO 28V
LOAD
51k
5V
5V
30k
*KEYSTONE RL2006-100-100-30-PT.
MOUNT ON MOSFET OR LOAD HEAT SINK.
+
10µF
18V
3k
*PTC
THERMISTOR
(100°C)
12
LTC1153
U
SA
O
PPLICATITYPICAL
12V Lamp Driver/Circuit Breaker
with Auto-Reset Relay Driver with Over-Current Protection
and Status Feedback
Logic Controlled Battery Switch with Reverse Battery Protection,
Ramped Turn-On and 10µA Standby Current
SCSI Termination Power 1A Circuit Breaker with
Auto-Reset and Ramped Turn-On
IN
CT
STATUS
GND
VS
DS
G
SD
LTC1153
0.33µF
+470µF
IRFZ34
12V
12V
0.02
LTC1153 • TA07
10k
1M 0.1µF
VN2222LL
100k
12V/2A
BULB
5V
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
1µF
MTD3055E
15V
12V
LTC1153 • TA08
5V 0.01µF
+
100µF
10k
1N4148
1N4001
20.02
TO 12V
LOAD
COIL CURRENT LIMITED TO 350mA
CONTACT CURRENT LIMITED TO 5A
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
0.47µF
LTC1153 • TA10
51k
ON/OFF
STATUS
Si9956DY
1N4148
100k
100k
0.22µF
+
47µF/16V
SWITCHED
BATTERY
4 TO 6
CELLS
0.05Ω
+
300
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
0.47µF
Z5U
5V
LTC1153 • TA09
51k 0.1µF
+
100µF
47µF
ON/OFF
STATUS
+
10k
1N4148
MTD3055EL
1N4148
100k
100k
0.22µF
1N5817
+
10µF
4.25V/1A
20
0.1
13
LTC1153
“4 Cell-to-5V” Regulator with 2A Current Limit, Auto-Reset,
Ramped Turn-On and 10µA Standby Current
U
SA
O
PPLICATITYPICAL
12V Step-Up Regulator with Soft Start, Auto-Reset Circuit Breaker (Pre-Regulator),
Status Feedback and 10µA Standby Current
12V Step-Up Regulator with 1A Circuit Breaker (Post Regulator), Breaker Status
Feedback and Ramped Output
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
0.47µF
LTC1153 • TA11
51k
ON/OFF
STATUS
1N4148
100k
100k
0.22µF
+
100µF
4-CELL
BATTERY
PACK
200pF
10k
8
LT1431
7
3
4
1
56
0.05
IRLR024
5V/1A
+
470µF
ESR < 0.5
+
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
0.47µF
Z5U
5V
LTC1153 • TA12
51k 0.22µF
+
470µF
47µF
ON/OFF
STATUS
+
100k
1N4148
IRLZ24
1N4148
100k
100k
0.22µF
+
330µF
12V/1A
20
150µF
+
V
IN
V
SW
FB
GND
V
C
LT1070
1k
1µF
13
5
4
2
50µH
10.72k
1%
1.24k
1%
1N5820
0.02
IN
C
T
STATUS
GND
VS
DS
G
SD
LTC1153
0.47µF
Z5U
5V
LTC1153 • TA13
51k 0.1µF
ON/OFF
STATUS
1N4148
100k
100k
0.22µF
+
330µF0.1
+
V
IN
V
SW
FB
GND
V
C
LT1070
1k
1µF
13
5
4
2
50µH
10.72k
1%
1.24k
1%
1N5820
10k
1N4148
IRF530
12V/1A
47µF
16V
12V
+
150µF
(12V)
14
LTC1153
U
SA
O
PPLICATITYPICAL
Auto-Reset Circuit Breaker with Programmable (1-6) Number of
Retries Using Binary Counter
DC Motor Driver with Stall-Current Circuit Breaking (Auto-Reset),
Thermal Overload Shutdown and 10µA Standby Current
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
0.47µF
Z5U
5V TO 18 V
LTC1153 • TA14
ON/OFF
1N4148
100k
100k
0.22µF
+
100µF0.1
+
IRF530
OUTPUT
47µF
12V
ABCDGND
LOAD V
CC
UP
CARRY
Q
D
15 1 10 9 8 14
INPUTS*
*SET WITH 3-BIT BINARY WORD = 7 – N
100k
5
12
FAULT
7
41611
5V
74C193
IN
C
T
STATUS
GND
V
S
DS
G
SD
LTC1153
0.33µF
LTC1153 • TA15
0.02
IRFZ34
+
470µF
10k
51k
240
2N2907
5V
MOTOR
FAULT
LED
ON/OFF
0.1µF100k
12V
12V
120k
*PTC
THERMISTOR
(100°C) M1N5400
*RL3006-50-100-25-PTO KEYSTONE
MOUNT ON MOTOR CHASIS OR MOSFET HEAT SINK
15
LTC1153
PACKAGE DESCRIPTIO
U
N8 Package
8-Lead Plastic Lead
N8 0392
0.045 ± 0.015
(1.143 ± 0.381)
0.100 ± 0.010
(2.540 ± 0.254)
0.065
(1.651)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.125
(3.175)
MIN
0.009 – 0.015
(0.229 – 0.381)
0.300 – 0.320
(7.620 – 8.128)
0.325 +0.025
0.015
+0.635
0.381
8.255
()
12 34
8765
0.250 ± 0.010
(6.350 ± 0.254)
0.400
(10.160)
MAX
S8 Package
8-Lead Plastic SOIC
1234
0.150 – 0.157
(3.810 – 3.988)
8765
0.189 – 0.197
(4.801 – 5.004)
0.228 – 0.244
(5.791 – 6.197)
0.010 – 0.020
(0.254 – 0.508)
0.016 – 0.050
0.406 – 1.270
× 45°
0°– 8° 
TYP
0.008 – 0.010
(0.203 – 0.254)
SO8 0392
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
16
LTC1153
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900
FAX
: (408) 434-0507
TELEX
: 499-3977
LT/GP 1092 10K REV 0
LINEAR TECHNOLOGY CORPORATION 1992
U.S. Area Sales Offices
NORTHEAST REGION CENTRAL REGION NORTHWEST REGION
Linear Technology Corporation Linear Technology Corporation Linear Technology Corporation
One Oxford Valley Chesapeake Square 782 Sycamore Dr.
2300 E. Lincoln Hwy.,Suite 306 229 Mitchell Court, Suite A-25 Milpitas, CA 95035
Langhorne, PA 19047 Addison, IL 60101 Phone: (408) 428-2050
Phone: (215) 757-8578 Phone: (708) 620-6910 FAX: (408) 432-6331
FAX: (215) 757-5631 FAX: (708) 620-6977
SOUTHEAST REGION SOUTHWEST REGION
Linear Technology Corporation Linear Technology Corporation
17060 Dallas Parkway 22141 Ventura Blvd.
Suite 208 Suite 206
Dallas, TX 75248 Woodland Hills, CA 91364
Phone: (214) 733-3071 Phone: (818) 703-0835
FAX: (214) 380-5138 FAX: (818) 703-0517
International Sales Offices
FRANCE KOREA TAIWAN
Linear Technology S.A.R.L. Linear Technology Korea Branch Linear Technology Corporation
Immeuble "Le Quartz" Namsong Building, #505 Rm. 801, No. 46, Sec. 2
58 Chemin de la Justice Itaewon-Dong 260-199 Chung Shan N. Rd.
92290 Chatenay Mallabry Yongsan-Ku, Seoul Taipei, Taiwan, R.O.C.
France Korea Phone: 886-2-521-7575
Phone: 33-1-46316161 Phone: 82-2-792-1617 FAX: 886-2-562-2285
FAX: 33-1-46314613 FAX: 82-2-792-1619
GERMANY SINGAPORE UNITED KINGDOM
Linear Techonolgy GMBH Linear Technology Pte. Ltd. Linear Technology (UK) Ltd.
Untere Hauptstr. 9 101 Boon Keng Road The Coliseum, Riverside Way
D-8057 Eching #02-15 Kallang Ind. Estates Camberley, Surrey GU15 3YL
Germany Singapore 1233 United Kingdom
Phone: 49-89-319741-0 Phone: 65-293-5322 Phone: 44-276-677676
FAX: 49-89-3194821 FAX: 65-292-0398 FAX: 44-276-64851
JAPAN
Linear Technology KK
5F YZ Building
4-4-12 Iidabashi Chiyoda-Ku
Tokyo, 102 Japan
Phone: 81-3-3237-7891
FAX: 81-3-3237-8010
World Headquarters
Linear Technology Corporation
1630 McCarthy Blvd.
Milpitas, CA 95035-7487
Phone: (408) 432-1900
FAX: (408) 434-0507
10/92