100LVEL11M8 - Fairchild Semiconductor

January 2003

Revised January 2003

100LVEL11 3.3V ECL 1:2 Differential Fanout Buffer

100LVEL11

3.3V ECL 1:2 Differential Fanout Buffer

General Description

The 100LVEL11 is a low voltage 1:2 differential fanout

buffer. One differential input signal is fanned out to two

identical di fferential ou tputs. By supplying a cons tant refer-

ence level to one input pin a single ended input condition is

created.

With inputs Open or both inputs at VEE, the differential Q

outputs default LOW and Q outputs default HIGH.

The 100 series is temperature compensated.

Features

■Typical propagation delay of 330 ps

■Typical IEE of 24 mA

■Typical skew of 5 ps between outputs

■Internal pull-down resistors on D

■Fairchild MSOP-8 package is a drop-in replacement to

ON TSSOP-8

■Meets or exceeds JEDEC specification EIA/JESD78 IC

latch-up tests

■Moisture Sensitivity Level 1

■ESD Perform ance:

Human Body Mod el > 2000V

Machine Model > 200V

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing suffix let te r “X” to the ord ering code.

Connection Diagram

Top View

Pin Descriptions

Logic Diagram

Order Number Package Product Package DescriptionNumber Code

Top Mark

100LVEL11M M08A KVL11 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

100LVEL11M8

(Preliminary) MA08D KV11 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide

Pin Name Description

Q0, Q0, Q1, Q1ECL Data Outputs

D, D ECL Data Inputs

VCC Positive Supply

VEE Negative Supp ly

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100LVEL11

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “Absolute Maximum Ratings” are thos e values bey ond which

the saf ety of the device cannot be gu aranteed. Th e device shoul d not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended Oper ating Co ndition s” table will def ine the condit ions

for actu al device operation.

LVPECL DC Electrical Characteristics VCC = 3.3V; VEE = 0.0V (Note 2)

Note 2: Input and output parameters vary 1 to 1 with VCC. VEE can vary ± 0.3V.

Note 3: Outputs ar e t erminat ed t hrough a 50Ω Re sistor to VCC − 2.0V.

Note 4: VIHCMR m inim um var ies 1 to 1 w ith VEE. VIHCMR m aximum varies 1-to-1 with VCC. The VIHCMR range is referenced to the most positive side of the

differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltag e lies between VPPMIN and

1V.

Note 5: Absolute v alue of the input H IG H and LOW c urrent sho uld not exc eed the absolute va lue of the sta t ed M i n or Max sp ec if ic at ion.

Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than

500LFPM maintained.

PECL Supply Voltage (VCC) VEE = 0V 0.0V to +8.0V

NECL Supply Voltage (VEE) VCC = 0V 0.0V to −8.0V

PECL DC In put Voltage (VI) VEE = 0V 0.0V to +6.0V

NECL DC Input V oltage (VI) VCC = 0V 0.0V to −6.0V

DC Output Current (IOUT)

Continuous 50 mA

Surge 100 mA

Storage Temperature (TSTG)−65°C to +150°C

PECL Power Supply Operating

(VEE = 0V) VCC = 3.0V to 3.8V

NECL Power Supply Operating

(VCC = 0V) VEE = −3.8V to −3.0V

Free Air Oper ating Te mperature (TA)−40°C to +85°C

Symbol Parameter −40°C 25°C 85°CUnits

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 24 28 24 28 25 30 mA

VOH Output HIGH Voltage (Note 3) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV

VOL Output LOW Voltage (Note 3) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV

VIH Input HIGH Voltage (Single Ended) 2135 2420 2135 2420 2135 2420 mV

VIL Input LOW Voltage (Single Ended) 1490 1825 1490 1825 1490 1825 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential) (Note 4)

VPP < 500m V 1.2 3.1 1.1 3.1 1.1 3.1 V

VPP ≥ 500m V 1.4 3.1 1.3 3.1 1.3 3.1

IIH Input HIGH Current (Note 5) 150 150 150 µA

IIL Input LOW Current (Note 5) D 0.5 0.5 0.5 µA

D−600 −600 −600

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100LVEL11

LVNECL DC Electrical Characteristics VCC = 0.0V; VEE = −3.3V (Note 6)

Note 6: Input and output parameters vary 1 to 1 with VCC. VEE can vary ±0.3V.

Note 7: Outputs are terminated through a 50Ω Resistor to VCC − 2.0V.

Note 8: VIHCMR minimum varies 1-to-1 with VEE. VIHCMR maximum varies 1 to 1 with VCC. The VIHCMR range is referenced to the most positive side of the

differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak volt age lies be tween VPPMIN and

1V.

Note 9: Absolute va lue of the input HIGH and LOW c urrent should no t e xceed the absolu te va lue of the st at ed Min or Ma x specification.

Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than

500LFP M maintained.

AC Electrical Characteristics VCC = 3.3V; VEE = 0.0V or VCC = 0.0V; VEE = −3.3V (Note 10)(Note 11)

Note 10: VEE can vary ±0.3V.

Note 11: Measured using a 750 mV input swing centered at VCC − 1.32V; 50% duty cycl e cl ock source ; tr = tf = 250 ps (20% - 80%) at fIN =1 MHz. All loading

with 50Ω to VCC − 2.0V.

Note 12: Within-device skew defined as identical transitions on similar paths through a device.

Note 13: D ut y cycle sk ew is th e difference between a tPLH and tPHL propagation delay thro ugh a dev ic e under ide nt ic al condit ions.

Symbol Parameter −40°C25°C85°CUnits

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 24 28 24 28 25 30 mA

VOH Output HIGH Voltage (Note 7) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV

VOL Output LOW Voltage (Note 7) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV

VIH Input HIGH Voltage (Single Ended) −1165 −880 −1165 −880 −1165 −880 mV

VIL Input LOW Voltage (Single Ended) −1810 −1475 −1810 −1475 −1810 -1475 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential) (Note 8)

VPP < 500mV −2.1 −0.2 −2.2 −0.2 −2.2 −0.2 V

VPP ≥ 500mV −1.9 −0.2 −2.0 −0.2 −2.0 −0.2

IIH Input HIGH Current (Note 9) 150 150 150 µA

IIL Input LOW Current (Note 9) D 0.5 0.5 0.5 µA

D−600 −600 −600

Symbol Parameter −40°C 25°C 85°CUnits Figure

Min Typ Max Min Typ Max Min Typ Max Number

fMAX Maximum Toggle Frequency 1 1 1 GHz

tPLH, tPHL Propagation Delay to Output 215 385 235 330 405 250 435 ps Figure 1

tSKEW Within Device Skew (Note 12) 5 20 5 20 5 20 ps

Duty Cycle Skew (Note 13) 5 20 5 20 5 20

tJITTER Cycle-to-Cycle Jitter TBD TBD TBD

VPP Input Swing 200 1000 200 1000 200 1000 mV Figure 1

tr, tfOutput Rise Times Q (20% to 80%) 120 320 120 320 120 320 ps Figure 2

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100LVEL11

Switching Waveforms

FIGURE 1. Differential to Differential Propagation Delay

FIGURE 2. Differential Output Edge Rates

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100LVEL11

Physical Dimensions inches (millimeters) unless otherwise noted

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M08A

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100LVEL11 3.3V ECL 1:2 Differential Fanout Buffer

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide

Package Number MA08D

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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