IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES FAST CMOS BUFFER CLOCK/DRIVER IDT49FCT805BT/CT FEATURES: DESCRIPTION: - - - - - - - - - - - This buffer/clock driver is built using advanced dual metal CMOS technology. The FCT805T is a non-inverting clock driver consisting of two banks of drivers. Each bank drives five output buffers from a standard TTL compatible input. This part has extremely low output skew, pulse skew, and package skew. The device has a "heart-beat" monitor for diagnostics and PLL driving. The monitor output is identical to all other outputs and complies with the output specifications in this document. - 0.5 MICRON CMOS Technology Guaranteed low skew < 500ps (max.) Very low duty cycle distortion < 600ps (max.) Low CMOS power levels TTL compatible inputs and outputs TTL level output voltage swings High drive: -32mA IOH, +48mA IOL Two independent output banks with 3-state control 1:5 fanout per bank "Heartbeat" monitor output ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Available in the following packages: * Commercial: SOIC, SSOP, QSOP * Military: CERDIP, LCC, CERPACK The FCT805T is designed for fast, clean edge rates to provide accurate clock distribution in high speed systems. FUNCTIONAL BLOCK DIAGRAM OE A 5 IN A OA 1 -OA 5 5 IN B OB 1 -OB 5 OE B MON MILITARY AND COMMERCIAL TEMPERATURE RANGES JULY 2000 1 c 1999 Integrated Device Technology, Inc. DSC-4771 IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES OB 1 OA 2 3 18 OB 2 OA 3 4 17 OB 3 GND 5 16 GND OA 4 6 15 OB 4 OA 5 7 (1) SO20-2 SO20-7 SO20-8 E20-1 D20-1 14 OB 5 8 13 MON OE A 9 12 OE B IN A 10 11 IN B 4 GND 5 OA 4 6 OA 5 7 (1) 2 20 19 1 L20-2 8 GND 9 OE A GND OA 3 3 OB 1 19 SOIC/ SSOP/ QSOP/ CERPACK/ CERDIP TOP VIEW 10 11 12 18 OB 2 17 OB 3 16 GND 15 OB 4 14 OB 5 13 MON 2 V CC OA 1 OE B V CC V CC 20 IN B 1 IN A VCC OA 1 INDEX OA 2 PIN CONFIGURATION LCC TOP VIEW NOTE: 1. Pin 8 is internally connected to GND. To insure compatibility with all products, pin 8 should be connected to GND at board level. ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM Rating Terminal Voltage with Respect to GND TSTG IOUT PIN DESCRIPTION Max. -0.5 to +7 Unit V Storage Temperature -65 to +150 C DC Output Current -65 to +120 mA Pin Names OEA, OEB INA, INB OAx, OBx MON NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. FUNCTION TABLE(1) Inputs CAPACITANCE (TA = +25OC, f = 1.0MHz) Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 4.5 Max. 6 Unit pF COUT Output Capacitance VOUT = 0V 5.5 8 pF Description 3-State Output Enable Inputs (Active LOW) Clock Inputs Clock Outputs Monitor Output Outputs OEA, OEB INA, INB OAx, OBx MON L L L L L H H H H L Z L H H Z H NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level Z = High-Impedance NOTE: 1. This parameter is measured at characterization but not tested. 2 IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10% Parameter Input HIGH Level Test Conditions(1) Guaranteed Logic HIGH Level VIL Input LOW Level Guaranteed Logic LOW Level II H Input HIGH Current(5) VCC = Max. VI = 2.7V II L Input LOW Current(5) VCC = Max. IOZH High Impedance Output Current VCC = Max. IOZL (3-State Output Pins) II Input HIGH Current VCC = Max., VI = VCC (Max.) VIK Clamp Diode Voltage VCC = Min., IIN = -18mA -- -0.7 -1.2 V IOS Short Circuit Current VCC = Max.(3), VO = GND -60 -120 -225 mA VOH Output HIGH Voltage VCC = Min. VIN = VIH or VIL 2.4 3.3 -- V 2 3 -- V -- 0.3 0.55 V Symbol VIH VOL Output LOW Voltage IOFF Input/Output Power Off Leakage(5) VH Input Hysteresis for all inputs ICCL ICCH ICCZ Quiescent Power Supply Current Min. 2 Typ.(2) -- Max. -- -- -- 0.8 V -- -- 1 A VI = 0.5V -- -- 1 A VO = 2.7V -- -- 1 A VO = 0.5V -- -- 1 -- -- 1 IOH = -12mA MIL IOH = -15mA COM'L IOH = -24mA MIL IOH = -32mA COM'L (4) IOL = 32mA MIL IOH = 48mA COM'L VCC = Min. VIN = VIH or VIL VCC = 0V, VIN or VO 4.5V Unit V A -- -- 1 A -- -- 150 -- mV VCC = Max., VIN = GND or VCC -- 5 500 A NOTES: 1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. Duration of the condition should not exceed one second. 5. The test limit for thie parameter is 5A at TA = -55C. 3 IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol ICC Parameter Quiescent Power Supply Current TTL Inputs HIGH Test Conditions(1) VCC = Max. VIN = 3.4V(3) Min. -- Typ.(2) 0.5 Max. 2 Unit mA ICCD Dynamic Power Supply Current(4) VCC = Max. Outputs Open OEA = OEB = GND 50% Duty Cycle VIN = VCC VIN = GND -- 60 100 A/ MHz/bit IC Total Power Supply Current(6) VCC = Max. Outputs Open fo = 25MHz 50% Duty Cycle OEA = OEB =VCC Mon. Output Toggling VIN = VCC VIN = GND -- 1.5 3 mA VIN = 3.4V VIN = GND -- 1.8 4 VIN = VCC VIN = GND -- 33 55.5(5) VIN = 3.4V VIN = GND -- 33.5 57.5(5) VCC = Max. Outputs Open fo = 50MHz 50% Duty Cycle OEA = OEB = GND Eleven Outputs Toggling NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH, and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz. 4 IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE (MILITARY)(1, 2) FCT805BT Symbol tPLH Propagation Delay tPHL INA to OAx, INB to OBx tR Output Rise Time Condition(3) CL = 50pF RL = 500 Parameter FCT805CT Min.(4) Max. Min.(4) Max. Unit 1.5 5.7 1.5 5.2 ns -- 2 -- 2 ns tF Output Fall Time -- 1.5 -- 1.5 ns tSK(o) Output skew: skew between outputs of all banks of same package (inputs tied together) -- 0.9 -- 0.7 ns tSK(p) Pulse skew: skew between opposite transitions of same output (|t PHL-t PLH|) -- 0.9 -- 0.8 ns tSK(pp) Part-to-part skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade -- 1.5 -- 1.2 ns tPZL tPZH tPLZ tPHZ Output Enable Time OEA to OAx, OEB to OBx Output Disable Time OEA to OAx, OEB to OBx 1.5 6.5 1.5 6 ns 1.5 6.5 1.5 6 ns NOTES: 1. tPLH, tPHL, and tSK(pp) are production tested. All other parameters are guaranteed but not production tested. 2. Propagation delay range indicated by Min. and Max. limit is dues to Vcc, operating temperature, and process parameters. These propagation delay limits do not imply skew. 3. See Test Circuits and Waveforms. 4. Minimum limits are guaranteed but not tested on Propagation Delays. SWITCHING CHARACTERISTICS OVER OPERATING RANGE (COMMERCIAL)(1, 2) FCT805BT Symbol tPLH Propagation Delay tPHL INA to OAx, INB to OBx tR Output Rise Time Condition(3) CL = 50pF RL = 500 Parameter FCT805CT Min.(4) Max. Min.(4) Max. Unit 1.5 5 1.5 4.5 ns -- 1.5 -- 1.5 ns tF Output Fall Time -- 1.5 -- 1.5 ns tSK(o) Output skew: skew between outputs of all banks of same package (inputs tied together) -- 0.7 -- 0.5 ns tSK(p) Pulse skew: skew between opposite transitions of same output (|t PHL-t PLH|) -- 0.7 -- 0.6 ns tSK(pp) Part-to-part skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade -- 1.2 -- 1 ns tPZL tPZH tPLZ tPHZ Output Enable Time OEA to OAx, OEB to OBx Output Disable Time OEA to OAx, OEB to OBx 1.5 6 1.5 5 ns 1.5 6 1.5 5 ns NOTES: 1. tPLH, tPHL, and tSK(pp) are production tested. All other parameters are guaranteed but not production tested. 2. Propagation delay range indicated by Min. and Max. limit is dues to Vcc, operating temperature, and process parameters. These propagation delay limits do not imply skew. 3. See Test Circuits and Waveforms. 4. Minimum limits are guaranteed but not tested on Propagation Delays. 5 IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS ENABLE AND DISABLE TIMES TEST CIRCUITS FOR ALL OUTPUTS SWITCH POSITION VCC 7V 500 Pulse Generator V IN V OUT D.U.T. 50pF 500 RT CL TEST SWITCH Disable LOW Enable LOW Closed Disable HIGH Enable HIGH Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. PACKAGE DELAY OUTPUT SKEW 3V 3V 1.5V 1.5V INPUT INPUT 0V t PHL t PLH 0V tPLH1 tPLH1 V OH V OH 2.0V 0.8V OUTPUT tR 1.5V OUTPUT 1 1.5V VO L t SK(o) VO L t SK(o) V OH 1.5V tF OUTPUT 2 PULSE SKEW - tSK(p) VO L tPH L2 t PLH 2 tSK (o) = t PLH2 - tPLH 1 3V or t PH L2 - t PHL1 1.5V INPUT 0V t PLH t PHL PART-TO-PART SKEW - t SK(pp) VO H 1.5V OUTPUT 3V V OL 1.5V tSK (p) = t PHL - tPLH INPUT t PH L1 tPLH1 ENABLE AND DISABLE TIMES DISABLE ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY LOW tPLZ 3.5V SW ITCH CLOSED SW ITCH O PEN 1.5V 0V 1.5V V OL tSK(pp) t SK(pp) 3V 1.5V PACKAGE 2 OUTPUT 0V VOH 1.5V V OL tPH L2 tPLH2 tSK (pp) = t PLH2 - t PLH1 tPH Z t PZH OUTPUT NORMALLY HIGH PACKAGE 1 OUTPUT 3.5V 0.3V V OL 1.5V 0V VOH or t PH L2 - tPHL1 NOTE: 1. Package 1 and Package 2 are same device type and speed grade. 0.3V V OH 0V NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns 6 IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT49FCT XX XX XX X Device Type Package Process Blank B Commercial (0 C to +70 C) M IL-STD-883, Class B ( - 55 C to +125 C) SO Q PY Commercial Options Small Outline IC (SO20-2) Quarter-size Small Outline Package (SO20-8) Shrink Small Outline Package (SO20-7) D E L Military Options CERDIP (D20-1) CERPACK (E20-1) Leadless Chip Carrier (L20-2) 805BT 805CT Fast CMOS Buffer/Clock Driver CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 7