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IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 2000
1999 Integrated Device Technology, Inc. DSC-4771c
IDT49FCT805BT/CT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS
BUFFER CLOCK/DRIVER
DESCRIPTION:
This buffer/clock driver is built using advanced dual metal CMOS
technology. The FCT805T is a non-inverting clock driver consisting of two
banks of drivers. Each bank drives five output buffers from a standard TTL
compatible input. This part has extremely low output skew, pulse skew, and
package skew. The device has a “heart-beat” monitor for diagnostics and
PLL driving. The monitor output is identical to all other outputs and complies
with the output specifications in this document.
The FCT805T is designed for fast, clean edge rates to provide accurate
clock distribution in high speed systems.
FUNCTIONAL BLOCK DIAGRAM
INA
INB
OEB
OEA
OA1-OA5
OB1-OB5
MON
5
5
FEATURES:
− 0.5 MICRON CMOS Technology
− Guaranteed low skew < 500ps (max.)
− Very low duty cycle distortion < 600ps (max.)
− Low CMOS power levels
− TTL compatible inputs and outputs
− TTL level output voltage swings
− High drive: -32mA IOH, +48mA IOL
− Two independent output banks with 3-state control
− 1:5 fanout per bank
− “Heartbeat” monitor output
− ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
− Available in the following packages:
• Commercial: SOIC, SSOP, QSOP
• Military: CERDIP, LCC, CERPACK
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
PIN CONFIGURATION
NOTE:
1. Pin 8 is internally connected to GND. To insure compatibility with all
products, pin 8 should be connected to GND at board level.
SOIC/ SSOP/ QSOP/ CERPACK/ CERDIP
TOP VIEW
LCC
TOP VIEW
1
2
3
4
5
6
7
8910 11 12 13
14
15
16
17
18
19
20
L20-2
OA3
OA4
OA5
GND
GND(1)
OB3
OB4
OB5
OB2
GND
OEA
INA
INB
OEB
MON
OA2
OA1
VCC
VCC
OB1
INDEX
VCC
OA1
OA2
GND
(1)
INA
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
201
OA3
OA4
OA5
OEA
VCC
OB1
GND
MON
INB
OB2
OB3
OB4
OB5
OEB
SO20-2
SO20-7
SO20-8
E20-1
D20-1
GND
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Max. Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –65 to +120 mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability. No
terminal voltage may exceed Vcc by +0.5V unless otherwise noted.
CAPACITANCE (TA = +25OC, f = 1.0MHz)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6pF
COUT Output Capacitance VOUT = 0V 5.5 8pF
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names Description
OEA, OEB3-State Output Enable Inputs (Active LOW)
INA, INBClock Inputs
OAx, OBx Clock Outputs
MON Monitor Output
FUNCTION TABLE(1)
Inputs Outputs
OEA, OEBINA, INBOAx, OBx MON
L L L L
LH H H
HLZL
H H ZH
NOTE:
1. H
= HIGH Voltage Level
L
= LOW Voltage Level
Z
= High-Impedance
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IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = -55°C to +125°C, VCC = 5.0V ± 10%
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2— — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II HInput HIGH Current(5) VCC = Max. VI = 2.7V — — ±1 µA
II LInput LOW Current(5) VCC = Max. VI = 0.5V — — ±1 µA
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA
IOZL (3-State Output Pins) VO = 0.5V — — ±1
IIInput HIGH Current VCC = Max., VI = VCC (Max.) — — ±1 µA
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA —–0.7 –1.2 V
IOS Short Circuit Current VCC = Max.(3), VO = GND –60 –120 –225 mA
VOH Output HIGH Voltage VCC = Min.
VIN = VIH or VIL
IOH = –12mA MIL
IOH = –15mA COM’L
2.4 3.3 —V
IOH = –24mA MIL
IOH = –32mA COM’L (4)
2 3 —V
VOL Output LOW Voltage VCC = Min.
VIN = VIH or VIL
IOL = 32mA MIL
IOH = 48mA COM’L
—0.3 0.55V
IOFF Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA
VHInput Hysteresis for all inputs ——150 —mV
ICCL
ICCH
ICCZ
Quiescent Power Supply Current VCC = Max., VIN = GND or VCC —5 500 µA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. Duration of the condition should not exceed one second.
5. The test limit for thie parameter is ±5µA at TA = -55°C.
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH, and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO = Output Frequency
NO = Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
∆ICC Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
—0.5 2mA
ICCD Dynamic Power Supply Current(4) VCC = Max.
Outputs Open
OEA = OEB = GND
50% Duty Cycle
VIN = VCC
VIN = GND
—60 100 µA/
MHz/bit
ICTotal Power Supply Current(6) VCC = Max.
Outputs Open
fo = 25MHz
VIN = VCC
VIN = GND
—1.5 3mA
50% Duty Cycle
OEA = OEB =VCC
Mon. Output Toggling
VIN = 3.4V
VIN = GND
—1.8 4
VCC = Max.
Outputs Open
fo = 50MHz
VIN = VCC
VIN = GND
—33 55.5(5)
50% Duty Cycle
OEA = OEB = GND
Eleven Outputs Toggling
VIN = 3.4V
VIN = GND
—33.5 57.5(5)
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IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(MILITARY)(1, 2)
FCT805BT FCT805CT
Symbol Parameter Condition(3) Min.(4) Max.Min.(4) Max.Unit
tPLH
tPHL
Propagation Delay
INA to OAx, INB to OBx
CL = 50pF
RL = 500Ω1.5 5.7 1.5 5.2 ns
tROutput Rise Time —2—2ns
tFOutput Fall Time —1.5 —1.5 ns
tSK(o) Output skew: skew between outputs of all banks of same package (inputs
tied together) —0.9 —0.7 ns
tSK(p) Pulse skew: skew between opposite transitions of same output (|tPHL–tPLH|) —0.9 —0.8 ns
tSK(pp) Part-to-part skew: skew between outputs of different packages at same
power supply voltage, temperature, package type and speed grade —1.5 —1.2 ns
tPZL
tPZH
Output Enable Time
OEA to OAx, OEB to OBx1.5 6.5 1.5 6ns
tPLZ
tPHZ
Output Disable Time
OEA to OAx, OEB to OBx1.5 6.5 1.5 6ns
NOTES:
1. tPLH, tPHL, and tSK(pp) are production tested. All other parameters are guaranteed but not production tested.
2. Propagation delay range indicated by Min. and Max. limit is dues to Vcc, operating temperature, and process parameters. These propagation
delay limits do not imply skew.
3. See Test Circuits and Waveforms.
4. Minimum limits are guaranteed but not tested on Propagation Delays.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(COMMERCIAL)(1, 2)
FCT805BT FCT805CT
Symbol Parameter Condition(3) Min.(4) Max.Min.(4) Max.Unit
tPLH
tPHL
Propagation Delay
INA to OAx, INB to OBx
CL = 50pF
RL = 500Ω1.5 51.5 4.5 ns
tROutput Rise Time —1.5 —1.5 ns
tFOutput Fall Time —1.5 —1.5 ns
tSK(o) Output skew: skew between outputs of all banks of same package (inputs
tied together) —0.7 —0.5 ns
tSK(p) Pulse skew: skew between opposite transitions of same output (|tPHL–tPLH|) —0.7 —0.6 ns
tSK(pp) Part-to-part skew: skew between outputs of different packages at same
power supply voltage, temperature, package type and speed grade —1.2 —1ns
tPZL
tPZH
Output Enable Time
OEA to OAx, OEB to OBx1.5 61.5 5ns
tPLZ
tPHZ
Output Disable Time
OEA to OAx, OEB to OBx1.5 61.5 5ns
NOTES:
1. tPLH, tPHL, and tSK(pp) are production tested. All other parameters are guaranteed but not production tested.
2. Propagation delay range indicated by Min. and Max. limit is dues to Vcc, operating temperature, and process parameters. These propagation
delay limits do not imply skew.
3. See Test Circuits and Waveforms.
4. Minimum limits are guaranteed but not tested on Propagation Delays.
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
7V
VCC
Pulse
GeneratorD.U.T.
500Ω
500Ω
RT
VIN VOUT
50pF
CL
0V
VOH
tPLHtPHL
VOL
tR
3V
1.5V
tF
2.0V
0.8V 1.5V
OUTPUT
INPUT
CONTROL
INPUT tPLZ0V
OUTPUT
NORMALLY
LOW tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE DISABLE
SWITCH
OPEN
tPHZ
0V
VOL
VOH
0.3V
0.3V
1.5V
1.5V
tPZL
3.5V 3.5V
3V
1.5V
0V
VOH
tPLH tPHL
VOL
3V
1.5V
1.5V
OUTPUT
INPUT
tSK(p) = tPHL - tPLH
0V
VOH
tPLH1
VOL
1.5V
OUTPUT 1
3V
1.5V
INPUT
VOH
tSK(o)
VOL
1.5V
tSK(o) = t PLH2 - tPLH1 o r tPHL2 - tPHL1
OUTPUT 2
tPLH1
tSK(o)
tPLH2tPHL2
0V
VOH
tPLH1
VOL
1.5VPACKAGE 1
OUTPUT
3V
1.5V
INPUT
VOH
tSK(pp)
VOL
1.5V
tSK(pp) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL1
tSK(pp)
tPLH2tPHL2
PACKAGE 2
OUTPUT
TEST CIRCUITS AND WAVEFORMS
ENABLE AND DISABLE TIMES
TEST CIRCUITS FOR ALL OUTPUTS
PART-TO-PART SKEW - tSK(pp)
PACKAGE DELAY OUTPUT SKEW
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
PULSE SKEW - tSK(p)
ENABLE AND DISABLE TIMES
SWITCH POSITION
TEST SWITCH
Disable LOW
Enable LOW
Closed
Disable HIGH
Enable HIGH
Open
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
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IDT49FCT805BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
CORPORATE HEADQUARTERS for SALES:
2975 Stender Way 800-345-7015 or 408-727-6116
Santa Clara, CA 95054 fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION
IDT49FCTXXXX
Device Type XX
Package X
Process
Fast CMOS Buffer/Clock Driver
805BT
805CT
SO
Q
PY
Commercial Options
Small Outline IC (SO20-2)
Quarter-size Small Outline Package (SO20-8)
Shrink Small Outline Package (SO20-7)
D
E
L
Military Options
CERDIP (D20-1)
CERPACK (E20-1)
Leadless Chip Carrier (L20-2 )
Blank
BCommercial (0 °C to +70°C)
MIL-STD-883, Class B (– 55°C to +125°C)
