LIS331DLFTR - STMicroelectronics - Datasheet.Directory

July 2009 Doc ID 15101 Rev 4 1/38

LIS331DLF

MEMS digital output motion sensor

ultra low-power high performance 3-axes “nano” accelerometer

Features

■Wide supply voltage, 2.16 V to 3.6 V

■Low voltage compatible IOs, 1.8 V

■Ultra low-power mode consumption

down to 10 µA

■±2g/±4g/±8g dynamically selectable full-scale

■I2C/SPI digital output interface

■6 bit resolution

■2 independent programmable interrupt

generators for free-fall and motion detection

■Sleep to wake-up function

■6D orientation detection

■Embedded self-test

■10000 g high shock survivability

■ECOPACK® RoHS and “Green” compliant (see

Section 8)

Applications

■Display orientation

■Gaming

■User interface

■Motion activated functions

■Intelligent power saving for handheld devices

■Impact recognition and logging

Description

The LIS331DLF is an ultra low-power high

performance three axes linear accelerometer

belonging to the “nano” family, with digital I2C/SPI

serial interface standard output.

The device features ultra low-power operational

modes that allow advanced power saving and

smart sleep to wake-up functions.

The LIS331DLF has dynamically user selectable

full scales of ±2g/±4g/±8g and it is capable of

measuring accelerations with output data rates

from 0.5 Hz to 400 Hz.

The self-test capability allows the user to check

the functioning of the sensor in the final

application.

The device may be configured to generate

interrupt signal by inertial wake-up/free-fall events

as well as by the position of the device itself.

Thresholds and timing of interrupt generators are

programmable by the end user on the fly.

The LIS331DLF is available in small thin plastic

land grid array package (LGA) and it is

guaranteed to operate over an extended

temperature range from -40 °C to +85 °C.

LGA 16

(3x3x1 mm)

Table 1. Device summary

Order codes Temperature range [°C] Package Packaging

LIS331DLF -40 to +85 LGA 16 Tray

LIS331DLFTR -40 to +85 LGA 16 Tape and reel

www.st.com

Obsolete Product(s) - Obsolete Product(s)

Contents LIS331DLF

2/38 Doc ID 15101 Rev 4

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.2 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5.3 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5.4 Sleep to wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2.3 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Obsolete Product(s) - Obsolete Product(s)

LIS331DLF Contents

Doc ID 15101 Rev 4 3/38

6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.2 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.3 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.4 CTRL_REG3 [Interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 27

7.5 CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.6 CTRL_REG5 (24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . h) 28

7.7 HP_FILTER_RESET (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.8 REFERENCE (26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . h) 28

7.9 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.10 OUT_X (29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.11 OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.12 OUT_Z (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.13 INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.14 INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.15 INT1_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.16 INT1_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.17 INT2_CFG (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.18 INT2_SRC (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.19 INT2_THS (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.20 INT2_DURATION (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Obsolete Product(s) - Obsolete Product(s)

List of tables LIS331DLF

4/38 Doc ID 15101 Rev 4

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Mechanical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted . . . . . . . . . . 7

Table 4. Electrical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted . . . . . . . . . . . . 8

Table 5. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. I2C slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 8. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 9. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 10. SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 11. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 12. Transfer when master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 13. Transfer when master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 17

Table 14. Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 17

Table 15. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 16. WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 17. CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 18. CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 19. Power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 24

Table 20. Normal-mode output data rate configurations and low-pass cut-off frequencies . . . . . . . . 24

Table 21. CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 22. CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 23. High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 24. High-pass filter cut-off frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 25. CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 26. CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 27. Data signal on INT 1 and INT 2 pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 28. CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 29. CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 30. CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 31. CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 32. REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 33. REFERENCE description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 34. STATUS_REG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 35. STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 36. INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 37. INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 38. Interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 39. INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 40. INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 41. INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 42. INT1_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 43. INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 44. INT2_DURATION description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 45. INT2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 46. INT2_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 47. Interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 48. INT2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Obsolete Product(s) - Obsolete Product(s)

LIS331DLF List of tables

Doc ID 15101 Rev 4 5/38

Table 49. INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 50. INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 51. INT2_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 52. INT2_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 53. INT2_DURATION description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 54. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Obsolete Product(s) - Obsolete Product(s)

List of figures LIS331DLF

6/38 Doc ID 15101 Rev 4

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. I2C Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. LIS331DLF electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 10. Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 12. LGA16: Mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Obsolete Product(s) - Obsolete Product(s)

LIS331DLF Block diagram and pin description

Doc ID 15101 Rev 4 7/38

1 Block diagram and pin description

1.1 Block diagram

Figure 1. Block diagram

1.2 Pin description

Figure 2. Pin connection

CHARGE

AMPLIFIER

Y+

Z+

Y-

Z-

X+

X-

SPI

SCL/SPC

SDA/SDO/SDI

SDO/SA0

CONTROL LOGIC

INTERRUPT GEN.

INT 1

CLOCK

TRIMMING

CIRCUITS

REFERENCESELF TEST

CONTROL LOGIC

A/D

CONVERTER

INT 2

MUX

(TOP VIEW)

DIRECTION OF THE

DETECTABLE

ACCELERATIONS

(BOTTOM VIEW)

Pin 1 indicator

Obsolete Product(s) - Obsolete Product(s)

Block diagram and pin description LIS331DLF

8/38 Doc ID 15101 Rev 4

Table 2. Pin description

Pin# Name Function

1 Vdd_IO Power supply for I/O pins

2 NC Not connected

3 NC Not connected

4SCL

SPC

I2C serial clock (SCL)

SPI serial port clock (SPC)

5 GND 0 V supply

SDA

SDI

SDO

I2C serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

7SDO

SA0

SPI serial data output (SDO)

I2C less significant bit of the device address (SA0)

8CS

SPI enable

I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)

9 INT 2 Inertial interrupt 2

10 Reserved Connect to GND

11 INT 1 Inertial interrupt 1

12 GND 0 V supply

13 GND 0 V supply

14 Vdd Power supply

15 Reserved Connect to Vdd

16 GND 0 V supply

Obsolete Product(s) - Obsolete Product(s)

LIS331DLF Mechanical and electrical specifications

Doc ID 15101 Rev 4 9/38

2 Mechanical and electrical specifications

2.1 Mechanical characteristics

Table 3. Mechanical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted (1)

Symbol Parameter Test conditions Min. Typ.(2) Max. Unit

FS Measurement range(3)

FS bit set to 00 ±2.0

gFS bit set to 01 ±4.0

FS bit set to 11 ±8.0

So Sensitivity

FS bit set to 00

6 bit representation 16

LSB/g

FS bit set to 01

6 bit representation 8

FS bit set to 11

6 bit representation 4

Dres Device resolution FS bit set to 00

ODR = 50 Hz 62.5 mg

TCSo Sensitivity change vs

temperature FS bit set to 00 ±0.01 %/°C

Ty O f f Typical zero-g level offset

accuracy(4),(5) FS bit set to 00 ±60 mg

TCOff Zero-g level change vs

temperature Max delta from 25°C ±0.5 mg/°C

Vst Self-test

output change(6),(7),(8)

FS bit set to 00

X axis 158LSb

FS bit set to 00

Y axis -1 -5 -8 LSb

FS bit set to 00

Z axis 158LSb

Top Operating temperature range -40 +85 °C

Wh Product weight 20 mgram

1. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V.

2. Typical specifications are not guaranteed

3. Verified by wafer level test and measurement of initial offset and sensitivity

4. Typical zero-g level offset value after MSL3 preconditioning

5. Offset can be eliminated by enabling the built-in high pass filter

6. The sign of “Self-test output change” is defined by CTRL_REG4 STsign bit (Table 28), for all axes.

Self-test output changes with the power supply. “Self-test output change” is defined as

OUTPUT[LSb]

(CTRL_REG4 ST bit=1)

- OUTPUT[LSb](CTRL_REG4 ST bit=0). 1LSb=4g/64 at 6 bit representation, ±2 g full-scale

8. Output data reach 99% of final value after 1/ODR+1 ms when enabling Self-test mode, due to device filtering

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2.2 Electrical characteristics

Table 4. Electrical characteristics @ Vdd = 2.5 V, T = 25 °C unless otherwise noted (1)

Symbol Parameter Test conditions Min. Typ.(2) Max. Unit

Vdd Supply voltage 2.16 2.5 3.6 V

Vdd_IO I/O pins supply voltage(3) 1.71 Vdd+0.1 V

Idd Current consumption

in normal mode 250 µA

IddLP Current consumption

in low-power mode 10 µA

IddPdn Current consumption in

power-down mode 1µA

VIH Digital high level input voltage 0.8*Vdd_IO V

VIL Digital low level input voltage 0.2*Vdd_IO V

VOH High level output voltage 0.9*Vdd_IO V

VOL Low level output voltage 0.1*Vdd_IO V

ODR Output data rate

in normal mode

DR bit set to 00 50

HzDR bit set to 01 100

DR bit set to 10 400

ODRLP

Output data rate

in low-power mode

PM bit set to 010 0.5

PM bit set to 011 1

PM bit set to 100 2

PM bit set to 101 5

PM bit set to 110 10

BW System bandwidth(4) ODR/2 Hz

Ton Turn-on time(5) ODR = 100 Hz 1/ODR+1ms s

Top Operating temperature range -40 +85 °C

1. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V.

2. Typical specification are not guaranteed

3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the

measurement chain is powered off.

4. Refer to Table 20 for filter cut-off frequency

5. Time to obtain valid data after exiting power-down mode

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Doc ID 15101 Rev 4 11/38

2.3 Communication interface characteristics

2.3.1 SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Figure 3. SPI slave timing diagram (2)

1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not

tested in production

2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and output port

3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors

Table 5. SPI slave timing values

Symbol Parameter

Value (1)

Unit

Min. Max.

tc(SPC) SPI clock cycle 100 ns

fc(SPC) SPI clock frequency 10 MHz

tsu(CS) CS setup time 6

th(CS) CS hold time 8

tsu(SI) SDI input setup time 5

th(SI) SDI input hold time 15

tv(SO) SDO valid output time 50

th(SO) SDO output hold time 9

tdis(SO) SDO output disable time 50

SPC

SDI

SDO

su(CS)

v(SO)

h(SO)

h(SI)

su(SI)

h(CS)

dis(SO)

c(SPC)

MSB IN

MSB OUT LSB OUT

LSB IN

(3)

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2.3.2 I2C - Inter IC control interface

Subject to general operating conditions for Vdd and top.

Figure 4. I2C Slave timing diagram (a)

Table 6. I2C slave timing values

Symbol Parameter

I2C standard mode (1) I2C fast mode (1)

Unit

Min Max Min Max

f(SCL) SCL clock frequency 0 100 0 400 KHz

tw(SCLL) SCL clock low time 4.7 1.3

µs

tw(SCLH) SCL clock high time 4.0 0.6

tsu(SDA) SDA setup time 250 100 ns

th(SDA) SDA data hold time 0.01 3.45 0.01 0.9 µs

tr(SDA) tr(SCL) SDA and SCL rise time 1000 20 + 0.1Cb (2) 300

tf(SDA) tf(SCL) SDA and SCL fall time 300 20 + 0.1Cb (2) 300

th(ST) START condition hold time 4 0.6

µs

tsu(SR) Repeated START condition

setup time 4.7 0.6

tsu(SP) STOP condition setup time 4 0.6

tw(SP:SR) Bus free time between STOP

and START condition 4.7 1.3

1. Data based on standard I2C protocol requirement, not tested in production

2. Cb = total capacitance of one bus line, in pF

a. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port

SDA

SCL

f(SDA)

su(SP)

w(SCLL)

su(SDA)

r(SDA)

su(SR)

h(ST)

w(SCLH)

h(SDA)

r(SCL)

f(SCL)

w(SP:SR)

START

REPEATED

START

STOP

STAR

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Doc ID 15101 Rev 4 13/38

2.4 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage

to the device. This is a stress rating only and functional operation of the device under these

conditions is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

Note: Supply voltage on any pin should never exceed 6.0 V

Table 7. Absolute maximum ratings

Symbol Ratings Maximum value Unit

Vdd Supply voltage -0.3 to 6 V

Vdd_IO I/O pins supply voltage -0.3 to 6 V

Vin Input voltage on any control pin

(CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0) -0.3 to Vdd_IO +0.3 V

APOW Acceleration (any axis, powered, Vdd = 2.5 V) 3000 g for 0.5 ms

10000 g for 0.1 ms

AUNP Acceleration (any axis, unpowered) 3000 g for 0.5 ms

10000 g for 0.1 ms

TOP Operating temperature range -40 to +85 °C

TSTG Storage temperature range -40 to +125 °C

ESD Electrostatic discharge protection

4 (HBM) kV

1.5 (CDM) kV

200 (MM) V

This is a mechanical shock sensitive device, improper handling can cause permanent

damages to the part

This is an ESD sensitive device, improper handling can cause permanent damages to

the part

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2.5 Terminology

2.5.1 Sensitivity

Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g

acceleration to it. As the sensor can measure DC accelerations this can be done easily by

pointing the axis of interest towards the center of the earth, noting the output value, rotating

the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing

so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the

smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This

value changes very little over temperature and also time. The Sensitivity Tolerance

describes the range of Sensitivities of a large population of sensors.

2.5.2 Zero-g level

Zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal

output signal if no acceleration is present. A sensor in a steady state on a horizontal surface

will measure 0 g in X axis and 0 g in Y axis whereas the Z axis will measure 1 g. The output

is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h,

data expressed as 2’s complement number). A deviation from ideal value in this case is

called Zero-g offset. Offset is to some extent a result of stress to MEMS sensor and

therefore the offset can slightly change after mounting the sensor onto a printed circuit

board or exposing it to extensive mechanical stress. Offset changes little over temperature,

see “Zero-g level change vs. temperature”. The Zero-g level tolerance (TyOff) describes the

Standard deviation of the range of Zero-g levels of a population of sensors.

2.5.3 Self-test

Self-test allows to check the sensor functionality without moving it. The Self-test function is

off when the self-test bit (ST) of CTRL_REG4 (control register 4) is programmed to ‘0‘.

When the self-test bit of CTRL_REG4 is programmed to ‘1‘ an actuation force is applied to

the sensor, simulating a definite input acceleration. In this case the sensor outputs will

exhibit a change in their DC levels which are related to the selected full scale through the

device sensitivity. When self-test is activated, the device output level is given by the

algebraic sum of the signals produced by the acceleration acting on the sensor and by the

electrostatic test-force. If the output signals change within the amplitude specified inside

Table 3, then the sensor is working properly and the parameters of the interface chip are

within the defined specifications.

2.5.4 Sleep to wake-up

The “sleep to wake-up” function, in conjunction with low-power mode, allows to further

reduce the system power consumption and develop new smart applications.

LIS331DLF may be set in a low-power operating mode, characterized by lower date rates

refreshments. In this way the device, even if sleeping, keep on sensing acceleration and

generating interrupt requests.

When the “sleep to wake-up” function is activated, LIS331DLF is able to automatically wake-

up as soon as the interrupt event has been detected, increasing the output data rate and

bandwidth.

With this feature the system may be efficiently switched from low-power mode to full-

performance depending on user-selectable positioning and acceleration events, thus

ensuring power saving and flexibility.

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LIS331DLF Functionality

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3 Functionality

The LIS331DLF is a “nano”, low-power, digital output 3-axis linear accelerometer packaged

in a LGA package. The complete device includes a sensing element and an IC interface

able to take the information from the sensing element and to provide a signal to the external

world through an I2C/SPI serial interface.

3.1 Sensing element

A proprietary process is used to create a surface micro-machined accelerometer. The

technology allows to carry out suspended silicon structures which are attached to the

substrate in a few points called anchors and are free to move in the direction of the sensed

acceleration. To be compatible with the traditional packaging techniques a cap is placed on

top of the sensing element to avoid blocking the moving parts during the moulding phase of

the plastic encapsulation.

When an acceleration is applied to the sensor the proof mass displaces from its nominal

position, causing an imbalance in the capacitive half-bridge. This imbalance is measured

using charge integration in response to a voltage pulse applied to the capacitor.

At steady state the nominal value of the capacitors are few pF and when an acceleration is

applied the maximum variation of the capacitive load is in the fF range.

3.2 IC interface

The complete measurement chain is composed by a low-noise capacitive amplifier which

converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is

finally available to the user by an analog-to-digital converter.

The acceleration data may be accessed through an I2C/SPI interface thus making the

device particularly suitable for direct interfacing with a microcontroller.

The LIS331DLF features a data-ready signal (RDY) which indicates when a new set of

measured acceleration data is available thus simplifying data synchronization in the digital

system that uses the device.

The LIS331DLF may also be configured to generate an inertial wake-up and free-fall

interrupt signal accordingly to a programmed acceleration event along the enabled axes.

Both Free-Fall and Wake-Up can be available simultaneously on two different pins.

3.3 Factory calibration

The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff).

The trimming values are stored inside the device in a non volatile memory. Any time the

device is turned on, the trimming parameters are downloaded into the registers to be used

during the active operation. This allows to use the device without further calibration.

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4 Application hints

Figure 5. LIS331DLF electrical connection

The device core is supplied through Vdd line while the I/O pads are supplied through

Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Aluminum) should

be placed as near as possible to the pin 14 of the device (common design practice).

All the voltage and ground supplies must be present at the same time to have proper

behavior of the IC (refer to Figure 5). It is possible to remove Vdd maintaining Vdd_IO

without blocking the communication bus, in this condition the measurement chain is

powered off.

The functionality of the device and the measured acceleration data is selectable and

accessible through the I2C or SPI interfaces.When using the I2C, CS must be tied high.

The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be

completely programmed by the user through the I2C/SPI interface.

4.1 Soldering information

The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard.

It is qualified for soldering heat resistance according to JEDEC J-STD-020C.

Leave “pin 1 indicator” unconnected during soldering.

Land pattern and soldering recommendations are available at www.st.com.

10µF

Vdd

100nF

GND

Vdd_IO

SDO/SA0

SDA/SDI/SDO

INT 1

SCL/SPC

Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

TOP VIEW

1416

INT 2

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5 Digital interfaces

The registers embedded inside the LIS331DLF may be accessed through both the I2C and

SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire

interface mode.

The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS

line must be tied high (i.e. connected to Vdd_IO).

5.1 I2C serial interface

The LIS331DLF I2C is a bus slave. The I2C is employed to write data into registers whose

content can also be read back.

The relevant I2C terminology is given in the table below.

There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial

data line (SDA). The latter is a bidirectional line used for sending and receiving the data

to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor

embedded inside the LIS331DLF. When the bus is free both the lines are high.

The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the

normal mode.

Table 8. Serial interface pin description

Pin name Pin description

CS SPI enable

I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)

SCL

SPC

I2C serial clock (SCL)

SPI serial port clock (SPC)

SDA

SDI

SDO

I2C serial data (SDA)

SPI serial data input (SDI)

3-wire interface serial data output (SDO)

SA0

SDO

I2C less significant bit of the device address (SA0)

SPI serial data output (SDO)

Table 9. Serial interface pin description

Term Description

Transmitter The device which sends data to the bus

Receiver The device which receives data from the bus

Master The device which initiates a transfer, generates clock signals and terminates a

transfer

Slave The device addressed by the master

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5.1.1 I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After

this has been transmitted by the Master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and

the eighth bit tells whether the Master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a start condition with its address. If they match, the device considers itself addressed

by the Master.

The slave address (SAD) associated to the LIS331DLF is 010100xb. SDO/SA0 pad can be

used to modify less significant bit of the device address. If SA0 pad is connected to voltage

supply, LSb is ‘1’ (address 0101001b) else if SA0 pad is connected to ground, LSb value is

‘0’ (address 0101000b). This solution permits to connect and address two different

accelerometers to the same I2C lines.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I2C embedded inside the LIS331DLF behaves like a slave device and the following

protocol must be adhered to. After the start condition (ST) a slave address is sent, once a

slave acknowledge (SAK) has been returned, a 8-bit sub-address (SUB) is transmitted: the

7 LSb represent the actual register address while the MSB enables address auto increment.

If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically increased to

allow multiple data read/write.

The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)

the Master will transmit to the slave with direction unchanged. Table 10 explains how the

SAD+Read/Write bit pattern is composed, listing all the possible configurations.

Table 10. SAD+Read/Write patterns

Command SAD[6:1] SAD[0] = SA0 R/W SAD+R/W

Read 010100 0 1 01010001 (51h)

Write 010100 0 0 01010000 (50h)

Read 010100 1 1 01010011 (53h)

Write 010100 1 0 01010010 (52h)

Table 11. Transfer when master is writing one byte to slave

Master ST SAD + W SUB DATA SP

Slave SAK SAK SAK

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Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number

of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit

(MSb) first. If a receiver can’t receive another complete byte of data until it has performed

some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait

state. Data transfer only continues when the receiver is ready for another byte and releases

the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to

receive because it is performing some real time function) the data line must be left HIGH by

the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line

while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be

terminated by the generation of a STOP (SP) condition.

In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-

address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the

address of first register to be read.

In the presented communication format MAK is master acknowledge and NMAK is no

master acknowledge.

5.2 SPI bus interface

The LIS331DLF SPI is a bus slave. The SPI allows to write and read the registers of the

device.

The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.

Table 12. Transfer when master is writing multiple bytes to slave:

Master ST SAD + W SUB DATA DATA SP

Slave SAK SAK SAK SAK

Table 13. Transfer when master is receiving (reading) one byte of data from slave:

Master ST SAD + W SUB SR SAD + R NMAK SP

Slave SAK SAK SAK DATA

Table 14. Transfer when Master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP

Slave SAK SAK SAK DATA DATA DATA

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Figure 6. Read and write protocol

CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of

the transmission and goes back high at the end. SPC is the Serial Port Clock and it is

controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and

SDO are respectively the serial port data input and output. Those lines are driven at the

falling edge of SPC and should be captured at the rising edge of SPC.

Both the Read Register and Write Register commands are completed in 16 clock pulses or

in multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two

falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling

edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just

before the rising edge of CS.

bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)

from the device is read. In latter case, the chip will drive SDO at the start of bit 8.

bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands.

When 1, the address is auto incremented in multiple read/write commands.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).

bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

In multiple read/write commands further blocks of 8 clock periods will be added. When MS

bit is ‘0’ the address used to read/write data remains the same for every block. When MS bit

is ‘1’ the address used to read/write data is increased at every block.

The function and the behavior of SDI and SDO remain unchanged.

5.2.1 SPI read

Figure 7. SPI read protocol

SPC

SDI

SDO

AD5 AD4 AD3 AD2 AD1 AD0

DI7DI6DI5DI4DI3DI2DI1DI0

DO7DO6DO5DO4DO3DO2DO1DO0

SPC

SDI

SDO

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

AD5 AD4 AD3 AD2 AD1 AD0

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The SPI read command is performed with 16 clock pulses. Multiple byte read command is

performed adding blocks of 8 clock pulses at the previous one.

bit 0: READ bit. The value is 1.

bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple

reading.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb

first).

bit 16-... : data DO(...-8). Further data in multiple byte reading.

Figure 8. Multiple bytes SPI read protocol (2 bytes example)

5.2.2 SPI write

Figure 9. SPI write protocol

The SPI Write command is performed with 16 clock pulses. Multiple byte write command is

performed adding blocks of 8 clock pulses at the previous one.

bit 0: WRITE bit. The value is 0.

bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple

writing.

bit 2 -7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device

(MSb first).

bit 16-... : data DI(...-8). Further data in multiple byte writing.

SPC

SDI

SDO

DO7DO6DO5DO4DO3DO2DO1DO0

AD5 AD4 AD3 AD2 AD1 AD0

DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8

SPC

SDI

RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

AD5 AD4 AD3 AD2 AD1 AD0MS

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Figure 10. Multiple bytes SPI write protocol (2 bytes example)

5.2.3 SPI read in 3-wires mode

3-wires mode is entered by setting to ‘1’ bit SIM (SPI serial interface mode selection) in

CTRL_REG4.

Figure 11. SPI read protocol in 3-wires mode

The SPI Read command is performed with 16 clock pulses:

bit 0: READ bit. The value is 1.

bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple

reading.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

Multiple read command is also available in 3-wires mode.

SPC

SDI

AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8

SPC

SDI/O

RW DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

AD5 AD4 AD3 AD2 AD1 AD0

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LIS331DLF Register mapping

Doc ID 15101 Rev 4 23/38

6 Register mapping

The table given below provides a listing of the 8 bit registers embedded in the device and

the related addresses:

Table 15. Register address map

Name Type

Default Comment

Hex Binary

Reserved (do not modify) 00 - 0E Reserved

WHO_AM_I r 0F 000 1111 01010010 Dummy register

Reserved (do not modify) 10 - 1F Reserved

CTRL_REG1 rw 20 010 0000 00000111

CTRL_REG2 rw 21 010 0001 00000000

CTRL_REG3 rw 22 010 0010 00000000

CTRL_REG4 rw 23 010 0011 00000000

CTRL_REG5 rw 24 010 0100 00000000

HP_FILTER_RESET r 25 010 0101 Dummy register

REFERENCE rw 26 010 0110 00000000

STATUS_REG r 27 010 0111 00000000

-- r 28 010 1000 00000000 Not used

OUT_X r 29 010 1001 output

-- r 2A 010 1010 00000000 Not used

OUT_Y r 2B 010 1011 output

-- r 2C 010 1100 00000000 Not used

OUT_Z r 2D 010 1101 output

Reserved (do not modify) 2E - 2F Reserved

INT1_CFG rw 30 011 0000 00000000

INT1_SOURCE r 31 011 0001 00000000

INT1_THS rw 32 011 0010 00000000

INT1_DURATION rw 33 011 0011 00000000

INT2_CFG rw 34 011 0100 00000000

INT2_SOURCE r 35 011 0101 00000000

INT2_THS rw 36 011 0110 00000000

INT2_DURATION rw 37 011 0111 00000000

Reserved (do not modify) 38 - 3F Reserved

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Registers marked as Reserved must not be changed. The writing to those registers may

cause permanent damages to the device.

The content of the registers that are loaded at boot should not be changed. They contain the

factory calibration values. Their content is automatically restored when the device is

powered-up.

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LIS331DLF Register description

Doc ID 15101 Rev 4 25/38

7 Register description

The device contains a set of registers which are used to control its behavior and to retrieve

acceleration data. The registers address, made of 7 bits, is used to identify them and to

write the data through serial interface.

7.1 WHO_AM_I (0Fh)

Device identification register.

This register contains the device identifier that for LIS331DLF is set to 52h.

7.2 CTRL_REG1 (20h)

PM bits allow to select between power-down and two operating active modes. The device is

in power-down mode when PD bits are set to “000” (default value after boot). Table 19

shows all the possible power mode configurations and respective output data rates. Output

data in the low-power modes are computed with low-pass filter cut-off frequency defined by

DR1, DR0 bits.

DR bits, in the normal-mode operation, select the data rate at which acceleration samples

are produced. In low-power mode they define the output data resolution. Table 20 shows all

the possible configuration for DR1 and DR0 bits.

Table 16. WHO_AM_I register

01010010

Table 17. CTRL_REG1 register

PM2 PM1 PM0 DR1 DR0 Zen Yen Xen

Table 18. CTRL_REG1 description

PM2 - PM0 Power mode selection. Default value: 000

(000: Power-down; Others: refer to Table 19)

DR1, DR0 Data rate selection. Default value: 00

(00:50 Hz; Others: refer to Table 20)

Zen Z axis enable. Default value: 1

(0: Z axis disabled; 1: Z axis enabled)

Ye n Y axis enable. Default value: 1

(0: Y axis disabled; 1: Y axis enabled)

Xen X axis enable. Default value: 1

(0: X axis disabled; 1: X axis enabled)

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7.3 CTRL_REG2 (21h)

Table 19. Power mode and low-power output data rate configurations

PM2 PM1 PM0 Power mode selection Output data rate [Hz]

ODRLP

0 0 0 Power-down --

0 0 1 Normal mode ODR

0 1 0 Low-power 0.5

0 1 1 Low-power 1

1 0 0 Low-power 2

1 0 1 Low-power 5

1 1 0 Low-power 10

Table 20. Normal-mode output data rate configurations and low-pass cut-off

frequencies

DR1(1)

1. “11” bit configuration is not allowed and may cause incorrect device functionality.

DR0(1) Output data rate [Hz]

ODR

Low-pass filter cut-off

frequency [Hz]

00 50 37

01 100 74

1 0 400 292

Table 21. CTRL_REG2 register

BOOT HPM1 HPM0 FDS HPen2 HPen1 HPCF1 HPCF0

Table 22. CTRL_REG2 description

BOOT Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

HPM1, HPM0 High pass filter mode selection. Default value: 00

(00: normal mode; Others: refer to Table 23)

FDS Filtered data selection. Default value: 0

(0: internal filter bypassed; 1: data from internal filter sent to output register)

HPen2 High pass filter enabled for interrupt 2 source. Default value: 0

(0: filter bypassed; 1: filter enabled)

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BOOT bit is used to refresh the content of internal registers stored in the flash memory

block. At the device power up the content of the flash memory block is transferred to the

internal registers related to trimming functions to permit a good behavior of the device itself.

If for any reason the content of trimming registers was changed it is sufficient to use this bit

to restore correct values. When BOOT bit is set to ‘1’ the content of internal flash is copied

inside corresponding internal registers and it is used to calibrate the device. These values

are factory trimmed and they are different for every accelerometer. They permit a good

behavior of the device and normally they have not to be changed. At the end of the boot

process the BOOT bit is set again to ‘0’.

HPCF[1:0]. These bits are used to configure high-pass filter cut-off frequency ft which is

given by:

The equation can be simplified to the following approximated equation:

HPen1 High pass filter enabled for interrupt 1 source. Default value: 0

(0: filter bypassed; 1: filter enabled)

HPCF1,

HPCF0

High pass filter cut-off frequency configuration. Default value: 00

(00: HPc=8; 01: HPc=16; 10: HPc=32; 11: HPc=64)

Table 23. High-pass filter mode configuration

HPM1 HPM0 High-pass filter mode

0 0 Normal mode (reset reading HP_RESET_FILTER)

0 1 Reference signal for filtering

1 0 Normal mode (reset reading HP_RESET_FILTER)

Table 24. High-pass filter cut-off frequency configuration

HPcoeff2,1 ft [Hz]

Data rate = 50 Hz

ft [Hz]

Data rate = 100 Hz

ft [Hz]

Data rate = 400 Hz

00 1 2 8

01 0.5 1 4

10 0.25 0.5 2

11 0.125 0.25 1

Table 22. CTRL_REG2 description (continued)

ft11

HPc

------------–

⎝⎠

⎛⎞

2π

------

⋅ln=

6HPc⋅

----------------------=

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7.4 CTRL_REG3 [Interrupt CTRL register] (22h)

7.5 CTRL_REG4 (23h)

Table 25. CTRL_REG3 register

IHL PP_OD LIR2 I2_CFG1 I2_CFG0 LIR1 I1_CFG1 I1_CFG0

Table 26. CTRL_REG3 description

IHL Interrupt active high, low. Default value: 0

(0: active high; 1: active low)

PP_OD Push-pull/Open drain selection on interrupt pad. Default value 0.

(0: push-pull; 1: open drain)

LIR2

Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by

reading INT2_SRC itself. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

I2_CFG1,

I2_CFG0

Data signal on INT 2 pad control bits. Default value: 00.

(see table below)

LIR1

Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by

reading INT1_SRC register. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

I1_CFG1,

I1_CFG0

Data signal on INT 1 pad control bits. Default value: 00.

(see table below)

Table 27. Data signal on INT 1 and INT 2 pad

I1(2)_CFG1 I1(2)_CFG0 INT 1(2) Pad

0 0 Interrupt 1 (2) source

0 1 Interrupt 1 source OR Interrupt 2 source

1 0 Data ready

1 1 Boot running

Table 28. CTRL_REG4 register

0 0 FS1 FS0 STsign 0 ST SIM

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7.6 CTRL_REG5 (24h)

TurnOn bits are used for turning on the sleep to wake function.

7.7 HP_FILTER_RESET (25h)

Dummy register. Reading at this address zeroes instantaneously the content of the internal

high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0g.

This allows to overcome the settling time of the high pass filter.

7.8 REFERENCE (26h)

This register sets the acceleration value taken as a reference for the high-pass filter output.

When filter is turned on (at least one of FDS, HPen2, or HPen1 bit is equal to ‘1’) and HPM

bits are set to “01”, filter out is generated taking this value as a reference.

Table 29. CTRL_REG4 description

FS1, FS0 Full-scale selection. Default value: 00.

(00: ±2 g; 01: ±4 g; 11: ±8 g)

STsign Self-test sign. Default value: 00.

(0: self-test plus; 1 self-test minus)

ST Self-test enable. Default value: 0.

(0: self-test disabled; 1: self-test enabled)

SIM SPI serial interface mode selection. Default value: 0.

(0: 4-wire interface; 1: 3-wire interface)

Table 30. CTRL_REG5 register

000000TurnOn1TurnOn0

Table 31. CTRL_REG5 description

Tu rn On 1 ,

Tu r n O n 0 Turn-on mode selection for sleep to wake function. Default value: 00.

Table 32. REFERENCE register

Ref7 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0

Table 33. REFERENCE description

Ref7 - Ref0 Reference value for high-pass filter. Default value: 00h.

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7.9 STATUS_REG (27h)

7.10 OUT_X (29)

X-axis acceleration data. The value is expressed as two’s complement with 6 bit data

representation right justified.

7.11 OUT_Y (2Bh)

Y-axis acceleration data. The value is expressed as two’s complement with 6 bit data

representation right justified.

7.12 OUT_Z (2Dh)

Z-axis acceleration data. The value is expressed as two’s complement with 6 bit data

representation right justified.

Table 34. STATUS_REG register

ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA

Table 35. STATUS_REG description

ZYXOR

X, Y and Z axis data overrun. Default value: 0

(0: no overrun has occurred;

1: new data has overwritten the previous one before it was read)

ZOR

Z axis data overrun. Default value: 0

(0: no overrun has occurred;

1: a new data for the Z-axis has overwritten the previous one)

YOR

Y axis data overrun. Default value: 0

(0: no overrun has occurred;

1: a new data for the Y-axis has overwritten the previous one)

XOR

X axis data overrun. Default value: 0

(0: no overrun has occurred;

1: a new data for the X-axis has overwritten the previous one)

ZYXDA X, Y and Z axis new data available. Default value: 0

(0: a new set of data is not yet available; 1: a new set of data is available)

ZDA Z axis new data available. Default value: 0

(0: a new data for the Z-axis is not yet available;

1: a new data for the Z-axis is available)

YDA Y axis new data available. Default value: 0

(0: a new data for the Y-axis is not yet available;

1: a new data for the Y-axis is available)

XDA X axis new data available. Default value: 0

(0: a new data for the X-axis is not yet available;

1: a new data for the X-axis is available)

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7.13 INT1_CFG (30h)

Configuration register for Interrupt 1 source.

Table 36. INT1_CFG register

AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE

Table 37. INT1_CFG description

AOI AND/OR combination of Interrupt events. Default value: 0.

(See Table 38)

6D 6 direction detection function enable. Default value: 0.

(See Table 38)

ZHIE

Enable interrupt generation on Z high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

ZLIE

Enable interrupt generation on Z low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

YHIE

Enable interrupt generation on Y high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

YLIE

Enable interrupt generation on Y low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

XHIE

Enable interrupt generation on X high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

XLIE

Enable interrupt generation on X low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

Table 38. Interrupt 1 source configurations

AOI 6D Interrupt mode

0 0 OR combination of interrupt events

0 1 6 direction movement recognition

1 0 AND combination of interrupt events

1 1 6 direction position recognition

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7.14 INT1_SRC (31h)

Interrupt 1 source register. Read only register.

Reading at this address clears INT1_SRC IA bit (and the interrupt signal on INT 1 pin) and

allows the refreshment of data in the INT1_SRC register if the latched option was chosen.

7.15 INT1_THS (32h)

7.16 INT1_DURATION (33h)

Table 39. INT1_SRC register

0 IA ZHZLYHYLXHXL

Table 40. INT1_SRC description

IA Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

ZH Z high. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

ZL Z low. Default value: 0

(0: no interrupt; 1: Z low event has occurred)

YH Y high. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

YL Y low. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

XH X high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

XL X low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Table 41. INT1_THS register

0 THS6 THS5 THS4 THS3 THS2 THS1 THS0

Table 42. INT1_THS description

THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000

Table 43. INT1_DURATION register

0 D6D5D4D3D2D1D0

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D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized. Duration

steps and maximum values depend on the ODR chosen.

7.17 INT2_CFG (34h)

Configuration register for Interrupt 2 source.

Table 44. INT2_DURATION description

D6 - D0 Duration value. Default value: 000 0000

Table 45. INT2_CFG register

AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE

Table 46. INT2_CFG description

AOI AND/OR combination of Interrupt events. Default value: 0.

(See table below)

6D 6 direction detection function enable. Default value: 0.

(See table below)

ZHIE

Enable interrupt generation on Z high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

ZLIE

Enable interrupt generation on Z low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

YHIE

Enable interrupt generation on Y high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

YLIE

Enable interrupt generation on Y low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

XHIE

Enable interrupt generation on X high event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value higher than preset threshold)

XLIE

Enable interrupt generation on X low event. Default value: 0

(0: disable interrupt request;

1: enable interrupt request on measured accel. value lower than preset threshold)

Table 47. Interrupt mode configuration

AOI 6D Interrupt mode

0 0 OR combination of interrupt events

0 1 6 direction movement recognition

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7.18 INT2_SRC (35h)

Interrupt 2 source register. Read only register.

Reading at this address clears INT2_SRC IA bit (and the interrupt signal on INT 2 pin) and

allows the refreshment of data in the INT2_SRC register if the latched option was chosen.

7.19 INT2_THS (36h)

1 0 AND combination of interrupt events

1 1 6 direction position recognition

Table 47. Interrupt mode configuration (continued)

AOI 6D Interrupt mode

Table 48. INT2_SRC register

0 IA ZHZLYHYLXHXL

Table 49. INT2_SRC description

IA Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

ZH Z high. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

ZL Z low. Default value: 0

(0: no interrupt; 1: Z low event has occurred)

YH Y high. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

YL Y low. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

XH X high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

XL X low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Table 50. INT2_THS register

0 THS6 THS5 THS4 THS3 THS2 THS1 THS0

Table 51. INT2_THS description

THS6 - THS0 Interrupt 1 threshold. Default value: 000 0000

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7.20 INT2_DURATION (37h)

D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized. Duration

time steps and maximum values depend on the ODR chosen.

Table 52. INT2_DURATION register

0 D6D5D4D3D2D1D0

Table 53. INT2_DURATION description

D6 - D0 Duration value. Default value: 000 0000

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Package information LIS331DLF

36/38 Doc ID 15101 Rev 4

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK is an ST trademark.

Figure 12. LGA16: mechanical data and package dimensions

Dimensions

Ref. mm inch

Min. Typ. Max. Min. Typ. Max.

A1 1.000 0.0394

A2 0.7850.0309

A30.200 0.0079

D1 2.850 3.000 3.150 0.1122 0.1181 0.1240

E1 2.850 3.000 3.150 0.1122 0.1181 0.1240

L1 1.000 1.060 0.0394 0.0417

L2 2.000 2.060 0.07870.0811

N1 0.500 0.0197

N2 1.000 0.0394

M 0.040 0.100 0.160 0.0016 0.0039 0.0063

P1 0.875 0.0344

P2 1.275 0.0502

T1 0.2900.350 0.410 0.0114 0.0138 0.0161

T2 0.190 0.250 0.310 0.0075 0.0098 0.0122

d 0.150 0.0059

k 0.050 0.0020

LGA16 (3x3x1.0mm)

Land Grid Array Package

Outline and

7983231

mechanical data

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LIS331DLF Revision history

Doc ID 15101 Rev 4 37/38

9 Revision history

Table 54. Document revision history

Date Revision Changes

16-Oct-2008 1 Initial release

03-Nov-2008 2 Table 10, 15, 16 have been updated

21-Nov-2008 3 Updated Table 4 on page 10

10-Jul-2009 4

Updated: Table 3 on page 9, Table 4 on page 10, Table 6 on

page 12, Table 7 on page 13, Table 28 on page 28, Table 29 on

page 29

Minor text changes to improve readability

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LIS331DLF

38/38 Doc ID 15101 Rev 4

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