ACen: AS7C3513 i ORO ms eM tom ONO Rs). 1.0i4 Features O wanization : 32,768 wordsx 16 bis TTL-com patibk, three-date 1/0 H igh speed 44-0in EDEC standard package - 10/12/15/20 ns address accesstine -400milSJd - 5/6/8/10 ns outoutenabk acesstime -400milTOPL e Low pow erconsum ption U pw ard com patibility -Actve: 504mW max (20 nscyck) - Sandby:18mW max,CMOS/V/O - Very low DC com ponent 3n active pow er 2 OV data retention Fqualaccess and cycE tim es Easy m em ory expansion w ith CE, OF inputs - 64Kx 16 (AS7C1026) - 256Kx16 (@S/C4098) Center pow er and ground pins eESD protection > 2000 volts eLatchwp acunent= 200mA 3 3V version avaibbk (AS7C3513) Logic block diagram Pin arrangement A0 Ly, SOITHPI AL | 4 oe A2>) G 32K x 16 kX GND nweL dig loa AS 3 Aray a3 C42 43[- 4] as aa>| 0 A2 D3 42] a6 as>| 2 Al Doj4 4107 OF aw Ao C45 40[-] UB AG > ce C6 390] TB AT >| yoo C47 38s] yols yo. Coys 37 you o0-Yo? yor L-]J9 361 O13 /o8-1/015 yo3 J} 10 35-1 yol2 Uv... ] Voge Fl 34{(-_] GND GND C712 33(- J] Voc yos (14 31( 1 Yolo yoo (15 30f(-] yoo L yo? 416 291 os a We C17 23f(-_] Nc aE Al4 C18 27] a7 AB Coji9 26{-] as OE Al2 2} 20 25(-] a9 = Al Coj2 24{(-7] Alo 1B ne C22 23] Ne CE Selection guide 7C513-10 70513-12 7513-15 7C513-20 703513-10 703513-12 7C3513-15 703513-20 Unit Maxmum address accesstime 10 12 15 20 ns Maximum outputenak accesstme 5 5 8 10 ns AS7C513 170 160 150 140 mA Maxmum operating cunent AS7C3513 130 120 110 100 mA Maxmum CMOS standby cunent 5 5 5 5 mA Shaded areas indicate advance infom ation. ee eye ALLIANCE SEMICONDUCTOR ss Copyright 1998 Alliance Semiconductor, All rights reserved,Seu AS7C513 AS7C3513 Ay Functional description The AS/C513 is ahigh perform ance CM OS 524,288-bit Static Random AccessM en ory (SRAM ) organized as 32,768 worlsx 16 bits. kis designed form em ory app ications w here fast data access, low power and sm pk Interfacing are desired. Equaladdress access and cycle tim es (Ha, tec: yc) Of 10/12/15/20 nsw ith outputenabk access tim es (fz) Of 5/6/8/10 ns are ideal for high perform ance applications. The chip enabke input CE pemn its easy m en ory expansion w ith m ulHple-bank m en ory system s. W hen CE jsH igh the device enters sandby m ode. The ASC513 is guaranteed notto exceed 28 mW powerconsum ption in CMOS standby m ode. This device also offers 2.0V data retention . A w rite cyck js accom plished by asserting w rife enabk WE) and chip abr CE).Dataon the input pins /0 0-015 iswritten on the rising edge of WE (w rite cycle 1) orCE (w rite cycle 2). To avoid bus contention, extemaldevices should drive I/O pins ony after outputs have been disebled w ith outputenabke E) orw rite nabke WE). A read cycle js accom plished by asserting outputenadble OE) and chip nde CF), w ith w rite encbke WE) High. The chip drives /O pins w ith the data word referenced by the input address. W hen etther chip enabk or output enabke is Inactive, orw rite enadbke js active, output drivers say In high-m pedancem ode. This device providesm ulHip ke centerpow er and ground pins, and separate byte enabk contiols, allow ing Individualbytes to bew ritten and ead. .TB controls the bw erbits, I/0 0-J/0 7, and UB cont the higherbits, 1/0 8-1/015. Allchip inputs and outputs ae TTL-com patbek, and operation is fom asmngk 5V sippy. TheAS/C513 is packaged In common Industry standard packages. Absolute maximum ratings Param eter Symbol Mm Max Unit Voltage on any pm welahve to GND Ve -1 +70 Vv Pow er dissipation Pp - 10 W Storage tem perature (plastic) Tae -55 +150 c Tem perature under bias Tas -10 +85 C DC outputcunent ut - 50 mA NOTE: Stresses greater than those listed under AtsdufeMaxirum Raingsm ay cause perm anent dam age to the device. This is a stress rating ony and fiinctional operation of the device at these or any other conditions outside those indicated in the operational sections of this goecification is not im plied. Exposure to absolitem aximum yating conditions frextended perodsm ay affect reliability. Truth table CE WE CE IB UB YOO-YO7 Yo8-lol5 Mode H x x x x High Z High Z Standby L H L L H Dour High Z Read 1/0 0-1/0 7 L H L H L High Z Dour Read 1/0 8-1/015 L H L L L Dour Dour Read 1/0 0-Y/015 L L xX L L Day Dy W nite 1/0 0-1/015 L L xX L H Day High Z W rte 00-07 L L xX H L High Z Dy W rite 1/0 8-1/015 : High Z High Z Outputdisxbke Key: X = dontcare, L= Low, H = High 58 ALLIANCE SEMICONDUCTOR See acAS7C513 i AS7C3513 I FY Recommended operating conditions Param eter Sym bol Min Typ Max Unit AS7C513 Veo 45 50 55 Vv Supply voltage AS7C3513 Vec 30 33 3.6 Vv GND 00 00 00 Vv ASIC513 Viz 22 - Veot 05 V Input voltage AS7C3513 Va 20 - Veco t+ 05 Vr -05' - 08 Vv Am bient operating tem perature Ta 0 - 70 C tyam in = 3.0V forpusew ith essthan R./2. DC operating characteristics 10 12 15 ~20 Payam eter Sym bol Test conditions Min Max!]Min Max|Min Max|Min Max! Unit Input kakage cunent | El OVS Vi, S Voc 5 5 5 5 5 5 5 5 A 0 tC 0 ts disalled utput Bakage ILo | utputs clisal. S 5 5 5 5 5 5 5 WA cunent OV S$ VourS Vee Operating CES Va Veo = Max AS7C513 = 170) - 160) - 150] - 140 power supply ke outputs open, mA cunent = 4. = 1/tee AS7C3513 = 130) - 120) - 110] - 100 CES Vy, Veco = Max Ip outputs open, = 70) - 60)] - 50] - 40] mA Standby = fx = 1/tee pow er supply _ cunent CE2 Vec-0 2V, Veg = Max, Tg34 Vi SGND + O2Vor = 58) - 5]- 5]- 5 ]ma Vin 2 Veco 0 2V, f= 0 Vi = 8mA,Ve-=Mn = O04) - O04] - OA} - O4 V Output volege ct bu < Vor by = -4mA,Voo=Min 24 -|24 -|]24 -]24 -] Vv Shaded areas indicate advance infor ation. Capacitance Param eter Sym bol Signals Test conditions Max Unit Thput capacitance Cy A, CE, W E, OE, LB, UB Vin = OV 5 pF YO capacitance Cryo Yo Van = Vour= OV 7 pF ee ere ALLIANCE SEMICONDUCTOR reSeu AS7C513 AS7C3513 | Fd Read cycle 37 10 12 -15 -20 Param eter Symbol | Min Max | Min Max] Min Max | Min Max | Unit Notes Read cyce tme tac 10 = 12 - 15 20 ns Address access tim e tan = 10 12 - 15 - 20 ns 3 Chip enable: CE) acesstime tacr = 10 - 12 - 15 - 20 ns 3 Outputenadbl OF) acesstme top = 5 5 - 8 - 10 ns Outputhol fom addresschange ty; 3 = 3 - 4 - 4 - ns 5 CE Low to outputin low Z tepz 0 = 0 - 0 - 0 - ns 4,5 CE H igh t output in high Z ter = 5 - 6 - 6 - 8 ns 4,5 OE Low to outputin lw Z to 0 = 0 - 0 - 0 - ns 4,5 Byte ect access tim e ten = 5 - 6 - 8 - 10 ns Byte seectLow to Low % ters 0 = 0 - 0 - 0 - ns 45 Byte sekctH igh to High-Z tery - 5 - 6 - 6 - 8 ns 4,5 OE H igh to output n high Z tous - 5 6 - 6 - 8 ns 4,5 Pow erup time toy 0 = 0 - 0 - 0 - ns 4,5 Pow er down tme tep 10 - 12 - 15 - 20 ns 4,5 Shaded areas indicate advance inform ation. Read waveform 1 %67? tre Adtas ton Ddaat Data valid Read waveform 27689 Acttes SF \\\\\ tou al ZF AAAS L__ tz KX TB terz _ Detaat ALLIANCE SEMICONDUCTOR i Ev.6 10d Bey ares t8y achesAS7C513 i AS7C3513 Fe: Write cycle 10 12 15 20 Param eter Symbol |Min Max|Min Max|Min Max|Mm Max| Unit Notes W ntecycetme tic 10 = 12 - 15 - 20 ns Chip enabke CE) tp w rite end tew 8 9 10 06 - | (13 ns Addiess setup to w rite end tw 7 8 10 - 12 ns Addiess setup tim e tas 0 0 0 - 0 ns W ote pulew ith ty p 7 8 - 10 - 12 ns Addiesshold from end ofw rte tay 0 0 0 0 ns Data valid tb w rte end tow 5 6 8 - 10 ns Datahokitme tor 0 0 0 - 0 ns 5 W rte end tb output in High Z ty = 5 - 6 - 6 8 ns 4,5 Output achive from w nite end tow 3 3 3 3 ns 4,5 Byte sekct Low to end ofw nte tay 7 9 9 12 ns Shaded areas indicate advance infor ation. Write waveform 1 7842 Adtes CE TB WE Daain Dettaat Write waveform 2144 Adtes Daain tetz, wor __ tow Ddaat Data undefined Sener) ALLIANCE SEMICONDUCTOR foSeu AS7C513 AS7C3513 Ay Data retention characteristics Pavan eter Sym bol Test conditions Min M ax Unit Voc Prdaa wtention Vor 20 - Vv , Veo = 2.0V D af vetention curent kcpr _ - 500 HA CE 2 Vece-0 2V Chip deselect to data retention tme tepR ce 0 - ns Vin 2 Veco (02 ao Operation recovery tim e me sce - ns P te Vn S 02V Es Thput kekage current | El - 1 pA Data retention waveform AC test conditions 4 5V or3.0V 4>W - Output bad: se Figure B, except asnoted. Input pul Evel GND to 3 0V. Se Fiquea. Input rise and falltim es: 2 ns. See FigureaA. Input and outout tm ing reference Evel: 1 5V. BON og 90% GND 10% Ons 10% Figure A: Input pulse Notes W E isH igh frread cyck. CE and OF are Low formad cycke. Oo OwmwA Do PB WHY PF le Data retention m ode Vor 2 2 0V J ASV 003 0V tepR Vor Thevenin equivalent: 168Q Dourrf\Ae +1.728V +5V +5V 480Q 480Q Dout Dou 25502 30 pF* 25502 5 pF* including scope and jig capacitance GND GND Figure B: Output load During Vee pow erup, apulhip resistorto Voc on CE is required to m eet. ky specification . This paran eter is sam pd andnot100% tested. For test conditions, see AC Tat Contig FiguresA,B,C. These param eters are soecified w ith C, = SpF as in Figure C . Transition ism easured +500m V from This param eter Js quayanteed but not tested. Address valid priorto or coincidentw ith CE transition Low . Allread cycle tin ings ave referenced from the /ast valid address to the first tansitioning address. 10 CEKorW Em ustbe H igh during address transitions. 11 Allw rite cycle tim ings ave referenced from the ast valid address to the first transitioning address. 62 ALLIANCE SEMICONDUCTOR Figure C: Output load for te, toyz; toLz touz: tow seady-state vo lage. JOSS Bl eo 28 Od Bee Mae Fay cone)AS7C513 / AS7C3513 | Fe Typical DC and AC characteristics Nom alized supply cunent Lc, kp Nom alized supply cunent Lc, kp Nom alized supply current kay vs. supply voltage Vec vs. an bientten peratize T, vs. an bient ten perature T, 14 14 12 12 ~ 625 io io 4 95 Q Q 3 og og g 5 k 06 k 06 i 1 S OA S OA & 02 02 02 = 904 00 00 40 45 50 55 60 55 -10 35 80 125 55 -10 35 80 125 Suppl volte (Vv) Am bienttem perature (C) Am bienttem perature (C) Noun alized access tim hy Norm alized access tm {ay Norm alized supply current ke vs. supply volege Voc vs. an bient tam perature T, vs. cycle frequency 1/tgo, 1/ty 15 15 14 14 14 12 5 T,= 25C 5 Veo = 5OV Veo = 5.0V B13 B13 19 8 T= 25 : 12 : 12 i os @aia k 11 06 i & 10 & 10 4 04 3 3 4 4 09 09 02 08 08 00 40 45 50 55 60 55 -10 35 80 125 0 25 50 75 100 Supply voltage (V) Am bienttem perature (C) Cycle frequency MHz) Output source cunent & x Output sink curent hy, Typical access tim e change Ata, vs. output vo lege Vo 4 vs. output vo tage Voz, vs. output capacitive lbading 140 140 35 wz 120 ~ 120 30 E Veco = 5OV e Voc = 5OV _ Voc = 45V i 100 F p= 95% 100 9, = 25% @ 25 3 80 p 80 #20 E60 : 60 O15 3 4 oO : 5 E 2 40 5 40 S 10 2 5 5 20 2 20 5 0 0 0 00 125 25 3.75 50 00 125 25 315 50 0 250 500 750 1000 Outputvolge (Vv) Output volege (Vv) Capacitance (oF) Sener) ALLIANCE SEMICONDUCTOR 63AS7C513 AS7C3513 Package dimensions OOO 0000 oOoooo ono 44-pin TSOP IE 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 T c . Min mm) Max fmm) A 12 = Ay 0.05 Ps 44-pin TSOP IE e Hs Ay 0.95 105 wn b 025 0 A5 | c 015 (typical) d 2085 21.05 e 10.06 1026 He 11.56 11.96 1 E 0.80 (typical) 1 0 A0 0.60 44-pin DT 400 mil Min Max A 0.128 0148 Al 0.025 - 2 1105 14115 B 0.026 0 032 b 0.015 0 020 c ce 0.007 0013 D 1120 1130 E 0370NOM Ai 0395 0 A05 B 0.435 0.445 e 0.050 NOM AS7C(3)513 ordering codes Package \ Access tim e 10 ns i2ns 15 ns 20 ns . . ASIC5S13-10 AS7C513412 AS7C513-15f ASIC513-20 P SOg 400 m aL AS/C 3513-100 AS7C3513412 AS7C3513-15f AS/C3513-20 TSOP I 184x102 mm ASIC513-10TC AS7C513-12TC AS7C513-15TC AS7IC513-20TC , AS/C3513-107C AS7C3513-12TC AS7C3513-15TC AS7/C3513-20TC AS7C(3)513 part numbering system ASIC x 513 XK x Cc Package: J = $0 J400m iL VoltageBhnk = 5V CMOS . . age m Comm ercialten perature SRAM prefix Device num ber Accesstme T = TSPI, 3 =33VCMOS range, 0C to 70 C 18 4x102mm 64 ALLIANCE SEMICONDUCTOR eer