1
®
FN3150.5
HI-546, HI-547, HI-548, HI-549
Single 16 and 8, Differential 8-Channel
and 4-Channel CMOS Analog MUXs with
Active Overvo ltage Protection
The HI-546, HI-547, HI-548 and HI-549 are analog
multiplexers with active overvoltage protection and
guaranteed rON matching. Analog input levels may greatly
exceed either power supply without damaging the device or
disturbing the signal path of other channels. Active
protection circuitry assures that signal fidelity is maintained
even under fault conditions that would destroy other
multiplexers.
Analog inputs can withstand constant 70VP-P levels with
±15V supplies. Digital inputs will also sustain continuous
faults up to 4V greater than either supply. In addition, signal
sources are protected from short circuiting sh ould
multiplexer supply loss occur. Each input presents 1kΩ of
resistance under this condition. These features mak e the
HI-546, HI-547, HI-548 and HI-549 ideal f or use in systems
where the analog inputs originate from external equipment
or separately powered circuitry. All devices are fabricated
with 44V Dielectrically Isolated CMOS technology. The
HI-546 is a single 16-Channel, the HI-547 is an 8-Channel
diff erential, the HI-548 is a single 8-Channel and the HI-549
is a 4-Channel differential device. If input overvoltage
protection is not needed the HI-506/507/508/509
multiplexers are recommended. For further informati on see
Application Notes AN520 and AN521.
F or MIL-STD-883 compliant parts, request the HI-546/883,
HI-547/883, HI-548/883 and HI-549/883 datasheets.
Features
• Analog Overvoltage Protection. . . . . . . . . . . . . . . . . . 70VP-P
• No Channel Interaction During Overvoltage
• Guaranteed rON Matching
• Maximum Power Supply. . . . . . . . . . . . . . . . . . . . . . . 44V
• Break-Before-Make Switching
• Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . . 500ns
• Standby Power (Typical). . . . . . . . . . . . . . . . . . . . . 7.5mW
•Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Data Acquisition
• Industrial Controls
• Telemetry
Data Sheet September 21, 2005
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Ordering Information
PART
NUMBER PART
MARKING
TEMP.
RANGE
(oC) PACKAGE PKG.
DWG. #
HI1-0546-5 HI1-546-5 0 to 75 28 Ld CERDIP F28.6
HI1-0546-2 HI1-546-2 -55 to 125 28 Ld CERDIP F28.6
HI3-0546-5 HI3-546-5 0 to 75 28 Ld PDIP E28.6
HI4P0546-5 HI4P546-5 0 to 75 28 Ld PLCC N28.45
HI4P0546-5Z
(Note) HI4P546-5Z 0 to 75 28 Ld PLCC
(Pb-free) N28.45
HI9P0546-9** HI9P546-9 -40 to 85 28 Ld SOIC M28.3
HI9P0546-9Z**
(Note) HI9P546-9Z -40 to 85 28 Ld SOIC
(Pb-free) M28.3
HI1-0547-5 HI1-547-5 0 to 75 28 Ld CERDIP F28.6
HI3-0547-5 HI3-547-5 0 to 75 28 Ld PDIP E28.6
HI3-0547-5Z
(Note) HI3-0547-5Z 0 to 75 28 Ld PDIP*
(Pb-free) E28.6
HI4P0547-5 HI4P547-5 0 to 75 28 Ld PLCC N28.45
HI4P0547-5Z
(Note) HI4P547-5Z 0 to 75 28 Ld PLCC
(Pb-free) N28.45
HI9P0547-9 HI9P547-9 -40 to 85 28 Ld SOIC M28.3
HI9P0547-9Z
(Note) HI9P547-9Z -40 to 85 28 Ld SOIC
(Pb-free) M28.3
HI1-0548-2 HI1-548-2 -55 to 125 16 Ld CERDIP F16.3
HI1-0548-5 HI1-548-5 0 to 75 16 Ld CERDIP F16.3
HI3-0548-5 HI3-548-5 0 to 75 16 Ld PDIP E16.3
HI4P0548-5 HI4P548-5 0 to 75 20 Ld PLCC N20.35
HI9P0548-5** HI9P548-5 0 to 75 16 Ld SOIC M16.15
HI9P0548-5Z**
(Note) HI9P548-5Z 0 to 75 16 Ld SOIC
(Pb-free) M16.15
HI9P0548-9 HI9P548-9 -40 to 85 16 Ld SOIC M16.15
HI9P0548-9Z
(Note) HI9P548-9Z -40 to 85 16 Ld SOIC
(Pb-free) M16.15
HI1-0549-2 HI1-549-2 -55 to 125 16 Ld CERDIP F16.3
HI3-0549-5 HI3-549-5 0 to 75 16 Ld PDIP E16.3
HI4P0549-5 HI4P549-5 0 to 75 20 Ld PLCC N20.35
HI4P0549-5Z
(Note) HI4P549-5Z 0 to 75 20 Ld PLCC
(Pb-free) N20.35
HI9P0549-9 HI9P549-9 -40 to 85 16 Ld SOIC M16.15
HI9P0549-9Z
(Note) HI9P549-9Z -40 to 85 16 Ld SOIC
(Pb-free) M16.15
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
**Add “96” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Ordering Information (Continued)
PART
NUMBER PART
MARKING
TEMP.
RANGE
(oC) PACKAGE PKG.
DWG. #
Pinouts HI-546 (CERDIP, PDIP, SOIC)
TOP VIEW HI-547 (CERDIP, PDIP, SOIC)
TOP VIEW
+VSUPPLY
NC
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
VREF
ADDRESS A3
OUT
IN 8
IN 7
IN 6
IN 5
IN 3
IN 1
ENABLE
ADDRESS A0
ADDRESS A1
ADDRESS A2
-VSUPPLY
IN 4
IN 2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+VSUPPLY
OUT B
NC
IN 8B
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B
GND
VREF
NC
OUT A
IN 8A
IN 7A
IN 6A
IN 5A
IN 3A
IN 1A
ENABLE
ADDRESS A0
ADDRESS A1
ADDRESS A2
-VSUPPLY
IN 4A
IN 2A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
HI-546, HI-547, HI-548, HI-549
3
HI-546 (PLCC)
TOP VIEW HI-547 (PLCC)
TOP VIEW
HI-548 (CERDIP, PDIP, SOIC)
TOP VIEW HI-549 (CERDIP, PDIP, SOIC)
TOP VIEW
HI-548 (PLCC)
TOP VIEW HI-549 (PLCC)
TOP VIEW
Pinouts (Continued)
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
IN 16
NC
NC
+VSUPPLY
OUT
-VSUPPLY
IN 8
GND
VREF
A3
A2
A1
ENABLE
A0
IN 7
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
1234
5
6
7
8
9
10
11
12 13 14 15 16 17 18
19
20
21
22
23
24
25
262728
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B
IN 8B
NC
OUT B
+VSUPPLY
OUT A
-VSUPPLY
IN 8A
GND
VREF
NC
A2
A1
ENABLE
A0
IN 7A
IN 6A
IN 5A
IN 4A
IN 3A
IN 2A
IN 1A
1234
5
6
7
8
9
10
11
12 13 14 15 16 17 18
19
20
21
22
23
24
25
262728
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
ENABLE
-VSUPPLY
IN 1
IN 2
IN 3
OUT
IN 4
A1
GND
+VSUPPLY
IN 5
IN 6
IN 7
IN 8
A2
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
ENABLE
-VSUPPLY
IN 1A
IN 2A
IN 3A
OUT A
IN 4A
A1
+VSUPPLY
IN 1B
IN 2B
IN 3B
IN 4B
OUT B
GND
-VSUPPLY
IN 1
NC
IN 2
IN 3
ENABLE
A0
NC
A1
A2
IN 4
OUT
NC
IN 8
IN 7
GND
+VSUPPLY
NC
IN 5
IN 6
193 2 201
15
16
17
18
14
910 11 12 13
4
5
6
7
8
-VSUPPLY
IN 1A
NC
IN 2A
IN 3A
ENABLE
A0
NC
A1
GND
IN 4A
OUT A
NC
OUT B
IN 4B
+VSUPPLY
IN 1B
NC
IN 2B
IN 3B
193 2 201
15
16
17
18
14
910 11 12 13
4
5
6
7
8
HI-546, HI-547, HI-548, HI-549
4
TRUTH TABLE HI-546
A3A2A1A0EN “ON” CHANNEL
XXXXL None
LLLLH 1
LLLHH 2
LLHLH 3
LLHHH 4
LHLLH 5
LHLHH 6
LHHLH 7
LHHHH 8
HLLLH 9
HLLHH 10
HLHLH 11
HLHHH 12
HHLLH 13
HHLHH 14
HHHLH 15
HHHHH 16
TRUTH TABLE HI-547
A2A1A0EN “ON” CHANNEL PAIR
X X X L None
LLLH 1
LLHH 2
LHLH 3
LHHH 4
HLLH 5
HLHH 6
HHLH 7
HHHH 8
TRUTH TABLE HI-548
A2A1A0EN “ON” CHANNEL
X X X L None
LLLH 1
LLHH 2
LHLH 3
LHHH 4
HLLH 5
HLHH 6
HHLH 7
HHHH 8
TRUTH TABLE HI-549
A1A0EN “ON” CHANNEL PAIR
X X L None
LLH 1
LHH 2
HLH 3
HHH 4
TRUTH TABLE HI-547 (Continued)
A2A1A0EN “ON” CHANNEL PAIR
Functional Diagrams
HI-546 HI-547
DECODER/
DRIVER
† † † †
OUT
IN 1
IN 2
IN 16
† DIGITAL INPUT
VREF A0A1A2
†
EN
LEVEL
SHIFT
5V
REF
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
PROTECTION
A3
1K
1K
1K DECODER/
DRIVER
† † †
OUT
IN 1A
IN 8A
IN 8B
† DIGITAL INPUT
VREF A0A1A2
†
EN
LEVEL
SHIFT
5V
REF
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
PROTECTION
1K
1K
1K
1K
A
OUT
B
IN 1B
HI-546, HI-547, HI-548, HI-549
5
HI-548 HI-549
Functional Diagrams (Continued)
DECODER/
DRIVER
† † †
OUT
IN 1
IN 2
IN 8
† DIGITAL INPUT
A0A1A2
†
EN
LEVEL
SHIFT
5V
REF
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
PROTECTION
1K
1K
1K DECODER/
DRIVER
† †
OUT
IN 1A
IN 4A
IN 4B
† DIGITAL INPUT
A0A1
†
EN
LEVEL
SHIFT
5V
REF
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
PROTECTION
1K
1K
1K
1K
A
OUT
B
IN 1B
Schematic Dia grams
ADDRESS DECODER
P
N
A0 OR A0
TO N-CHANNEL
DEVICE OF
THE SWITCH
A1 OR A1
A2 OR A2
A3 OR A3
ENABLE
PP PP P P
V+
V-
N
N
N
N
NN
T O P-CHANNEL
DEVICE OF
THE SWITCH
DELETE A3 OR A3 INPUT FOR HI-547, HI-548, HI-549
DELETE A2 OR A2 INPUT FOR HI-549
HI-546, HI-547, HI-548, HI-549
6
MULTIPLEX SWITCH
Schematic Dia grams (Continued)
IN
FROM
DECODE
R11
1K
V+
P
D6 D7
Q6
FROM
DECODE
OVERVOLTAGE PROTECTION
V-
Q5
D4 D5
N
N
N
P
OUT
HI-546, HI-547, HI-548, HI-549
7
ADDRESS INPUT BUFFER AND LEVEL SHIFTER
Schematic Dia grams (Continued)
LEVEL SHIFTER
P
N
P
N
N
P
N
P
VREF
ADD
IN
N
P
N
P P
N
P
NN
P
N
P
LEVEL
SHIFTED
ADDRESS
TO
TTL REFERENCE
CIRCUIT
V+
R10
R9
Q1
Q4
D3
GND
OVERVOLTAGE
PROTECTION
D2
R1
200
V-
Ω
D1
V+
R2
R3
GND
V+
V-
DECODE
R4
R5 R7
R8
R6
HI-546, HI-547, HI-548, HI-549
8
Absolute Maximum Ratings Thermal Info rmation
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V
Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . (V-) -4V to (V+) +4V
Analog Signal (VIN, VOUT). . . . . . . . . . . . . . . (V-) -20V to (V+) +20V
or 20mA, Whichever Occurs First
Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, IN or OUT (Pulsed 1ms, 10% Duty Cycle Max). . 40mA
Operating Conditions
Temperature Ranges
HI-546/548/549-2 . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
HI-546/547/548/549-5 . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
HI-546/547/548/549-9 . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
16 Ld CERDIP Package. . . . . . . . . . . 85 32
28 Ld CERDIP Package. . . . . . . . . . . 55 18
28 Ld PDIP Package*. . . . . . . . . . . . . 60 N/A
16 Ld PDIP Package . . . . . . . . . . . . . 90 N/A
28 Ld PLCC Package. . . . . . . . . . . . . 70 N/A
20 Ld PLCC Package. . . . . . . . . . . . . 80 N/A
28 Ld SOIC Package . . . . . . . . . . . . . 75 N/A
16 Ld SOIC Package . . . . . . . . . . . . . 105 N/A
Maximum Junction Temperature
Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(PLCC, SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above t hose indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V; Unless
Otherwise Specified. For Test Conditions, Consult Test Circuits Section
PARAMETER TEST
CONDITIONS TEMP
(oC)
-2 -5, -9
UNITSMIN TYP MAX MIN TYP MAX
SWITCHING CHARACTERISTICS
Access Time, tA25 - 0.5 - - 0.5 - µs
Full - - 1.0 - - 1.0 µs
Break-Before Make Delay, tOPEN 25 25 80 - 25 80 - ns
Enable Delay (ON), tON(EN) 25 - 300 500 - 300 - ns
Full - - 1000 - - 1000 ns
Enable Delay (OFF), tOFF(EN) 25 - 300 500 - 300 - ns
Full - - 1000 - - 1000 ns
Settling Time To 0.1% 25 - 1.2 - - 1.2 - µs
To 0.01% 25 - 3.5 - - 3. 5 - µs
Off Isolation Note 6 25 50 68 - 50 68 - dB
Channel Input Capacitance, CS(OFF) 25-10- -10-pF
Channel Output Capacitance CD(OFF)
HI-546 25 - 52 - - 52 - pF
HI-547 25 - 30 - - 30 - pF
HI-548 25 - 25 - - 25 - pF
HI-549 25 - 12 - - 12 - pF
Input to Output Capacitance, CDS(OFF) 25 - 0.1 - - 0.1 - pF
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, TTL Drive, VAL Full - - 0.8 - - 0.8 V
Input High Threshold, VAH (Note 8) Full 4.0 - - 4.0 - - V
MOS Drive, VAL (HI-546/547 Only) VREF = 10V 25 - - 0.8 - - 0.8 V
HI-546, HI-547, HI-548, HI-549
9
MOS Drive, VAH (HI-546/547 Only) VREF = 10V 25 6.0 - - 6.0 - - V
Input Leakage Current (High or Low), IANote 5 Full - - 1.0 - - 1.0 µA
ANALOG CHANNEL CHARACTERISTICS
Analog Signal Range, VIN Full -15 - +15 -15 - +15 V
On Resistance, rON Note 2 25 - 1.2 1.5 - 1.5 1.8 kΩ
Full - 1.5 1.8 - 1.8 2.0 kΩ
∆rON, (Any Two Channels) 25 - - 7.0 - - 7.0 %
Off Input Leakage Current, IS(OFF) Note 3 25 - 0.03 - - 0.03 - nA
Full - - 50 - - 50 nA
Off Output Leakage Current, ID(OFF) Note 3 25 - 0.1 - - 0.1 - nA
HI-546 Full - - 300 - - 300 nA
HI-547 Full - - 200 - - 200 nA
HI-548 Full - - 200 - - 200 nA
HI-549 Full - - 100 - - 100 nA
ID(OFF) With Input Overvoltage Applied Note 4 25 - 4.0 - - 4.0 - nA
Full--2.0---µA
On Channel Leakage Current, ID(ON) Note 3 25 - 0.1 - - 0.1 - nA
HI-546 Full - - 300 - - 300 nA
HI-547 Full - - 200 - - 200 nA
HI-548 Full - - 200 - - 200 nA
HI-549 Full - - 100 - - 100 nA
Differential Off Output Leakage Current
IDIFF (HI-547, HI-549 Only) Full - - 50 - - 50 nA
POWER SUPPLY CHARACTERISTICS
Power Dissipation, PDFull - 7.5 - - 7.5 - mW
Current, I+ Note 7 Full - 0.5 2.0 - 0.5 2.0 mA
Current, I- Note 7 Full - 0.02 1.0 - 0.02 1.0 mA
NOTES:
2. VOUT = ±10V, IOUT = 100µA.
3. 10nA is the practical lower limit for high speed measurement in the production test environments.
4. Analog Overvoltage = ±33V.
5. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25oC.
6. VEN = 0.8V, RL = 1K, CL = 15pF, VS = 7VRMS, f = 100kHz.
7. VEN, VA = 0V or 4V.
8. To drive from DTL/TTLCircuits, 1kΩ pull-up resistors to +5V supply are recommended.
Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V; Unless
Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued)
PARAMETER TEST
CONDITIONS TEMP
(oC)
-2 -5, -9
UNITSMIN TYP MAX MIN TYP MAX
±
HI-546, HI-547, HI-548, HI-549
10
Test Circuits and W a veforms TA = 25oC, VSUPPLY = ±15V, VAH = 4V, V AL = 0.8V, VREF = Open, Unless Otherwise Specified
FIGURE 1A. ON RESISTANCE TEST CIRCUIT
FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY
VOLTAGE
FIGURE 1. ON RESISTANCE
FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 9)
100µA
OUTIN
VIN rON = V2
100µA
V2
1.4
1.3
1.2
1.1
1.0
0.9
0.8
-10-8-6-4-20246810
ANALOG INPUT (V)
ON RESISTANCE (kΩ)
125oC
25oC
-55oC
0.7
0.6
1.4
1.3
1.2
1.1
1.0
0.9
0.8 5 6 7 8 9 101112131415
1.5
NORMALIZED ON RESISTANCE
(REFERRED TO VALUE AT ±15V)
SUPPLY VOLTAGE (±V)
100nA
10nA
1nA
100pA
10pA
LEAKAGE CURRENT
25 50 75 100 125
TEMPERATURE (oC)
OFF OUTPUT
CURRENT
ID(OFF)
OFF INPUT
LEAKAGE CURRENT
IS(OFF)
ON LEAKAGE
CURRENT
ID(ON)
A
OUT
10V
±
±10V
EN
ID(OFF)
+0.8V
HI-546, HI-547, HI-548, HI-549
11
FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 9) FIGURE 2D. ID(ON) TEST CIRCUIT (NOTE 9)
NOTE:
9. Two measurements per channel: ±10V and 10V. (Two measurements per device for ID(OFF): ±10V and 10V.)
FIGURE 2. LEAKAGE CURRENTS
FIGURE 3A. ANALOG INPUT CURRENT AND OU TPUT OFF
LEAKAGE CURRENT vs ANALOG INPUT
OVER-VOLTAGE
FIGURE 3B. TEST CIRCUIT
FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARA CTERISTICS
FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 4B. TEST CIRCUIT
FIGURE 4. ON CHANNEL CURRENT
T est Cir cuits and W aveforms TA = 25oC, VSUPPLY = ±15V, V AH = 4V, V AL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
10V
±
±10V
+0.8V
EN
A
OUT
IS(OFF) A
±
OUT
ID(ON)
10V ±10V
4V
EN
±
±
15 18 21 24 27 30 33 36
ANALOG INPUT OVERVOLTAGE (±V)
ANALOG INPUT CURRENT (mA)
18
15
12
9
0
6
3
OUTPUT OFF LEAKA GE CURRENT (nA)
5
4
3
2
1
0
ANALOG INPUT
CURRENT (IIN)
OUTPUT OFF LEAKAGE
CURRENT ID(OFF)
ID(OFF)
A
±VIN
AIIN
02 4 6 8 10 12 14
0
±14
±12
±10
±8
±6
±4
±2
VOLTAGE ACROSS SWITCH (±V)
SWITCH CURRENT (mA)
-55oC25oC
125oC
A
±VIN
HI-546, HI-547, HI-548, HI-549
12
FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 5B. TEST CIRCUIT
FIGURE 5. DYNAMIC SUPPLY CURRENT
FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 6B. TEST CIRCUIT
FIGURE 6C. MEASUREMENT POINTS FIGURE 6D. WAVEFORMS
FIGURE 6. ACCESS TIME
T est Cir cuits and W aveforms TA = 25oC, VSUPPLY = ±15V, V AH = 4V, V AL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
8
6
4
2
01K
TOGGLE FREQUENCY (Hz)
SUPPLY CURRENT (mA)
10K 100K 1M 10M
VSUPPLY = ± 10V
VSUPPLY = ± 15V
+15V/+10V
V+
V-
IN 1
IN 2
IN 16
OUT
A0
EN
A1
10MΩ14pF
A3
A2
50Ω
VA
+4V GND
A
-15V/-10V
A-ISUPPLY
+ISUPPLY
±10V/±5V
THRU
IN 15
HI-546†
†Similar connection for HI-547/HI-548/HI-549.
10V/
±
5V
±
900
700
500
300 3
A CCESS TIME (ns)
LOGIC LEVEL (HIGH) (V)
579 151311
800
600
400
4 6 8101214
VREF = OPEN FOR LOGIC HIGH LEVEL < 6V
VREF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V
±10V
+15V
V+
V-
IN 1
IN 2 THRU
IN 16
OUT
A0
EN
A1
10kΩ50pF
A3
A2
50Ω
VA
+4V GND
-15V
10V
IN 15
HI-546†
†Similar connection for HI-547/HI-548/HI-549.
±
VREF
VAH = 4.0V
10%
+10V
0V
OUTPUT
-10V
tA
ADDRESS
DRIVE (VA)
50%
200ns/DIV.
VA INPUT
2V/DIV.
OUTPUT
5V/DIV.
S16 ON
S1 ON
HI-546, HI-547, HI-548, HI-549
S1 ON S16 ON
VA INPUT
2V/DIV.
OUTPUT
0.5V/DIV.
100ns/DIV.
13
FIGURE 7A. TEST CIRCUIT FIGURE 7B. MEASUREMENT POINTS
FIGURE 7C. WAVEFORMS
FIGURE 7. BREAK-BEFORE-MAKE DELAY
FIGURE 8A. TEST CIRCUIT FIGURE 8B. MEASUREMENT POINTS
T est Cir cuits and W aveforms TA = 25oC, VSUPPLY = ±15V, V AH = 4V, V AL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
IN 1
IN 2 THRU
IN 16
OUT
A0
EN
A1
50pF
VOUT
A3
A2
50Ω
VA
+4V
GND 1kΩ
IN 15
HI-546†
†Similar connection for HI-547/HI-548/HI-5 49
+5V
50% 50%
VAH = 4V
0V
OUTPUT
ADDRESS
DRIVE (VA)
tOPEN
IN 1
IN 2 THRU
OUT
A0
EN
A1
50pF
A3
A2
VAGND 1kΩ
+10V
IN16
HI-546†
†Similar connection for HI-547/HI-548/HI-549
50Ω
VOUT
50%
90%
tON(EN)
VAH = 4V
0V
OUTPUT
tOFF(EN)
10%
50%
ENABLE DRIVE
(VA)
0V
HI-546, HI-547, HI-548, HI-549
14
FIGURE 8C. WAVEFORMS
FIGURE 8. ENABLE DELAYS
T est Cir cuits and W aveforms TA = 25oC, VSUPPLY = ±15V, V AH = 4V, V AL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
DISABLED OUTPUT
2V/DIV.
ENABLE
100ns/DIV.
DRIVE
2V/DIV.
ENABLED (S1 ON)
HI-546, HI-547, HI-548, HI-549
15
Die Characteristics
DIE DIMENSIONS:
83.9 mils x 159 mils
METALLIZATION:
Type: CuAl
Thickness: 16kÅ ±2kÅ
SUBSTRATE POTENTIAL (NOTE):
-VSUPPLY
PASSIVATION:
Type: Nitride Over Silox
Nitride Thickness: 3.5kÅ ±1kÅ
Silox Thickness: 12kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
1.4 x 105 A/cm2
TRANSIST OR COUNT:
485
PROCESS:
CMOS-DI
NO TE: The substrate appears resistive to the -VSUPPLY terminal, theref ore it may be left floating (Insulating Die Mount) or it may be mounted on a
conductor at -VSUPPLY potential.
Metallization Mask La youts
HI-546 HI-547
IN 9
IN 10
IN 11
IN 12
IN 13
IN 14
IN 15
IN 16
V- (27) +V (1) NC (2)
IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
IN 8
EN A0A1A2VREF GND
(18) (17) (16) (15) (13) (12)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26) (4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
OUT (28)
A3
(14)
IN 1B
IN 2B
IN 3B
IN 4B
IN 5B
IN 6B
IN 7B
IN 8B
V- (27) +V (1) OUT B(2)
IN 1A
IN 2A
IN 3A
IN 4A
IN 5A
IN 6A
IN 7A
IN 8A
EN A0A1A2NC VREF GND
(18) (17) (16) (15) (14) (13) (12)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26) (4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
OUT A (28)
HI-546, HI-547, HI-548, HI-549
16
Die Characteristics
DIE DIMENSIONS:
83 mils x 108 mils
METALLIZATION:
Type: CuAl
Thickness: 16kÅ ±2kÅ
SUBSTRATE POTENTIAL (NOTE):
-VSUPPLY
PASSIVATION:
Type: Nitride Over Silox
Nitride Thickness: 3.5kÅ ±1kÅ
Silox Thickness: 12kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
1.4 x 105 A/cm
TRANSIST OR COUNT:
253
PROCESS:
CMOS-DI
NO TE: The substrate appears resistive to the -VSUPPLY terminal, theref ore it may be left floating (Insulating Die Mount) or it may be mounted on a
conductor at -VSUPPLY potential.
Metallization Mask La youts
HI-548 HI-549
IN 6 IN 7 IN 8 OUT IN 4 IN 3
IN 1
IN 2
-V
A0
A1
A2EN
IN 5
GND
+V
(11) (10) (9) (8) (7) (6)
(12)
(13)
(14)
(5)
(4)
(3)
(15) (16) (1) (2)
IN 3B IN 4BOUT B OUT A IN 4A IN 3A
IN 1A
IN 2A
-V
A0
A1
GND EN
IN 2B
+V
IN 1B
(11) (10) (9) (8) (7) (6)
(12)
(13)
(14)
(5)
(4)
(3)
(15) (16) (1) (2)
HI-546, HI-547, HI-548, HI-549
17
HI-546, HI-547, HI-548, HI-549
18
HI-546, HI-547, HI-548, HI-549
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
SS
ccc C A - B
MD
SSaaa CA - B
MD
SS
eA
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)
28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.232 - 5.92 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 1.490 - 37.85 5
E 0.500 0.610 12.70 15.49 5
e 0.100 BSC 2.54 BSC -
eA 0.600 BSC 15.24 BSC -
eA/2 0.300 BSC 7.62 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2, 3
N28 288
Rev. 0 4/94
19
HI-546, HI-547, HI-548, HI-549
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E28.6 (JEDEC MS-011-AB ISSUE B)
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.250 - 6.35 4
A1 0.015 - 0.39 - 4
A2 0.125 0.195 3.18 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.030 0.070 0.77 1.77 8
C 0.008 0.015 0.204 0.381 -
D 1.380 1.565 35.1 39.7 5
D1 0.005 - 0.13 - 5
E 0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5
e 0.100 BSC 2.54 BSC -
eA0.600 BSC 15.24 BSC 6
eB- 0.700 - 17.78 7
L 0.115 0.200 2.93 5.08 4
N28 289
Rev. 1 12/00
20
HI-546, HI-547, HI-548, HI-549
Plastic Leaded Chip Carrier Packages (PLCC)
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
-C-
A1
ASEATING
PLANE
0.020 (0.51)
MIN
VIEW “A”
D2/E2
0.025 (0.64)
0.045 (1.14) R
0.042 (1.07)
0.056 (1.42)
0.050 (1.27) TP
EE1
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER
C
L
D1
D
0.020 (0.51) MAX
3 PLCS 0.026 (0.66)
0.032 (0.81)
0.045 (1.14)
MIN
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
VIEW “A” TYP.
0.004 (0.10) C
-C-
D2/E2
C
L
N28.45 (JEDEC MS-018AB I SSU E A)
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.165 0.180 4.20 4.57 -
A1 0.090 0.120 2.29 3.04 -
D 0.485 0.495 12.32 12.57 -
D1 0.450 0.456 11.43 11.58 3
D2 0.191 0.219 4.86 5.56 4, 5
E 0.485 0.495 12.32 12.57 -
E1 0.450 0.456 11.43 11.58 3
E2 0.191 0.219 4.86 5.56 4, 5
N28 286
Rev. 2 11/97
21
HI-546, HI-547, HI-548, HI-549
Small Outline Plastic Packages (SOIC)
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H0.25(0.010) BM M
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N28 287
α0o8o0o8o-
Rev. 0 12/93
22
HI-546, HI-547, HI-548, HI-549
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
SS
ccc C A - B
MD
SSaaa CA - B
MD
SS
eA
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 0.840 - 21.34 5
E 0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2, 3
N16 168
Rev. 0 4/94
23
HI-546, HI-547, HI-548, HI-549
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169
Rev. 0 12/93
24
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Cor poration reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license i s gr a nted b y imp lica tion or oth erw ise unde r any patent or paten t rights of In t ersil or its sub sidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
HI-546, HI-547, HI-548, HI-549
Plastic Leaded Chip Carrier Packages (PLCC)
A1
ASEATING
PLANE
0.020 (0.51)
MIN
VIEW “A”
D2/E2
0.025 (0.64)
0.045 (1.14) R
0.042 (1.07)
0.056 (1.42)
0.050 (1.27) TP
EE1
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER
C
L
D1
D
0.020 (0.51) MAX
3 PLCS 0.026 (0.66)
0.032 (0.81)
0.045 (1.14)
MIN
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
VIEW “A” TYP.
0.004 (0.10) C
-C-
D2/E2
C
L
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
4. To be measured at seating plane contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
-C-
N20.35 (JEDEC MS-018AA I SSU E A)
20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.165 0.180 4.20 4.57 -
A1 0.090 0.120 2.29 3.04 -
D 0.385 0.395 9.78 10.03 -
D1 0.350 0.356 8.89 9.04 3
D2 0.141 0.169 3.59 4.29 4, 5
E 0.385 0.395 9.78 10.03 -
E1 0.350 0.356 8.89 9.04 3
E2 0.141 0.169 3.59 4.29 4, 5
N20 206
Rev. 2 11/97
