M25PE80 Serial Flash Memory Features M25PE80 8Mb 3V NOR Serial Flash Memory Serial Flash Memory with Byte Alterability, 75 MHz SPI bus, Standard Pinout Features * * * * * * * * * * * * * * 8Mb of page-erasable Flash memory 2.7V to 3.6V single supply voltage SPI bus-compatible serial interface 75 MHz clock rate (maximum) Page size: 256 bytes - Page write in 11ms (TYP) - Page program in 0.8ms (TYP) - Page erase in 10ms (TYP) Subsector erase: 4KB - Sector erase: 64KB - Bulk erase: 8Mb Deep power-down mode: 1A (TYP) Electronic signature - JEDEC standard 2-byte signature (8014h) - Unique ID code (UID) with 16 bytes read-only Software write-protection on a 64KB sector basis Hardware write protection of the memory area selected using the BP0, BP1, and BP2 bits More than 100,000 write cycles More than 20 years of data retention Packages (RoHS compliant) - VFQFPN8 (MP) 6mm x 5mm (MLP8) - QFN8L (MS) 6mm x 5mm (MLP8) - SO8W (MW) 208 mils - SO8N (MN) 150 mils Automotive grade parts available 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. M25PE80 Serial Flash Memory Features Contents Important Notes and Warnings ......................................................................................................................... 6 Functional Description ..................................................................................................................................... 7 Signal Descriptions ........................................................................................................................................... 9 SPI Modes ...................................................................................................................................................... 10 Operating Features ......................................................................................................................................... 12 Sharing the overhead of modifying data ...................................................................................................... 12 An easy way to modify data ......................................................................................................................... 12 A fast way to modify data ............................................................................................................................ 12 Polling during a Write, Program, or Erase Cycle ............................................................................................ 13 Reset .......................................................................................................................................................... 13 Active Power, Standby Power, and Deep Power-Down .................................................................................. 13 Status Register ............................................................................................................................................ 13 Protection Modes ....................................................................................................................................... 13 Specific Hardware and Software Protection ................................................................................................. 14 Memory Organization .................................................................................................................................... 17 Command Set Overview ................................................................................................................................. 20 WRITE ENABLE .............................................................................................................................................. 22 WRITE DISABLE ............................................................................................................................................. 23 READ IDENTIFICATION ................................................................................................................................. 24 READ STATUS REGISTER ................................................................................................................................ 25 WIP Bit ...................................................................................................................................................... 25 WEL Bit ...................................................................................................................................................... 25 Block Protect Bits ....................................................................................................................................... 26 SRWD Bit ................................................................................................................................................... 26 WRITE STATUS REGISTER .............................................................................................................................. 27 READ DATA BYTES ......................................................................................................................................... 29 READ DATA BYTES at HIGHER SPEED ............................................................................................................ 30 READ LOCK REGISTER ................................................................................................................................... 31 PAGE WRITE .................................................................................................................................................. 33 PAGE PROGRAM ............................................................................................................................................ 35 WRITE to LOCK REGISTER ............................................................................................................................. 37 PAGE ERASE ................................................................................................................................................... 40 SUBSECTOR ERASE ....................................................................................................................................... 41 SECTOR ERASE .............................................................................................................................................. 42 BULK ERASE .................................................................................................................................................. 43 DEEP POWER-DOWN ..................................................................................................................................... 44 RELEASE from DEEP POWER-DOWN .............................................................................................................. 45 Power-Up and Power-Down ............................................................................................................................ 46 RESET ............................................................................................................................................................ 48 Initial Delivery State ....................................................................................................................................... 48 Maximum Ratings and Operating Conditions .................................................................................................. 49 DC Parameters ............................................................................................................................................... 50 AC Characteristics .......................................................................................................................................... 52 Package Information ...................................................................................................................................... 59 Device Ordering Information .......................................................................................................................... 63 Revision History ............................................................................................................................................. 64 Rev. E - 06/18 ............................................................................................................................................. 64 Rev. D - 6/2014 ........................................................................................................................................... 64 Rev. C - 3/2013 ........................................................................................................................................... 64 Rev. B - 11/2012 ......................................................................................................................................... 64 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Features Rev. A - 09/2012 .......................................................................................................................................... 64 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Features List of Figures Figure 1: Logic Diagram ................................................................................................................................... 7 Figure 2: Pin Connections: VFQFPN, QFN8L, and SO ........................................................................................ 8 Figure 3: SPI Modes Supported ...................................................................................................................... 10 Figure 4: Bus Master and Memory Devices on the SPI Bus ............................................................................... 11 Figure 5: Block Diagram ................................................................................................................................ 19 Figure 6: WRITE ENABLE Command Sequence .............................................................................................. 22 Figure 7: WRITE DISABLE Command Sequence ............................................................................................. 23 Figure 8: READ IDENTIFICATION Command Sequence ................................................................................. 25 Figure 9: READ STATUS REGISTER Command Sequence ................................................................................ 25 Figure 10: Status Register Format ................................................................................................................... 26 Figure 11: WRITE STATUS REGISTER Command Sequence ............................................................................. 27 Figure 12: READ DATA BYTES Command Sequence ........................................................................................ 29 Figure 13: READ DATA BYTES at HIGHER SPEED Command Sequence ........................................................... 30 Figure 14: READ LOCK REGISTER Command Sequence ................................................................................. 31 Figure 15: PAGE WRITE Command Sequence ................................................................................................. 34 Figure 16: PAGE PROGRAM Command Sequence ........................................................................................... 36 Figure 17: WRITE to LOCK REGISTER Instruction Sequence ........................................................................... 37 Figure 18: PAGE ERASE Command Sequence ................................................................................................. 40 Figure 19: SUBSECTOR ERASE Command Sequence ...................................................................................... 41 Figure 20: SECTOR ERASE Command Sequence ............................................................................................. 42 Figure 21: BULK ERASE Command Sequence ................................................................................................. 43 Figure 22: DEEP POWER-DOWN Command Sequence ................................................................................... 44 Figure 23: RELEASE from DEEP POWER-DOWN Command Sequence ............................................................. 45 Figure 24: Power-Up Timing .......................................................................................................................... 47 Figure 25: AC Measurement I/O Waveform ..................................................................................................... 52 Figure 26: Serial Input Timing ........................................................................................................................ 56 Figure 27: Write Protect Setup and Hold Timing ............................................................................................. 56 Figure 28: Output Timing .............................................................................................................................. 57 Figure 29: Reset AC Waveforms ...................................................................................................................... 58 Figure 30: VFQFPN8 (MLP8) 6mm x 5mm ...................................................................................................... 59 Figure 31: QFN8L (MLP8) 8-lead, quad flat package no lead, 6mm x 5mm ....................................................... 60 Figure 32: SO8W - 8 lead plastic small outline, 208 mils body width ................................................................. 61 Figure 33: SO8N - 8 lead plastic small outline, 150 mils body width ................................................................. 62 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Features List of Tables Table 1: Signal Names ...................................................................................................................................... 8 Table 2: Signal Descriptions ............................................................................................................................. 9 Table 3: Software Protection Truth Table, 64KB granularity (sectors 0-15) ........................................................ 15 Table 4: Not for new design: TY7 process only, software protection scheme truth table (sectors 0 and 15) .......... 15 Table 5: Protected Area Sizes .......................................................................................................................... 16 Table 6: Memory Organization ....................................................................................................................... 17 Table 7: Command Set Codes ........................................................................................................................ 21 Table 8: READ IDENTIFICATION Data Out Sequence ..................................................................................... 24 Table 9: Status Register Protection Modes ...................................................................................................... 28 Table 10: Lock Register Out ............................................................................................................................ 31 Table 11: Not for new design: Lock Registers for the M25PE80 in T7Y Process ................................................... 31 Table 12: Lock Register In .............................................................................................................................. 37 Table 13: Not for new design: lock registers for the M25PE80 in T7Y process .................................................... 37 Table 14: Power-up Timing and V WI Threshold ............................................................................................... 47 Table 15: Device Status After a RESET# LOW Pulse .......................................................................................... 48 Table 16: Absolute Maximum Ratings ............................................................................................................. 49 Table 17: Operating Conditions ...................................................................................................................... 49 Table 18: DC Characteristics .......................................................................................................................... 50 Table 19: DC Characteristics 75 MHz Operation ............................................................................................. 50 Table 20: AC Measurement Conditions ........................................................................................................... 52 Table 21: Capacitance .................................................................................................................................... 52 Table 22: AC Characteristics ........................................................................................................................... 53 Table 23: AC Characteristics (50MHz operation) ............................................................................................. 54 Table 24: AC Specifications (75 MHz operation) .............................................................................................. 55 Table 25: Reset Conditions ............................................................................................................................. 57 Table 26: Timings After a RESET# LOW Pulse .................................................................................................. 57 Table 27: Standard Part Number Information Scheme ..................................................................................... 63 Table 28: Automotive Part Number Information Scheme ................................................................................. 63 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Important Notes and Warnings Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Functional Description Functional Description The M25PE80 is an 8Mb (1Mb x 8 bit) serial-paged Flash memory device accessed by a high-speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time using the PAGE WRITE or PAGE PROGRAM command. The PAGE WRITE command consists of an integrated PAGE ERASE cycle followed by a PAGE PROGRAM cycle. The memory is organized as 16 sectors, divided into 16 subsectors each (256 subsectors total). Each sector contains 256 pages and each subsector contains 16 pages. Each page is 256 bytes wide. The entire memory can be viewed as consisting of 4096 pages, or 1,048,576 bytes. The memory can be erased one page at a time using the PAGE ERASE command, one sector at a time using the SECTOR ERASE command, one subsector at a time using the SUBSECTOR ERASE command, or as a whoe using the BULK ERASE command. The memory can be write-protected by either hardware or software using a mix of volatile and non-volatile protection features, depending on application needs. The protection granularity is 64Kb (sector granularity). The entire memory array is partitioned into 4Kb subsectors. Note: The write protection (defined by the WL and LD lock bits) of the 4KB subsectors in the top and bottom sectors is no longer offered. For more details, see PCNMPG062148. Figure 1: Logic Diagram VCC DQ0 DQ1 C S# W# RESET# VSS 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Functional Description Table 1: Signal Names Signal Name Function Direction C Serial clock Input DQ0 Serial data Input DQ1 Serial data Output S# Chip select Input W# Write Protect Input RESET# Reset Input VCC Supply voltage Input VSS Ground - Figure 2: Pin Connections: VFQFPN, QFN8L, and SO VCC S# 1 8 DQ1 2 7 RESET# TSL#/W# 3 6 C VSS 4 5 DQ0 There is an exposed central pad on the underside of the MLP8 package that is pulled internally to V SS and must not be connected to any other voltage or signal line on the PCB. The Package Mechanical section provides information on package dimensions and how to identify pin 1. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Signal Descriptions Signal Descriptions Table 2: Signal Descriptions Signal Type DQ1 Output Serial data: The DQ1 output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock (C). DQ0 Input Serial data: The DQ0 input signal is used to transfer data serially into the device. It receives commands, addresses, and the data to be programmed. Values are latched on the rising edge of the serial clock (C). C Input Clock: The C input signal provides the timing of the serial interface. Commands, addresses, or data present at serial data input (DQ0) is latched on the rising edge of the serial clock (C). Data on DQ1 changes after the falling edge of C. S# Input Chip select: When the S# input signal is HIGH, the device is deselected and DQ1 is at HIGH impedance. Unless an internal READ, PROGRAM, ERASE, or WRITE cycle is in progress, the device will be in the standby power mode (not the DEEP POWER-DOWN mode). Driving S# LOW enables the device, placing it in the active power mode. After power-up, a falling edge on S# is required prior to the start of any command. RESET# Input Reset: The RESET# input provides a hardware reset for the memory. When RESET# is driven HIGH, the memory is in the normal operating mode. When RESET# is driven LOW, the memory will enter the Reset mode. In this mode, the output is at HIGH impedance. Driving RESET# LOW while an internal operation is in progress affects the WRITE, PROGRAM, or ERASE cycle, and data may be lost. W# Input Write protect: The W# input signal is used to freeze the size of the area of memory that is protected against WRITE, PROGRAM, and ERASE commands as specified by the values in the block protect bits in the status register. VCC Input Supply voltage VSS Input Ground: Reference for the VCC supply voltage. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN Description 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory SPI Modes SPI Modes These devices can be driven by a microcontroller with its serial peripheral interface (SPI) running in either of the following two SPI modes: * CPOL=0, CPHA=0 * CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of serial clock (C), and output data is available from the falling edge of C. The difference between the two modes is the clock polarity when the bus master is in STANDBY mode and not transferring data: * C remains at 0 for (CPOL=0, CPHA=0) * C remains at 1 for (CPOL=1, CPHA=1) Figure 3: SPI Modes Supported CPOL CPHA 0 0 C 1 1 C DQ0 MSB MSB DQ1 Because only one device is selected at a time, only one device drives the serial data output (DQ1) line at a time, while the other devices are HIGH-Z. An example of three devices connected to an MCU on an SPI bus is shown here. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory SPI Modes Figure 4: Bus Master and Memory Devices on the SPI Bus VSS VCC R SDO SPI interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C DQ1 DQ0 SPI Bus Master SPI memory device R CS3 CS2 DQ1 DQ0 SPI memory device R VCC C VSS R DQ1 DQ0 VSS SPI memory device CS1 S# Notes: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN VCC C VSS W# HOLD# S# W# HOLD# S# W# HOLD# 1. WRITE PROTECT (W#) and HOLD# should be driven HIGH or LOW as appropriate. 2. Resistors (R) ensure that the memory device is not selected if the bus master leaves the S# line HIGH-Z. 3. The bus master may enter a state where all I/O are HIGH-Z at the same time; for example, when the bus master is reset. Therefore, the C must be connected to an external pull-down resistor so that when all I/O are HIGH-Z, S# is pulled HIGH while C is pulled LOW. This ensures that S# and C do not go HIGH at the same time and that the tSHCH requirement is met. 4. The typical value of R is 100 k, assuming that the time constant R x Cp (Cp = parasitic capacitance of the bus line) is shorter than the time during which the bus master leaves the SPI bus HIGH-Z. 5. Example: Given that Cp = 50 pF (R x Cp = 5s), the application must ensure that the bus master never leaves the SPI bus HIGH-Z for a time period shorter than 5s. 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Operating Features Operating Features Sharing the overhead of modifying data To write or program one or more data bytes, two commands are required: WRITE ENABLE (WREN), which is one byte, and a PAGE WRITE (PW) or PAGE PROGRAM (PP) sequence, which consists of four bytes plus data. This is followed by the internal cycle of duration tPW or tPP. To share this overhead, the PW or PP command allows up to 256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at a time, provided that they lie in consecutive addresses on the same page of memory. An easy way to modify data The Page Write (PW) instruction provides a convenient way of modifying data (up to 256 contiguous bytes at a time), and simply requires the start address, and the new data in the instruction sequence. The Page Write (PW) instruction is entered by driving Chip Select (S#) LOW, and then transmitting the instruction byte, three address bytes (A23-A0) and at least one data byte, and then driving S# HIGH. While S# is being held LOW, the data bytes are written to the data buffer, starting at the address given in the third address byte (A7-A0). When Chip S# is driven HIGH, the Write cycle starts. The remaining unchanged bytes of the data buffer are automatically loaded with the values of the corresponding bytes of the addressed memory page. The addressed memory page is then automatically put into an Erase cycle. Finally, the addressed memory page is programmed with the contents of the data buffer. All of this buffer management is handled internally, and is transparent to the user. The user is given the facility of being able to alter the contents of the memory on a byte-bybyte basis. For optimized timings, it is recommended to use the PAGE WRITE (PW) instruction to write all consecutive targeted bytes in a single sequence versus using several PAGE WRITE (PW) sequences with each containing only a few bytes. A fast way to modify data The PAGE PROGRAM (PP) command providesa fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. This might be: * When the designer is programming the device for the first time. * When the designer knows that the page has already been erased by an earlier PAGE ERASE (PE), SUBSECTOR ERASE (SSE), SECTOR ERASE (SE), or BULK ERASE (BE) command. This is useful, for example, when storing a fast stream of data, having first performed the erase cycle when time was available. * When the designer knows that the only changes involve resetting bits to 0 that are still set to 1. When this method is possible, it has the additional advantage of minimizing the number of unnecessary erase operations, and the extra stress incurred by each page. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Operating Features For optimized timings, it is recommended to use the PAGE PROGRAM (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several PAGE PROGRAM (PP) sequences with each containing only a few bytes. Polling during a Write, Program, or Erase Cycle An improvement in the time to complete the following commands can be achieved by not waiting for the worst case delay (tPW, tPP, tPE, tBE, tWor tSE). The write in progress (WIP) bit is provided in the status register so that the application program can monitor this bit in the status register, polling it to establish when the previous WRITE cycle, PROGRAM cycle, or ERASE cycle is complete. Reset An internal power-on reset circuit helps protect against inadvertent data writes. Additional protection is provided by driving RESET# LOW during the power-on process, and only driving it HIGH when V CC has reached the correct voltage level, V CC(min). Active Power, Standby Power, and Deep Power-Down When chip select (S#) is LOW, the device is selected and in the ACTIVE POWER mode. When S# is HIGH, the device is deselected, but could remain in the ACTIVE POWER mode until all internal cycles have completed (PROGRAM, ERASE, WRITE). The device then goes in to the STANDBY POWER mode. The device consumption drops to I CC1. The DEEP POWER-DOWN mode is entered when the DEEP POWER-DOWN command is executed. The device consumption drops further to I CC2. The device remains in this mode until the RELEASE FROM DEEP POWER-DOWN command is executed. While in the DEEP POWER-DOWN mode, the device ignores all WRITE, PROGRAM, and ERASE commands. This provides an extra software protection mechanism when the device is not in active use, by protecting the device from inadvertent WRITE, PROGRAM, or ERASE operations. Status Register The status register contains a number of status bits that can be read by the READ STATUS REGISTER (RDSR) command. Protection Modes Non-volatile memory is used in environments that can include excessive noise. The following capabilities help protect data in these noisy environments. Power on reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. WRITE, PROGRAM, and ERASE commands are checked before they are accepted for execution to ensure they consist of a number of clock pulses that is a multiple of eight. All commands that modify data must be preceded by a WRITE ENABLE command to set the write enable latch (WEL) bit. This bit is returned to its reset state by the following events. * Power-up * Reset (RESET#) driven LOW 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Operating Features * * * * * * * * WRITE DISABLE (WRDI) command completion PAGE WRITE (PW) command completion PAGE PROGRAM (PP) command completion WRITE TO LOCK REGISTER (WRLR) command completion PAGE ERASE (PE) command completion SUBSECTOR ERASE (SSE) command completion SECTOR EASE (SE) command completion BULK ERASE (BE) command completion The Reset (RESET#) signal can be driven LOW to freeze and reset the internal logic. In addition to the low power consumption feature, DEEP POWER-DOWN mode offers extra software protection from inadvertant WRITE, PROGRAM, and ERASE commands while the device is not in active use. Specific Hardware and Software Protection The M25PE80 features a hardware protected mode (HPM) and two software protected modes (SPM1 and SPM2). SPM1 and SPM2 can be combined to protect the memory array as required. Hardware Protected Mode (HPM) The Hardware Protected Mode (HPM) is used to write-protect the non-volatile bits of the Status Register (that is, the Block Protect Bits and the Status Register bit). HPM is entered by driving the Write Protect (W#) signal LOW with the SRWD bit set to HIGH. This additional protection allows the Status Register to be hardware-protected. SPM1 and SPM2 The first Software Protected Mode (SPM1) is managed by specific Lock Registers assigned to each 64KB sector. The Lock Registers can be read and written using the Read Lock Register (RDLR) and Write to Lock Register (WRLR) commands. In each Lock Register, two bits control the protection of each sector: the Write Lock bit and the Lock Down bit. * Write lock bit: This bit determines whether the contents of the sector can be modified using the WRITE, PROGRAM, and ERASE commands. When the bit is set to `1', the sector is write protected, and any operations that attempt to change the data in the sector will fail. When the bit is reset to `0', the sector is not write protected by the lock register, and may be modified. * Lock down bit: This bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the bit is set to '1', further modification to the write lock bit and lock down bit cannot be performed. A power-up, is required before changes to these bits can be made. When the bit is reset to `0', the write lock bit and lock down bit can be changed. The Write Lock bit and the Lock Down bit are volatile and their value is reset to 0 after a power-down or reset. The software protection truth table shows the lock down bit and write lock bit settings and the sector protection status. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Operating Features Table 3: Software Protection Truth Table, 64KB granularity (sectors 0-15) Sector Lock Register: Lock Down Bit Sector Lock Register: Write Lock Bit 0 0 Sector unprotected from PROGRAM / ERASE / WRITE operations; protection status reversible 0 1 Sector protected from PROGRAM / ERASE / WRITE operations; protection status reversible 1 0 Sector unprotected from PROGRAM / ERASE / WRITE operations; protection status cannot be changed except by a reset or power-up. 1 1 Sector protected from PROGRAM / ERASE / WRITE operations; protection status cannot be changed except by a reset or power-up. Protection Status Table 4: Not for new design: TY7 process only, software protection scheme truth table (sectors 0 and 15) Sector Lock Register Lock Down Bit Write Lock Bit Subsector Lock Register Lock Down Bit Write Lock Bit 0 0 Current subsector unprotected from PROGRAM / ERASE / WRITE operations; current subsector protection status reversible. 0 1 Current subsector protected from PROGRAM / ERASE / WRITE operations; current subsector protection status reversible. 1 0 Current subsector unprotected from PROGRAM / ERASE / WRITE operations; current subsector protection status cannot be changed except by a reset or power-up. 1 1 Current subsector protected from PROGRAM / ERASE / WRITE operations; protection status cannot be changed except by a reset or power-up. 0 1 All subsectors protected from PROGRAM / ERASE / WRITE operations, current subsector protection status reversible. 1 1 All subsectors protected from PROGRAM / ERASE / WRITE operations, current subsector protection cannot be changed except by a reset or power-up. 1 0 Current subsector unprotected from PROGRAM / ERASE / WRITE operations, all subsectors protection status cannot be changed except by a reset or power-up. 1 1 Current subsector protected from PROGRAM / ERASE / WRITE operations, all subsectors protection status cannot be changed except by a reset or power-up. 1 1 All subsectors protected with their protection status cannot be changed except by a reset or power-up. 0 0 1 0 1 1 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN Protection Status 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Operating Features All other bit combinations are not-applicable. For more details, see the WRLR instruction. The second software protected mode (SPM2) uses the block protect (BP2, BP1, BP0) bits to allow part of the memory to be configured as read-only. Table 5: Protected Area Sizes Status Register Content Memory Content BP Bit 2 BP Bit 1 BP Bit 0 0 0 0 none All sectors (sectors 0 to 15) 0 0 1 Upper sixteenth (sector 15) Lower 15/16ths (sectors 0 to 14) 0 1 0 Upper eighth (sectors 14 and 15) Lower 7/8ths (sectors 0 to 13) 0 1 1 Upper quarter (sectors 12 to 15) Lower three quarters (sectors 0 to 11) 1 0 0 Upper half (sectors 8 to 15) Lower half (sectors 0 to 7) 1 0 1 All sectors (sectors 0 to 15) none 1 1 0 All sectors (sectors 0 to 15) none 1 1 1 All sectors (sectors 0 to 15) none Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN Protected Area Unprotected Area Notes 1 1. The device is ready to accept a BULK ERASE command only if all block protect bits (BP2, BP1, BP0) are 0. 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Memory Organization Memory Organization The M25PE80 memory is organized as follows: * * * * 4096 pages (256 bytes each) 1,048,576 bytes (8 bits each) 16 sectors (512Kb, 65,536 bytes each) 256 sectors (32Kb, 4096 bytes each) Each page can be individually: * programmed (bits are programmed from 1 to 0) * erased (bits are erased from 0 to 1) * written (bits are changed to either 0 or 1) The device is page- or sector- or bulk-erasable (bits are erased from 0 to 1). Table 6: Memory Organization Address Range Sector Subsector Start End 15 255 FF000h FFFFFh 240 F0000h F0FFFh 239 EF000h EFFFFh 14 13 12 11 10 9 8 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 224 E0000h E0FFFh 223 DF000h DFFFFh 208 D0000h D0FFFh 207 CF000h CFFFFh 192 C0000h C0FFFh 191 BF000h BFFFFh 176 B0000h B0FFFh 175 AF000h AFFFFh 160 A0000h A0FFFh 159 9F000h 9FFFFh 144 90000h 90FFFh 143 8F000h 8FFFFh 128 80000h 80FFFh 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Memory Organization Table 6: Memory Organization (Continued) Address Range Sector Subsector Start End 7 127 7F000h 7FFFFh 6 5 4 3 2 1 0 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 112 70000h 70FFFh 111 6F00h 6FFFFh 96 60000h 60FFFh 95 5F000h 5FFFFh 80 50000h 50FFFh 79 4F000h 4FFFFh 64 40000h 40FFFh 63 3F000h 3FFFFh 48 30000h 30FFFh 47 2F000h 2FFFFh 32 20000h 20FFFh 31 1F000h 1FFFFh 16 10000h 10FFFh 15 0F000h 0FFFFh 4 04000h 04FFFh 3 03000h 03FFFh 2 02000h 02FFFh 1 01000h 01FFFh 0 00000h 00FFFh 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Memory Organization Figure 5: Block Diagram RESET# W# High Voltage Generator Control Logic S# C DQ0 I/O Shift Register DQ1 Address Register and Counter Status Register 256 Byte Data Buffer FFFFFh Y Decoder F0000h 00000h 000FFh 256 bytes (page size) X Decoder Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 1. Entire memory array can be made read-only on a 64KB basis through the lock registers. 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Command Set Overview Command Set Overview All commands, addresses, and data are shifted in and out of the device, most significant bit first. Serial data input (DQ1) is sampled on the first rising edge of serial clock (C) after chip select (S#) is driven LOW. Then, the one-byte command code must be shifted in to the device, most significant bit first, on DQ1, each bit being latched on the rising edges of C. Every command sequence starts with a one-byte command code. Depending on the command, this command code might be followed by address or data bytes, by address and data bytes, or by neither address or data bytes. For the following commands, the shifted-in command sequence is followed by a data-out sequence. S# can be driven HIGH after any bit of the data-out sequence is being shifted out. * * * * READ DATA BYTES (READ) READ DATA BYTES at HIGHER SPEED READ STATUS REGISTER READ TO LOCK REGISTER For the following commands, S# must be driven HIGH exactly at a byte boundary. That is, after an exact multiple of eight clock pulses following S# being driven LOW, S# must be driven HIGH. Otherwise, the command is rejected and not executed. * * * * * * * * * * * * PAGE WRITE PAGE PROGRAM PAGE ERASE SUBSECTOR ERASE SECTOR ERASE BULK ERASE WRITE ENABLE WRITE DISABLE WRITE STATUS REGISTER WRITE TO LOCK REGISTER DEEP POWER-DOWN RELEASE FROM DEEP POWER-DOWN All attempts to access the memory array are ignored during a WRITE cycle, a PROGRAM cycle, or an ERASE cycle. In addition, the internal cycle for each of these commands continues unaffected. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Command Set Overview Table 7: Command Set Codes Command Name Bytes One-Byte Command Code Address Dummy Data WRITE ENABLE 0000 0110 06h 0 0 0 WRITE DISABLE 0000 0100 04h 0 0 0 READ IDENTIFICATION 1001 1111 9Fh 0 0 1 to 20 READ STATUS REGISTER 0000 0101 05h 0 0 1 to WRITE STATUS REGISTER 0000 0001 01h 0 0 1 WRITE to LOCK REGISTER 1110 0101 E5h 3 0 1 READ LOCK REGISTER 1110 1000 E8h 3 0 1 READ DATA BYTES 0000 0011 03h 3 0 1 to READ DATA BYTES at HIGHER SPEED 0000 1011 0Bh 3 1 1 to PAGE WRITE 0000 1010 0Ah 3 0 1 to 256 PAGE PROGRAM 0000 0010 02h 3 0 1 to 256 PAGE ERASE 1101 1011 DBh 3 0 0 SUBSECTOR ERASE 0010 0000 20h 3 0 0 SECTOR ERASE 1101 1000 D8h 3 0 0 BULK ERASE 1100 0111 C7h 0 0 0 DEEP POWER-DOWN 1011 1001 B9h 0 0 0 RELEASE from DEEP POWER-DOWN 1010 1011 ABh 0 0 0 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory WRITE ENABLE WRITE ENABLE The WRITE ENABLE command sets the write enable latch (WEL) bit. The WEL bit must be set before execution of every PAGE WRITE, PAGE PROGRAM, PAGE ERASE, SECTOR ERASE, BULK ERASE, and WRITE to LOCK REGISTER command. The WRITE ENABLE command is entered by driving chip select (S#) LOW, sending the command code, and then driving S# HIGH. Figure 6: WRITE ENABLE Command Sequence 0 1 2 3 4 5 6 7 C S# Command bits DQ[0] 0 0 0 0 0 LSB 1 1 0 MSB DQ1 High-Z Don't Care 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory WRITE DISABLE WRITE DISABLE The WRITE DISABLE command resets the write enable latch (WEL) bit. The WRITE DISABLE command is entered by driving chip select (S#) LOW, sending the command code, and then driving S# HIGH. The WEL bit is reset under the following conditions: * * * * * * * * * * Power-up Completion of WRITE DISABLE operation Completion of PAGE WRITE operation Completion of PAGE PROGRAM operation Completion of WRITE STATUS REGISTER operation Completion of WRITE TO LOCK REGISTER operation Completion of PAGE ERASE operation Completion of SUBSECTOR ERASE operation Completion of SECTOR ERASE operation Completion of BULK ERASE operation Figure 7: WRITE DISABLE Command Sequence 0 1 2 3 4 5 6 7 C S# Command bits DQ[0] 0 0 0 0 0 LSB 1 0 0 MSB DQ1 High-Z Don't Care 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory READ IDENTIFICATION READ IDENTIFICATION The READ IDENTIFICATION command reads the following device identification data: * Manufacturer identification (1 byte): This is assigned by JEDEC. * Device identification (2 bytes): This is assigned by device manufacturer; the first byte indicates memory type and the second byte indicates device memory capacity. * A Unique ID code (UID) (17 bytes,16 available upon customer request): The first byte contains length of data to follow; the remaining 16 bytes contain optional Customized Factory Data (CFD) content. Table 8: READ IDENTIFICATION Data Out Sequence Device Identification UID Manufacturer Identification Memory Type Memory Capacity CFD Length CFD Content 20h 80h 14h 10h 16 bytes Note: 1. The CFD bytes are read-only and can be programmed with customer data upon demand. If customers do not make requests, the devices are shipped with all the CFD bytes programmed to zero (00h). A READ IDENTIFICATION command is not decoded while an ERASE or PROGRAM cycle is in progress and has no effect on a cycle in progress. The device is first selected by driving chip select (S#) LOW. Then, the 8-bit command code is shifted in and content is shifted out on serial data output (DQ1) as follows: the 24-bit device identification that is stored in the memory, the 8-bit CFD length, followed by 16 bytes of CFD content. Each bit is shifted out during the falling edge of serial clock (C). The READ IDENTIFICATION command is terminated by driving S# HIGH at any time during data output. When S# is driven HIGH, the device is put in the STANDBY POWER mode and waits to be selected so that it can receive, decode, and execute commands. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory READ STATUS REGISTER Figure 8: READ IDENTIFICATION Command Sequence 0 7 16 15 8 31 32 C LSB Command DQ0 MSB DOUT High-Z DOUT DOUT MSB LSB LSB LSB DQ1 DOUT DOUT MSB MSB Manufacturer identification DOUT Device identification UID Don't Care READ STATUS REGISTER The READ STATUS REGISTER command allows the status register to be read. The status register may be read at any time, even while a PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress. When one of these cycles is in progress, it is recommended to check the write in progress (WIP) bit before sending a new command to the device. It is also possible to read the status register continuously. Figure 9: READ STATUS REGISTER Command Sequence 0 7 8 9 10 11 12 13 14 15 C LSB Command DQ0 MSB LSB DQ1 High-Z DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Don't Care WIP Bit The write in progress (WIP) bit indicates whether the memory is busy with a WRITE cycle, a PROGRAM cycle, or an ERASE cycle. When the WIP bit is set to 1, a cycle is in progress; when the WIP bit is set to 0, a cycle is not in progress. WEL Bit The write enable latch (WEL) bit indicates the status of the internal write enable latch. When the WEL bit is set to 1, the internal write enable latch is set; when the WEL bit is set to 0, the internal write enable latch is reset and no WRITE , PROGRAM, or ERASE command is accepted. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory READ STATUS REGISTER Block Protect Bits The block protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against PROGRAM and ERASE commands. The block protect bits are written with the WRITE STATUS REGISTER command. When one or more of the block protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area, as defined in the Protected Area Sizes table, becomes protected against PAGE PROGRAM, SECTOR ERASE, and SUBSECTOR ERASE commands. The block protect BP2, BP1, BP0) bits can be written provided that the HARDWARE PROTECTED mode has not been set. The BULK ERASE command is executed only if all block protect (BP2, BP1, BP0) bits are 0 and the Lock Register protection bits are not all set to 1. SRWD Bit The status register write disable (SRWD) bit is operated in conjunction with the write protect (W#) signal. When the SRWD bit is set to 1 and W# is driven LOW, the device is put in the hardware protected mode. In the hardware protected mode, the non-volatile bits of the status register (SRWD, BP2, BP1, BP0) become read-only bits and the WRITE STATUS REGISTER command is no longer accepted for execution. Figure 10: Status Register Format b7 SRWD b0 0 BP2 0 BP1 BP0 WEL WIP status register write protect block protect bits write enable latch bit write in progress bit Note: WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is automatically set and rest by the internal logic of the device). SRWD = status register write protect bit; BP0, BP1, BP2 = block protect bits. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory WRITE STATUS REGISTER WRITE STATUS REGISTER The WRITE STATUS REGISTER command allows new values to be written to the status register. Before the WRITE STATUS REGISTER command can be accepted, a WRITE ENABLE command must have been executed previously. After the WRITE ENABLE command has been decoded and executed, the device sets the write enable latch (WEL) bit. The WRITE STATUS REGISTER command is entered by driving chip select (S#) LOW, followed by the command code and the data byte on serial data input (DQ0). The WRITE STATUS REGISTER command has no effect on b6, b5, b4, b1 and b0 of the status register. The status register b6, b5, and b4 are always read as 0. S# must be driven HIGH after the eighth bit of the data byte has been latched in. If not, the WRITE STATUS REGISTER command is not executed. Figure 11: WRITE STATUS REGISTER Command Sequence 0 7 8 9 10 11 12 13 15 14 C LSB Command DQ0 MSB LSB DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB As soon as S# is driven HIGH, the self-timed WRITE STATUS REGISTER cycle is initiated; its duration is tW. While the WRITE STATUS REGISTER cycle is in progress, the status register may still be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed WRITE STATUS REGISTER cycle, and is 0 when the cycle is completed. Also, when the cycle is completed, the WEL bit is reset. The WRITE STATUS REGISTER command allows the user to change the values of the block protect bits. Setting these bit values defines the size of the area that is to be treated as read-only, as defined in the Protected Area Sizes table. The WRITE STATUS REGISTER command also allows the user to set and reset the status register write disable (SRWD) bit in accordance with the write protect (W#) signal. The SRWD bit and the W# signal allow the device to be put in the HARDWARE PROTECTED (HPM) mode. The WRITE STATUS REGISTER command is not executed once the HPM is entered. The options for enabling the status register protection modes are summarized here. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory WRITE STATUS REGISTER Table 9: Status Register Protection Modes Memory Content W# Signal SRWD Bit 1 0 0 0 1 1 0 1 Protection Mode (PM) Status Register Write Protection Protected Area1 Unprotected Area1 SECOND SOFTWARE PROTECTED mode (SPM2) Software protection Commands not accepted Commands accepted HARDWARE PROTECTED mode (HPM) Hardware protection Commands not accepted Commands accepted Note: 1. As defined by the values in the Block Protect bits of the status register. When the SRWD bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the WEL bit has been set previously by a WRITE ENABLE command, regardless of whether the W# signal is driven HIGH or LOW. When the status register SRWD bit is set to 1, two cases need to be considered depending on the state of the W# signal: * If the W# signal is driven HIGH, it is possible to write to the status register provided that the WEL bit has been set previously by a WRITE ENABLE command. * If the W# signal is driven LOW, it is not possible to write to the status register even if the WEL bit has been set previously by a WRITE ENABLE command. Therefore, attempts to write to the status register are rejected, and are not accepted for execution. The result is that all the data bytes in the memory area that have been put in SPM2 by the status register block protect bits (BP1, BP0) are also hardware protected against data modification. Regardless of the order of the two events, the HPM can be entered in either of the following ways: * Setting the status register SRWD bit after driving the W# signal LOW * Driving the W# signal LOW after setting the status register SRWD bit. The only way to exit the HPM is to pull the W# signal HIGH. If the W# signal is permanently tied HIGH, the HPM can never be activated. In this case, only the SPM2 is available, using the status register block protect bits. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory READ DATA BYTES READ DATA BYTES The device is first selected by driving chip select (S#) LOW. The command code for READ DATA BYTES is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of serial clock (C). Then the memory contents at that address is shifted out on serial data output (DQ1), each bit being shifted out at a maximum frequency fR during the falling edge of C. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Therefore, the entire memory can be read with a single READ DATA BYTES command. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The READ DATA BYTES command is terminated by driving S# HIGH. S# can be driven HIGH at any time during data output. Any READ DATA BYTES command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 12: READ DATA BYTES Command Sequence 0 7 8 Cx C LSB MSB DQ1 A[MIN] Command DQ[0] A[MAX] DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Don't Care Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 1. Address bits A23-A20 are don't care. 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory READ DATA BYTES at HIGHER SPEED READ DATA BYTES at HIGHER SPEED The device is first selected by driving chip select (S#) LOW. The command code for the READ DATA BYTES at HIGHER SPEED command is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (C). Then the memory contents at that address are shifted out on serial data output (DQ1) at a maximum frequency fC, during the falling edge of C. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Therefore, the entire memory can be read with a single READ DATA BYTES at HIGHER SPEED command. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The READ DATA BYTES at HIGHER SPEED command is terminated by driving S# HIGH. S# can be driven HIGH at any time during data output. Any READ DATA BYTES at HIGHER SPEED command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 13: READ DATA BYTES at HIGHER SPEED Command Sequence 0 7 8 Cx C LSB A[MIN] Command DQ0 MSB DQ1 A[MAX] DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Dummy cycles Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN Don't Care 1. Address bits A23-A20 are don't care . 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory READ LOCK REGISTER READ LOCK REGISTER The device is first selected by driving chip select (S#) LOW. The command code for the READ LOCK REGISTER command is followed by a 3-byte address (A23-A0) pointing to any location inside the concerned sector (or subsector). Each address bit is latched-in during the rising edge of serial clock (C). Then the value of the lock register is shifted out on serial data output (DQ1), each bit being shifted out at a maximum frequency fC during the falling edge of C. The READ LOCK REGISTER command is terminated by driving S# HIGH at any time during data output. Figure 14: READ LOCK REGISTER Command Sequence 0 7 8 Cx C LSB MSB DQ1 A[MIN] Command DQ[0] A[MAX] DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Don't Care Any READ LOCK REGISTER command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Values of b1 and b0 after power-up are defined in the table below. Table 10: Lock Register Out Bit Bit name Value b7-b4 b1 b0 Function Reserved Sector lock down Sector write lock 1 The write lock and lock-down bits cannot be changed. Once a value of 1 is written to the lock-down bit, it cannot be cleared to a value of 0 except by a powerup. 0 The write lock and lock-down bits can be changed by writing new values to them. 1 WRITE, PROGRAM, and ERASE operations in this sector will not be executed. The memory contents will not be changed. 0 WRITE, PROGRAM, or ERASE operations in this sector are executed and will modify the sector contents. Table 11: Not for new design: Lock Registers for the M25PE80 in T7Y Process Bit Bit name b7-b4 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN Value Function Reserved 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory READ LOCK REGISTER Table 11: Not for new design: Lock Registers for the M25PE80 in T7Y Process (Continued) Bit b3 b2 b1 b0 Bit name Subsector lock down Subsector write lock Sector lock down Sector write lock Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN Value Function 1 This functionality must not be used for new designs, as the M25PE80 delivered from Feb 2007 will not offer this functionality. The write lock and lock down bits cannot be changed. Once a 1 is written to the lock down bit it cannot be cleared to 0 except by a reset or power-up. 0 This functionality must not be used for new designs, as the M25PE80 delivered from Feb 2007 will not offer this functionality. The write lock and lock down bits can be changed by writing new values to them (default value). 1 This functionality must not be used for new designs, as the M25PE80 delivered from Feb 2007 will not offer this functionality. WRITE, PROGRAM, and ERASE operations in this subsector will not be executed. The memory contents will not be changed. 0 This functionality must not be used for new designs, as the M25PE80 delivered from Feb 2007 will not offer this functionality. WRITE, PROGRAM, and ERASE operations in this subsector are executed and will modify the subsector contents (default value). 1 The write lock and lock-down bits cannot be changed. Once a value of 1 is written to the lock-down bit, it cannot be cleared to a value of 0 except by a reset or power-up. 0 The write lock and lock-down bits can be changed by writing new values to them (default value) . 1 WRITE, PROGRAM, and ERASE operations in this sector will not be executed. The memory contents will not be changed. 0 WRITE, PROGRAM, or ERASE operations in this sector are executed and will modify the sector contents (default value). 1. Subsector write lock is valid for sector 0 and 15 only (the value 0 is returned for other sectors). 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory PAGE WRITE PAGE WRITE The PAGE WRITE command allows bytes in the memory to be programmed. Before a PAGE WRITE command can be accepted a WRITE ENABLE command must be executed. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit. The PAGE WRITE command is entered by driving chip select (S#) LOW, followed by the command code, three address bytes, and at least one data byte on serial data input (DQ0). The reset of the page remains unchanged if no power failure occurs during this write cycle. The PAGE WRITE command performs a page erase cycle even if only one byte is updated. If the eight least-significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page; that is, from the address whose eight least significant bits (A7-A0) are all zero. S# must be driven LOW for the entire duration of the sequence. If more than 256 bytes are sent to the device, previously latched data is discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without any effects on the other bytes of the same page. For optimized timings, it is recommended to use the PAGE WRITE command to program all consecutive targeted bytes in a single sequence rather than to use several PAGE WRITE sequences, each containing only a few bytes. S# must be driven HIGH after the eighth bit of the last data byte has been latched in. Otherwise the PAGE WRITE command is not executed. As soon as S# is driven HIGH, the self-timed PAGE WRITE cycle is initiated. While the PAGE WRITE cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed PAGE WRITE cycle, and 0 when the cycle is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. A PAGE WRITE command applied to a page that is hardware or software protected is not executed. Any PAGE WRITE command while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without having any effects on the cycle that is in progress. If RESET is drive LOW while a PAGE WRITE cycle is in progress, the PAGE WRITE cycle is interrupted and the programmed data may be corrupted. On RESET going LOW, the device enters the reset mode and a time of tRHSL is then required before the device can be rescheduled by selecting Chip Select (S#) LOW. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory PAGE WRITE Figure 15: PAGE WRITE Command Sequence S# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C 24-bit address instruction 23 DQ0 22 21 3 2 data byte 1 1 MSB 0 7 6 5 4 3 2 1 0 MSB 47 48 49 50 51 52 53 54 55 2079 46 2078 45 2077 44 2076 43 2075 42 2074 41 2073 40 2072 S# 1 0 C data byte 2 DQ0 7 MSB 6 5 4 3 data byte 3 2 1 0 7 6 5 4 3 data byte 256 2 1 0 7 6 5 4 3 2 MSB MSB Note: Address bits A23-A20 are don't care. 1 n 256. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory PAGE PROGRAM PAGE PROGRAM The PAGE PROGRAM command allows bytes in the memory to be programmed, which means the bits are changed from 1 to 0. Before a PAGE PROGRAM command can be accepted a WRITE ENABLE command must be executed. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit. The PAGE PROGRAM command is entered by driving chip select (S#) LOW, followed by the command code, three address bytes, and at least one data byte on serial data input (DQ0). If the eight least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page; that is, from the address whose eight least significant bits (A7-A0) are all zero. S# must be driven LOW for the entire duration of the sequence. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without any effects on the other bytes of the same page. For optimized timings, it is recommended to use the PAGE PROGRAM command to program all consecutive targeted bytes in a single sequence rather than to use several PAGE PROGRAM sequences, each containing only a few bytes. S# must be driven HIGH after the eighth bit of the last data byte has been latched in. Otherwise the PAGE PROGRAM command is not executed. As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle is initiated; the cycles's duration is tPP. While the PAGE PROGRAM cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed PAGE PROGRAM cycle, and 0 when the cycle is completed. At some unspecified time before the cycle is completed, the write enable latch (WEL) bit is reset. A PAGE PROGRAM command applied to a page that is hardware protected is not executed. Any PAGE PROGRAM command while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without having any effects on the cycle that is in progress. If RESET# is driven LOW while a page program cycle is in progress, the page program cycle is interrupted and the programmed data may be corrupted. On RESET going LOW, the device enters the reset mode and a time of tRHSL is then required before the device can be reselected by driving Chip Select (S#) LOW. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory PAGE PROGRAM Figure 16: PAGE PROGRAM Command Sequence S# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C 24-bit address instruction 23 DQ0 22 21 3 2 data byte 1 1 MSB 7 0 6 5 4 3 2 1 0 MSB S# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C data byte 2 DQ0 7 6 MSB Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 5 4 3 data byte 3 2 1 0 7 6 5 4 MSB 3 data byte n 2 1 0 7 6 5 4 3 2 1 0 MSB 1. Address bits A23-A20 are don't care. 1n 256. 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory WRITE to LOCK REGISTER WRITE to LOCK REGISTER The WRITE to LOCK REGISTER instruction allows the lock register bits to be changed. Before the WRITE to LOCK REGISTER instruction can be accepted, a WRITE ENABLE instruction must have been executed previously. After the WRITE ENABLE instruction has been decoded, the device sets the write enable latch (WEL) bit. The WRITE to LOCK REGISTER instruction is entered by driving chip select (S#) LOW, followed by the instruction code, three address bytes, and one data byte on serial data input (DQ0). The address bytes must point to any address in the targeted sector. S# must be driven HIGH after the eighth bit of the data byte has been latched in. Otherwise the WRITE to LOCK REGISTER instruction is not executed. Lock register bits are volatile, and therefore do not require time to be written. When the WRITE to LOCK REGISTER instruction has been successfully executed, the WEL bit is reset after a delay time of less than tSHSL minimum value. Any WRITE to LOCK REGISTER instruction issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 17: WRITE to LOCK REGISTER Instruction Sequence S# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 1 0 C instruction 24-bit address 23 DQ0 22 21 3 MSB 2 lock register in 1 0 7 6 5 4 3 2 MSB Table 12: Lock Register In Sector Bit Value All sectors except for sector 0 and sector 15 in T7Y process b7-b2 0 b1 Sector lock-down bit value b0 Sector write lock bit value Table 13: Not for new design: lock registers for the M25PE80 in T7Y process Sector Bit All sectors except for sector b7-b2 0 and sector 15 in T7Y proc- b1 ess b0 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 37 Value 0 Sector lock-down bit value Sector write lock bit value Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory WRITE to LOCK REGISTER Table 13: Not for new design: lock registers for the M25PE80 in T7Y process (Continued) Sector Bit Value 1 Only b3 and b2 are taken into account to modify the subsector write lock and lock down bits1 0 Only b1 and b0 are taken into account to modify the sector write lock and lock down bits2 b7 Sector 0, sector 15 in T7Y process Notes: b3 Subsector lock down bit value b2 Subsector write lock bit value b1 Sector lock down bit value b0 Sector write lock bit value 1. b6-b4 and b1-b0 must be reset to 0. 2. b6-b2 must be reset to 0. For products processed in the T7Y process only: Protection always prevails: * When the lock down bit of sector 0 or sector 15 is set to 1. - If the lock down bit of sector 0 is 1, all the lock down bits of the subsectors in sector 0 are forced to 1. - If the lock down bit of sector 15 is 1, all the lock down bits of the subsectors in sector 15 are forced to 1. * When the write lock bit of sector 0 or sector 15 is set to 1. - If the write lock bit of sector 0 is 1, the write lock bits of all the subsectors in sector 0 are forced to 1 (even if their lock down bits are set to 1). - If the write lock bit of sector 15 is 1, the write lock bits of all the subsectors in sector 15 are forced to 1 (even if their lock down bits are set to 1). * When the write lock bit of sector 0 or sector 15 is reset to 0. - If the write lock bit of sector 0 is 0, all the subsectors in sector 0 whose lock down bits are 0 have their write lock bits forced to 0. - If the write lock bit of sector 15 is 0, all the subsectors in sector 15 whose lock down bit is 0 have their write lock bits forced to 0. * When the write lock bit of any sector or subsector is set to 1, any instruction that may modify the contents of this sector or subsector will be rejected (including SECTOR ERASE and BULK ERASE). Note that when the WRLR instruction acts both on WRITE LOCK (WL) and LOCK DOWN (LD) bits, it programs the WL bit first, and then the LD bit. As an example, if a subsector lock register settings are xxxx0101b and a WRLR instruction is issued with a lock register in data set to 00000010b: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory WRITE to LOCK REGISTER 1. The sector WL bit is first set to 0 (and all subsectors that are not locked down will have their WL bit reset to 0). 2. The sector LD bit and all subsectors LD bits are set to 1. In this case, the final value of the above subsector lock register is xxxx1010b. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory PAGE ERASE PAGE ERASE The PAGE ERASE command sets to 1 (FFh) all bits inside the chosen page. Before the PAGE ERASE command can be accepted, a WRITE ENABLE command must have been executed previously. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit. The PAGE ERASE command is entered by driving chip select (S#) LOW, followed by the command code, and three address bytes on serial data input (DQ0). Any address inside the sector is a valid address for the PAGE ERASE command. S# must be driven LOW for the entire duration of the sequence. S# must be driven HIGH after the eighth bit of the last address byte has been latched in. Otherwise the PAGE ERASE command is not executed. As soon as S# is driven HIGH, the self-timed PAGE ERASE cycle is initiated; the cycle's duration is tPE. While the PAGE ERASE cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed PAGE ERASE cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is completed, the WEL bit is reset. A PAGE ERASE command applied to a page that is hardware or software protected is not executed. A PAGE ERASE command while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without having any effects on the cycle that is in progress. If RESET# is driven LOW while a PAGE ERASE cycle is in progress, the PAGE ERASE cycle is interrupted and the programmed data may be corrupted. On RESET going LOW, the device enters the reset mode and a time of tRHSL is then required before the device can be reselected by driving Chip Select (S#) LOW. Figure 18: PAGE ERASE Command Sequence 0 7 8 Cx C LSB DQ0 MSB Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN A[MIN] Command A[MAX] 1. Address bits A23-A20 are don't care. 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory SUBSECTOR ERASE SUBSECTOR ERASE The SUBSECTOR ERASE command sets to 1 (FFh) all bits inside the chosen subsector. Before the SUBSECTOR ERASE command can be accepted, a WRITE ENABLE command must have been executed previously. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit. The SUBSECTOR ERASE command is entered by driving chip select (S#) LOW, followed by the command code, and three address bytes on serial data input (DQ0). Any address inside the subsector is a valid address for the SUBSECTOR ERASE command. S# must be driven LOW for the entire duration of the sequence. S# must be driven HIGH after the eighth bit of the last address byte has been latched in. Otherwise the SUBSECTOR ERASE command is not executed. As soon as S# is driven HIGH, the self-timed SUBSECTOR ERASE cycle is initiated; the cycle's duration is tSSE. While the SUBSECTOR ERASE cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SUBSECTOR ERASE cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is complete, the WEL bit is reset. A SUBSECTOR ERASE command issued to a sector that is hardware or software protected is not executed. Any SUBSECTOR ERASE command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. If RESET# is driven LOW while a SUBSECTOR ERASE cycle is in progress, the SUBSECTOR ERASE cycle is interrupted and data may not be erased correctly. On RESET# going LOW, the device enters the RESET mode and a time of tRHSL is then required before the device can be reselected by driving S# LOW. Figure 19: SUBSECTOR ERASE Command Sequence S# 0 1 2 3 4 5 6 7 8 9 29 30 31 1 0 C instruction 24 bit address 23 DQ0 22 2 MSB Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 1. Address bits A23-A20 are don't care. 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory SECTOR ERASE SECTOR ERASE The SECTOR ERASE command sets to 1 (FFh) all bits inside the chosen sector. Before the SECTOR ERASE command can be accepted, a WRITE ENABLE command must have been executed previously. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit. The SECTOR ERASE command is entered by driving chip select (S#) LOW, followed by the command code, and three address bytes on serial data input (DQ0). Any address inside the sector is a valid address for the SECTOR ERASE command. S# must be driven LOW for the entire duration of the sequence. S# must be driven HIGH after the eighth bit of the last address byte has been latched in. Otherwise the SECTOR ERASE command is not executed. As soon as S# is driven HIGH, the self-timed SECTOR ERASE cycle is initiated; the cycle's duration is tSE. While the SECTOR ERASE cycle is in progress, the status register may be read to check the value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed SECTOR ERASE cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is completed, the WEL bit is reset. A SECTOR ERASE command applied to a sector that contains a page that is hardware protected is not executed. Any SECTOR ERASE command while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without having any effects on the cycle that is in progress. If RESET# is driven LOW while a SECTOR ERASE cycle is in progress, the SECTOR ERASE cycle is interrupted and the programmed data may be corrupted. On RESET going LOW, the device enters the reset mode and a time of tRHSL is then required before the device can be reselected by driving Chip Select (S#) LOW. Figure 20: SECTOR ERASE Command Sequence S# 0 1 2 3 4 5 6 7 8 9 29 30 31 1 0 C 24 bit address instruction 23 DQ0 22 2 MSB Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 1. Address bits A23-A20 are don't care . 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory BULK ERASE BULK ERASE The BULK ERASE command sets all bits to 1 (FFh). Before the BULK ERASE command can be accepted, a WRITE ENABLE command must have been executed previously. After the WRITE ENABLE command has been decoded, the device sets the write enable latch (WEL) bit. The BULK ERASE command is entered by driving chip select (S#) LOW, followed by the command code on serial data input (DQ0). S# must be driven LOW for the entire duration of the sequence. S# must be driven HIGH after the eighth bit of the command code has been latched in; otherwise, the BULK ERASE command is not executed. As soon as S# is driven HIGH, the self-timed BULK ERASE cycle is initiated; the cycle's duration is tBE. While the BULK ERASE cycle is in progress, the status register may be read to check the value of the write In progress (WIP) bit. The WIP bit is 1 during the self-timed BULK ERASE cycle, and is 0 when the cycle is completed. At some unspecified time before the cycle is completed, the WEL bit is reset. Any BULK ERASE command while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without having any effects on the cycle that is in progress. A BULK ERASE command is ignored if at least one sector or subsector is write-protected (hardware or software protection). If RESET# is driven LOW while a BULK ERASE is in progress, the BULK ERASE cycle is interrupted and data may not be erased correctly. On RESET# going LOW, the device enters the RESET mode and a time of tRHSL is then required before the device can be reselected by driving S# LOW. Figure 21: BULK ERASE Command Sequence 0 7 C LSB Command DQ0 MSB 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory DEEP POWER-DOWN DEEP POWER-DOWN Executing the DEEP POWER-DOWN command is the only way to put the device in the lowest power consumption mode, the DEEP POWER-DOWN mode. The DEEP POWERDOWN command can also be used as a software protection mechanism while the device is not in active use because in the DEEP POWER-DOWN mode the device ignores all WRITE, PROGRAM, and ERASE commands. Driving chip select (S#) HIGH deselects the device, and puts it in the STANDBY POWER mode if there is no internal cycle currently in progress. Once in STANDBY POWER mode, the DEEP POWER-DOWN mode can be entered by executing the DEEP POWERDOWN command, subsequently reducing the standby current from ICC1 to ICC2. To take the device out of DEEP POWER-DOWN mode, the RELEASE from DEEP POWER-DOWN command must be issued. Other commands must not be issued while the device is in DEEP POWER-DOWN mode. The DEEP POWER-DOWN mode stops automatically at power-down. The device always powers up in STANDBY POWER mode. The DEEP POWER-DOWN command is entered by driving S# LOW, followed by the command code on serial data input (DQ0). S# must be driven LOW for the entire duration of the sequence. S# must be driven HIGH after the eighth bit of the command code has been latched in. Otherwise the DEEP POWER-DOWN command is not executed. As soon as S# is driven HIGH, it requires a delay of tDP before the supply current is reduced to ICC2 and the DEEP POWER-DOWN mode is entered. Any DEEP POWER-DOWN command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 22: DEEP POWER-DOWN Command Sequence 0 7 C LSB t DP Command DQ0 MSB Standby Mode Deep Power-Down Mode Don't Care 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory RELEASE from DEEP POWER-DOWN RELEASE from DEEP POWER-DOWN Once the device has entered DEEP POWER-DOWN mode, all commands are ignored except RELEASE from DEEP POWER-DOWN. Executing this command takes the device out of the DEEP POWER-DOWN mode. The RELEASE from DEEP POWER-DOWN command is entered by driving chip select (S#) LOW, followed by the command code on serial data input (DQ0). S# must be driven LOW for the entire duration of the sequence. The RELEASE from DEEP POWER-DOWN command is terminated by driving S# high. Sending additional clock cycles on serial clock C while S# is driven LOW causes the command to be rejected and not executed. After S# has been driven high, followed by a delay, tRDP, the device is put in the STANDBY mode. S# must remain HIGH at least until this period is over. The device waits to be selected so that it can receive, decode, and execute commands. Any RELEASE from DEEP POWER-DOWN command issued while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected without any effect on the cycle that is in progress. Figure 23: RELEASE from DEEP POWER-DOWN Command Sequence 0 7 C LSB RDP t Command DQ0 MSB DQ1 High-Z Deep Power-Down Mode Standby Mode Don't Care 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Power-Up and Power-Down Power-Up and Power-Down At power-up and power-down, the device must not be selected; that is, chip select (S#) must follow the voltage applied on V CC until V CC reaches the correct value: * VCC(min) at power-up, and then for a further delay of tVSL * VSS at power-down A safe configuration is provided under the SPI modes heading. To avoid data corruption and inadvertent write operations during power-up, a poweron-reset (POR) circuit is included. The logic inside the device is held reset while V CC is less than the POR threshold voltage, V WI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores the following instructions until a time delay of tPUW has elapsed after the moment that V CC rises above the VWI threshold: * * * * * WRITE ENABLE PAGE WRITE PAGE PROGRAM PAGE ERASE SECTOR ERASE However, the correct operation of the device is not guaranteed if, by this time, V CC is still below V CC(min). No WRITE, PROGRAM, or ERASE instruction should be sent until: * tPUW after V CC has passed the V WI threshold * tVSL after V CC has passed the V CC(min) level If the time, tVSL, has elapsed, after V CC rises above V CC(min), the device can be selected for READ instructions even if the tPUW delay has not yet fully elapsed. As an extra precaution, the RESET# signal could be driven LOW for the entire duration of the power-up and power-down phases. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Power-Up and Power-Down Figure 24: Power-Up Timing VCC VCC,max PROGRAM, ERASE, and WRITE commands are rejected by the device Chip selection not allowed VCC,min t RESET state of the device VSL READ access allowed Device fully accessible VWI t PUW Time Table 14: Power-up Timing and VWI Threshold Note: These parameters are characterized only, over the temperature range -40 C to +85 C. Symbol Parameter Min Max Unit tVSL VCC(min) to S# LOW 30 - s tPUW Time delay before the first WRITE, PROGRAM, or ERASE instruction 1 10 ms VWI Write inhibit voltage 1.5 2.5 V After power-up, the device is in the following state: * * * * Standby Power mode (not the Deep Power-down mode). Write enable latch (WEL) bit is reset. Write in progress (WIP) bit is reset. The Lock Registers are reset (write lock bit, lock down bit) = (0,0). Normal precautions must be taken for supply line decoupling to stabilize the V CC supply. Each device in a system should have the V CC line decoupled by a suitable capacitor close to the package pins; generally, this capacitor is of the order of 100 nF. At power-down, when V CC drops from the operating voltage to below the POR threshold voltage V WI, all operations are disabled and the device does not respond to any instruction. Note: Designers need to be aware that if power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress, some data corruption may result. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory RESET RESET Driving RESET# LOW while an internal operation is in progress will affect this operation (WRITE, PROGRAM, or ERASE cycle) and data may be lost. All lock bits are reset to 0 after a RESET# LOW pulse. Table 15: Device Status After a RESET# LOW Pulse Conditions: RESET Pulse Occurred Lock Bits Status Internal Logic Status Addressed Data Reset to 0 Same as power-on/reset Not significant While decoding the following commands: WRITE ENABLE, WRITE DISABLE, READ ID, READ STATUS REGISTER, READ, READ LOCK REGISTER, FAST READ, WRITE LOCK REGISTER, PAGE WRITE, PAGE PROGRAM, PAGE ERASE, SECTOR ERASE, BULK ERASE, SUBSECTOR ERASE, DEEP POWERDOWN, RELEASE DEEP POWER-DOWN Under completion of ERASE or PROGRAM cycle for the following commands: PAGE WRITE, PAGE PROGRAM, PAGE ERASE, SUBSECTOR ERASE, SECTOR ERASE, or BULK ERASE Reset to 0 Equivalent to power-on/reset Addressed data could be modified Under completion of a WRITE STATUS REGISTER operation Reset to 0 Equivalent to power-on/reset (after tW) Write is correctly completed Device deselected (S# HIGH) and in STANDBY mode Reset to 0 Same as power-on/reset Not significant Note: 1. S# remains LOW while RESET# is LOW. Initial Delivery State The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). All usable status register bits are 0. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Maximum Ratings and Operating Conditions Maximum Ratings and Operating Conditions Caution: Stressing the device beyond the absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device beyond any specification or condition in the operating sections of this datasheet is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 16: Absolute Maximum Ratings Symbol Parameter TSTG Storage temperature TLEAD Lead temperature during soldering Min Max Units -65 150 C See note C VIO Input and output voltage (with respect to ground) -0.6 VCC+0.6 V VCC Supply voltage -0.6 4.0 V VESD Electrostatic discharge voltage (Human Body model) -2000 2000 V Notes: Notes 1 2 1. The TLEAD signal is compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Micron RoHS compliant 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. The VESD signal: JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 , R2 = 500 ). Table 17: Operating Conditions Symbol Parameter Min Max Unit VCC Supply voltage 2.7 3.6 V TA Ambient operating temperature -40 85 C 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory DC Parameters DC Parameters Table 18: DC Characteristics Symbol ILI Parameter Test Conditions (in addition to those listed in Operating Conditions table) Min Max Units - - 2 A Input leakage current ILO Output leakage current - - 2 A ICC1 Standby current (Standby and Reset modes) S# = VCC, VIN = VSS or VCC - 50 A ICC2 Deep power-down current S# = VCC, VIN = VSS or VCC - 10 A ICC3 Operating current (FAST_READ) C = 0.1VCC / 0.9VCC at 50 MHz, DQ1 = open - 8 mA C = 0.1VCC / 0.9VCC at 33 MHz, DQ1 = open - 6 mA ICC4 Operating current (PAGE WRITE) S# = VCC - 15 mA ICC5 Operating current (SECTOR ERASE) S# = VCC - 15 mA VIL Input Low Voltage -0.5 0.3VCC V 0.7VCC VCC+0.4 V 0.4 V VIH Input High Voltage VOL Output Low Voltage IOL = 1.6mA VOH Output High Voltage IOH = -100 A VCC-0.2 Test Conditons (in addition to those listed in Operating Conditions table) Min V Table 19: DC Characteristics 75 MHz Operation Symbol Parameter Max Units ILI Input leakage current - - 2 A ILO Output leakage current - - 2 A ICC1 Standby current (Standby and Reset modes) S# = VCC, VIN = VSS or VCC - 50 A ICC2 Deep power-down current S# = VCC, VIN = VSS or VCC - 10 A ICC3 Operating current (FAST_READ) C = 0.1VCC / 0.9VCC at 33 MHz, DQ1 = open - 4 mA C = 0.1VCC / 0.9VCC at 75 MHz, DQ1 = open - 12 mA ICC4 Operating current (PAGE WRITE) S# = VCC - 15 mA ICC5 Operating current (SECTOR ERASE) S# = VCC - 15 mA VIL Input Low Voltage -0.5 0.3VCC V 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory DC Parameters Table 19: DC Characteristics 75 MHz Operation (Continued) Symbol Parameter Test Conditons (in addition to those listed in Operating Conditions table) VIH Input High Voltage VOL Output Low Voltage IOL = 1.6mA VOH Output High Voltage IOH = -100 A 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 51 Min Max Units 0.7VCC VCC+0.4 V 0.4 V VCC-0.2 V Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory AC Characteristics AC Characteristics In the following AC measurement conditions, output HIGH-Z is defined as the point where data out is no longer driven. Table 20: AC Measurement Conditions Symbol CL Parameter Min Max Unit 30 30 pF - 5 ns Input pulse voltages 0.2VCC 0.8VCC V Input and output timing reference voltages 0.3VCC 0.7VCC V Load capacitance Input rise and fall times Figure 25: AC Measurement I/O Waveform Input levels Input and output timing reference levels 0.8VCC 0.7VCC 0.5VCC 0.2VCC 0.3VCC Table 21: Capacitance Symbol Parameter Test condition Min Max Unit Notes 1 COUT Output capacitance (DQ0/DQ1) VOUT = 0 V - 8 pF CIN Input capacitance (other pins) VIN = 0 V - 6 pF Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 1. Values are sampled only, not 100% tested, at TA=25C and a frequency of 33MHz. 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory AC Characteristics Table 22: AC Characteristics Test conditions are specified in the Operating Conditions and AC Measurement Conditions tables. Symbol Alt. fC fC fR - tCH tCLH tCL tCLL tSLCH tCSS Parameter Typ Max Unit Clock frequency for the following commands: FAST_READ, PW, PP, PE, SE, DP, RDP, WREN, WRDI, RDSR D.C. - 50 MHz Clock frequency for READ command D.C. - 20 MHz Clock HIGH time 9 - - ns 1 Clock LOW time 9 - - ns 1 2 Clock Slew Rate (peak to peak) tCHSL Not es Min 0.1 - - V/ns S# active setup time (relative to C) 5 - - ns S# not active hold time (relative to C) 5 - - ns Data In setup time 2 - - ns tDVCH tDSU tCHDX tDH Data In hold time 5 - - ns tCHSH - S# active hold time (relative to C) 5 - - ns tSHCH - S# not active setup time (relative to C) 5 - - ns tSHSL tCSH S# deselect time 100 - - ns tSHQZ tDIS Output disable time - - 8 ns tCLQV tV Clock LOW to output valid - - 8 ns tCLQX tHO Output hold time 0 - - ns tTHSL - TOP SECTOR LOCK setup time 50 - - ns tTSHTL - TOP SECTOR LOCK hold time 100 - - ns tDP - S# to DEEP POWER-DOWN mode - - 3 s 2 tRDP - S# HIGH to STANDBY mode - - 30 s 2 tPW - PAGE WRITE cycle time (256 bytes) - 11 25 ms 3 tPW - PAGE WRITE cycle time (n bytes) 10.1+n*0.9/256 25 ms 3 tPP - PAGE PROGRAM cycle time (256 bytes) - 1.35 3 ms 3 tPP - PAGE PROGRAM cycle time (n bytes) - 0.45+n*0.9/256 5 ms 3 tPE - PAGE ERASE cycle time - 10 20 ms tSE - SECTOR ERASE cycle time - 1 5 s tSE - BULK ERASE cycle time - 10 60 s Notes: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 2 1. The tCH and tCL signal values must be greater than or equal to 1/fC. 2. Signal values are guaranteed by characterization, not 100% tested in production. 3. When using PP and PW commands to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 <n<256). 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory AC Characteristics Table 23: AC Characteristics (50MHz operation) Test conditions are specified in the Operating Conditions and AC Measurement Conditions tables. Symbol Alt. fC fC fR - tCH tCLH tCL tCLL tSLCH tCSS Parameter Typ Max Unit Clock frequency for the following commands: FAST_READ, RDLR, PW, PP, WRLR, PE, SE, SSE, DP, RDP, WREN, WRDI, RDSR, WRSR D.C. - 50 MHz Clock frequency for READ command D.C. - 33 MHz Clock HIGH time 9 - - ns 1 Clock LOW time 9 - - ns 1 1 Clock Slew Rate (peak to peak) tCHSL Not es Min 0.1 - - V/ns S# active setup time (relative to C) 5 - - ns S# not active hold time (relative to C) 5 - - ns Data In setup time 2 - - ns tDVCH tDSU tCHDX tDH Data In hold time 5 - - ns tCHSH - S# active hold time (relative to C) 5 - - ns tSHCH - S# not active setup time (relative to C) 5 - - ns tSHSL tCSH S# deselect time 100 - - ns tSHQZ tDIS Output disable time - - 8 ns tCLQV tV Clock LOW to output valid - - 8 ns tCLQX tHO Output hold time 0 - - ns tTHSL - WRITE PROTECT setup time 50 - - ns tTSHTL - WRITE PROTECT hold time 100 - - ns 3 tDP - S# to DEEP POWER-DOWN mode - - 3 s 2 tRDP - S# HIGH to STANDBY mode - - 30 s 2 tW - WRITE STATUS REGISTER cycle time - 3 15 ms tPW - PAGE WRITE cycle time (256 bytes) - 11 23 ms 4 tPP - PAGE PROGRAM cycle time (256 bytes) - 0.8 3 ms 4, 5 20 ms PAGE PROGRAM cycle time (n bytes) - PAGE ERASE cycle time - 10 tSE - SECTOR ERASE cycle time - 1 5 s tSSE - SUBSECTOR ERASE cycle time - 50 150 ms tBE - BULK ERASE cycle time - 10 20 s 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 3 int(n/8) x 0.025 tPE Notes: 2 1. 2. 3. 4. The tCH and tCL signal values must be greater than or equal to 1/fC. Signal values are guaranteed by characterization, not 100% tested in production. Only applicable as a constraint for a WRSR instruction when SRWD is set to 1. When using PP and PW commands to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 <256). 5. int(A) corresponds to the upper integer part of A. For instance, int(12/8) = 2, int(32/8) = 4 int(15.3) = 16. 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory AC Characteristics Table 24: AC Specifications (75 MHz operation) Test conditions are specified in the Operating Conditions and AC Measurement Conditions tables. Symbol Alt. fC fC fR - tCH tCLH tCL tCLL tSLCH tCSS Parameter Typ Max Unit Clock frequency for the following commands: FAST_READ, RDLR, PW, PP, WRLR, PE, SE, SSE, DP, RDP, WREN, WRDI, RDSR, WRSR D.C. - 75 MHz Clock frequency for READ command D.C. - 33 MHz Clock HIGH time 6 - - ns 1 Clock LOW time 6 - - ns 1 1 Clock Slew Rate (peak to peak) tCHSL Not es Min 0.1 - - V/ns S# active setup time (relative to C) 5 - - ns S# not active hold time (relative to C) 5 - - ns Data In setup time 2 - - ns tDVCH tDSU tCHDX tDH Data In hold time 5 - - ns tCHSH - S# active hold time (relative to C) 5 - - ns tSHCH - S# not active setup time (relative to C) 5 - - ns tSHSL tCSH S# deselect time 100 - - ns tSHQZ tDIS Output disable time - - 8 ns tCLQV tV Clock LOW to output valid under 30pF/10pF - - 8/6 ns tCLQX tHO Output hold time 0 - - ns tWHSL - WRITE PROTECT setup time 20 - - ns tSHWL - WRITE PROTECT hold time 100 - - ns 3 tDP - S# to DEEP POWER-DOWN mode - - 3 s 2 tRDP - S# HIGH to STANDBY mode - - 30 s 2 tW - WRITE STATUS REGISTER cycle time 3 15 ms tPW - PAGE WRITE cycle time (256 bytes) - 11 23 ms tPP - PAGE PROGRAM cycle time (256 bytes) - 0.8 3 ms 4 tPP - PAGE PROGRAM cycle time (n bytes) - int(n/8) x 0.025 3 ms 4, 5 tPE - PAGE ERASE cycle time - 10 20 ms tSE - SECTOR ERASE cycle time - 1 5 s tSSE - SUBSECTOR ERASE cycle time - 50 150 ms tBE - BULK ERASE cycle time - 10 20 s Notes: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 2 3 1. 2. 3. 4. The tCH and tCL signal values must be greater than or equal to 1/fC. Signal values are guaranteed by characterization, not 100% tested in production. Only applicable as a constraint for a WRSR instruction when SRWD is set to 1. When using PP and PW commands to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 <n<256). 5. int(A) corresponds to the upper integer part of A. For example, int(12/8) = 2, int(32/8) = 4, int(15.3) = 16. 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory AC Characteristics Figure 26: Serial Input Timing tSHSL S# tCHSL tCHSH tSLCH tSHCH C tDVCH tCHCL tCHDX DQ0 tCLCH LSB IN MSB IN high impedance DQ1 Figure 27: Write Protect Setup and Hold Timing W#/VPP tSHWL tWHSL S# C DQ0 high impedance DQ1 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory AC Characteristics Figure 28: Output Timing S# tCH C tCLQV tCLQV tCLQX tCL tSHQZ tCLQX LSB OUT DQ1 tQLQH tQHQL DQ0 ADDRESS LSB IN Table 25: Reset Conditions Symbol Alt Parameter tRLRH tRST Reset Pulse width tSHRH Conditions Chip Select HIGH to RESET HIGH Note: Chip should have been deselected before RESET is de-asserted Min Typ Max Unit 10 - - s 10 - - s 1. Test conditions specified in Operating Conditions and AC Measurement Conditions tables. tRLRH value guaranteed by characterization; not 100% tested in production. Table 26: Timings After a RESET# LOW Pulse Symbol Alt Parameter Conditions: Reset Pulse Occurred Max Unit 30 s 300 s 3 ms Under completion of a WRSR operation tW ms Device deselected (S# HIGH) and in Standby mode 0 s While decoding an instruction: WREN, WRDI, RDID, RDSR, READ, RDLR, FAST_READ, WRLR, PW, PP, PE, SE, BE, SSE, DP, RDP tRHSL tREC Under completion of an ERASE or PROGRAM cycle of a Reset recov- PW, PP, PE, SE, BE operation ery time Under completion of an ERASE cycle of an SSE operation Notes: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 2 1. All values are guaranteed by characterization; not 100% tested in production. See Device Status after a RESET# LOW Pulse table for a description of the device status after a RESET# LOW pulse. While decoding an instruction, S# remains LOW while RESET# is LOW. 2. See AC Characteristics 75 MHz operation tables. 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory AC Characteristics Figure 29: Reset AC Waveforms S# tSHRH tRHSL tRLRH RESET# Don't Care 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Package Information Package Information Figure 30: VFQFPN8 (MLP8) 6mm x 5mm 6 TYP 5.75 TYP Pin 1 ID 4.75 TYP 4.00 0.20 5 TYP 1.27 TYP 0.4 +0.08 -0.05 3.4 0.2 12 0.6 +0.15 -0.1 0.65 TYP 0.85 TYP/ 0.05 MAX 0.20 TYP 0 MIN/ 0.05 MAX Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 1. Drawing is not to scale. 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Package Information Figure 31: QFN8L (MLP8) 8-lead, quad flat package no lead, 6mm x 5mm 5.00 TYP 0PIN 1 ID OPTION 3.00 + 0.20 +0.15 0.60 -0.10 6.00 TYP 3.00 +0.20 1.27 TYP 0.90 +0.10 +0.08 0.40 -0.05 0.02 TYP/0.05 MAX 0.08 0.20 TYP Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 1. Drawing is not to scale. 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Package Information Figure 32: SO8W - 8 lead plastic small outline, 208 mils body width 1.70 MIN/ 1.91 MAX 0.36 MIN/ 0.48 MAX 1.78 MIN/ 2.16 MAX 0.15 MIN/ 0.25 MAX 0.10 MAX 1.27 TYP 5.08 MIN/ 5.49 MAX 7.70 MIN/ 8.10 MAX 8 5.08 MIN/ 5.49 MAX 1 Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 0.05 MIN/ 0.25 MAX 0 MIN/ 10 MAX 0.50 MIN/ 0.80 MAX 1. Drawing is not to scale. 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Package Information Figure 33: SO8N - 8 lead plastic small outline, 150 mils body width 0.25 MIN/ x 45 0.50 MAX 1.75 MAX/ 1.25 MIN 0.17 MIN/ 0.23 MAX 0.10 MAX 0.28 MIN/ 0.48 MAX 1.27 TYP 0.25 mm GAUGE PLANE 4.90 0.10 8 0o MIN/ 8o MAX 6.00 0.20 3.90 0.10 1 0.10 MIN/ 0.25 MAX 0.40 MIN/ 1.27 MAX 1.04 TYP Note: 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 1. Drawing is not to scale. 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Device Ordering Information Device Ordering Information Micron Serial NOR Flash memory is available in different configurations and densities. Verify valid part numbers by using Micron's part catalog search at www.micron.com. To compare features and specifications by device type, visit www.micron.com/products. Contact the factory for devices not found. For more information on how to identify products and top-side marking by the process identification letter, refer to technical note TN-12-24, Serial Flash Memory Device Marking for the M25P, M25PE, M25PX, and N25Q Product Families. Table 27: Standard Part Number Information Scheme Part Number Category Category Details Device type M25PE = Page-erasable serial Flash memory Density 80 = 8Mb (1Mb x 8-bit) Operating voltage V = VCC = 2.7V to 3.6V Package MW = SO8W (208 mils width) Notes MN = SO8N (150 mils width) MP = VFQFPN8 6mm x 5mm (MLP8) MS = QFN8L 6mm x 5mm (MLP8) 1 Device Grade 6 = Industrial temperature range: -40 C to 85 C. Device tested with standard test flow. Packing Option - = Standard packing T = Tape and reel packing Plating technology P or G = RoHS compliant Note: 1. Exposed pad of 3mm x 3mm. Table 28: Automotive Part Number Information Scheme Part Number Category Category Details Device type M25PE = Page-erasable serial Flash memory Density 80 = 8Mb (1Mb x 8-bit) Operating voltage V = VCC = 2.7V to 3.6V Package MN = SO8N (150 mils width) Device Grade 6 = Industrial temperature range: -40 C to 85 C. Device tested with standard test flow. Packing Option - = Standard packing T = Tape and reel packing Plating technology P = RoHS compliant Lithography B = 110nm, Fab 2 diffusion plant blank = Industrial part (Refer to Standard Part Number Information Scheme) Automotive grade A = Automotive grade -40 to 85 C. Device tested with high reliability certified flow blank = Standard -40 to 85 C device (Refer to Standard Part Number Information Scheme) 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved. M25PE80 Serial Flash Memory Revision History Revision History Rev. E - 06/18 * Added Important Notes and Warnings section for further clarification aligning to industry standards Rev. D - 6/2014 * Added SO8N package dimension figure Rev. C - 3/2013 * Replaced SO8W package dimension figure * Revised text at the beginning of Ordering Information. Rev. B - 11/2012 * Removed T9HX process information * Added automotive grade part information Rev. A - 09/2012 * Applied Micron branding. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 09005aef845660f2 m25pe80.pdf - Rev. E 06/18 EN 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2013 Micron Technology, Inc. All rights reserved.