S1D13742 Mobile Graphics Engine Hardware Functional Specification Document Number: X63A-A-001-06 Status: Revision 6.2 Issue Date: 2008/07/07 (c) SEIKO EPSON CORPORATION 2004 - 2008. All Rights Reserved. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 3 Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Features . . . . . . . . . . 2.1 Integrated Frame Buffer 2.2 CPU Interface . . . . 2.3 Input Data Formats . . 2.4 Display Support . . . . 2.5 Display Modes . . . . 2.6 Display Features . . . 2.7 Clock Source . . . . . 2.8 Miscellaneous . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Pinout Diagram . . . . . . . . . . . 4.1 Pin-Out . . . . . . . . . . . 4.2 Pin Descriptions . . . . . . . 4.2.1 Intel 80 Host Interface . . . . 4.2.2 LCD Interface . . . . . . . . 4.2.3 Clocks . . . . . . . . . . . . 4.2.4 Miscellaneous . . . . . . . . 4.2.5 Power And Ground . . . . . 4.3 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 13 14 15 16 16 17 18 5 Pin Mapping . . . . . . . . . . . . 5.1 Intel 80 Data Pins . . . . . . 5.2 LCD Interface Pin Mapping . . 5.3 LCD Interface Data Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 20 21 6 D.C. Characteristics . . . . . . . . . 6.1 Absolute Maximum Ratings . . . . 6.2 Recommended Operating Conditions 6.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 22 23 7 A.C. Characteristics . . 7.1 Clock Timing . . . 7.1.1 Input Clocks . . 7.1.2 PLL Clock . . . 7.2 RESET# Timing . . 7.3 Host interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 26 27 29 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Functional Specification Issue Date: 2008/07/07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 .8 .8 .8 .8 .8 .9 .9 .9 S1D13742 X63A-A-001-06 Revision 6.2 Page 4 Epson Research and Development Vancouver Design Center 7.3.1 Intel 80 Interface Timing - 1.8 Volt . . . . . . . 7.3.2 Intel 80 Interface Timing - 3.3 Volt . . . . . . . 7.3.3 Definition of Transition Time to Hi-Z State . . . 7.4 Display Interface . . . . . . . . . . . . . . . 7.4.1 TFT Power-On Sequence . . . . . . . . . . . . 7.4.2 TFT Power-Off Sequence . . . . . . . . . . . . 7.4.3 18/36-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Clocks . . . . . . . . . . . . . 8.1 Clock Descriptions . . . . 8.2 PLL Block Diagram . . . 8.3 Clocks versus Functions . . 8.4 Setting SYSCLK and PCLK . . . . . . . . . . . 9 Registers . . . . . . . . . . . . . . . . . 9.1 Register Mapping . . . . . . . . . 9.2 Register Set . . . . . . . . . . . . 9.3 Register Descriptions . . . . . . . . 9.3.1 Read-Only Configuration Registers 9.3.2 Clock Configuration Registers . . 9.3.3 Panel Configuration Registers . . . 9.3.4 Input Mode Register . . . . . . . . 9.3.5 Display Mode Registers . . . . . . 9.3.6 Window Settings . . . . . . . . . . 9.3.7 Memory Access . . . . . . . . . . 9.3.8 Gamma Correction Registers . . . 9.3.9 Miscellaneous Registers . . . . . . 9.3.10 General Purpose IO Pins Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 . . 32 . . 34 . .35 . . 36 . . 37 . . 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 .40 .41 .42 .43 . . .44 . . .44 . . .45 . . .46 . . . 46 . . . 47 . . . 52 . . . 55 . . . 60 . . . 64 . . . 66 . . . 68 . . . 70 . . . 72 10 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 11 Intel 80, 8-bit Interface Color Formats . . . . . . . 11.1 16 bpp Mode (R 5-bit, G 6-bit, B 5-bit), 65,536 colors 11.2 18 bpp (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . 11.3 24 bpp (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 .75 .76 .77 12 Intel 80, 16-bit Interface Color Formats . . . . . . . . . . . 12.1 16 bpp (R 5-bit, G 6-bit, B 5-bit), 65,536 colors . . . . . . 12.2 18 bpp Mode 1 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . 12.3 18 bpp Mode 2 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . 12.4 24 bpp Mode 1 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors 12.5 24 bpp Mode 2 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 .78 .79 .80 .81 .82 13 YUV Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 13.1 YUV 4:2:2 with Intel 80, 8-bit Interface . . . . . . . . . . . . . . . . . . . . .84 S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center 13.2 13.3 13.4 13.5 13.6 Page 5 YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface . . YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface . YUV 4:2:2 with Intel 80, 16-bit Interface . . . . . . YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface . YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 85 86 87 88 14 Gamma Correction Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . 89 14.1 Gamma Correction Example Programming . . . . . . . . . . . . . . . . . . . 90 15 Display Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 16 SwivelViewTM . . . . . . . . . . . . 16.1 Concept . . . . . . . . . . . 16.2 90 SwivelViewTM . . . . . . 16.2.1 Register Programming . . . 16.3 180 SwivelViewTM . . . . . . 16.3.1 Register Programming . . . 16.4 270 SwivelViewTM . . . . . . 16.4.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 95 95 95 96 96 97 97 17 Host Interface . . . . . . . . . . . . . . . . . . . . 17.1 Using the Intel 80 Interface . . . . . . . . . . 17.1.1 Register write procedure . . . . . . . . . . . 17.1.2 Register read procedure . . . . . . . . . . . . 17.1.3 New Window Aperture Write procedure . . . 17.1.4 Opening Multiple Windows . . . . . . . . . . 17.1.5 Individual Memory Location Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 . . . . . . 98 . . . . . . . . 98 . . . . . . . . 99 . . . . . . . . 100 . . . . . . . . 102 . . . . . . . . 102 18 Double Buffer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.1 Double Buffer Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 103 19 Interfacing the S1D13742 and a TFT Panel . . . . . . . 19.1 Overview . . . . . . . . . . . . . . . . . . . 19.1.1 Electrical Interface . . . . . . . . . . . . . . . . . 19.1.2 S1D13742 Register Settings for 352x416 TFT Panel 19.1.3 S1D13742 Register Settings for 800x480 TFT Panel 19.2 Host Bus Timing . . . . . . . . . . . . . . . . 19.2.1 Host Bus Timing for 352x416 TFT Panel . . . . . . 19.2.2 Host Bus Timing for 800x480 TFT Panel . . . . . . 19.3 Panel Timing . . . . . . . . . . . . . . . . . . 19.3.1 Panel Timing for 352x416 Panel . . . . . . . . . . 19.3.2 Panel Timing for 800x480 Panel . . . . . . . . . . 19.4 Example Play.exe Scripts . . . . . . . . . . . . . 19.5 References . . . . . . . . . . . . . . . . . . . 19.5.1 Documents . . . . . . . . . . . . . . . . . . . . . . Hardware Functional Specification Issue Date: 2008/07/07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 . . . . . . 106 . . . . . . . . 106 . . . . . . . . 107 . . . . . . . . 109 . . . . . . 111 . . . . . . . . 112 . . . . . . . . 113 . . . . . . 114 . . . . . . . . 115 . . . . . . . . 115 . . . . . . 116 . . . . . . 122 . . . . . . . . 122 S1D13742 X63A-A-001-06 Revision 6.2 Page 6 Epson Research and Development Vancouver Design Center 20 PLL Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 123 20.1 Guidelines for PLL Power Layout . . . . . . . . . . . . . . . . . . . . . . 123 21 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 22 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 23 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 23.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 7 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13742 Embedded Memory LCD Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This document is updated as appropriate. Please check the Epson Research and Development Website at www.erd.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via email at documentation@erd.epson.com. 1.2 Overview Description The S1D13742 is a color LCD graphics controller with an embedded 768K byte display buffer. The S1D13742 supports a 8/16-bit Intel 80 CPU architecture while providing high performance bandwidth into display memory allowing for fast screen updates. Products requiring a rotated display image can take advantage of the SwivelViewTM feature which provides hardware rotation of the display memory transparent to the software application. Resolutions supported include 800x480 single buffered and 352x416 double buffered. The S1D13742 uses a double-buffer architecture to prevent any visual tearing during streaming video screen updates. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 8 Epson Research and Development Vancouver Design Center 2 Features 2.1 Integrated Frame Buffer * Embedded 768K byte SRAM display buffer. 2.2 CPU Interface * 8/16-bit Intel 80 interface (used for display or register data). * Chip select is used to select device. When inactive, any input data/command will be ignored. 2.3 Input Data Formats * RGB: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or 18 bpp). * YUV 4:2:2, 4:2:0 (Internal YUV to RGB Converter stored as 16 or 18 bpp). Note All input data must be internally converted to the same format before being stored in the display buffer. Different data types can not be mixed within a common display buffer. 2.4 Display Support * Active Matrix TFT interface. * 18/36-bit interface. * Supports resolutions up to 800x480. 2.5 Display Modes * 16/18 bit-per-pixel (bpp) color depths. * 16 bpp to 18 bpp conversion: Input data can be converted from 16 bpp to 18 bpp in one of three ways. 1. RGB (5:6:5) msb copying to create new lsb for the Red and Blue components. This conversion is done prior to storing in memory, as this allows for 16 bpp and 18 bpp input data to be mixed. 2. Gamma Correction Look-Up-Tables: there are three, 64 position, 8-bit wide LUT's. The data stored in memory can be used as an index into these tables. The LUT's are placed on the display side and therefore do not affect the data stored in memory. 3. RGB (5:6:5) stored in memory: LUT is by-passed. Copy msb to lsb for red and blue during the display read from memory. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 9 2.6 Display Features * All display writes will be handled by window apertures/position for complete or partial display updates. All window coordinates are referenced to top left corner of the displayed image (even in a rotated display, the top-left corner is maintained and no host side translation need take place). * SwivelViewTM: 90, 180, 270 counter-clockwise hardware rotation of display image. All displayed windows can have independent rotation. No additional programming necessary when enabling these modes. * Double-Buffer available to prevent image tearing during streaming input. Resolutions supported must fit inside 384K bytes (1/2 of total available display buffer). Typical resolution of 352x416. * Pixel Doubling: Horizontal and Vertical averaging for smooth doubling of a single window. * Pixel Halving: no limitation on number of windows. 2.7 Clock Source * Internal programmable PLL. * Single MHz clock input: CLKI. * CLKI available as CLKOUT (separate CLKOUTEN pin associated with output). * output state = 0 when disabled. 2.8 Miscellaneous * Hardware / Software Power Save mode. * Input pin to Enable/Disable Power Save Mode. * General Purpose Input/Output pins are available (GPIO[7:0]). * INT pin associated with selectable GPIO inputs. * Package: FCBGA 121-pin package QFP20 144-pin package Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 10 Epson Research and Development Vancouver Design Center 3 Block Diagram MClk Data Control Intel 80 8/16 IF MClk YUV Converter MClk YUV to RGB MClk Rotation (Pixel Halving) MClk Memory Controller MClk PClk LCD Disp Pipe PClk PClk Gamma Correction LCD IF Registers RegWrClk MClk Clocks Double Buffer Controller Test Mux PClk LCD Ctc Figure 3-1: Block Diagram S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 11 4 Pinout Diagram 4.1 Pin-Out A NC NC CLKOUT CLKI MD3 MD4 MD5 MD6 MD7 NC NC B NC MD2 MD12 CLKOUTEN MD13 MD14 MD15 MD8 MD9 MD10 NC C MD0 MD11 MD1 IOVDD VSS VSS CS# WE# RD# D/C# DE D RESET# TE GPIO_INT PLLVDD VCP PLLVSS COREVDD IOVDD HS VS PCLK E TEST1 TEST2 TESTEN COREVDD VSS VSS VSS PIOVDD NC VD35 VD34 F TEST0 SCANEN CNF0 VSS VSS VSS VSS VD33 VD32 VD31 VD30 G GPIO0 GPIO1 CNF1 PIOVDD VSS VSS COREVDD VD29 VD28 VD27 VD26 H GPIO2 GPIO3 CNF2 IOVDD PIOVDD COREVDD PIOVDD VD25 VD24 VD23 VD22 J GPIO4 GPIO5 PWRSVE VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 K NC GPIO6 GPIO7 VD13 VD12 VD11 VD10 VD9 VD8 VD7 NC L NC NC VD6 VD5 VD4 VD3 VD2 VD1 VD0 NC NC 1 2 3 4 5 6 7 8 9 10 11 Figure 4-1: S1D13742 FCBGA Pinout (Top View) Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Epson Research and Development Vancouver Design Center NC NC NC VSS COREVDD VSS IOVDD MD0 MD11 GPIO_INT TE RESET# TESTEN SCANEN TEST2 TEST1 TEST0 CNF0 VSS COREVDD GPIO0 GPIO1 CNF1 CNF2 GPIO3 GPIO2 GPIO4 GPIO5 PWRSVE GPIO6 VSS IOVDD NC NC NC NC Page 12 73 108 109 MD2 MD1 MD12 VSS IOVDD CLKOUT CLKOUTEN VSS COREVDD CLKI VSS IOVDD PLLVDD VCP PLLVSS MD13 MD3 MD4 MD14 IOVDD VSS CS# MD15 MD5 MD6 COREVDD VSS MD8 WE# RD# MD9 MD7 MD10 D/C# IOVDD VSS 108 107 106 105 104 103 102 101 100 99 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 144 72 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 INDEX 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 NC GPIO7 VSS PIOVDD VSS COREVDD VD6 VD5 VD13 VD21 VD4 VD12 VD20 VD3 VD11 VD19 VSS PIOVDD VD2 VSS PIOVDD VD10 VD18 VD1 VD9 VD17 VD25 VD0 VD8 VD16 VD7 VSS COREVDD VSS PIOVDD NC 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 NC NC NC PIOVDD VSS COREVDD VSS DE HS VS PCLK VD34 VD35 VD33 VD32 VD31 PIOVDD VSS VD30 PIOVDD VSS VD26 VD27 VD28 VD29 VD24 VD23 VD22 VD15 VD14 COREVDD VSS PIOVDD VSS NC NC 36 Figure 4-2: S1D13742 QFP20 Pinout (Top View) S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 13 4.2 Pin Descriptions Key: Pin Types I O IO P = = = = Input Output Bi-Directional (Input/Output) Power pin RESET# / Power Save Status H = High level output L = Low level output Hi-Z = High Impedance Table 4-1: Cell Description Item Description 1 HI H System LVCMOS3 Input Buffer HIS H System LVCMOS Schmitt Input Buffer HID H System LVCMOS Input Buffer with pull-down resistor HO H System LVCOMOS Output buffer HB H System LVCMOS Bidirectional Buffer HBD H System LVCMOS Bidirectional Buffer with pull-down resistor HB_DSEL H System LVCMOS Bidirectional Buffer with Drive Selector LIDS L System2 LVCMOS Schmitt Input Buffer with pull-down resistor LITR L System Transparent Input Buffer 1 H System is IOVDD and PIOVDD (see Section 6, "D.C. Characteristics"). L System is COREVDD (see Section 6, "D.C. Characteristics"). 3 LVCMOS is Low Voltage CMOS (see Section 6, "D.C. Characteristics"). 2 Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 14 Epson Research and Development Vancouver Design Center 4.2.1 Intel 80 Host Interface Table 4-2: Host Interface Pin Descriptions Pin Name Type FCBGA Pin # QFP Pin # Cell IO RESET# Voltage State Power Save Status Description Intel 80 Data lines. MD[15:0] IO B7,B6, B5,B3, C2,B10, B9, B8, A9,A8,A7, A6,A5,B2, C3,C1 131,127, 124,111, 100,141, 139,136, 140,133, 132,126, 125,109, 110,101 HB IOVDD Hi-Z Hi-Z * For the S1D13742B00, when the 8-bit bus interface is selected by CNF1, MD[15:8] are pulled low by internal resistors. * For the S1D13742B01, when the 8-bit bus interface is selected by CNF1, MD[15:8] should be connected to VSS. Note: The Host Data lines can be swapped (i.e. MD15 = MD0) using the CNF0 pin. For details, see Section 4.3, "Summary of Configuration Options" on page 18. WE# I C8 137 HI IOVDD Input RD# I C9 138 HI IOVDD Input Input This input pin is the Read Enable signal. CS# I C7 130 HI IOVDD Input Input This input pin is the Chip Select signal. D/C# I C10 142 HI IOVDD Input Input This input pin is used to select between Intel 80 address and data TE O D2 98 HO IOVDD L L GPIO_INT O D3 99 HO IOVDD L RESET# I D1 97 HI IOVDD Input S1D13742 X63A-A-001-06 Input This input pin is the Write Enable signal. Tearing Effect: this pin will reflect the VSYNC, HSYNC or the OR'd combination status of the display. This interrupt pin is associated with selected GPIO pins when configured as inputs or outputs. Interrupt functionality is Output not affected by Power Save. See Section 9.3.10, "General Purpose IO Pins Registers" on page 72 for operational description. Input Active low input to set all internal registers to the default state and to force all signals to their inactive states. Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 15 4.2.2 LCD Interface Table 4-3: LCD Interface Pin Descriptions Pin Name VD[35:0] FCBGA Pin # IO E10,E11, F8,F9,F10, F11,G8, G9,G10, G11,H8, H9,H10, H11,J4,J5, J6,J7,J8,J9, J10,J11,K4, K5,K6, K7, K8,K9,K10, L3,L4,L5,L6, L7,L8,L9 13,12,14,15, 16,19,25,24, 23,22,46,26, 27,28,63,60, 57,50,47,43, 29,30,64,61, 58,51,48,44, 42,66,65,62, 59,54,49,45 HB_ DSEL D10 10 HO PIOVDD VS O QFP Pin # IO RESET# Voltage State Type Cell Power Save Status Description Panel Data bits 35-0. VD[35:0] are used for all modes. In 2 pixels/clock mode, VD[17:0] represent the 1st pixel sent in a 2 pixel/clock operation. PIOVDD L L Note: The Panel Data Lines can be swapped (i.e. VD23 = VD0) using the VD Data Swap bit, REG[14h] bit 7. Note: The VD output drive is selectable between 2.5mA and 6.5mA using the CNF2 pin. For details, see Section 4.3, "Summary of Configuration Options" on page 18. H L This output pin is the Vertical Sync pulse HS O D9 9 HO PIOVDD H L This output is the Horizontal Sync pulse PCLK O D11 11 HO PIOVDD CLKI L This output pin is the Data Clock DE O C11 8 HO PIOVDD L L This output pin is the Data Enable Note The LCD interface requires a separate power rail (PIOVDD) to support the configurable IO drive. For details, see the CNF2 description in Section 4.3, "Summary of Configuration Options" on page 18. Note Input of VD[35:0] is used for production test only. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 16 Epson Research and Development Vancouver Design Center 4.2.3 Clocks Table 4-4: Clock Input Pin Descriptions Pin Name Type FCBGA Pin # QFP Pin # Cell IO RESET# Voltage State CLKI I A4 118 HIS IOVDD Input Power Save Status Input Description MHz input for PLL operation or MHz input if PLL is bypassed Input frequency range: 1MHz ~ 33MHz CLKOUT O A3 114 HO IOVDD L CLKI This output pin represents the CLKI pin if enabled by CLKOUTEN. When disabled the output is low. Note: this output is not affected by the various power save modes CLKOUTEN I B4 115 HI IOVDD Input Input This pin enables/disables the CLKOUT pin. 4.2.4 Miscellaneous Table 4-5: Miscellaneous Pin Descriptions Pin Name CNF[2:0] Type I FCBGA Pin # QFP Pin # H3,G3,F 85,86,91 3 Cell HI IO RESET# Voltage State IOVDD Input Power Save Status Input Description These inputs are used for power-up configuration. For details, see Section 4.3, "Summary of Configuration Options" on page 18. Note: These pins must be connected directly to IOVDD or VSS. TESTEN GPIO[7:0] PWRSVE I IO I E3 96 K3,K2, 71,79,81, J2,J1, 82,84,83, H2,H1,G 87,88 2, G1 J3 80 LIDS HBD HI IOVDD IOVDD IOVDD S1D13742 X63A-A-001-06 -- -- L Pull Down Active Input Input Test Enable input used for production test only This pin should be left unconnected for normal use. These pins are general purpose input/output pins. These pins have internal pull-down resistors which can be controlled using REG[64h]. This pin enables/disables the Standby Power Save Mode When unused this pin must be connected to VSS. Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 17 Table 4-5: Miscellaneous Pin Descriptions (Continued) Pin Name TEST[2:0] SCANEN VCP NC Type I I I -- FCBGA Pin # QFP Pin # E2,E1,F1 94,93,92 F2 D5 95 Cell HID HID 122 1,2,3, A1,A2, 35,36, A10,A11, 37,72, B1,B11, 73,74, E9,K1,K 75,76, 11,L1,L2, 106,107, L10,L11 108 IO RESET# Voltage State IOVDD IOVDD -- -- Power Save Status Description -- These are Test Function pins and are used for production test only. These pins should be left unconnected for normal operation. -- This is the Test Scan Enable input and is used for production test only. This pin should be left unconnected for normal operation. LITR PLLVDD -- -- This is the PLL VCP Test pin and is used for production test only. This pin should be left unconnected for normal operation. -- -- -- -- These pins are not connected. 4.2.5 Power And Ground Table 4-6: Power And Ground Pin Descriptions Pin Name Type FCBGA Pin # QFP Pin # Cell COREVDD P D7,E4,G7,H6 6,31,40,67,89, 104,117,134 P Core power supply IOVDD P C4,D8,H4 77,102,113, 120,128,143 P IO power supply for the host interface PIOVDD P E8,G4,H5,H7 4,17,20,33,38, 52,55,69 P IO power supply for the panel interface Description PLLVDD P D4 121 P PLL power supply PLLVSS P D6 123 P GND for PLL C5,C6,E5,E6, E7,F4, F5,F6, F7,G5,G6 5,7,18,21,32, 34,39,41,53, 56,68,70,78, 90,103,105, 112,116,119, 129, 135,144 P GND VSS P Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 18 Epson Research and Development Vancouver Design Center 4.3 Summary of Configuration Options These pins are used for power-up configuration and must be connected directly to IOVDD or VSS. The state of CNF[2:0] may be changed at any time. Table 4-7: Summary of Power-On/Reset Options Power-On/Reset State Configuration Input 1 (connected to IOVDD) 0 (Connected to VSS) CNF0 Host Data Lines are normal: If CNF1 = 1, then D15 = D15, etc. If CNF1 = 0, then D7 = D7, etc. Host Data Lines are swapped: If CNF1 = 1, then D15 = D0, etc. If CNF1 = 0, then D7 = D0, etc. CNF1 Host Data is 16-bit Host Data is 8-bit CNF2 PIOVDD output current (IOL2) = 6.5mA PIOVDD output current (IOL2) = 2.5mA Note When CNF1=0, all Register access is 8-bit only. When CNF1 =1 (16-bit): All Register access is 8-bit ONLY (the most significant byte on the data bus is ignored) except the Memory Data Port. Access to the Memory Data Port is 16-bit. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 19 5 Pin Mapping 5.1 Intel 80 Data Pins This function is controlled by CNF [1:0] Table 5-1: S1D13742B00 Intel 80 Data Pin Mapping Pin Name 8-Bit Data 8-Bit Data 16-Bit Data 16-Bit Data Swapped No Swap Swapped No Swap (CNF1=1, CNF0=1) (CNF1=1, CNF0=0) (CNF1=0, CNF0=1) (CNF1=0, CNF0=0) MD15 MD15 MD0 Pulled Low by Internal Resistor Pulled Low by Internal Resistor * * * * * * * * * * * * * * * MD8 MD8 MD7 Pulled Low by Internal Resistor Pulled Low by Internal Resistor MD7 MD7 MD8 MD7 MD0 * * * * * * * * * * * * * * * MD0 MD0 MD15 MD0 MD7 Table 5-2: S1D13742B01 Intel 80 Data Pin Mapping Pin Name 8-Bit Data 8-Bit Data 16-Bit Data 16-Bit Data Swapped No Swap Swapped No Swap (CNF1=1, CNF0=1) (CNF1=1, CNF0=0) (CNF1=0, CNF0=1) (CNF1=0, CNF0=0) MD15 MD15 MD0 Hi-Z Hi-Z * * * * * * * * * * * * * * * MD8 MD8 MD7 Hi-Z Hi-Z MD7 MD7 MD8 MD7 MD0 * * * * * * * * * * * * * * * MD0 MD0 MD15 MD0 MD7 Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 20 Epson Research and Development Vancouver Design Center 5.2 LCD Interface Pin Mapping Table 5-3: LCD Interface Pin Mapping for Mode 1 and Mode 2 Pin Name VS HS PCLK DE VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VD16 VD17 VD18 VD19 VD20 VD21 VD22 VD23 VD24 VD25 VD26 VD27 VD28 VD29 VD30 VD31 VD32 VD33 VD34 VD35 16bpp Single (18-bit) Normal Swap B4 B0 B1 B2 B3 B4 G0 G1 G2 G3 G4 G5 R4 R0 R1 R2 R3 R4 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 R4 R3 R2 R1 R0 R4 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 B4 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 18bpp Double (36-bit) Single (18-bit) Double (36-bit) Normal Swap Normal Swap Normal Swap Vertical Sync Horizontal Sync Pixel Clock Data Enable B4 R4 B0 R5 B0 R5 B0 R3 B1 R4 B1 R4 B1 R2 B2 R3 B2 R3 B2 R1 B3 R2 B3 R2 B3 R0 B4 R1 B4 R1 B4 R4 B5 R0 B5 R0 G0 G5 G0 G5 G0 G5 G1 G4 G1 G4 G1 G4 G2 G3 G2 G3 G2 G3 G3 G2 G3 G2 G3 G2 G4 G1 G4 G1 G4 G1 G5 G0 G5 G0 G5 G0 R4 B4 R0 B5 R0 B5 R0 B3 R1 B4 R1 B4 R1 B2 R2 B3 R2 B3 R2 B1 R3 B2 R3 B2 R3 B0 R4 B1 R4 B1 R4 B4 R5 B0 R5 B0 B4 R4 driven 0 driven 0 B0 R5 B0 R3 driven 0 driven 0 B1 R4 B1 R2 driven 0 driven 0 B2 R3 B2 R1 driven 0 driven 0 B3 R2 B3 R0 driven 0 driven 0 B4 R1 B4 R4 driven 0 driven 0 B5 R0 G0 G5 driven 0 driven 0 G0 G5 G1 G4 driven 0 driven 0 G1 G4 G2 G3 driven 0 driven 0 G2 G3 G3 G2 driven 0 driven 0 G3 G2 G4 G1 driven 0 driven 0 G4 G1 G5 G0 driven 0 driven 0 G5 G0 R4 B4 driven 0 driven 0 R0 B5 R0 B3 driven 0 driven 0 R1 B4 R1 B2 driven 0 driven 0 R2 B3 R2 B1 driven 0 driven 0 R3 B2 R3 B0 driven 0 driven 0 R4 B1 R4 B4 driven 0 driven 0 R5 B0 S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 21 5.3 LCD Interface Data Pins This function is controlled by REG[14h] bit 7. Table 5-4: LCD Interface Data Pin Mapping Pin Name 36-Bit Data No Swap REG[14] b7=0 36-Bit Data Swapped REG[14] b7=1 18-Bit Data No Swap REG[14] b7=0 18-Bit Data Swapped REG[14] b7=1 VD35 VD35 VD0 Driven Low Driven Low * * * * * * * * * * * * * * * VD18 VD18 VD17 Driven Low Driven Low VD17 VD17 VD18 VD17 VD0 * * * * * * * * * * * * * * * VD0 VD0 VD35 VD0 VD17 Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 22 Epson Research and Development Vancouver Design Center 6 D.C. Characteristics 6.1 Absolute Maximum Ratings Table 6-1: Absolute Maximum Ratings Symbol Parameter Rating Units Core VDD Core Supply Voltage VSS - 0.3 ~ 2.0 V PLL VDD PLL Supply Voltage VSS - 0.3 ~ 2.0 V IO VDD Host IO Supply Voltage COREVDD ~ 4.0 V PIO VDD Panel IO Supply Voltage COREVDD ~ 4.0 V VIN Input Signal Voltage VSS - 0.3 ~ IOVDD + 0.3 V VOUT Output Signal Voltage VSS - 0.3 ~ IOVDD + 0.3 V IOUT Output Signal Current 10 mA 6.2 Recommended Operating Conditions Table 6-2: Recommended Operating Conditions Symbol Parameter Condition Min Typ Max Units Core VDD Core Supply Voltage VSS = 0 V 1.40 1.50 1.60 V PLL VDD PLL Supply Voltage VSS = 0 V 1.40 1.50 1.60 V IO VDD Host IO Supply Voltage VSS = 0 V 1.65 -- 3.6 V PIO VDD Panel IO Supply Voltage VSS = 0 V 1.65 -- 3.6 V VIN Input Voltage -- VSS -- IOVDD V TOPR Operating Temperature -- -40 +25 +85 C Note There are no special Power On/Off requirements with respect to sequencing the various VDD pins. There are also no special requirements for the IO signals, however Inputs should not be floating. If the input signals were to power up in a valid cycle, the S1D13742 would decode the cycle. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 23 6.3 Electrical Characteristics The following characteristics are for: IOVDD. VSS = 0V, TOPR = -40 to +85C. Table 6-3: Electrical Characteristics for IOVDD or PIOVDD = 1.8V 0.15V Symbol Parameter Condition Min Typ Max Units -- 100 -- A IQALL Quiescent Current CLKI stopped (grounded), Sleep Mode enabled, all power supplies active IPLL PLL Current fPLL = 54MHz -- 500 1000 A ICORE Operation Peak Current COREVDD Power Pin -- -- 62 mA PCORE Core Typical Operating Power -- 9.15 -- mW PPLL PLL Typical Operating Power -- 0.7 -- mW PPIO PIO Typical Operating Power PHIO HIO Typical Operating Power see Note 1 -- 2.8 -- mW -- 0.018 -- mW PCORE Core Typical Operating Power -- 10.9 -- mW PPLL PLL Typical Operating Power -- 0.77 -- mW PPIO PIO Typical Operating Power PHIO HIO Typical Operating Power IIZ Input Leakage Current -- -5 IOZ Output Leakage Current -- -5 IOVOH2 High Level Output Voltage IOVDD = min IOH2 = -2.5mA IOVDD - 0.40 PIOVOH2 High Level Output Voltage PIOVDD = min IOH2 = -2.5mA PIOVOH4 High Level Output Voltage PIOVDD = min IOH2 = -6.5mA IOVOL2 Low Level Output Voltage PIOVOL2 see Note 2 -- 2.124 -- mW -- 0.001 -- mW -- 5 A -- 5 A -- IOVDD V PIOVDD - 0.40 -- PIOVDD V PIOVDD - 0.40 -- PIOVDD V IOVDD = min IOL2 = 2.5mA VSS -- 0.40 V Low Level Output Voltage PIOVDD = min IOL2 = 2.5mA VSS -- 0.40 V PIOVOL4 Low Level Output Voltage PIOVDD = min IOL2 = 6.5mA VSS -- 0.40 V IOVIH High Level Input Voltage CMOS Input 1.27 -- -- V PIOVIH High Level Input Voltage CMOS Input 1.27 -- -- V IOVIL Low Level Input Voltage CMOS Input -- -- 0.57 V PIOVIL Low Level Input Voltage CMOS Input -- -- 0.57 V IOVT+ Positive Trigger Voltage CMOS Schmitt 0.57 -- 1.56 V IOVT- Negative Trigger Voltage CMOS Schmitt 0.33 -- 1.27 V IO VH Hysteresis Voltage CMOS Schmitt 0.24 -- -- V RPU1 Pull-Up Resistance Type1 VI = VSS 40 100 240 k RPD1 Pull-Down Resistance Type1 VI = VDD 40 100 240 k RPU2 Pull-Up Resistance Type2 VI = VSS 80 200 480 k RPD2 Pull-Down Resistance Type2 VI = VDD 80 200 480 k CIO Pin Capacitance f = 1MHz, VDD = 0V -- -- 8 pF Note 1. Typical Operating Current Environment: 352x416 K2 TFT panel with PCLK divide by 4. SYSCLK=48.5MHz from PLL, PLL Source from 19.2MHz CLKI input. 18bpp memory storage. COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 1.8V 2. Typical Operating Current Environment: 800 x 480 TFT panel with PCLK divide by 3. SYSCLK= 59MHz from PLL, PLL Source from 12MHz CLKI input. 16bpp memory storage. COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 1.8V Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 24 Epson Research and Development Vancouver Design Center The following characteristics are for: IOVDD. VSS = 0V, TOPR = -40 to +85C. Table 6-4: Electrical Characteristics for IOVDD or PIOVDD = 2.8V 0.14V Symbol Parameter Condition Min Typ Max Units -- 120 -- A 500 1000 A IQALL Quiescent Current CLKI stopped (grounded), Sleep Mode enabled, all power supplies active IPLL PLL Current fPLL = 54MHz -- ICORE Operation Peak Current COREVDD Power Pin -- -- 62 mA IIZ Input Leakage Current -- -5 -- 5 A IOZ Output Leakage Current -- -5 -- 5 A IOVOH2 High Level Output Voltage IOVDD = min IOH2 = -3.6mA IOVDD - 0.40 -- IOVDD V PIOVOH2 High Level Output Voltage PIOVDD = min IOH2 = -3.6mA PIOVDD 0.40 -- PIOVDD V PIOVOH4 High Level Output Voltage PIOVDD = min IOH2 = -10.8mA PIOVDD 0.40 -- PIOVDD V IOVOL2 Low Level Output Voltage IOVDD = min IOL2 = 3.6mA VSS -- 0.40 V PIOVOL2 Low Level Output Voltage PIOVDD = min IOL2 = 3.6mA VSS -- 0.40 V PIOVOL4 Low Level Output Voltage PIOVDD = min IOL2 = 10.8mA VSS -- 0.40 V IOVIH High Level Input Voltage CMOS Input 1.75 -- -- V PIOVIH High Level Input Voltage CMOS Input 1.75 -- -- V IOVIL Low Level Input Voltage CMOS Input -- -- 0.70 V PIOVIL Low Level Input Voltage CMOS Input -- -- 0.70 V IOVT+ Positive Trigger Voltage CMOS Schmitt 0.93 -- 2.36 V IOVT- Negative Trigger Voltage CMOS Schmitt 0.53 -- 1.92 V IO VH Hysteresis Voltage CMOS Schmitt 0.40 -- -- V RPU1 Pull-Up Resistance Type1 VI = VSS 24 60 144 k RPD1 Pull-Down Resistance Type1 VI = VDD 24 60 144 k RPU2 Pull-Up Resistance Type2 VI = VSS 48 120 288 k RPD2 Pull-Down Resistance Type2 VI = VDD 48 120 288 k CIO Pin Capacitance -- -- 8 pF f = 1MHz, VDD = 0V Note 1. Typical Operating Current Environment: 352x416 K2 TFT panel with PCLK divide by 4. SYSCLK=48.5MHz from PLL, PLL Source from 19.2MHz CLKI input. 18bpp memory storage. COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 2.8V 2. Typical Operating Current Environment: 800 x 480 TFT panel with PCLK divide by 3. SYSCLK= 59MHz from PLL, PLL Source from 12MHz CLKI input. 16bpp memory storage. COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 2.8V S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 25 The following characteristics are for: IOVDD, VSS = 0V, TOPR = -40 to +85C. Table 6-5: Electrical Characteristics for IOVDD or PIOVDD = 3.3V 0.3V Min Typ Max Units IQALL Symbol Quiescent Current Parameter Quiescent Conditions Condition -- 160 -- A IPLL PLL Current fPLL = 54MHz -- 500 1000 A ICORE Operation Peak Current COREVDD Power Pin -- -- 62 mA IIZ Input Leakage Current -- -5 -- 5 A IOZ Output Leakage Current -- -5 -- 5 A IOVOH2 High Level Output Voltage IOVDD = min IOH2 = -4.0mA IOVDD - 0.40 -- IOVDD V PIOVOH2 High Level Output Voltage PIOVDD = min IOH2 = -4.0mA PIOVDD 0.40 -- PIOVDD V PIOVOH4 High Level Output Voltage PIOVDD = min IOH2 = -12.0mA PIOVDD 0.40 -- PIOVDD V IOVOL2 Low Level Output Voltage IOVDD = min IOL2 = 4.0mA VSS -- 0.40 V PIOVOL2 Low Level Output Voltage PIOVDD = min IOL2 = 4.0mA VSS -- 0.40 V PIOVOL4 Low Level Output Voltage PIOVDD = min IOL2 = 12.0mA VSS -- 0.40 V IOVIH High Level Input Voltage CMOS Input 2.20 -- -- V PIOVIH High Level Input Voltage CMOS Input 2.20 -- -- V IOVIL Low Level Input Voltage CMOS Input -- -- 0.80 V PIOVIL Low Level Input Voltage CMOS Input -- -- 0.80 V IOVT+ Positive Trigger Voltage CMOS Schmitt 1.40 -- 2.70 V IOVT- Negative Trigger Voltage CMOS Schmitt 0.60 -- 1.80 V IO VH Hysteresis Voltage CMOS Schmitt 0.45 -- -- V RPU1 Pull-Up Resistance Type1 VI = VSS 20 50 120 k RPD1 Pull-Down Resistance Type1 VI = VDD 20 50 120 k RPU2 Pull-Up Resistance Type2 VI = VSS 40 100 240 k RPD2 Pull-Down Resistance Type2 VI = VDD 40 100 240 k CIO Pin Capacitance f = 1MHz, VDD = 0V -- -- 8 pF Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 26 Epson Research and Development Vancouver Design Center 7 A.C. Characteristics Conditions: IOVDD = PIOVDD = 1.8V 0.15V or 2.8V 0.14V TA = -40 C to 85 C Trise and Tfall for all inputs except Schmitt and CLKI must be < 50 ns (10% ~ 90%) Trise and Tfall for all Schmitt must be < 5 ms (10% ~ 90%) CL = 8pF ~ 30pF (MD[15:0]) CL = 15pF (TE, GPIO_INT, CLKOUT) CL = 30pF (LCD Panel/GPIO Interface) 7.1 Clock Timing 7.1.1 Input Clocks t1 t2 90% VIH CLKI VIL 10% t4 t3 tOSC t5 tOSC tOSC CLKI Figure 7-1 Clock Input Required (CLKI) S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 27 Table 7-1 Clock Input Requirements (CLKI) Symbol Parameter Input clock frequency - PLL used for System Clock fOSC (see note 6) Input clock frequency - CLKI used for System Clock Input clock period tOSC t1 Input clock pulse width high t2 Input clock pulse width low t3 Input clock rise time (10% - 90%) t4 Input clock fall time (90% - 10%) t5 Input clock period jitter (see notes 2 and 4) t6 Input clock cycle jitter (see notes 3 and 4) (see note 1) Min 1 0 -- 0.4tOSC 0.4tOSC -- -- -300 -300 Typ -- -- 1/fOSC -- -- -- -- Max 66 68.90 -- 0.6tOSC 0.6tOSC 5.0 5.0 300 Units MHz MHz s s s ns ns ps 300 ps 1. t6 = 2*tOSC 2. The input clock period jitter is the displacement relative to the center period (reciprocal of the center frequency). 3. The input clock cycle jitter is the difference in period between adjacent cycles. 4. The jitter characteristics must satisfy both the t5 and t6 characteristics 5. Input Duty cycle is not critical and can be 40/60 6. The minimum System Clock frequency required for correct operation depends on the cycle length of the Intel 80 interface. See Section 8.4, "Setting SYSCLK and PCLK" on page 43 for more details. 7.1.2 PLL Clock The PLL circuit is an analog circuit and is very sensitive to noise on the input clock waveform or the power supply. Noise on the clock or the supplied power may cause the operation of the PLL circuit to become unstable or increase the jitter. Due to these noise constraints, it is highly recommended that the power supply traces or the power plane for the PLL be isolated from those of other power supplies. Filtering should also be used to keep the power as clean as possible. The jitter of the input clock waveform should be as small as possible. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 28 Epson Research and Development Vancouver Design Center PLL Enable 10 ms Lock In Time PLL Stable MHz Reference Clock PLL xxMHz Output (xx = 44.26~66.95MHz) Jitter (ns) Lock in time 10 ms Time (ms) The PLL frequency will ramp between the OFF state and the programmed frequency. To guarantee the lowest possible clock jitter, 10ms is required for stabilization. Note: PLL minimum frequency = 44.26MHz (Based on Intel 80 cycle length. Refer to Section 8.4 for more information) PLL maximum frequency = 66.95MHz Figure 7-2: PLL Start-Up Time Table 7-2: PLL Clock Requirements Symbol 1 Parameter fPLL PLL output clock frequency Min Max Units 44.261 66.95 MHz tPJref PLL output clock period jitter -3 3 % tPDuty PLL output clock duty cycle 40 60 % tPStal PLL output stable time 10 ms Refer to Section 8.4, "Setting SYSCLK and PCLK" on page 43. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 29 7.2 RESET# Timing t1 RESET# tCLKI CLKI Figure 7-3 S1D13742 RESET# Timing Table 7-3 S1D13742 RESET# Timing Symbol t1 Parameter Active Reset Pulse Width Hardware Functional Specification Issue Date: 2008/07/07 Min Max Units 1 -- CLKI S1D13742 X63A-A-001-06 Revision 6.2 Page 30 Epson Research and Development Vancouver Design Center 7.3 Host interface Timing 7.3.1 Intel 80 Interface Timing - 1.8 Volt D/C# (Note 1) twcs twah tast tcsf tch CS# (Note 2) tcsf twl twh tch twc WE# tr2w tw2r tdst MD[15:0] write (Note 3) tdht trcs trah trc trl RD# trh trodh trdd MD[15:0] read (Note 3) trdv trrdz tcodh tcrdz Note 1: The D/C# input pin is used to distinguish between Address and Data. Note 2: The CS# pin can be kept low between write and read pulses as the register addresses will auto-increment. The register address will auto-increment in word increments for all register access except the Memory Data Port. Writes to the Memory Data Port will not increment the register address to support burst data writes to memory. Note 3: When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[15:0] are used for accesses to the Memory Data Port. MD[7:0] are used for all other accesses. Figure 7-4: Intel 80 Input A.C. Characteristics - 1.8 Volt S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 31 Table 7-4: Intel 80 Input A.C. Characteristics - 1.8 Volt Signal D/C# CS# Symbol Min Max Unit tast Address setup time (read/write) 1 -- ns twah Address hold time (write) 5 -- ns trah Address hold time (read) 29 -- ns twcs Chip Select setup time (write) twl -- ns trcs Chip Select setup time (read) trl -- ns tch Chip Select hold time (read/write) 0 -- ns tcsf Chip Select Wait time (read/write) 1 -- ns Register Write cycle 12 -- ns LUT write cycle 2SYSCLK + 1 -- ns Memory write cycle 2SYSCLK + 1 -- ns twl Pulse low duration 5 -- ns twc WE# RD# Parameter Description twh Pulse high duration twc - twl -- ns tw2r WR# rising edge to RD# falling edge 11 -- ns Note 1 tr2w RD# rising edge to WR# falling edge 26 -- ns Note 2 trc Read cycle trl + trh -- ns trl Pulse low duration trdv -- ns Pulse high duration for Registers 35 -- ns trh 1SYSCLK + 26 -- ns tdst Write data setup time 4 -- ns tdht Write data hold time 5 -- ns trodh Read data hold time from RD# rising edge 11 -- ns trrdz RD# rising edge to MD Hi-Z -- 31 ns tcodh Read data hold time from CS# rising edge 1 -- ns tcrdz CS# rising edge to MD Hi-Z -- 8 ns RD# falling edge to MD valid for Registers -- 16 ns RD# falling edge to MD valid for LUT -- 4SYSCLK + 26 ns RD# falling edge to MD valid for Memory -- 5SYSCLK + 19 ns RD# falling edge to MD valid for Registers -- 11 ns RD# falling edge to MD valid for LUT -- 4SYSCLK + 21 ns RD# falling edge to MD valid for Memory -- 5SYSCLK + 14 ns RD# falling edge to MD driven 4 -- ns CL=30pF RD# falling edge to MD driven 3 -- ns CL = 8pF MD[15:0] (Note 3) trdv trdd Pulse high duration for Memory and LUT CL=30pF CL = 8pF Note 1. For a read cycle after a write cycle, MD[15:0] must be driven Hi-Z a maximum of trdd after the falling edge of RD#. 2. For a write cycle after a read cycle, MD[15:0] should not be driven by the host until trrdz after the rising edge of RD#. 3. When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[7:0] are used for all accesses except for the Memory Data Port when MD[15:0] are used. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 32 Epson Research and Development Vancouver Design Center 7.3.2 Intel 80 Interface Timing - 3.3 Volt D/C# (Note 1) twcs twah tast tcsf tch CS# (Note 2) tcsf twl twh tch twc WE# tr2w tw2r tdst MD[15:0] write (Note 3) tdht trcs trah trc trl RD# trh trdd MD[15:0] read (Note 3) trdv trodh trrdz tcodh tcrdz Note 1: The D/C# input pin is used to distinguish between Address and Data. Note 2: The CS# pin can be kept low between write and read pulses as the register addresses will auto-increment. The register address will auto-increment in word increments for all register access except the Memory Data Port. Writes to the Memory Data Port will not increment the register address to support burst data writes to memory. Note 3: When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[15:0] are used for accesses to the Memory Data Port. MD[7:0] are used for all other accesses. Figure 7-5: Intel 80 Input A.C. Characteristics - 3.3 Volt S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 33 Table 7-5: Intel 80 Input A.C. Characteristics - 3.3 Volt Signal D/C# CS# Symbol Min Max Unit tast Address setup time (read/write) 1 -- ns twah Address hold time (write) 5 -- ns trah Address hold time (read) 29 -- ns twcs Chip Select setup time (write) twl -- ns trcs Chip Select setup time (read) trl -- ns tch Chip Select hold time (read/write) 0 -- ns tcsf Chip Select Wait time (read/write) 1 -- ns Register Write cycle 12 -- ns LUT write cycle 2SYSCLK + 1 -- ns Memory write cycle 2SYSCLK + 1 -- ns twl Pulse low duration 5 -- ns twc WE# RD# Parameter Description twh Pulse high duration twc - twl -- ns tw2r WR# rising edge to RD# falling edge 16 -- ns Note 1 tr2w RD# rising edge to WR# falling edge 26 -- ns Note 2 trc Read cycle trl + trh -- ns trl Pulse low duration trdv -- ns Pulse high duration for Registers 36 -- ns ns trh 1SYSCLK + 26 -- tdst Write data setup time 4 -- ns tdht Write data hold time 5 -- ns trodh Read data hold time from RD# rising edge 11 -- ns trrdz RD# rising edge to MD Hi-Z -- 31 ns tcodh Read data hold time from CS# rising edge 1 -- ns tcrdz CS# rising edge to MD Hi-Z -- 8 ns RD# falling edge to MD valid for Registers -- 11 ns RD# falling edge to MD valid for LUT -- 4SYSCLK + 21 ns RD# falling edge to MD valid for Memory -- 5SYSCLK + 14 ns RD# falling edge to MD valid for Registers -- 9 ns RD# falling edge to MD valid for LUT -- 4SYSCLK + 18 ns RD# falling edge to MD valid for Memory -- 5SYSCLK + 11 ns RD# falling edge to MD driven 3 -- ns CL=30pF RD# falling edge to MD driven 2 -- ns CL = 8pF MD[15:0] (Note 3) trdv trdd Pulse high duration for Memory and LUT CL=30pF CL = 8pF Note 1. For a read cycle after a write cycle, MD[15:0] must be driven Hi-Z a maximum of trdd after the falling edge of RD#. 2. For a write cycle after a read cycle, MD[15:0] should not be driven by the host until trrdz after the rising edge of RD#. 3. When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[7:0] are used for all accesses except for the Memory Data Port when MD[15:0] are used. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 34 Epson Research and Development Vancouver Design Center 7.3.3 Definition of Transition Time to Hi-Z State Due to the difficulty of Hi-Z impedance measurement for high speed signals, transition time from High/Low to Hi-Z specified as follows. * High to Hi-Z delay time: tpHZ, delay time when a gate voltage of final stage of the Pch-MOSFET turns to 0.8 x IOVDD (Pch-MOSFET is off). Total delay time to Hi-Z is calculated as follows: Internal logic delay + tpHZ (from High to Hi-Z) * Low to Hi-Z delay time: tpLZ, delay time when a gate voltage of final stage of the NchMOSFET turns to 0.2 x IOVDD (Nch-MOSFET is off). Total delay time to Hi-Z is calculated as follows: Internal logic delay + tpHZ (from High to Hi-Z) The functional model of a final stage of the Tri state Output Cell is shown in Figure 7-6: "Definition of transition time to Hi-Z state". to measure tpHZ Tri state Output Cell P IOVDD EN X A VSS N to measure tpLZ Volt Volt IOVDD 0.8 IOVDD P EN 1/2IOVDD IOVDD 0.2 IOVDD N EN 1/2IOVDD Time Time tpHZ tpLZ Figure 7-6: Definition of Transition Time to Hi-Z State S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 35 7.4 Display Interface The timing parameters required to drive a flat panel display are shown below. Timing details for each supported panel type are provided in the remainder of this section. Note All timing measurements are taken to/from the 1/2PIOVDD level in the following Display Interface timing diagrams. HT TE HNDP DE HDISP DE TE HPS HSW VDISP VDISP HDISP VPS VNDP VSW Figure 7-7: Panel Timing Parameters Table 7-6: Panel Timing Parameter Definition and Register Summary Symbol HDISP Description Derived From Horizontal Display Width (REG[16h] bits 6-0) x 8 HNDP Horizontal Non-Display Period (REG[18h] bits 6-0) HPS HS Pulse Start Position REG[22h] bits 6-0 HSW HS Pulse Width (REG[20h] bits 6-0) VDISP Vertical Display Height (REG[1Ch] bits 1-0, REG[1Ah] bits 7-0) VNDP Vertical Non-Display Period REG[1Eh] bits 7-0 VPS VS Pulse Start Position REG[26h] bits 7-0 VSW VS Pulse Width REG[24h] bits 6-0 Units Ts Lines (HT) Note TS = 1/PCLK Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 36 Epson Research and Development Vancouver Design Center 7.4.1 TFT Power-On Sequence t1 Power Save Mode Enable** (REG[56h] bits 1-0) LCD Signals*** **The LCD power-on sequence is activated by programming the Power Save Register (REG[56h]) bit 1 or bit 0 to 0. ***LCD Signals include: VD[35:0], PCLK, HS, VS, and DE. Figure 7-8: TFT Power-On Sequence Timing Table 7-7: TFT Power-On Sequence Timing Symbol t1 Parameter Power Save Mode disabled to LCD signals active S1D13742 X63A-A-001-06 Min Max Units 0 20 ns Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 37 7.4.2 TFT Power-Off Sequence Power Save Mode Enable** (REG[56h] bits 1-0) t1 LCD Signals*** **The LCD power-off sequence is activated by programming the Power Save Register (REG[56h]) bit 1 or bit 0 to 1. ***LCD Signals include: VD[35:0], PCLK, HS, VS, and DE. Figure 7-9: TFT Power-Off Sequence Timing Table 7-8: TFT Power-Off Sequence Timing Symbol t1 Parameter Power Save Mode enabled to LCD signals low Hardware Functional Specification Issue Date: 2008/07/07 Min Max Units 0 20 ns S1D13742 X63A-A-001-06 Revision 6.2 Page 38 Epson Research and Development Vancouver Design Center 7.4.3 18/36-Bit TFT Panel Timing t1 t2 VS t3 HS t17 t18 DE t4 HS t5 t8 t7 t6 DE t9 t12 t10 t11 t13 t14 t13 t14 PCLK REG[28h] b7=1 t9 t12 t10 t11 PCLK REG[28h] b7=0 t15 t16 invalid VD[17:0] 2 320 invalid 3-4 n+1 invalid 1 Note: 1 pixel/clock Mode invalid VD[35:0] 1-2 Note: 2 pixels/clock Mode Figure 7-10: 18/36-Bit TFT A.C. Timing Note HS, VS, PCLK all have Polarity Select bits via registers S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 39 Table 7-9: 18/36-Bit TFT A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 1. Ts Parameter VS cycle time VS pulse width low VS falling edge to HS falling edge phase difference HS cycle time HS pulse width low HS Falling edge to DE active DE pulse width DE falling edge to HS falling edge PCLK period PCLK pulse width low PCLK pulse width high HS setup to PCLK active edge DE to PCLK rising edge setup time DE hold from PCLK active edge Data setup to PCLK active edge Data hold from PCLK active edge DE Stop setup to VS start Vertical Non-Display Period Min -- -- -- -- -- -- -- -- 1 0.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- Typ VDISP + VNDP VSW HPS HDISP + HNDP HSW HNDP-HPS HDISP HPS -- -- -- -- -- -- -- -- VPS VNDP Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Units Lines Lines Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts = pixel clock period Note In 36-bit mode, the data is always guaranteed to be launched on the correct edge of PCLK. In this mode, the frequency of PCLK is 1/2 the programmed internal value. If it is desired that HS and VS are always launched on the same edge of PCLK as the data, then HNDP, HSW, and HSS should be programmed with even values. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 40 Epson Research and Development Vancouver Design Center 8 Clocks 8.1 Clock Descriptions Internal PLL Enable Clock Source Select (REG[12h] bit 0) Glitch Free PLL 1 MHz 0 SYSCLK CLKI External Clock Source Divider 1 2 3 Internal PCLK ** * 32 CLKOUTEN /2 PCLK Divide Select (REG[12h] bits 7-3) CLKOUT 1 0 External PCLK Panel Data Width Select (REG[14h] bit 0) Figure 8-1: S1D13742 Clock Block Diagram S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 41 8.2 PLL Block Diagram VCP VC REG[0Ah] CP REG[08h] REG[04h] AMON CLKI M-Divider PLLCLK PFD CP VCO RS REG[0Ah] CS REG[0Ch] Loop Filter MUX TCK REG[08h] REG[0Eh] V-Divider L-Counter N-Counter MUX Where: PFD = Phase Frequency Detector CP = Charge Pump VCO = Voltage Controlled Oscillator Loop Filter = Low Pass Filter TEST Control = Internal Control Logic SYSCLK REFCK MUX 1/32 TOUT Figure 8-2: PLL Block Diagram Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 42 Epson Research and Development Vancouver Design Center 8.3 Clocks versus Functions This table lists the internal clocks required for the following S1D13742 functions. Internal Clock Requirements Function Internal SYSCLK Internal PCLK Register Read/Write No No Memory Read/Write Yes No Look-Up Table Register Read/Write Yes No Power Save No No LCD Output Yes Yes Note Register access does not require an internal clock as the S1D13742 creates a clock from the bus cycle alone. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 43 8.4 Setting SYSCLK and PCLK The period of the system clock, TSYSCLK, must be set such that it falls within the following range: For PLL: For CLKI: 14.94ns < TSYSCLK < (TBBC - 0.914) x 0.485 ns 14.50ns < TSYSCLK < (TBBC - 0.914) x 0.5ns where TBBC is the minimum back-to-back cycle time of the Intel 80 Interface. For example, if the minimum back-to-back cycle time of the Intel 80 Interface is 5 x 9.5 = 47.5ns, then: For PLL: For CLKI: 14.94ns < TSYSCLK < 22.594ns 14.50ns < TSYSCLK < 23.293ns Therefore, For PLL: For CLKI: 44.26MHz < fSYSCLK < 66.95MHz 42.94MHz < fSYSCLK < 68.96MHz SYSCLK Frequency (MHz) Care should be taken when setting TSYSCLK so that the desired PCLK frequency, fPCLK, can be achieved. PCLK is an integer divided version of SYSCLK. The following graph shows the suggested setting for SYSCLK for a given value of PCLK for TBBC = 47.5ns. 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 SysClk/3 SysClk/4 SysClk/5 SysClk/6 SysClk/7 SysClk/2 6 8 10 12 14 16 18 20 22 24 26 PCLK Frequency (MHz) Figure 8-3: Setting of SYSCLK For a Desired PCLK Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 44 Epson Research and Development Vancouver Design Center 9 Registers This section discusses how and where to access the S1D13742 registers. It also provides detailed information about the layout and usage of each register. Burst data writes to the register space is supported. This applies to all register write access except the Memory Data Port (REG[48h - 49h]) and the Gamma Correction Table Data Register [REG[54h]). All writes to these two registers will auto-increment the internal memory address only. 9.1 Register Mapping All registers and memory are accessed via the Intel 80 interface. All access is 8-bit only except for the Memory Data Port (REG[48h - 49h]) which is accessed as 16-bit (if CNF1=1) or 8-bit (if CNF1=0). S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 45 9.2 Register Set The S1D13742 registers are listed in the following table. Table 9-1: S1D13742 Register Set Register Pg Read-Only Configuration Registers REG[00h] Revision Code Register 46 Register Pg REG[02h] Configuration Readback Register 46 Clock Configuration Registers REG[04h] PLL M-Divider Register 47 REG[06h] PLL Setting Register 0 REG[08h] PLL Setting Register 1 48 REG[0Ah] PLL Setting Register 2 48 REG[0Ch] PLL Setting Register 3 49 REG[0Eh] PLL Setting Register 4 49 49 REG[12h] Clock Source Select Register 50 REG[10h] 48 Panel Configuration Registers REG[14h] Panel Type Register 52 REG[16h] Horizontal Display Width Register (HDISP) REG[18h] Horizontal Non-Display Period Register (HNDP) 52 REG[1Ah] Vertical Display Height Register 0 (VDISP) 52 53 REG[1Ch] Vertical Display Height Register 1 (VDISP) 53 REG[1Eh] Vertical Non-Display Period Register (VNDP) 53 REG[20h] HS Pulse Width Register (HSW) 53 REG[22h] HS Pulse Start Position Register 0 (HPS) 54 REG[24h] VS Pulse Width Register (VSW) 54 REG[26h] VS Pulse Start Position Register 0 (VPS) 54 REG[28h] PCLK Polarity Register 54 Input Mode Register REG[2Ah] Input Mode Register 55 REG[2Ch] Input YUV/RGB Translate Mode Register 0 57 REG[2Eh] YUV/RGB Translate Mode Register 1 57 REG[30h] U Data Fix Register 59 REG[32h] V Data Fix Register 59 Display Mode Registers REG[34h] Display Mode Register 60 REG[36h] Special Effects Register 61 Window Settings REG[38h] Window X Start Position Register 0 64 REG[3Ah] Window X Start Position Register 1 REG[3Ch] Window Y Start Position Register 0 64 REG[3Eh] Window Y Start Position Register 1 64 REG[40h] Window X End Position Register 0 65 REG[42h] Window X End Position Register 1 65 65 REG[46h] Window Y End Position Register 1 65 REG[44h] Window Y End Position Register 0 64 Memory Access REG[48h] Memory Data Port Register 0 66 REG[49h] Memory Data Port Register 1 66 REG[4Ah] Memory Read Address Register 0 67 REG[4Ch] Memory Read Address Register 1 67 REG[4Eh] Memory Read Address Register 2 67 Gamma Correction Registers REG[50h] Gamma Correction Enable Register 68 REG[54h] Gamma Correction Table Data Register 69 REG[52h] Gamma Correction Table Index Register 69 Miscellaneous Registers REG[56h] Power Save Register 70 REG[58h] Non-Display Period Control / Status Register 70 General Purpose IO Pins Registers REG[5Ah] General Purpose IO Pins Configuration Register 0 72 REG[5Ch] General Purpose IO Pins Status/Control Register 0 72 REG[5Eh] GPIO Positive Edge Interrupt Trigger Register 72 REG[60h] GPIO Negative Edge Interrupt Trigger Register 73 REG[62h] GPIO Interrupt Status Register 73 REG[64h] GPIO Pull Down Control Register 0 73 Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 46 Epson Research and Development Vancouver Design Center 9.3 Register Descriptions All reserved bits must be set to the default value. Writing a non-default value to a reserved bit may produce undefined results. Bits marked as n/a have no hardware effect. Unless specified otherwise, all register bits are set to 0 during power-on reset. 9.3.1 Read-Only Configuration Registers REG[00h] Revision Code Register Default = 80h for S1D13742B00 or 81h for S1D13742B01 Read Only Product Code bits 5-0 7 6 5 4 Revision Code bits 1-0 3 2 1 0 bits 7-2 Product Code bits [5:0] These are read-only bits that indicates the product code. The product code is 100000b. bits 1-0 Revision Code bits [1:0] These are read-only bits that indicates the revision code. The revision code for the S1D13742B00 is 00b, and for the S1D13742B01 is 01b. REG[02h] Configuration Readback Register Default = xxh Read Only n/a 7 bits 2-0 6 5 4 3 CNF2 Status CNF1 Status CNF0 Status 2 1 0 CNF[2:0] Status These read-only status bits return the status of the configuration pins CNF[2:0]. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 47 9.3.2 Clock Configuration Registers REG[04h] PLL M-Divider Register Default = 00h PLL Lock Bit (RO) n/a 7 6 Read/Write M-Divider bits 5-0 5 4 3 2 1 0 bit 7 PLL Lock Bit (read only) When this bit = 0, the PLL output is not stable. In this state R/W access to the display buffer is prohibited. When this bit = 1, the PLL output is stable. bits 5-0 M-Divider bits [5:0] These bits determine the divide ratio between CLKI and the actual input clock to the PLL Note The internal input clock to the PLL (PLLCLK) must be between 1 MHz and 2 MHz. Depending on CLKI, these bits will have to be set accordingly. Note Values higher then 20h are not allowed. Table 9-2: PLL M-Divide Selection REG[04h] bits 5-0 M-Divide Ratio 0h 1:1 01h 2:1 02h 3:1 03h 4:1 * * * * * * 20h 33:1 21h to 3Fh Reserved Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 48 Epson Research and Development Vancouver Design Center REG[06h] PLL Setting Register 0 Default = 00h Read/Write PLL Setting Register 0 bits 7-0 7 6 5 4 3 2 1 0 This register must be programmed with the value F8h. REG[08h] PLL Setting Register 1 Default = 00h Read/Write PLL Setting Register 1 bits 7-0 7 6 5 4 3 2 1 0 This register must be programmed with the value 80h. REG[0Ah] PLL Setting Register 2 Default = 00h Read/Write PLL Setting Register 2 bits 7-0 7 6 5 4 3 2 1 0 This register must be programmed with the value 28h. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 49 REG[0Ch] PLL Setting Register 3 Default = 00h Read/Write PLL Setting Register 3 bits 7-0 7 6 5 4 3 2 1 0 This register must be programmed with the value 00h. REG[0Eh] PLL Setting Register 4 Default = 00h Read/Write n/a L-Counter bits 6-0 7 6 bits 6-0 5 4 3 2 1 0 L-Counter bits [6:0] These bits are used to configure the PLL Output (in MHz) and must be set according to the following formula. PLL Output = (L-Counter +1) x PLLCLK = LL x PLLCLK Where: PLL Output is the desired PLL output frequency (in MHz). L-Counter is the value of this register (in decimal). PLLCLK is the internal input clock to the PLL (in MHz). Please refer to Section 8.4, "Setting SYSCLK and PCLK" on page 43 for restrictions on PLL Output frequencies. Table 9-3 PLL Setting Example Target Frequency (MHz) LL CLKI Input Clock (MHz) M-Divider REG[04] bits 5-0 M-Divide Ratio PLLCLK (MHz) POUT (MHz) 53 53 12 0Bh 12:1 1.0 53 60 60 12 0Bh 12:1 1.0 60 * * * * * * * 53 53 19.2 12h 19:1 1.0105 53.53 60 60 19.2 12h 19:1 1.0105 60.63 REG[10h] Default = 00h Read/Write n/a 7 6 5 4 3 2 1 0 Writes to this register have no effect on hardware. During Auto Increment, a dummy write needs to be performed to this register. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 50 Epson Research and Development Vancouver Design Center REG[12h] Clock Source Select Register Default = 00h Read/Write PCLK Divide Select bits 4-0 7 bits 7-3 6 5 SYSCLK Source Select n/a 4 3 2 1 0 PCLK Divide Select bits [5:0] These bits specify the divide ratio for the panel clock (PCLK). The clock source for PCLK is SYSCLK. All resulting clock frequencies will maintain a 50/50 duty cycle regardless of divide ratio. Table 9-4 PCLK Divide Ratio Selection REG[0012h] bits 7-3 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h * * * 1Fh S1D13742 X63A-A-001-06 PCLK Divide Ratio Reserved 2:1 3:1 4:1 5:1 6:1 7:1 8:1 9:1 10:1 11:1 12:1 13:1 14:1 15:1 16:1 17:1 18:1 * * * 32:1 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center bit 0 Page 51 SYSCLK Source Select This bit selects the system clock (SYSCLK) source for the controller. When this bit = 0, the SYSCLK source is the external CLKI input. When this bit = 1, the SYSCLK source is the internal PLL. If the PLL is selected as the SYSCLK source (bit 0 = 1), the PLL must be configured using REG[06h], REG[08h], REG[0Ah], REG[0Ch], REG[0Eh] and REG[10h] before setting this bit. Note To use PLL as system clock source (SYSCLK), Sleep Mode needs to be first enabled, REG[56h] bit 1 = 1. Once in Sleep Mode, REG[04h] and REG[0Eh] can be changed to set the desired PLL frequency. Once REG[04h] and REG[0Eh] have been set, REG[12h] bit 0 can be set to 1b to select PLL as the system clock source. The PLL output will only be active after exiting the Sleep Mode (REG[56h] bit 1 = 0). The PLL output will become stable after 10msec. The display memory or the Gamma Correction Table must not be accessed before this time. REG[04h] bit 7, the PLL Lock Bit, can be used to determine if the PLL output is stable. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 52 Epson Research and Development Vancouver Design Center 9.3.3 Panel Configuration Registers REG[14h] Panel Type Register Default = 00h Read/Write VD Data Swap 7 n/a 6 bit 7 5 4 Panel Data Width 3 2 1 0 VD Data Swap When this bit = 0, data lines are normal (i.e.: output pin VD35 = VD35, etc.) When this bit = 1, data lines are swapped (i.e.: output pin VD35 = VD0, etc.) Note The Data swap will always go from the msb to the lsb on the active output pins. See "LCD Interface Data Pins" on page 21. bit 0 Panel Data Width When this bit = 0, the LCD interface is configured as 18-bit. When this bit = 1, the LCD interface is configured as 36-bit. REG[16h] Horizontal Display Width Register (HDISP) Default = 01h n/a 7 Read/Write Horizontal Display Period bits 6-0 6 bits 6-0 5 4 3 2 1 0 Horizontal Display Width bits [6:0] These bits specify the LCD panel Horizontal Display Width (HDISP), in 8 pixel resolution. Horizontal Display Width in number of pixels = ((REG[16h] bits 6-0) x 8 Note Minimum value of 8 pixels (register programmed to 1). REG[18h] Horizontal Non-Display Period Register (HNDP) Default = 00h n/a 7 bits 6-0 Read/Write Horizontal Non-Display Period bits 6-0 6 5 4 3 2 1 0 Horizontal Non-Display Period bits [6:0] These bits specify the horizontal non-display period in pixels. For 36-bit wide panels, there are 2 pixels per external PCLK. HNDP is calculated using the following formula. HNDP = (REG[18h] bits 6-0) Note The minimum Horizontal Non-Display Period is 3 Pixels (REG[18h] bits 6-0 = 03h). HS Start + HS Width <= HNDP S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 53 REG[1Ah] Vertical Display Height Register 0 (VDISP) Default = 01h Read/Write Vertical Display Height bits 7-0 7 6 5 4 3 2 1 REG[1Ch] Vertical Display Height Register 1 (VDISP) Default = 00h Read/Write n/a 7 6 REG[1Ch] bits 1-0 REG[1Ah] bits 7-0 0 Vertical Display Height bits 9-8 5 4 3 2 1 0 Vertical Display Height bits [9:0] These bits specify the LCD panel Vertical Display Height, in 1 line resolution. Vertical Display Height in number of lines = (REG[1Ch] bits 1-0, REG[1Ah] bits 7-0) Note Minimum value = 1 line REG[1Eh] Vertical Non-Display Period Register (VNDP) Default = 01h Read/Write Vertical Non-Display Period bits 7-0 7 6 bits 7-0 5 4 3 2 1 0 Vertical Non-Display Period bits [7:0] These bits specify the Vertical Non-Display Period for panels in 1 line resolution. Note Minimum value = 2 lines REG[20h] HS Pulse Width Register (HSW) Default = 00h Read/Write HS Pulse Polarity 7 HS Pulse Width bits 6-0 6 5 4 3 2 1 0 bit 7 HS Pulse Polarity This bit selects the polarity of the horizontal sync signal. This bit is set according to the horizontal sync signal of the panel. When this bit = 0, the horizontal sync signal is active low. When this bit = 1, the horizontal sync signal is active high. bits 6-0 HS Pulse Width bits [6:0] These bits specify the width of the panel horizontal sync signal, in 1 pixel resolution. The horizontal sync signal is typically HS, depending on the panel type. The minimum value for these bits is 1. HS Pulse Width in number of pixels = (REG[20h] bits 6-0) For 36-bit wide panels, there are 2 pixels per external PCLK. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 54 Epson Research and Development Vancouver Design Center REG[22h] HS Pulse Start Position Register 0 (HPS) Default = 00h n/a 7 Read/Write HS Pulse Start Position bits 6-0 6 bits 6-0 5 4 3 2 1 0 HS Pulse Start Position bits [6:0] These bits specify the start position of the horizontal sync signal with respect to the start of Horizontal Non-Display period, in 1 pixel resolution. For 36-bit wide panels, there are 2 pixels per external PCLK. HPS = (REG[22h] bits 6-0) REG[24h] VS Pulse Width Register (VSW) Default = 00h VS Pulse Polarity n/a 7 6 Read/Write VS Pulse Width bits 5-0 5 4 3 2 1 0 bit 7 VS Pulse Polarity This bit selects the polarity of the vertical sync signal. This bit is set according to the vertical sync signal of the panel. When this bit = 0, the vertical sync signal is active low. When this bit = 1, the vertical sync signal is active high. bits 5-0 VS Pulse Width bits [5:0] These bits specify the width of the panel vertical sync signal, in 1 line resolution. The vertical sync signal is typically VS, depending on the panel type. VS Pulse Width in number of lines = REG[24h] bits 5-0 REG[26h] VS Pulse Start Position Register 0 (VPS) Default = 00h Read/Write VS Pulse Start Position bits 7-0 7 6 bits 7-0 5 4 3 2 1 0 VS Pulse Start Position bits [7:0] These bits specify the start position of the vertical sync signal with respect to the start of Vertical Non-Display period, in 1 line resolution. VPS is calculated using the following formula: VPS = (REG[26h] bits 7-0) REG[28h] PCLK Polarity Register Default = 00h Read/Write PCLK Polarity 7 bit 7 n/a 6 5 4 3 2 1 0 PCLK Polarity When this bit = 0, the PCLK outputs data transitions on the rising edge When this bit = 1, the PCLK outputs data transitions on the falling edge S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 55 9.3.4 Input Mode Register REG[2Ah] Input Mode Register Default = 01h Memory Data Format 7 bit 7 Read/Write n/a 6 Input Data Format 5 4 3 2 1 0 Memory Data Format This bit determines how the data is stored in memory When this bit = 0, the data stored in memory is 16 bpp. In this case 18 bpp input data will be truncated to 16 bpp When this bit = 1, the data stored in memory is 18 bpp. In this case 16 bpp input data (as determined by bits 3-0) will be expanded to 18 bpp. Note In 18-bpp mode, memory above $A0000h is reserved for 2 bits of each 18 bit pixel. Therefore the maximum display resolution supported can be calculated as follows: X x Y x 2 640KB In 16-bpp mode the entire 768K Byte display buffer is available and therefore the maximum display resolution is X x Y x 2 768KB Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 56 bits 4-0 Epson Research and Development Vancouver Design Center Input Data Format bits [4:0] Table 9-5: Input Data Type Selection REG[2Ah] bits 3-0 Input Data Type 0000 Reserved 0001 RGB 5:6:5 0010 RGB 6:6:6 Mode 1 RGB 8:8:8 Mode 1 0011 (LSBs will be truncated to 16 bpp or 18 bpp) 0100 Reserved 0101 Reserved 0110 RGB 6:6:6 Mode 2 RGB 8:8:8 Mode 2 0111 (LSBs will be truncated to 16 bpp or 18 bpp) 1000 YUV 4:2:2 1001 YUV 4:2:0 1010 * * * 1111 Reserved Note For YUV 4:2:2 and YUV 4:2:0 settings, the image width must be a multiple of 2 and 4 respectively. For YUV 4:2:0 the height must be a multiple of 2. For RGB 6:6:6 and RGB 8:8:8 Mode 1, if the image width is odd, the red pixel data in the last word in each line will be ignored. The red pixel data will need to be re-written on the following transfer along with the green data. See Figure 12-2: "18 bpp Mode 1(R 6-bit, G 6-bit, B 6-bit), 262,144 colors," on page 79 or Figure 12-4: "24 bpp Mode 1(R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors," on page 81. Note For further information on Input Data Format and Memory Data Format, see Section 11, "Intel 80, 8-bit Interface Color Formats" on page 75, Section 12, "Intel 80, 16-bit Interface Color Formats" on page 78 and Section 13, "YUV Timing" on page 83. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 57 REG[2Ch] Input YUV/RGB Translate Mode Register 0 Default = 00h Reserved YUV/RGB Converter Reset 7 6 Read/Write UV Fix bits 1-0 5 n/a 4 3 2 1 0 bit 7 Reserved The default value for this bit is 0. bit 6 YUV/RGB Converter Reset This bit performs a software reset of the YUV to RGB Converter (YRC). To perform a reset, write a 1 to enter reset, and then write a 0 to return from the reset state. For Reads: When this bit = 0, the YRC is not in a reset state. When this bit = 1, the YRC is in a reset state. For Writes: Writing a 0 to this bit returns the YRC from the reset state. Writing a 1 to this bit initiates a software reset of the YRC. bits 5-4 UV Fix Select bits [1:0] These bits control the UV input to the YUV/RGB Converter (YRC). Table 9-6: UV Fix Selection REG[2Ch] bits 5-4 UV Input to the YUV/RGB Converter 00 Original U data, original V data 01 U data = REG[30h] bits 7-0, original V data 10 Original U data, V data = REG[032h] bits 7-0 11 U data = REG[30h] bits 7-0, V data = REG[32h] bits 7-0 REG[2Eh] YUV/RGB Translate Mode Register 1 Default = 05h Reserved 7 bits 7-6 YUV Input Data Type Select bits 1-0 6 5 4 Read/Write Reserved 3 YUV/RGB Transfer Mode bits 2-0 2 1 0 Reserved The default value for these bits is 0. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 58 bits 5-4 Epson Research and Development Vancouver Design Center YUV Input Data Type Select bits [1:0] These bits specify the data type of the YUV input to the YUV to RGB Converter (YRC). Table 9-7: YUV Data Type Selection REG[2Eh] bits 5-4 YRC Input Data Range 00 0 Y 255 -128 U 127 -128 V 127 01 16 Y 235 -113 U 112 -113 V 112 10 0 Y 255 0 U 255 0 V 255 11 16 Y 235 16 U 240 16 V 240 bit 3 Reserved The default value for this bit is 0. bits 2-0 YUV/RGB Transfer Mode bits [2:0] These bits specify the YUV/RGB Transfer mode. Recommended settings are provided for various specifications. Table 9-8: YUV/RGB Transfer Mode Selection REG[2Eh] bits 2-0 YUV/RGB Specification 000 Reserved 001 Recommended for ITU-R BT.709 010 Reserved 011 Reserved 100 Recommended for ITU-R BT.470-6 System M 101 (Default) Recommended for all other systems in ITU-R BT.470-6 (Recommended for ITU-R BT.601-5) 110 SMPTE 170M 111 SMPTE 240M(1987) S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 59 REG[30h] U Data Fix Register Default = 00h Read/Write U Data Fix bits 7-0 7 6 bits 7-0 5 4 3 2 1 0 U Data Fix bits [7:0] These bits only have an effect when the UV Fix Select bits are set to 01 or 11 (REG[2Ch] bits 5-4 = 01 or 11). The U Data Input of the YUV/RGB Converter data is fixed to the value of these bits. REG[32h] V Data Fix Register Default = 00h Read/Write V Data Fix bits 7-0 7 bits 7-0 6 5 4 3 2 1 0 V Data Fix bits [7:0] These bits only have an effect when the UV Fix Select bits are set to 10 or 11 (REG[2Ch] bits 5-4 = 10 or 11). The V Data Input of YUV/RGB Converter data is fixed to the value of these bits. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 60 Epson Research and Development Vancouver Design Center 9.3.5 Display Mode Registers REG[34h] Display Mode Register Default = 00h Read/Write Display Blank 7 SwivelView Mode Select bits 1-0 n/a 6 5 4 3 2 1 0 bit 7 Display Blank When this bit = 0, the LCD display pipeline is enabled. When this bit = 1, the LCD display pipeline is disabled and all LCD data outputs are forced to zero (i.e., the screen is blanked). bits 1-0 Window SwivelView Mode Select bits [1:0] These bits select different SwivelViewTM orientations: Table 9-9: SwivelViewTM Mode Select Options REG[34h] bits 1-0 00 01 10 11 SwivelView Orientation 0 (Normal) 90 180 270 Note All windows written to the active display can have independent rotation as the rotation is performed prior to writing to the display buffer. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 61 REG[36h] Special Effects Register Default = 00h Window Data Type Double Buffer Enable 7 6 bit 7 Read/Write n/a 5 4 Window Pixel Sizing bits 1-0 3 2 1 0 Window Data Type When this bit = 0, the data being written from the Host is intended for single buffer only. When this bit = 1, the data being written from the Host is intended for double buffer operation. If the Input Data Format is YUV 4:2:0 (REG[2Ah] bits 4-0 = 1001), the Window Data Type should not be changed while the YYC is busy (REG[58h] bit 4 = 1). Note This bit must be set before the window being written. The window coordinates will be latched internally to be used by the display pipe during display cycles. Note This bit setting is necessary for the Double-Buffer architecture when enabled (bit 6=1) Note While double buffering is enabled, the window coordinates should not be modified. Table 9-10: Window Data Type/Buffer Selection REG[36h] Bit 7 REG[36h] Bit 6 Use Case 0 0 Single buffered window with no double buffering anywhere on the display. Use this to write a single buffered window while preventing tearing in a 0 1 previously defined double buffered window. 1 0 Reserved 1 1 Use this to write data to be double buffered. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 62 Epson Research and Development Vancouver Design Center bit 6 Double Buffer Enable This bit enables the Double Buffer architecture. When this bit = 0, the double buffer is disabled. When this bit =1, the double buffer is enabled. This feature is only available if the memory size resulting from the display size and color depth will fit within the 1/2 the allowable size for the display buffer. When enabled, this feature is intended for streaming input sources to prevent visual tearing when updating the display. Note This bit must be set before the window being written. The window coordinates will be latched internally to be used by the display pipe during display cycles. Note While double buffering is enabled, the window coordinates should not be modified. Note Only one window can be double-buffered. All other windows are single buffered. Table 9-11: Window Data Type Selection REG[36h] Bit 7 REG[36h] Bit 6 Use Case 0 0 Single buffered window with no double buffering anywhere on the display. Use this to write a single buffered window while preventing tearing in a 0 1 previously defined double buffered window. 1 0 Reserved 1 1 Use this to write data to be double buffered. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center bits 1-0 Page 63 Window Pixel Sizing bits [1:0] Table 9-12: Window Pixel Sizing REG[36h] bits 1-0 Result 00 No Resizing 01 Pixel Doubling 10 Pixel Halving 11 Reserved Note These bits must be set before the window being written. The window coordinates will be latched internally to be used by the display pipe during display cycles. Note Only 1 active window can be pixel doubled. The pixel doubling design uses horizontal and vertical averaging for smooth doubling. Note The sizing is performed with respect to the top left corner Display Original Window Pixel Halved Window Pixel Doubled Window Figure 9-1: Sizing Example Note To turn off pixel doubling for a currently pixel doubled window, either: 1. Overwrite any part of the pixel doubled window with a new window. 2. Write a new pixel doubled window. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 64 Epson Research and Development Vancouver Design Center 9.3.6 Window Settings REG[38h] Window X Start Position Register 0 Default = 00h Read/Write Window X Start Position bits 7-0 7 6 5 4 3 2 1 REG[3Ah] Window X Start Position Register 1 Default = 00h Read/Write n/a 7 6 REG[3Ah] bits 1-0 REG[38h] bits 7-0 5 0 Window X Start Position bits 9-8 4 3 2 1 0 Window X Start Position bits [9:0] These bits determine the X start position of the window in relation to the top left corner of the displayed image. Even in a rotated orientation, the top left corner is still relative to the displayed image. Note When pixel doubling or pixel halving is enabled, these registers should be programmed with the pre-resized coordinates. REG[3Ch] Window Y Start Position Register 0 Default = 00h Read/Write Window Y Start Position bits 7-0 7 6 5 4 3 2 1 REG[3Eh] Window Y Start Position Register 1 Default = 00h Read/Write n/a 7 REG[3Eh] bits 1-0 REG[3Ch] bits 7-0 6 5 0 Window Y Start Position bits 9-8 4 3 2 1 0 Window Y Start Position bits [9:0] These bits determine the Y start position of the window in relation to the top left corner of the displayed image. Even in a rotated orientation, the top left corner is still relative to the displayed image. Note When pixel doubling or pixel halving is enabled, these registers should be programmed with the pre-resized coordinates. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 65 REG[40h] Window X End Position Register 0 Default = 00h Read/Write Window X End Position bits 7-0 7 6 5 4 3 2 1 REG[42h] Window X End Position Register 1 Default = 00h Read/Write n/a 7 6 REG[42h] bits 1-0 REG[40h] bits 7-0 0 Window X End Position bits 9-8 5 4 3 2 1 0 Window X End Position bits [9:0] These bits determine the X end position of the window in relation to the top left corner of the displayed image. Even in a rotated orientation, the top left corner is still relative to the displayed image. Note When pixel doubling or pixel halving is enabled, these registers should be programmed with the pre-resized coordinates. REG[44h] Window Y End Position Register 0 Default = 00h Read/Write Window Y End Position bits 7-0 7 6 5 4 3 2 1 REG[46h] Window Y End Position Register 1 Default = 00h Read/Write n/a 7 REG[46h] bits 1-0 REG[44h] bits 7-0 6 5 0 Window Y End Position bits 9-8 4 3 2 1 0 Window Y End Position bits [9:0] These bits determine the Y end position of the window in relation to the top left corner of the displayed image. Even in a rotated orientation, the top left corner is still relative to the displayed image. Note When pixel doubling or pixel halving is enabled, these registers should be programmed with the pre-resized coordinates. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 66 Epson Research and Development Vancouver Design Center 9.3.7 Memory Access REG[48h] Memory Data Port Register 0 Default = XXh Read/Write Memory Data Port bits [7:0] 7 6 5 4 3 2 1 REG[49h] Memory Data Port Register 1 Default = XXh 0 Read/Write Memory Data Port bits [15:8] 7 6 5 4 3 REG[48h] bits 7-0 Memory Data Port bits [7:0] These specify the lsb for the data word REG[49h] bits 7-0 Memory Data Port bits [15:8] These bits specify the msb of the data word. 2 1 0 Note If CNF1=0 (8-bit interface), REG[49h] is not used. The data read back from memory will be byte swapped (i.e. if 12 34 56 78 is written to memory, data read back will be 34 12 78 56). Note Burst data writes are supported through this register. Register auto-increment is automatically disabled once reaching this address. All writes to this register will auto-increment the internal memory address only. Note Panel dimension registers must be set before writing any window data. Note Upon writing the last pixel in the defined window, this register will automatically point back to the first pixel in the window. Therefore there is no need to re-initialize the pointers. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 67 REG[4Ah] Memory Read Address Register 0 Default = 00h Read/Write Memory Address bits 7-0 7 6 5 4 3 2 1 REG[4Ch] Memory Read Address Register 1 Default = 00h 0 Read/Write Memory Address bits 15-8 7 6 5 4 3 2 1 REG[4Eh] Memory Read Address Register 2 Default = 00h Read/Write n/a 7 REG[4Eh] bits 3-0 REG[4Ch] bits 7-0 REG[4Ah] bits 7-0 6 0 Memory Address bit 19-16 5 4 3 2 1 0 Memory Read Address bits [19:0] This register is only used for individual memory location reads. Individual memory location writes are not supported. After a completed memory access, this register is incremented automatically. To perform memory reads: * perform a register address write to point to this register * followed by 3 data writes to set-up the memory address * read the Memory Data Port (REG[48h - 49h]) Note All write data uses the Memory Data Port and the Window coordinates. Note For Intel 80, 16-bit interface, the least significant bit is not used (data is fetched on word boundaries). For Intel 80, 8-bit interface, the least significant bit is used (data is fetched on byte boundaries) Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 68 Epson Research and Development Vancouver Design Center 9.3.8 Gamma Correction Registers Note Gamma correction is implemented as a look-up table. RGB input data (if the input is YUV, it will be converted to RGB first) is used to look-up the values from the programmed tables. The Gamma LUT's are placed on the display read path and the 18-bit (6 msb's from each channel) output goes to the LCD interface. Note The Gamma Correction Tables should not be accessed during display period as this will result in visual anomalies. All updates to the LUT's should be performed during nondisplay period or when the LUT's are disabled and not in use. REG[50h] Gamma Correction Enable Register Default = 00h Read/Write n/a 7 bits 2-1 6 Look-Up Table Access Mode bits 1-0 5 4 3 2 1 Gamma Correction Enable 0 Look-Up Table Access Mode bits [1:0] Table 9-13: Look-Up Table Access Mode REG[50h] bits 2-1 bit 0 Description 00 Writing will be done to all Red, Green, & Blue tables. Reading will be done from Red table. 01 Reading and writing will be done to Red table. 10 Reading and writing will be done to Green table. 11 Reading and writing will be done to Blue table. Gamma Correction Enable When this bit = 0, gamma correction is disabled and the input data will bypass the gamma correction look-up table. In this case, data stored as 16 bpp will automatically be converted to 18 bpp by copying the Red and Blue msb to create new lsb's. This will be performed on the display read therefore not requiring any additional memory. When this bit = 1, gamma correction is enabled and the input data will go through the gamma correction look-up table. Note The Gamma Correction Tables should not be accessed during display period as this will result in visual anomalies. All updates to the LUT's should be performed during nondisplay period or when the LUT's are disabled and not in use. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 69 REG[52h] Gamma Correction Table Index Register Default = 00h n/a 7 Read/Write Gamma Correction Table Index bits 5-0 6 bits 5-0 5 4 3 2 1 0 Gamma Correction Table Index bits [5:0] These bits will specify the index of the gamma correction look-up table which subsequent read/write will start at. REG[54h] Gamma Correction Table Data Register Default = XXh Read/Write Gamma Correction Table Data bits 5-0 7 bits 7-0 6 5 4 3 2 1 0 Gamma Correction Table Data bits [7:0] When writing to Gamma Correction Table Data register, the index to the internal table will be automatically incremented. For continuous update to the table, the Gamma Correction Table Index register needs only to be written once. The index will incremented by 1 for every write to Gamma Correction Table Data register. Note Although bits 7 and 6 are programmed to the LUT, they are ignored in the final output from the LUT. Note All 64 positions of each LUT must be written when using auto-increment writes.In the 5:6:5 case, the first 32 positions of the Red and Blue LUT's will be used. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 70 Epson Research and Development Vancouver Design Center 9.3.9 Miscellaneous Registers REG[56h] Power Save Register Default = 00h Read/Write PWRSVE Input Pin Function 7 n/a 6 5 4 3 Sleep Mode Enable/Disable Standby Mode Enable/Disable 1 0 2 bit 7 PWRSVE Input Pin Function When this bit = 0, the PWRSVE pin is OR'd with bit 1 (setting either to 1 will enable Sleep Mode) When this bit = 1, the PWRSVE pin is OR'd with bit 0 (setting either to 1 will enable Standby Mode) bit 1 Sleep Mode Enable/Disable When this bit = 0, Sleep Mode is disabled (normal operation) When this bit = 1, Sleep Mode is enabled. Sleep Mode disables all internal blocks including the PLL. When Sleep Mode is disabled (low), the PLL requires approximately 10msec lock time before any memory access should be attempted. The PLL Lock bit, REG[04] bit 7, can be read to verify when the PLL becomes stable. bit 0 Standby Mode Enable/Disable When this bit = 0, Standby Mode is disabled (normal operation) When this bit = 1, Standby Mode is enabled Standby Mode disables all internal blocks except the PLL. Using this mode, the chip can be accessed immediately when Standby is disabled. Note Standby Mode can also be enabled/disabled using the PWRSVE input pin. REG[58h] Non-Display Period Control / Status Register Default = 00h Read/Write Vertical NonDisplay Period Status (RO) Horizontal NonDisplay Period Status (RO) VS OR'd with HS Status (RO) YYC Last Line n/a TE Output Pin Enable 7 6 5 4 3 2 bit 7 TE Output Pin Function Select bits 1-0 1 0 Vertical Non-Display Period Status This is a read-only status bit. When this bit = 0, the LCD panel output is in a Vertical Non-Display Period. When this bit = 1, the LCD panel output is in a Vertical Display Period. Note VNDP is defined as time between the last pixel on the last line of one frame to the first pixel on the first line of the next frame. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center bit 6 Page 71 Horizontal Non-Display Period Status This is a read only status bit When this bit = 0, the LCD panel output is in a Horizontal Non-Display Period When this bit = 1, the LCD panel output is in a Horizontal Display Period Note HNDP is defined as the time between the last pixel in line n to the first pixel in line n+1. bit 5 VDP OR'd with HDP Status This bit is a read only status bit. When this bit = 0, the LCD panel output is in either the Horizontal or Vertical Non-Display period. When this bit = 1, the LCD panel output is in a Display period. bit 4 YYC Last Line If the input data type is YUV 4:2:0, this bit will go high 5 MClk's after the Intel 80 interface has finished writing the last pixel of the current window. This bit will go low once the YYC is idle. At this point, a new window can be written. When doing back-to-back window writes with a different dimension or format, and the first window is YUV 4:2:0, before starting to write the second window, make sure this bit is low. Note It can take up to five SYSCLKs from the rising edge of WE# of the last byte/word of a frame before this bit is set. bit 2 TE Output Pin Enable When this bit = 0, the TE output pin is disabled When this bit = 1, the TE output pin is enabled. bits 1-0 TE Output Pin Function Select bits [1:0] Table 9-14: TE Output Pin Function Select REG[58h] bits 1-0 TE Output Pin Function 00 Reserved 01 Horizontal Non-Display Period 10 Vertical Non-Display Period 11 HS OR'd with VS Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 72 Epson Research and Development Vancouver Design Center 9.3.10 General Purpose IO Pins Registers REG[5Ah] General Purpose IO Pins Configuration Register 0 Default =00h Read/Write GPIO7 Configuration GPIO6 Configuration GPIO5 Configuration GPIO4 Configuration GPIO3 Configuration GPIO2 Configuration GPIO1 Configuration GPIO0 Configuration 7 6 5 4 3 2 1 0 bits 7-0 GPIO[7:0] Configuration When this bit = 0 (normal operation), the associated GPIO is configured as an input pin. When this bit = 1, the associated GPIO is configured as an output pin. Note When configured as an input or an output, the associated GPIO can also be configured to produce an interrupt (GPIO_INT) based on selectable Interrupt Trigger conditions (see REG[5E], [60]) REG[5Ch] General Purpose IO Pins Status/Control Register 0 Default = 00h Read/Write GPIO7 Status GPIO6 Status GPIO5 Status GPIO4 Status GPIO3 Status GPIO2 Status GPIO1 Status GPIO0 Status 7 6 5 4 3 2 1 0 bits 7-0 GPIO[7:0] Status When the associated GPIO is configured as an output, writing a 1 to this bit drives it high and writing a 0 to this bit drives it low. When the associated GPIO is configured as an input, a read from this bit returns the raw status. Note When configured as an output, the GPIO_INT pin can still be toggled by writing the appropriate value to this register if enabled by REG[5E],[60]. REG[5Eh] GPIO Positive Edge Interrupt Trigger Register Default = 00h Read/Write GPIO7 Positive Edge Interrupt Trigger GPIO6 Positive Edge Interrupt Trigger GPIO5 Positive Edge Interrupt Trigger GPIO4 Positive Edge Interrupt Trigger GPIO3 Positive Edge Interrupt Trigger GPIO2 Positive Edge Interrupt Trigger GPIO1 Positive Edge Interrupt Trigger GPIO0 Positive Edge Interrupt Trigger 7 6 5 4 3 2 1 0 bits 7-0 GPIO[7:0] Positive Edge Interrupt Trigger Setting these bits = 1, will enable the associated interrupt. This bit determines whether the associated GPIO interrupt is triggered on the positive edge (when the GPIOx pin changes from 0 to 1). When this bit = 0, the associated GPIO interrupt (GPIO_INT) is disabled. When this bit = 1, the associated GPIO interrupt (GPIO_INT) is triggered on the positive edge. Once triggered, the GPIO_INT pin will toggle from 0 to 1. The GPIO_INT pins is cleared (non-active state (0)) by clearing the associated GPIO Interrupt Status bit (REG[62]) S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 73 REG[60h] GPIO Negative Edge Interrupt Trigger Register Default = 00h Read/Write GPIO7 Negative Edge Interrupt Trigger GPIO6 Negative Edge Interrupt Trigger GPIO5 Negative Edge Interrupt Trigger GPIO4 Negative Edge Interrupt Trigger GPIO3 Negative Edge Interrupt Trigger GPIO2 Negative Edge Interrupt Trigger GPIO1 Negative Edge Interrupt Trigger GPIO0 Negative Edge Interrupt Trigger 7 6 5 4 3 2 1 0 bits 7-0 GPIO[7:0] Negative Edge Interrupt Trigger Setting these bits = 1, will enable the associated interrupt. This bit determines whether the associated GPIO interrupt is triggered on the negative edge (when the GPIOx pin changes from 1 to 0). When this bit = 0, the associated GPIOx interrupt (GPIO_INT) is disabled. When this bit = 1, the associated GPIOx interrupt (GPIO_INT) is triggered on the negative edge. Once triggered, the GPIO_INT pin will toggle from 0 to 1. The GPIO_INT pins is cleared (non-active state (0)) by clearing the associated GPIO Interrupt Status bit (REG[62]) REG[62h] GPIO Interrupt Status Register Default = 00h Read/Write GPIO7 Interrupt Status GPIO6 Interrupt Status GPIO5 Interrupt Status GPIO4 Interrupt Status GPIO3 Interrupt Status GPIO2 Interrupt Status GPIO1 Interrupt Status GPIO0 Interrupt Status 7 6 5 4 3 2 1 0 bits 7-0 GPIO[7:0] Interrupt Status If configured to generate an Interrupt (GPIO_INT), this status bit will show which GPIO generated the interrupt. To clear this status bit, you must perform two writes to it: first write = 1, the second write = 0. Note The GPIO_INT pin will also toggle back to 0 upon clearing the status. However, if the original interrupt condition still exists on the GPIO input pin, the GPIO_INT will immediately set again. REG[64h] GPIO Pull Down Control Register 0 Default = FFh Read/Write GPIO7 Pull-down Control GPIO6 Pull-down Control GPIO5 Pull-down Control GPIO4 Pull-down Control GPIO3 Pull-down Control GPIO2 Pull-down Control GPIO1 Pull-down Control GPIO0 Pull-down Control 7 6 5 4 3 2 1 0 bits 7-0 GPIO[7:0] Pull-down Control All GPIO pins have internal pull-down resistors. These bits individually control the state of the pull-down resistors. When the bit = 0, the pull-down resistor for the associated GPIO pin is inactive. When the bit = 1, the pull-down resistor for the associated GPIO pin is active. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 74 Epson Research and Development Vancouver Design Center 10 Frame Rate Calculation The following formula is used to calculate the display frame rate. f PCLK FrameRate = ------------------------------( HT ) x ( VT ) Where: fPCLK = PClk frequency (Hz) HT = Horizontal Total = Horizontal Display Width + Horizontal Non-Display Period VT = Vertical Total = Vertical Display Height + Vertical Non-Display Period Note For definitions of panel timing parameters, see Section 7.4, "Display Interface" on page 35. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 75 11 Intel 80, 8-bit Interface Color Formats 11.1 16 bpp Mode (R 5-bit, G 6-bit, B 5-bit), 65,536 colors CS# D/C# WR# RD# MD7 Bit 7 R1, Bit 4 G1, Bit 2 R2, Bit 4 G2, Bit 2 MD6 Bit 6 R1, Bit 3 G1, Bit 1 R2, Bit 3 G2, Bit 1 MD5 Bit 5 R1, Bit 2 G1, Bit 0 R2, Bit 2 G2, Bit 0 MD4 Bit 4 R1, Bit 1 B1, Bit 4 R2, Bit 1 B2, Bit 4 MD3 Bit 3 R1, Bit 0 B1, Bit 3 R2, Bit 0 B2, Bit 3 MD2 Bit 2 G1, Bit 5 B1, Bit 2 G2, Bit 5 B2, Bit 2 MD1 Bit 1 G1, Bit 4 B1, Bit 1 G2, Bit 4 B2, Bit 1 MD0 Bit 0 G1, Bit 3 B1, Bit 0 G2, Bit 3 B2, Bit 0 Pixel n Pixel Note: The Data order is as follows, MSB = MD7, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0 for Green data and MSB = Bit 4, LSB = Bit 0 for Red and Blue data. Figure 11-1: 16 bpp Mode (R 5-bit, G 6-bit, B 5-bit), 65,536 colors Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 76 Epson Research and Development Vancouver Design Center 11.2 18 bpp (R 6-bit, G 6-bit, B 6-bit), 262,144 colors CS# D/C# WRX RD# MD7 Bit 7 R1, Bit 5 G1, Bit 5 B1, Bit 5 R2, Bit 5 MD6 Bit 6 R1, Bit 4 G1, Bit 4 B1, Bit 4 R2, Bit 4 MD5 Bit 5 R1, Bit 3 G1, Bit 3 B1, Bit 3 R2, Bit 3 MD4 Bit 4 R1, Bit 2 G1, Bit 2 B1, Bit 2 R2, Bit 2 MD3 Bit 3 R1, Bit 1 G1, Bit 1 B1, Bit 1 R2, Bit 1 MD2 Bit 2 R1, Bit 0 G1, Bit 0 B1, Bit 0 R2, Bit 0 MD1 Bit 1 MD0 Bit 0 Pixel n Pixel n + 1 Note: The Data order is as follows, MSB = MD7, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0. Figure 11-2: 18 bpp (R 6-bit, G 6-bit, B 6-bit), 262,144 colors S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 77 11.3 24 bpp (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors CS# D/C# WR# RD# MD7 Bit 7 R1, Bit 7 G1, Bit 7 B1, Bit 7 R2, Bit 7 MD6 Bit 6 R1, Bit 6 G1, Bit 6 B1, Bit 6 R2, Bit 6 MD5 Bit 5 R1, Bit 5 G1, Bit 5 B1, Bit 5 R2, Bit 5 MD4 Bit 4 R1, Bit 4 G1, Bit 4 B1, Bit 4 R2, Bit 4 MD3 Bit 3 R1, Bit 3 G1, Bit 3 B1, Bit 3 R2, Bit 3 MD2 Bit 2 R1, Bit 2 G1, Bit 2 B1, Bit 2 R2, Bit 2 MD1 Bit 1 R1, Bit 1 G1, Bit 1 B1, Bit 1 R2, Bit 1 MD0 Bit 0 R1, Bit 0 G1, Bit 0 B1, Bit 0 R2, Bit 0 Pixel n Pixel n + 1 Note: The Data order is as follows, MSB = MD7, LSB = MD0 and Picture Data is MSB = Bit 7, LSB = Bit 0. Figure 11-3: 24 bpp (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 78 Epson Research and Development Vancouver Design Center 12 Intel 80, 16-bit Interface Color Formats 12.1 16 bpp (R 5-bit, G 6-bit, B 5-bit), 65,536 colors CS# D/C# WR# RD# MD15 Bit 15 R1, Bit 4 R2, Bit 4 R3, Bit 4 MD14 Bit 14 R1, Bit 3 R2, Bit 3 R3, Bit 3 MD13 Bit 13 R1, Bit 2 R2, Bit 2 R3, Bit 2 MD12 Bit 12 R1, Bit 1 R2, Bit 1 R3, Bit 1 MD11 Bit 11 R1, Bit 0 R2, Bit 0 R3, Bit 0 MD10 Bit 10 G1, Bit 5 G2, Bit 5 G3, Bit 5 MD9 Bit 9 G1, Bit 4 G2, Bit 4 G3, Bit 4 MD8 Bit 8 G1, Bit 3 G2, Bit 3 G3, Bit 3 MD7 Bit 7 G1, Bit 2 G2, Bit 2 G3, Bit 2 MD6 Bit 6 G1, Bit 1 G2, Bit 1 G3, Bit 1 MD5 Bit 5 G1, Bit 0 G2, Bit 0 G3, Bit 0 MD4 Bit 4 B1, Bit 4 B2, Bit 4 B3, Bit 4 MD3 Bit 3 B1, Bit 3 B2, Bit 3 B3, Bit 3 MD2 Bit 2 B1, Bit 2 B2, Bit 2 B3, Bit 2 MD1 Bit 1 B1, Bit 1 B2, Bit 1 B3, Bit 1 MD0 Bit 0 B1, Bit 0 B2, Bit 0 B3, Bit 0 Pixel n Pixel n + 1 Pixel n + 2 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0 for Green data and MSB = Bit 4, LSB = Bit 0 for Red and Blue data. Figure 12-1: 16 bpp (R 5-bit, G 6-bit, B 5-bit), 65,536 colors S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 79 12.2 18 bpp Mode 1 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors CS# D/C# WR# RD# MD15 Bit 15 R1, Bit 5 B1, Bit 5 G2, Bit 5 MD14 Bit 14 R1, Bit 4 B1, Bit 4 G2, Bit 4 MD13 Bit 13 R1, Bit 3 B1, Bit 3 G2, Bit 3 MD12 Bit 12 R1, Bit 2 B1, Bit 2 G2, Bit 2 MD11 Bit 11 R1, Bit 1 B1, Bit 1 G2, Bit 1 MD10 Bit 10 R1, Bit 0 B1, Bit 0 G2, Bit 0 MD9 Bit 9 MD8 Bit 8 MD7 Bit 7 G1, Bit 5 R2, Bit 5 B2, Bit 5 MD6 Bit 6 G1, Bit 4 R2, Bit 4 B2, Bit 4 MD5 Bit 5 G1, Bit 3 R2, Bit 3 B2, Bit 3 MD4 Bit 4 G1, Bit 2 R2, Bit 2 B2, Bit 2 MD3 Bit 3 G1, Bit 1 R2, Bit 1 B2, Bit 1 MD2 Bit 2 G1, Bit 0 R2, Bit 0 B2, Bit 0 MD1 Bit 1 MD0 Bit 0 Pixel n Pixel n + 1 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0. Figure 12-2: 18 bpp Mode 1(R 6-bit, G 6-bit, B 6-bit), 262,144 colors Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 80 Epson Research and Development Vancouver Design Center 12.3 18 bpp Mode 2 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors CS# D/C# WR# RD# MD15 Bit 15 G1, Bit 5 MD14 Bit 14 G1, Bit 4 MD13 Bit 13 G1, Bit 3 MD12 Bit 12 G1, Bit 2 MD11 Bit 11 G1, Bit 1 MD10 Bit 10 G1, Bit 0 MD9 Bit 9 MD8 Bit 8 MD7 Bit 7 R1, Bit 5 B2, Bit 5 R2, Bit 5 MD6 Bit 6 R1, Bit 4 B2, Bit 4 R2, Bit 4 MD5 Bit 5 R1, Bit 3 B2, Bit 3 R2, Bit 3 MD4 Bit 4 R1, Bit 2 B2, Bit 2 R2, Bit 2 MD3 Bit 3 R1, Bit 1 B2, Bit 1 R2, Bit 1 MD2 Bit 2 R1, Bit 0 B2, Bit 0 R2, Bit 0 MD1 Bit 1 MD0 Bit 0 Pixel n Pixel n + 1 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0. Figure 12-3: 18 bpp Mode 2 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 81 12.4 24 bpp Mode 1 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors CS# D/C# WR# RD# MD15 Bit 15 R1, Bit 7 B1, Bit 7 G2, Bit 7 MD14 Bit 14 R1, Bit 6 B1, Bit 6 G2, Bit 6 MD13 Bit 13 R1, Bit 5 B1, Bit 5 G2, Bit 5 MD12 Bit 12 R1, Bit 4 B1, Bit 4 G2, Bit 4 MD11 Bit 11 R1, Bit 3 B1, Bit 3 G2, Bit 3 MD10 Bit 10 R1, Bit 2 B1, Bit 2 G2, Bit 2 MD9 Bit 9 R1, Bit 1 B1, Bit 1 G2, Bit 1 MD8 Bit 8 R1, Bit 0 B1, Bit 0 G2, Bit 0 MD7 Bit 7 G1, Bit 7 R2, Bit 7 B2, Bit 7 MD6 Bit 6 G1, Bit 6 R2, Bit 6 B2, Bit 6 MD5 Bit 5 G1, Bit 5 R2, Bit 5 B2, Bit 5 MD4 Bit 4 G1, Bit 4 R2, Bit 4 B2, Bit 4 MD3 Bit 3 G1, Bit 3 R2, Bit 3 B2, Bit 3 MD2 Bit 2 G1, Bit 2 R2, Bit 2 B2, Bit 2 MD1 Bit 1 G1, Bit 1 R2, Bit 1 B2, Bit 1 MD0 Bit 0 G1, Bit 0 R2, Bit 0 B2, Bit 0 Pixel n Pixel n + 1 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 7, LSB = Bit 0. Figure 12-4: 24 bpp Mode 1(R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 82 Epson Research and Development Vancouver Design Center 12.5 24 bpp Mode 2 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors CS# D/C# WR# RD# MD15 Bit 15 G1, Bit 7 MD14 Bit 14 G1, Bit 6 MD13 Bit 13 G1, Bit 5 MD12 Bit 12 G1, Bit 4 MD11 Bit 11 G1, Bit 3 MD10 Bit 10 G1, Bit 2 MD9 Bit 9 G1, Bit 1 MD8 Bit 8 G1, Bit 0 MD7 Bit 7 R1, Bit 7 B1, Bit 7 R2, Bit 7 MD6 Bit 6 R1, Bit 6 B1, Bit 6 R2, Bit 6 MD5 Bit 5 R1, Bit 5 B1, Bit 5 R2, Bit 5 MD4 Bit 4 R1, Bit 4 B1, Bit 4 R2, Bit 4 MD3 Bit 3 R1, Bit 3 B1, Bit 3 R2, Bit 3 MD2 Bit 2 R1, Bit 2 B1, Bit 2 R2, Bit 2 MD1 Bit 1 R1, Bit 1 B1, Bit 1 R2, Bit 1 MD0 Bit 0 R1, Bit 0 B1, Bit 0 R2, Bit 0 Pixel n Pixel n + 1 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 7, LSB = Bit 0. Figure 12-5: 24 bpp Mode 2 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 83 13 YUV Timing Format Definition * The number of pixels per line is always even * The YCBCR colorspace is defined in ITU-R BT601.4 * YUV 4:2:2 format U11Y11V11Y12U13Y13V13Y14... * YUV 4:2:0 format Odd Line: UY11Y12... Even Line: VY21Y22... Note When a window is setup for YUV data, the data must always alternate between odd and even lines, starting with an odd line. YUV 4:2:2 U11 Odd Line Y11 U13 Y12 Y13 V11 V13 U21 U23 Even Line Y21 Y22 V21 Y23 Y14 Y24 V23 YUV 4:2:0 Odd Line (must start with this line) Y11 Y12 Y13 U/V Even Line Y21 Y14 U/V Y22 Y23 Y24 Figure 13-1: YUV Format Definition Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 84 Epson Research and Development Vancouver Design Center 13.1 YUV 4:2:2 with Intel 80, 8-bit Interface CS# RESET# D/C# WR# RD# MD7 Bit7 MD6 Bit6 MD5 Bit5 MD4 Bit4 MD3 Bit3 U Y11 V MD2 Bit2 MD1 Bit1 MD0 Bit0 Y12 U Y13 (13,14) (11,12) (11,12) V (13,14) Y14 Figure 13-2: YUV 4:2:2 with Intel 80, 8-bit Interface 13.2 YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface CS# RESET# D/C# WR# RD# MD7 Bit7 MD6 Bit6 MD5 Bit5 MD4 Bit4 MD3 Bit3 MD2 Bit2 MD1 Bit1 MD0 Bit0 U (11,12,21,22) Y11 Y12 U (13,14,23,24) Y13 Y14 U (15,16,25,26) Y15 Figure 13-3: YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 85 13.3 YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface CS# RESET# D/C# WR# RD# MD7 Bit7 MD6 Bit6 MD5 Bit5 MD4 Bit4 MD3 Bit3 MD2 Bit2 MD1 Bit1 MD0 Bit0 V (11,12,21,22) Y21 Y22 V (13,14,23,24) Y23 Y24 V (15,16,25,26) Y25 Figure 13-4: YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 86 Epson Research and Development Vancouver Design Center 13.4 YUV 4:2:2 with Intel 80, 16-bit Interface CS# RESET# D/C# WR# RD# MD15 Bit15 MD14 Bit14 MD13 Bit13 MD12 Bit12 MD11 Bit11 MD10 Bit10 MD9 Bit9 MD8 Bit8 MD7 Bit7 MD6 Bit6 MD5 Bit5 MD4 Bit4 MD3 Bit3 MD2 Bit2 MD1 Bit1 MD0 Bit0 U11 V11 U13 V13 U15 V15 U17 V17 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Figure 13-5: YUV 4:2:2 with Intel 80, 16-bit Interface S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 87 13.5 YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface CS# RESET# D/C# WR# RD# MD15 Bit15 MD14 Bit14 MD13 Bit13 MD12 Bit12 MD11 Bit11 MD10 Bit10 MD9 Bit9 MD8 Bit8 MD7 Bit7 MD6 Bit6 MD5 Bit5 MD4 Bit4 MD3 MD2 Bit3 U (11,12,21,22) Y11 U Y12 Y13 (15,16,25,26) U Y14 Y15 (13,14,23,24)) Y16 Y17 U Y18 (17,18,27,28) Bit2 MD1 Bit1 MD0 Bit0 Figure 13-6: YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 88 Epson Research and Development Vancouver Design Center 13.6 YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface CS# RESET# D/C# WR# RD# MD15 Bit15 MD14 Bit14 MD13 Bit13 MD12 Bit12 MD11 Bit11 MD10 Bit10 MD9 Bit9 MD8 Bit8 MD7 Bit7 MD6 Bit6 MD5 Bit5 MD4 Bit4 MD3 Bit3 MD2 Bit2 MD1 Bit1 MD0 Bit0 V (11,12,21,22) Y21 V Y22 Y23 (15,16,25,26) V Y24 Y25 (13,14,23,24) Y26 Y27 V Y28 (17,18,27,28) Figure 13-7: YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 89 14 Gamma Correction Look-Up Table Architecture The following figures are intended to show the display data output path only. The following diagram shows the architecture for 18 bpp using LUT. Red Look-Up Table 64x8 00 01 02 03 04 05 06 07 00 0000 00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 38 39 3A 3B 3C 3D 3E 3F 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 Green Look-Up Table 64x8 00 01 02 03 04 05 06 07 00 0000 00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 38 39 3A 3B 3C 3D 3E 3F 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 Blue Look-Up Table 64x8 00 01 02 03 04 05 06 07 00 0000 00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 38 39 3A 3B 3C 3D 3E 3F 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 6-bit Red Data 6-bit Red Data from Display Buffer 6-bit Green Data 6-bit Green Data from Display Buffer 6-bit Blue Data 6-bit Blue Data from Display Buffer Note: Only the 6 LSB's from each table are used to construct an 18-bit pixel. Figure 14-1: Look-Up Table Architecture Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 90 Epson Research and Development Vancouver Design Center 14.1 Gamma Correction Example Programming * Disable the LUT's or ensure you are in a non-display period when accessing to avoid visual anomalies. * Write register "address" for Gamma Correction Enable Register. * Write data to set LUT Access Mode. * Write data to set LUT Index to "x" (auto-increment is already enabled therefore the LUT Index Register address does not have to be written). * Write data to Gamma Correction Data Register (data value for Index "x"). * Write data to Gamma Correction Data Register (data value for Index "x+1"). * Continue until complete (64 positions). Even in the case of 5:6:5, all 64 positions of each RGB LUT must be programmed when using the auto-increment method. * Enable Gamma Correction. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 91 15 Display Data Format Table 15-1: 36-Bit Data Format (Non-Swapped) Cycle Count 1 2 3 ... n VD35 R1 5 R35 R55 ... Rn+15 VD34 R14 R34 R54 ... Rn+14 VD33 R13 R33 R53 ... Rn+13 VD32 R12 R32 R52 ... Rn+12 VD31 R11 R31 R51 ... Rn+11 VD30 R1 0 Rn+10 G15 ... Gn+15 VD28 G14 ... Gn+14 VD27 G13 ... Gn+13 VD26 G1 2 ... Gn+12 VD25 G11 ... Gn+11 VD24 G10 ... Gn+10 VD23 B15 ... Bn+15 VD22 B14 B13 B12 B11 B10 R05 R04 R03 R02 R01 R00 G05 G04 G03 G02 G01 G00 B05 B04 B03 B02 B01 B00 R50 G55 G54 G53 G52 G51 G50 B55 B54 B53 B52 B51 B50 R45 R44 R43 R42 R41 R40 G45 G44 G43 G42 G41 G40 B45 B44 B43 B42 B41 B40 ... VD29 R30 G35 G34 G33 G32 G31 G30 B35 B34 B33 B32 B31 B30 R25 R24 R23 R22 R21 R20 G25 G24 G23 G22 G21 G20 B25 B24 B23 B22 B21 B20 ... Bn+14 ... Bn+13 ... Bn+12 ... Bn+11 ... Bn+10 ... Rn5 ... Rn4 ... Rn3 ... Rn2 ... Rn1 ... Rn0 ... Gn5 ... Gn4 ... Gn3 ... Gn2 ... Gn1 ... Gn0 ... Bn5 ... Bn4 ... Bn3 ... Bn2 ... Bn1 ... Bn0 VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 92 Epson Research and Development Vancouver Design Center Table 15-2: 36-Bit Data Format (Swapped) Cycle Count VD35 VD34 VD33 VD32 VD31 VD30 VD29 VD28 VD27 VD26 VD25 VD24 VD23 VD22 VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 1 2 3 ... n B00 B01 B02 B03 B04 B05 G00 G01 G02 G03 G04 G05 R00 R01 R02 R03 R04 R05 B10 B11 B12 B13 B14 B15 G10 G11 G12 G13 G14 G15 R10 R11 R12 R13 R14 R15 B20 B21 B22 B23 B24 B25 G20 G21 G22 G23 G24 G25 R20 R21 R22 R23 R24 R25 B30 B31 B32 B33 B34 B35 G30 G31 G32 G33 G34 G35 R30 R31 R32 R33 R34 R35 B40 B41 B42 B43 B44 B45 G40 G41 G42 G43 G44 G45 R40 R41 R42 R43 R44 R45 B50 B51 B52 B53 B54 B55 G50 G51 G52 G53 G54 G55 R50 R51 R52 R53 R54 R55 ... Bn0 ... Bn1 ... Bn2 ... Bn3 ... Bn4 ... Bn5 ... Gn0 ... Gn1 ... Gn2 ... Gn3 ... Gn4 ... Gn5 ... Rn0 ... Rn1 ... Rn2 ... Rn3 ... Rn4 ... Rn5 ... Bn+10 ... Bn+11 ... Bn+12 ... Bn+13 ... Bn+14 ... Bn+15 ... Gn+10 ... Gn+11 ... Gn+12 ... Gn+13 ... Gn+14 ... Gn+15 ... Rn+10 ... Rn+11 ... Rn+12 ... Rn+13 ... Rn+14 ... Rn+15 S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 93 Table 15-3: 18-Bit Data Format (Non-Swapped) Cycle Count 1 2 VD[35:18] 3 ... n Driven Low R0 5 R15 R25 ... Rn5 VD16 R0 4 Rn4 R03 ... Rn3 VD14 R02 ... Rn2 VD13 R01 ... Rn1 VD12 R0 0 ... Rn0 VD11 G05 ... Gn5 VD10 G04 ... Gn4 VD9 G03 ... Gn3 VD8 G0 2 ... Gn2 VD7 G01 ... Gn1 VD6 G00 ... Gn0 VD5 B05 ... Bn5 VD4 B04 B03 B02 B01 B00 R24 R23 R22 R21 R20 G25 G24 G23 G22 G21 G20 B25 B24 B23 B22 B21 B20 ... VD15 R14 R13 R12 R11 R10 G15 G14 G13 G12 G11 G10 B15 B14 B13 B12 B11 B10 ... Bn4 ... Bn3 ... Bn2 ... Bn1 ... Bn0 VD17 VD3 VD2 VD1 VD0 Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 94 Epson Research and Development Vancouver Design Center Table 15-4: 18-Bit Data Format (Swapped) Cycle Count 1 2 B00 B01 B02 B03 B04 B05 G00 G01 G02 G03 G04 G05 R00 R01 R02 R03 R04 R05 B10 B11 B12 B13 B14 B15 G10 G11 G12 G13 G14 G15 R10 R11 R12 R13 R14 R15 VD[35:18] VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 3 ... n B20 ... Bn0 B21 ... Bn1 B22 B23 B24 B25 G20 G21 G22 G23 G24 G25 R20 R21 R22 R23 R24 R25 ... Bn2 ... Bn3 ... Bn4 ... Bn5 ... Gn0 ... Gn1 ... Gn2 ... Gn3 ... Gn4 ... Gn5 ... Rn0 ... Rn1 ... Rn2 ... Rn3 ... Rn4 ... Rn5 Driven Low S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 95 16 SwivelViewTM 16.1 Concept Most computer displays are refreshed in landscape orientation - from left to right and top to bottom. Computer images are stored in the same manner. SwivelViewTM is designed to rotate the displayed image on an LCD by 90, 180, or 270 in a counter-clockwise direction. The rotation is done in hardware and is transparent to the user for all display buffer writes. By processing the rotation in hardware, SwivelViewTM offers a performance advantage over software rotation of the displayed image. The actual address translation is performed during the Host Write and is therefore stored in memory as rotated. Because of where the rotation logic is, each Window written to the S1D13742 can be independently rotated with respect to each other. 16.2 90 SwivelViewTM The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. The application image is written to the S1D13742 in the following sense: A-B-C-D. The display is refreshed in the following sense: B-D-A-C. physical memory start address 320 C display start address (panel origin) SwivelView window B SwivelView window D B A 480 A D C 480 320 image seen by programmer = image in display buffer image refreshed by the S1D13742 Figure 16-1: Relationship Between The Screen Image and the Image Refreshed in 90 SwivelView. 16.2.1 Register Programming There is no special programming requirements other than simply enabling the rotation itself. All start addresses and Line Offset's are automatically calculated by hardware. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 96 Epson Research and Development Vancouver Design Center 16.3 180 SwivelViewTM The following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed. The application image is written to the S1D13742 in the following sense: A-B-C-D. The display is refreshed in the following sense: D-C-B-A. display start address (panel origin) D D B C 320 320 SwivelView window A B SwivelView window A C physical memory start address 480 480 image seen by programmer = image in display buffer image refreshed by the S1D13742 Figure 16-2: Relationship Between The Screen Image and the Image Refreshed in 180 SwivelView. 16.3.1 Register Programming There is no special programming requirements other than simply enabling the rotation itself. All start addresses and Line Offset's are automatically calculated by hardware. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 97 16.4 270 SwivelViewTM The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. The application image is written to the S1D13742 in the following sense: A-B-C-D. The display is refreshed in the following sense: C-A-D-B. physical memory start address B 320 display start address (panel origin) A SwivelView window SwivelView window C 480 A B D D C 480 320 image seen by programmer = image in display buffer image refreshed by the S1D13742 Figure 16-3: Relationship Between The Screen Image and the Image Refreshed in 270 SwivelView. 16.4.1 Register Programming There is no special programming requirements other than simply enabling the rotation itself. All start addresses and Line Offset's are automatically calculated by hardware. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 98 Epson Research and Development Vancouver Design Center 17 Host Interface 17.1 Using the Intel 80 Interface Accessing the S1D13742 through the Intel 80 interface is a multiple step process. All Registers and Memory are accessed through register space. Note All Register accesses, except the Memory Data Port, are 8-bit only. If the Host interface is 16-bits wide, the lsb's (MD[7:0]) are used for all registers except the Memory Data Port. The Memory Data Port (REG[48h, 49h]) is handled as 8-bit if CNF1 = 0 (REG[49h] not used) or 16-bit if CNF1 =1. First, perform a single "Address Write" to setup the register address. Next a "Data Read/Write" is performed that specifies the data to be stored or read from the registers or memory specified in the "Address Write" cycle. Subsequent data Read/Writes without a Address Write to change the register address, will automatically "auto" increment the register address or the internal memory address if accessing the Memory Data Port. To write display data to a Window Aperture, simply set-up the Window coordinates followed by the burst data writes to the Memory Data Port to fill the window. In this sequence, the internal memory addressing is automatic (see examples). The Memory Data Port is located directly following the Window coordinates to minimize the number of Address Writes. To Read display data, perform an Address Write to the Memory Address Port (3 bytes) and then read data from the Memory Data Port. Sequential reads will auto-increment the internal memory address 17.1.1 Register write procedure 1. Perform address write to setup register address bits 7-0. 2. Perform data write to update the register. 3. Additional data writes are supported. In this case, the register addresses will be autoincremented. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 99 CS# D/C# RD# WE# MD[7:0] Address bits 7-0 Write Data Write Data Write Data Write 1 2 3 4 Figure 17-1: Register Write Example Sequence 17.1.2 Register read procedure 1. Perform address write to setup register address bits 7-0. 2. Perform data read to get the register value. 3. Additional data reads are supported. In this case, the register addresses will be auto-incremented. CS# D/C# WE# MD[7:0] Write RD# MD[7:0] Read Address bits 7-0 Write Data Read Data Read Data Read 1 2 3 4 Figure 17-2: Register Read Example Sequence Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 100 Epson Research and Development Vancouver Design Center 17.1.3 New Window Aperture Write procedure The S1D13742 has a special procedure to minimize set-up accesses when bursting window data. 1. The panel dimension registers must be set before writing any Window data. 2. Perform an Address Write to point to the first Window Register (Window X Start Position). 3. Perform eight "data" writes to the next eight, 8-bit registers (this will set-up all the Window coordinates. Note In this case the register addresses will be auto-incremented until you reach the Memory Data Port Register 4. Perform burst data writes to fill the window (the register address will already be pointing at the Memory Data Port) The Memory Data Port Register is located in the 9th register address after the Window X Start Position. Every write to the Memory Data Port will auto-increment the internal memory address only. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 MD[7:0] WE# RD# D/C# CS# Window Y Start Data Window Y Start Data Window x Start Data Window X Start Data Window X Start Register Address Window X End Data Window X End Data Window Y End Data Window Y End Data Display Data Epson Research and Development Vancouver Design Center Page 101 Figure 17-3: Sequential Memory Write Example Sequence S1D13742 X63A-A-001-06 Page 102 Epson Research and Development Vancouver Design Center 17.1.4 Opening Multiple Windows 1. Repeat steps above (New Window Aperture write procedure) with new window coordinates for each new window. 2. Non-pixel doubled windows can overlap with the last one being written considered the top. Update Window using existing Window Coordinates: 1. Perform an Address Write to point to the Memory Data Port 2. Perform burst data writes to fill the window. Note In this case the previous coordinates of the Window Aperture will be used. Every write to the Memory Data Port will auto-increment the internal memory address only. 17.1.5 Individual Memory Location Reads Note This function is for test purposes only and serves no practical use in a system. 1. Set the Memory Data Format to 16bpp. 2. Write the physical address of the memory location to read from, to the Memory Read Address Registers (for a 16bit bus, the LSB of this address is ignored). 3. Perform a read from the Memory Data Port Register. 4. Continuous reads from the Memory Data Port Register will cause the address in the Memory Read Address Registers to increment, thereby supporting burst reads. Note To access the 2 msb's for each 18-bit value, you must know the physical address as they are stored at different locations as compared to the lower 16-bits. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 103 18 Double Buffer Description 18.1 Double Buffer Controller Double buffering is provided to prevent tearing of streaming video data. All static (nonvideo) image data will always be written to the upper half (Buffer 1) of the frame buffer. When video is being input, the first frame will be written to the lower half (Buffer 2) of the double buffer. The second frame will be written to Buffer 1. While video data is being input, the static part of the image going to the LCD will still always come from Buffer 1. The source of the video window will come from either Buffer 1 or Buffer 2, depending on which one was the last to be completely updated. The switching of the buffer read/write pointers can only occur once per frame, at the beginning of the vertical non-display period. The pointers will only switch if: a video frame had completed being updated within the last output frame period, and no new video frame is currently being written. Because of this, each time the user finishes writing a frame of video data, they should wait until the next vertical non-display period before writing the next frame. This can be accomplished by using the TE pin or by polling the Vertical Display Period Status (REG[58h] bit 7). Alternatively, if the user can guarantee that the maximum input video frame rate is 1/2 the LCD frame rate and that the burst length for writing a video frame is less than one LCD frame period, then no checking for the vertical non-display period is required. If attention is not paid to allowing the pointers to switch, then frames may be dropped. Switch buffer pointers since a frame completed being updated in the last LCD frame period Don't switch buffer pointers since a frame is currently being written. Switch buffer pointers since a frame completed being updated in the last LCD frame period Switch buffer pointers since a frame completed being updated in the last LCD frame period Vertical Non-Display Period Input Video Frame Burst Read Buffer Pointer Write Buffer Pointer Figure 18-1: Switching of Buffer Pointers To use the double buffer feature: * Set the Special Effects Register REG[36h] bits 7-6 to 11. * Setup the Window Position Registers REG[38h] - REG[46h]. * Write the video data to the Memory Data Port REG[48h] - REG[49h]. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 104 Epson Research and Development Vancouver Design Center It is also possible to update a static window while double buffering is enabled, even in the middle of a video stream. To do this: * Write the last pixel of the current frame of video data. * Set the Special Effects Register REG[36h] bits 7-6 to 01. * Setup the Window Position Registers REG[38h] - REG[46h]. * Write the static data to the Memory Data Port REG[48h] - REG[49h]. This allows a static image to be written at any time, while still preventing the double buffered window from tearing. Once the static window has been written, the user can go back to writing the streaming video data by following the steps described above for using the double buffer feature. Buffer 1 Buffer 1 Buffer 1 Buffer 1 Input Background image Background Output Output image Background PIP Background image image Output Input Output Buffer 2 Buffer 2 Buffer 2 Buffer 2 Input Time 1: Time 2: Time 3: Time 4: The main/background image is in Buffer 1. Buffer 2 is empty. The data output to the LCD comes entirely from Buffer 1. The main/background image is in Buffer 1. Buffer 2 is written with video data. The data output to the LCD comes entirely from Buffer 1. The main/background image is in Buffer 1, but part of this data is destructively overwritten by the second frame of video data. The static image data from Buffer 1 is sent to the LCD, but the video window comes from Buffer 2. A static PIP is destructively written into Buffer 1. Since the most recently updated video frame is in Buffer 1, the entire image output to the LCD comes from Buffer 1. There may be tearing in the PIP window, but the video window will not tear. Figure 18-2: Double Buffer Example S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 105 There are some limitations to double buffering: * Consider the case where there is a video stream being input and the user wants to place a static PIP over all or some part of the video window. The user can write the PIP, but when the video stream is continued, it will destructively overwrite the PIP, so that it will appear as though the PIP is under the video window. * Consider the case where there is a video stream which stops after the last frame of video is sent. The final frame of video will continue to be displayed on the LCD. Assume that this last frame is stored in Buffer 2. Now, if the user disables double buffering, the buffer read pointer will immediately reset to Buffer 1. This means that the 2nd to last frame will now be displayed instead of the last frame. * The user must either wait for a vertical non-display period between writing frames of video data, or guarantee that their maximum input frame rate is 1/2 the LCD frame rate and that the length of time it takes to burst write a frame of video data is less than one LCD frame period. * Only one window can be double buffered at a time. Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 106 Epson Research and Development Vancouver Design Center 19 Interfacing the S1D13742 and a TFT Panel This section describes the hardware and software environment required to interface the S1D13742 Mobile Graphics Engine and a 352x416 or 800x480 TFT Panel. The designs described in this section are presented only as examples of how such interfaces might be implemented. 19.1 Overview The S1D13742 was designed to directly support the Sanyo LC13015 and requires no additional hardware and minimal programming. The S1D13742 register settings and electrical interface is described below. 19.1.1 Electrical Interface Table 19-1: Pin Mapping S1D13742 Pin Name S1D13742 Pin Number LCD13015 Pin Name HS D9 HS VS D10 VS PCLK D11 PCLK DE C11 DE VD[17:0] J8,J9,J10,J11,K4,K5,K6,K R5,R4,R3,R2,R1,R0,G5,G 7,K8,K9,K10,L3,L4,L5,L6, 4,G3,G2,G1,G0,B5,B4,B3, L7,L8,L9 B2,B1,B0 S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 107 19.1.2 S1D13742 Register Settings for 352x416 TFT Panel Note The registers listed below are only those associated with panel specific timing issues All other registers are not shown here. Note When a window is setup for YUV data, the data must always alternate between odd and even lines, starting with an odd line. Table 19-2: Example Register Settings for 352x416 TFT Panel Register Value Comment All default REG[56h] 02h enter sleep mode (or use PWRSVE pin) REG[04h] 12h set PLL M-Divider. CLKI = 19.2MHz, PLL input clock = CLKI/19 = 1.01MHz. REG[06h] F8h Come out of reset - all registers set to default values REG[08h] 80h REG[0Ah] 28h REG[0Ch] 00h REG[0Eh] 2Fh LL = 48, resulting SYSCLK = LL x PLL input clock = 48MHz REG[12h] 19h set PCLK divide, PCLK = 12.1MHz set SYSCLK source = PLL REG[14h] 0h no panel data swap, 18-bit panel REG[16h] 2Ch HDP = 352 pixels HNDP = 90 pixels REG[18h] 5Ah REG[1Ah] A0h REG[1Ch] 01h REG[1Eh] 06h VNDP = 6 lines REG[20h] 14h HS Pulse Width = 20 pixels REG[22h] 2Dh HS Start Position = 45 pixels REG[24h] 02h VS Width = 2 lines REG[26h] 01h VS Start Position (VFP) = 1 line REG[28h] 80h PCLK Polarity: data output on falling edge REG[2Ah] 01h set memory to 16 bpp, set input data mode to RGB 5:6:5 REG[56h] 00h disable sleep mode REG[04h] bit 7 -- REG[38h] 00h REG[3Ah] 00h REG[3Ch] 00h REG[3Eh] 00h VDP = 416 lines wait for PLL to lock - poll REG[04h] bit 7 Window X Start Position = 0 Window Y Start Position = 0 Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 108 Epson Research and Development Vancouver Design Center Table 19-2: Example Register Settings for 352x416 TFT Panel (Continued) Register Value REG[40h] 5Fh REG[42h] 01h REG[44h] 9Fh REG[46h] 01h REG[48h] REG[49h] Comment Window X End Position = 351 Window Y End Position = 415 Write the image data to the Memory Data Port, REG[48h] and REG[49h]. The image will immediately begin to appear on the LCD. Note The above values are intended as examples. This example assumes that CLKI = 19.2MHz and that the PLL is used to generate SYSCLK. Actual settings can vary and still remain within the LCD panel timing requirements. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 109 19.1.3 S1D13742 Register Settings for 800x480 TFT Panel Note The registers listed below are only those associated with panel specific timing issues All other registers are not shown here. Note When a window is setup for YUV data, the data must always alternate between odd and even lines, starting with an odd line. Table 19-3: Example Register Settings for 800x480 TFT Panel Register Value Comment All default REG[56h] 02h enter sleep mode (or use PWRSVE pin) REG[04h] 0Bh set PLL M-Divider. CLKI = 12MHz, PLL input clock = CLKI/12 = 1.0MHz. REG[06h] F8h Come out of reset - all registers set to default values REG[08h] 80h REG[0Ah] 28h REG[0Ch] 00h REG[0Eh] 2Dh LL = 45, resulting SYSCLK = LL x PLL input clock = 45MHz REG[12h] 09h set PCLK divide, PCLK = 22.5MHz set SYSCLK source = PLL REG[14h] 0h no panel data swap, 18-bit panel REG[16h] 64h HDP = 800 pixels HNDP = 20 pixels REG[18h] 14h REG[1Ah] E0h REG[1Ch] 01h REG[1Eh] 06h VNDP = 6 lines REG[20h] 14h HS Pulse Width = 20 pixels REG[22h] 2Dh HS Start Position = 45 pixels REG[24h] 02h VS Width = 2 lines REG[26h] 01h VS Start Position (VFP) = 1 line REG[28h] 80h PCLK Polarity: data output on falling edge REG[2Ah] 01h set memory to 16 bpp, set input data mode to RGB 5:6:5 REG[56h] 00h disable sleep mode REG[04h] bit 7 -- REG[38h] 00h REG[3Ah] 00h REG[3Ch] 00h REG[3Eh] 00h VDP = 480 lines wait for PLL to lock - poll REG[04h] bit 7 Window X Start Position = 0 Window Y Start Position = 0 Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 110 Epson Research and Development Vancouver Design Center Table 19-3: Example Register Settings for 800x480 TFT Panel (Continued) Register Value REG[40h] 1Fh REG[42h] 03h REG[44h] DFh REG[46h] 01h REG[48h] REG[49h] Comment Window X End Position = 799 Window Y End Position = 479 Write the image data to the Memory Data Port, REG[48h] and REG[49h]. The image will immediately begin to appear on the LCD. Note The above values are intended as examples. This example assumes that CLKI = 12MHz and that the PLL is used to generate SYSCLK. Actual settings can vary and still remain within the LCD panel timing requirements. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 111 19.2 Host Bus Timing D/C# 1/2IOVDD 1/2IOVDD tast tcs CS# taht 1/2IOVDD 1/2IOVDD twrl tcsf tcsf twrh twc WE# 1/2IOVDD 1/2IOVDD 1/2IOVDD tdst MD[15:0] write 1/2IOVDD tdht 1/2IOVDD 1/2IOVDD trcs taht trc trdl RD# 1/2IOVDD trat MD[15:0] read 1/2IOVDD trdh 1/2IOVDD todh tddt Note: The D/C# input pin is used to distinguish between Address and Data. Note: The register address will auto-increment in word increments for all register access except the Gamma Correction Table Data register and Memory Data Port. Writes to the Gamma Correction Table Data register and Memory Data Port will not increment the register address to support burst data writes to the gamma correction table and to memory. Figure 19-1: Intel 80 Input A.C. Characteristics Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 112 Epson Research and Development Vancouver Design Center 19.2.1 Host Bus Timing for 352x416 TFT Panel Table 19-4: Intel 80 Input A.C. Characteristics (352x416 Panel Timings) Signal D/C# CS# WE# Symbol Parameter Unit Description tast Address setup time 1.4 -- nsec Address hold time 0.3 -- nsec tcs Chip Select setup time (write) 0.6 + twrl -- nsec trcs Chip Select setup time (read) 1.3 + trdl -- nsec tcsf Chip Select Wait time 9.2 -- nsec twc Write cycle (rising edge to next rising edge) 42.6 -- nsec twrh Pulse high duration Note 1 -- twrl Pulse low duration 0.1 -- nsec Read cycle for Registers trdh trdl MD[15:0] Max taht trc RD# Min 42.6 -- nsec Read cycle for Memory 122.1 + trdh -- nsec Read cycle for LUT 108.1 + trdh -- nsec Pulse high duration Note 2 -- Pulse low duration for Registers 10.2 -- nsec Pulse low duration for Memory 122.1 -- nsec Pulse low duration for LUT 108.1 -- nsec tdst Data setup time 0.3 -- nsec tdht Data hold time 6.4 -- nsec Read falling edge to Data valid for Registers -- 12.2 nsec Read falling edge to Data valid for Memory -- 122.1 Read falling edge to Data valid for LUT -- 108.1 todh (See note) Read hold time 10.7 32.1 For maximum CL=30pF nsec For minimum CL=8pF nsec tddt (See note) Read falling edge to Data driven 3.0 12.3 nsec trat (See note) nsec SYSCLK = 48MHz, PCLK = 12MHz, CLKI = 12MHz 1. twrh min = long enough to satisfy twc 2. trdh min = long enough to satisfy trc S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 113 19.2.2 Host Bus Timing for 800x480 TFT Panel Table 19-5: Intel 80 Input A.C. Characteristics (800x480 Panel Timings) Signal D/C# CS# WE# Symbol Parameter MD[15:0] Max Unit tast Address setup time 1.4 -- nsec taht Address hold time 0.3 -- nsec tcs Chip Select setup time (write) 0.6 + twrl -- nsec trcs Chip Select setup time (read) 1.3 + trdl -- nsec tcsf Chip Select Wait time 9.2 -- nsec twc Write cycle (rising edge to next rising edge) 34.8 -- nsec twrh Pulse high duration Note 1 -- twrl Pulse low duration 0.1 -- nsec 34.8 -- nsec trc Read cycle for Memory 102.7 + trdh -- nsec nsec Read cycle for Registers RD# Min Read cycle for LUT 92.5 + trdh -- trdh Pulse high duration Note 2 -- Pulse low duration for Registers 10.2 -- nsec trdl Pulse low duration for Memory 102.7 -- nsec Pulse low duration for LUT 92.5 -- nsec tdst Data setup time 0.3 -- nsec tdht Data hold time 6.4 -- nsec Read falling edge to Data valid for Registers -- 12.2 nsec Read falling edge to Data valid for Memory -- 102.7 Read falling edge to Data valid for LUT -- 92.5 Description todh (See note) Read hold time 10.7 32.1 For maximum CL=30pF nsec For minimum CL=8pF nsec tddt (See note) Read falling edge to Data driven 3.0 12.3 nsec trat (See note) nsec SYSCLK = 59 MHz, PCLK = 19.67 MHz, CLKI = 12MHz 1. twrh min = long enough to satisfy twc 2. trdh min = long enough to satisfy trc Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 114 Epson Research and Development Vancouver Design Center 19.3 Panel Timing t1 t2 VS t3 HS t4 HS t5 t8 t7 t6 DE t9 t12 t10 t11 t13 t14 t13 t14 PCLK REG[28h] b7=1 t9 t12 t10 t11 PCLK REG[28h] b7=0 t15 t16 VD[17:0] invalid 1 2 320 invalid 3-4 n+1 invalid Note: 1 pixel/clock Mode VD[35:0] invalid 1-2 Note: 2 pixels/clock Mode Figure 19-2: 18/36-Bit TFT A.C. Timing S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 115 19.3.1 Panel Timing for 352x416 Panel Table 19-6: 18/36-Bit TFT A.C. Timing (352x416 Panel Timing) Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 1. Ts Parameter VS cycle time VS pulse width low VS falling edge to HS falling edge phase difference HS cycle time HS pulse width low HS Falling edge to DE active DE pulse width DE falling edge to HS falling edge PCLK period PCLK pulse width low PCLK pulse width high HS setup to PCLK falling edge DE to PCLK rising edge setup time DE hold from PCLK rising edge Data setup to PCLK rising edge Data hold from PCLK rising edge Min 0 83.3 41.7 41.7 41.7 41.7 41.7 41.7 41.7 Typ 15.54 73.67 -- 36.83 1.67 3.75 29.3 3.75 -- -- -- -- -- -- -- -- Max -- -- 36.75 -- -- -- -- -- -- -- -- -- -- -- -- -- Units ms us us us us us us us ns ns ns ns ns ns ns ns = pixel clock period = 83.3 ns (12MHz PCLK) 19.3.2 Panel Timing for 800x480 Panel Table 19-3 18/36-Bit TFT A.C. Timing (800x480 Panel Timings) Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 1. Ts Parameter VS cycle time VS pulse width low VS falling edge to HS falling edge phase difference HS cycle time HS pulse width low HS Falling edge to DE active DE pulse width DE falling edge to HS falling edge PCLK period PCLK pulse width low PCLK pulse width high HS setup to PCLK falling edge DE to PCLK rising edge setup time DE hold from PCLK rising edge Data setup to PCLK rising edge Data hold from PCLK rising edge Min 0 50.84 25.42 25.42 25.42 25.42 25.42 25.42 25.42 Typ 20.34 83.4 -- 41.68 1.02 966 40.67 50.84 -- -- -- -- -- -- -- -- Max -- -- 41.63 -- -- -- -- -- -- -- -- -- -- -- -- -- Units ms us us us us ns us ns ns ns ns ns ns ns ns ns = pixel clock period = 50.84 (19.67 PCLK) Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 116 Epson Research and Development Vancouver Design Center 19.4 Example Play.exe Scripts The following example scripts are written for the PLAY.EXE program. The script Demo.txt will initialize the S1D13742, then display horizontal bars at different rotations, and then display a PIP+ window. Demo.txt verbose cmd:off out:on set:off halt 0 '============================================================================== ' _DEMO_.txt - Play script for 13742 to demonstrate various features. ' ' This demonstration code is written in the Play.exe script language so that ' various steps can be easily observed. Some steps such as the initialization ' and the memory fills use Play intrinsic commands. These operation of these ' commands are easily determined. '============================================================================== ' Initialize the registers to the default state by ' running the register list generated by 13742CFG '---------------------------------------------------------init ' Set the window to the full screen and clear the display '---------------------------------------------------------SetWin.txt f WIN 0 ' ROTATE 0 '---------------------------------------------------------print "Color bars at SwivelView 0\n" x 34 0 DrawBarsA.txt Pause.txt ' ROTATE 90 ' NOTE: There is a bug with the Fill WINdow command in ' Play which causes the 90 and 270 degree fills ' to be filled incorrectly. This will be corrected. '---------------------------------------------------------print "Color bars at SwivelView 90\n" x 34 1 DrawBarsB.txt Pause.txt ' ROTATE 180 '---------------------------------------------------------print "Color bars at SwivelView 180\n" x 34 2 S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 117 DrawBarsA.txt Pause.txt ' ROTATE 270 ' NOTE: There is a bug with the Fill WINdow command in ' Play which causes the 90 and 270 degree fills ' to be filled incorrectly. This will be corrected. '---------------------------------------------------------print "Color bars at SwivelView 270\n" x 34 3 DrawBarsB.txt Pause.txt ' PIP '---------------------------------------------------------print "Draw Color bars in a PIP (small window)\n" x 34 0 SetWin.txt f WIN 0 DrawBarsA.txt DrawPIP.txt 50 50 100 128 Pause.txt section END Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 118 Epson Research and Development Vancouver Design Center DrawBarsA.txt verbose cmd:off out:on set:off '============================================================================== ' DrawBars.txt - Play script for the 13742 ' ' This script draws eight equally sized horizontal ' bars on the display. '============================================================================== set set set set set set $Height $Lines $StartX $StartY $EndX $EndY set $Color set $Bars ((reg[1C] << 8) + (reg[1A])) ($Height / 8) 0 0 width $Lines 0 8 section LOOP SetWin.txt $StartX $StartY $EndX $EndY f WIN $Color set $StartY ($StartY + $Lines) set $EndY ($EndY + $Lines) set $Color ($Color + 0821) set $Bars ($Bars - 1) if $Bars!=0 then goto LOOP S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 119 DrawBarsB.txt verbose cmd:off out:on set:off '============================================================================== ' DrawBarsB.txt - Play script for the 13742 ' ' This script draws horizontal bars in SwivelView 90 and SwivelView 270 ' display modes. '============================================================================== set set set set set set $Height $Lines $StartX $StartY $EndX $EndY set $Color set $Bars (reg[16] * 8) ($Height / 8) 0 0 height $Lines 0 8 section LOOP SetWin.txt $StartX $StartY $EndX $EndY f WIN $Color set $StartY ($StartY + $Lines) set $EndY ($EndY + $Lines) set $Color ($Color + 0821) set $Bars ($Bars - 1) if $Bars!=0 then goto LOOP Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 120 Epson Research and Development Vancouver Design Center DrawPIP.txt verbose cmd:off out:on set:off '============================================================================== ' DrawPIP.txt - Play script for the 13742 ' ' This script draws eight equally sized horizontal bars on the display. '============================================================================== set set set set $StartX arg[1].nt $StartY arg[2].nt $Width arg[3].nt $Height arg[4].nt set $Lines ($Height / 8) set $Color set $Bars 0 8 section LOOP SetWin.txt $StartX $StartY $Width $Lines f WIN $Color set $StartY ($StartY + $Lines) set $Color ($Color + 0821) set $Bars ($Bars - 1) if $Bars!=0 then goto LOOP Pause.txt verbose cmd:off out:on set:off halt 0 print "Paused . . . press any key to continue\n" input line S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 121 SetWin.txt verbose cmd:off out:on set:off '-----------------------------------------------------------------------------' SetWin.txt - Play script for the 13742 ' ' This script is functionally identical to the Play command 'win'. Call this ' script to set the 13742 window co-ordinates as specified by the arguments. ' ' Syntax: SetWin X Y W H ' Where: X - Left edge window X position ' Y - Top edge window Y position ' W - Window width ' H - Window height ' ' Example: SetWin 0 0 100 100 ' Sets the window to start at 0,0 and end at 100, 100 ' ' SetWin ' Sets the window size to the size of the display ' ' win SX:0 SY:0 EX:width EY:height '-----------------------------------------------------------------------------' Set the default window values to the display size. set $SX 0 set $SY 0 set $EX (width - 1) SET $EY (height - 1) ' Use non-default values ONLY if all four arguments are given if (argn!=5) then goto SETWINDOW set set set set $SX $SY $EX $EY arg[1].n arg[2].n (arg[1].n + arg[3].n - 1) (arg[2].n + arg[4].n - 1) section SETWINDOW ' Change the register window settings x 38 $SX x 3A ($SX >> 8) x 3C $SY x 3E ($SY >> 8) x 40 $EX x 42 ($EX >> 8) x 44 $EY x 46 ($EY >> 8) Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 122 Epson Research and Development Vancouver Design Center 19.5 References 19.5.1 Documents * Sanyo Electric Co., Ltd. Display Company, LC13015 Low Temperature P-Si TFT-LCD Specification, Document Number LC13015-040302 * Epson Research and Development, Inc., S1D13742 Hardware Functional Specification, Document Number X63A-A-001-xx. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 123 20 PLL Power Supply Considerations The PLL circuit is an analog circuit which is very sensitive to noise on the input clock waveform or the power supply. Noise on the clock or the supplied power may cause the operation of the PLL circuit to become unstable or increase the jitter. Due to these noise constraints, it is highly recommended that the power supply traces or the power plane for the PLL be isolated from those of other power supplies. Filtering should also be used to keep the power as clean as possible. The following are guidelines which, if followed, will result in cleaner power to the PLL, this will result in a cleaner and more stable clock. Even a partial implementation of these guidelines will give results. 20.1 Guidelines for PLL Power Layout The PLL circuit is an analog circuit and is very sensitive to noise on the input clock waveform or the power supply. Noise on the clock or the supplied power may cause the operation of the PLL circuit to become unstable or increase the jitter. Due to these noise constraints, it is highly recommended that the power supply traces or the power plane for the PLL be isolated from those of other power supplies. Filtering should also be used to keep the power as clean as possible. The following are guidelines which, if followed, will result in cleaner power to the PLL, resulting in a cleaner and more stable clock. Even a partial implementation of these guidelines will give results. Optional, but recommended To Digital IOVDD Plane L1 Voltage Regulator PLL power traces must split from the digital traces very close to the regulator PLLVDD C3 C2 C1 S1D13742 PLLVSS L2 To Digital VSS Plane Notes: * PLLVDD and PLLVSS traces should be as short as possible * PLLVDD and PLLVSS must be separated from the digital supply * Digital power and ground to L1 and L2 should be short parallel traces on the same side of the board to reduce any loop area that can induce noise Typical Values: L1, L2 isolation bead C1 ~10uf bypass C2 1nf bypass C3 .1uf bypass Actual values may be different and subject to validation Figure 20-1: PLL Power Layout Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 124 Epson Research and Development Vancouver Design Center * Place the ferrite beads (L1 and L2) parallel to each other with minimal clearance between them. Both bypass caps (C2 and C3) should be as close as possible to the inductors. The traces from C3 to the power planes should be short parallel traces on the same side of the board with just the normal small clearance between them. Any significant loop area here will induce noise. If there is a voltage regulator on the board, try to run these power traces directly to the regulator instead of dropping to the power planes (still follow above rules about parallel traces). * The analog ground point where bypass cap (C2) connects to the ground isolation inductor (L2) becomes the analog ground central point for a ground star topology. None of the components connect directly to the analog ground pin of the MGE (PLLVSS) except for a single short trace from C2 to the PLLVSS pin. The ground side of the large bypass capacitor (C1) should also have a direct connection to the star point. * The same star topology rules used for analog ground apply to the analog power connection where L2 connects to C2. * All of the trace lengths should be as short as possible. * If possible, have all the PLL traces on the same outside layer of the board. The only exception is C1, which can be put on the other side of the board if necessary. C1 does not have to be as close to the analog ground and power star points as the other components. * If possible, include a partial plane under the PLL area only (area under PLL components and traces). The solid analog plane should be grounded to the C2 (bypass) pad. This plane won't help if it is too large. It is strictly an electrostatic shield against coupling from other layers' signals in the same board area. If such an analog plane is not possible, try to have the layer below the PLL components be a digital power plane instead of a signal layer. * If possible, keep other board signals from running right next to PLL pin vias on any layer. * Wherever possible use thick traces, especially with the analog ground and power star connections to either side of C2. Try to make them as wide as the component pads - thin traces are more inductive. It is likely that manufacturing rules will prohibit routing the ground and power star connections as suggested. For instance, four wide traces converging on a single pad could have reflow problems during assembly because of the thermal effect of all the copper traces around the capacitor pad. One solution might be to have only a single trace connecting to the pad and then have all the other traces connecting to this wide trace a minimum distance away from the pad. Another solution might be to have the traces connect to the pad, but with thermal relief around the pad to break up the copper connection. Ultimately the board must also be manufacturable, so best effort is acceptable. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 125 21 Mechanical Data TOP VIEW 8.00.20 A1 corner SIDE VIEW 0.65 8.00.20 0.75 0.65 L K J H G F E D C B A A1 corner 0.75 0.30.05 BOTTOM VIEW 1.0 max. 0.280.05 Die Size Die Size 1 2 3 4 5 6 7 8 9 1011 units = mm Figure 21-1: S1D13742 FCBGA 121-pin Package Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 126 Epson Research and Development Vancouver Design Center HD D 108 73 109 HE E 72 INDEX 37 144 1 e b 36 Amax A2 c A1 yS L L1 Symbol Dimension in Millimeters Min Nom E -- 20 Max -- D -- 20 -- -- HE -- 22 HD -- 22 -- Amax -- -- 1.7 A1 -- 0.1 -- A2 -- 1.4 -- e -- 0.5 -- b 0.17 -- 0.27 c 0.09 -- 0.2 0 -- 10 L 0.3 -- 0.75 L1 -- 1 -- y -- -- 0.08 units = mm Figure 21-2: S1D13742 QFP20 144-pin Package S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 127 units = mm Number of row and column not fixed Y Index Mark Package Center Line 3.18 2.28 2.2 (15) (6) (21) (16) (7) B (22) (17) (8) D D (19) (24) B A C A = 0.3 (10) (18) (23) B C (9) D A X' 0.8 (20) B D EE JAP A N D C (1) D (5) (14) (4) (13) (3) (12) B (2) (11) B D 0.8 2.13 D 74 2 B D B 3.03 X B = 0.4 C = 0.6 A 0.74 D = 0.1 E = 0.2 Package Center Line Item Logo Specified Device Name Die Revision Code Package Type Process and Package Revision Code [Blank] Control Code Year of Manufacture Y' No. (1) (2) ~ (5) (6) (7) (8) (9) ~ (10) (11) ~ (19) (12) ~ (13) Month of Manufacture (14) ~ (15) W/F Lot No. (16) ~ (19) (20) ~ (24) JAPAN Notes C: FCBGA Last two numbers of A.D. 1-9: Jan - Sep x: Oct, Y: Nov, Z: Dec Figure 21-3: S1D13742 FCBGA 121-pin Package Marking Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 128 Epson Research and Development Vancouver Design Center units = mm Y X Y X' Package Center Line Pin 1 Y' 8.0 (1) 0.3 (2) (3) (4) (5) (6) 2.0 1.2 A B X (7) (8) (9) (10) (11) (12) (13) A B (14) A B (15) A B A (16) (17) (18) (19) A X' 1.5 C B C B C B C B (20) C B (21) C (22) B D D B (23) C (24) B (25) C B (26) C B (27) C B C B C A (28) 1.2 Package Center Line A B A B A B A B A B A B A B A B A A = 0.8 B = 0.25 C = 1.0 D = 0.5 Y' Item Logo Specified JAPAN Device Name Control Code Year of Manufacture Week of Manufacture W/F Lot No. No. (1) (2) ~ (6) (7) ~ (19) (20) ~ (28) (21) ~ (22) (23) ~ (24) (25) ~ (28) Notes EPSON S1D13742F01A2 Last two numbers of A.D. Calendar Week of the Year Figure 21-4: S1D13742 QFP 144-pin Package Marking S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 129 22 References The following documents contain additional information related to the S1D13742. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com. * S1D13742 Product Brief (X63A-C-001-xx) * S5U13742P00C100 Evaluation Board User Manual (X63A-G-002-xx) Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 130 Epson Research and Development Vancouver Design Center 23 Sales and Technical Support AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. HEADQUARTERS EPSON (CHINA) CO., LTD. 2580 Orchard Parkway San Jose , CA 95131,USA Phone: +1-800-228-3964 23F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: +86-10-6410-6655 FAX: +86-10-6410-7320 FAX: +1-408-922-0238 SHANGHAI BRANCH SALES OFFICES Northeast 7F, High-Tech Bldg., 900, Yishan Road, Shanghai 200233, CHINA Phone: +86-21-5423-5522 FAX: +86-21-5423-5512 301 Edgewater Place, Suite 210 Wakefield, MA 01880, U.S.A. Phone: +1-800-922-7667 FAX: +1-781-246-5443 EPSON HONG KONG LTD. EUROPE EPSON EUROPE ELECTRONICS GmbH HEADQUARTERS Riesstrasse 15 80992 Munich, GERMANY Phone: +49-89-14005-0 FAX: +49-89-14005-110 20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 FAX: +852-2827-4346 Telex: 65542 EPSCO HX EPSON Electronic Technology Development (Shenzhen) LTD. 12/F, Dawning Mansion, Keji South 12th Road, Hi- Tech Park, Shenzhen Phone: +86-755-2699-3828 FAX: +86-755-2699-3838 EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110 Phone: +886-2-8786-6688 FAX: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD. 1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore 098633 Phone: +65-6586-5500 FAX: +65-6271-3182 SEIKO EPSON CORPORATION KOREA OFFICE 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: +82-2-784-6027 FAX: +82-2-767-3677 GUMI OFFICE 2F, Grand B/D, 457-4 Songjeong-dong, Gumi-City, KOREA Phone: +82-54-454-6027 FAX: +82-54-454-6093 SEIKO EPSON CORPORATION SEMICONDUCTOR OPERATIONS DIVISION IC Sales Dept. IC International Sales Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-42-587-5814 FAX: +81-42-587-5117 23.1 Ordering Information To order the S1D13742 Mobile Graphics Engine, contact the Epson sales representative in your area. S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 Epson Research and Development Vancouver Design Center Page 131 Change Record X63A-A-001-06 Revision 6.2 - Issued: 2008/07/07 * all changes from the last revision of the spec are highlighted in Red * Set revision to 6.2 to align with Japan revision numbering * section 8.4 Setting SYSCLK and PCLK - add CLKI information to this section X63A-A-001-06 Revision 6.01 - Issued: 2007/09/18 * all changes from the last revision of the spec are highlighted in Red * section 5.1, for the Intel 80 Data Pin Mapping tables, swapped the MD[15:8] descriptions for CNF1=0, B00 should be "internal resistors" and B01 should be "Hi-Z" * section 7.3.1 ~ 7.3.2, added note and clarified the usage of MD[15:8] pins in the Host Timing figures and tables * section 17.1.3, updated the X/Y Start/End data order in the Sequential Memory Write Example Sequence figure and moved it to section 17.1.3 * section 22, added References * section 23, added Sales and Technical Support addresses X63A-A-001-06 Revision 6.0 (Issued 2007/05/29) * all changes from the last revision of the spec are highlighted in Red * section 14 Gamma Correction Look-Up Table Architecture - correct typos in Figure 14 1; change data from display buffers to 6 bit, change the multiplexers to 64 positions from 256 * section 19.1.3 S1D13742 Register Settings for 800x480 TFT Panel - correct typo in Table 19-3, change the REG[04h] value to 0Bh X63A-A-001-05 Revision 5.02 (Issued 2006/08/23) * all changes from the last revision of the spec are highlighted in Red * globally add QFP20 144-pin package information * section 5.3 LCD Interface Data Pins - correct typos in table, change Hi-Z to Driven Low * section 6.3 Electrical Characteristics - add table 6-5 Electrical Characteristics for IOVDD or PIOVDD = 3.3V 0.3V * section 7.2 RESET# Timing - add CLKI signal to figure * section 7.3.1 Intel 80 Interface Timing - 1.8 Volt - rewrite section for 1.8 volts * section 7.3.2 Intel 80 Interface Timing - 3.3 Volt - add this section * REG[2Ah] bits 4-0 - add note "RGB 6:6:6 mode 2 and RGB 8:8:8 mode 2..." X63A-A-001-05 Revision 5.01 (Issued 2006/04/28) Hardware Functional Specification Issue Date: 2008/07/07 S1D13742 X63A-A-001-06 Revision 6.2 Page 132 Epson Research and Development Vancouver Design Center * updated EPSON tagline * all changes from the last revision of the spec are highlighted in Red * section 4.2.1 Intel 80 Host Interface - for MD[15:0] rewrite the note in pin description, for GPIO_INT add reference to General Purpose IO Pins Registers to pin description. * section 4.2.2 LCD Interface - for VD[35:0] rewrite both notes in pin description * section 4.2.4 Miscellaneous - for GPIO[7:0] rewrite pin description, for PWRSVE rewrite pin description for no pull-down resistor * section 4.2.4, change SCANEN pin description IO Voltage from "VSS" to "IOVDD" * section 7.2 RESET# Timing - add this section * section 17.1.2 and 17.1.5, for the Host Interface section changed the references in the figures from "D[15:0]" to "MD[15:0]" * fixed typo in change record, document numbers should be listed as "X63..." instead of "X59..." * section 6.3 Electrical Characteristics - in tables 6-3 and 6-4, define the conditions for Quiescent Current X63A-A-001-04 Revision 4.0 (Issued 2005/11/29) * section 7.3.3 18/36-Bit TFT Panel Timing - correct typos in figure 7-8 18/36-Bit TFT A/C Timing - change references to REG[2Ah] to REG[28h], change t17 reference to falling edge of VS, and in table 7-7 18/36-Bit TFT A/C Timing change PCLK edge references to "active" S1D13742 X63A-A-001-06 Hardware Functional Specification Issue Date: 2008/07/07 Revision 6.2 GRAPHICS S1D13742 S1D13742 Mobile Graphics Engine August 2007 The S1D13742 is a color LCD graphics controller with an embedded 768K byte display buffer. The S1D13742 supports a 8/16-bit Intel 80 CPU architecture while providing high performance bandwidth into display memory allowing for fast screen updates. Products requiring a rotated display image can take advantage of the SwivelViewTM feature which provides hardware rotation of the display memory transparent to the software application. Resolutions supported include 800x480 single buffered and 352x416 double buffered. The S1D13742 uses a double-buffer architecture to prevent any visual tearing during streaming video screen updates. FEATURES * Embedded 768K byte SRAM Display Buffer * Low Operating Voltage * 8/16-bit Intel 80 interface (used for display or regis* * * * * ter data). RGB: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or 18 bpp). YUV 4:2:2, 4:2:0 (Internal YUV to RGB Converter stored as 16 or 18 bpp). Active Matrix TFT interface - 18/36-bit interface. Supports resolutions up to 800x480. Hardware / Software Power Save mode. * 16/18 bit-per-pixel (bpp) color depths. * SwivelViewTM: 90, 180, 270 counter-clockwise hardware rotation of display image * Double-Buffer available to prevent image tearing during streaming input * Pixel Doubling: Horizontal and Vertical averaging * * * * for smooth doubling of a single window Pixel Halving: no limitation on number of windows Internal programmable PLL. Single MHz clock input: CLKI. General Purpose Input/Output pins. SYSTEM BLOCK DIAGRAM Active Matrix TFT Display 13742 Data and Control Signals CPU X63A-C-001-03 Revision 3.01 S1D13742 Includes: * 768K Bytes SRAM * Pixel Doubling * Pixel Halving * SwivelviewTM 1 GRAPHICS S1D13742 DESCRIPTION Integrated Frame Buffer * Digital Video * Embedded 768K byte SRAM display buffer. CPU Interface * * * 8/16-bit Intel 80 interface (used for display or register data). Chip select is used to select device. When inactive, any input data/command will be ignored. Panel Support * * * * * * * * * * * Display Features * * * Active Matrix TFT interface. 18/36-bit interface. Supports resolutions up to 800x480. Miscellaneous * Internal programmable PLL. Single MHz clock input: CLKI. CLKI available as CLKOUT (separate CLKOUTEN pin associated with output). Hardware / Software Power Save mode. Input pin to Enable/Disable Power Save Mode. General Purpose Input/Output pins are available (GPIO[7:0]). COREVDD 1.5 volts and IOVDD 1.65 ~ 3.6 volts FCBGA 121-pin or QFP20 144-pin package RGB: 8:8:8, 6:6:6, 5:6:5 (8:8:8 will be truncated to 16 or 18 bpp). YUV 4:2:2, 4:2:0 (Internal YUV to RGB Converter stored as 16 or 18 bpp). * * * 16/18 bit-per-pixel (bpp) color depths. 16 bpp to 18 bpp Input Data conversion. All display writes are handled by window apertures/position for complete or partial display updates. All window coordinates are referenced to top left corner of the displayed image (even in a rotated display, the top-left corner is maintained and no host side translation need take place). SwivelViewTM: 90, 180, 270 counter-clockwise hardware rotation of display image. All displayed windows can have independent rotation. No additional programming necessary when enabling these modes. Double-Buffer available to prevent image tearing during streaming input. Resolutions supported must fit inside 384K bytes (1/2 of total available display buffer). Typical resolution of 352x416. Pixel Doubling: Horizontal and Vertical averaging for smooth doubling of a single window. Pixel Halving: no limitation on number of windows. CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS * S1D13742 Technical Documentation * S1D13742 Evaluation Boards * CPU Independent Software Utilities * Royalty Free source level driver code Japan Seiko Epson Corporation IC International Sales Group 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp/ North America Epson Electronics America, Inc. 2580 Orchard Parkway San Jose, CA 95131, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com/ Taiwan Epson Taiwan Technology & Trading Ltd. 14F, No. 7 Song Ren Road Taipei 110 Tel: 02-8786-6688 Fax: 02-8786-6677 http://www.epson.com.tw/ Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 http://www.epson.com.hk/ Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 http://www.epson-electronics.de/ Singapore Epson Singapore Pte Ltd 1 HarbourFront Place #03-02 HarbourFront Tower One Singapore, 098633 Tel: (65) 6586-5500 Fax: (65) 6271-3182 http://www.epson.com.sg/ (c)SEIKO EPSON CORPORATION 2005 - 2007. All rights reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. 2 Revision 3.01 X63A-C-001-03