HCPL-0723 - Agilent / Hewlett-Packard

Agilent HCPL-7723 & HCPL-0723

50 MBd 2 ns PWD

High Speed CMOS Optocoupler

Data Sheet

Description

Available in either 8-pin DIP or

SO-8 package style respectively, the

HCPL-7723 or HCPL-0723

optocoupler utilize the latest CMOS

IC technology to achieve out-

standing speed performance of

minimum 50 MBd data rate and

2 ns maximum pulse width

distortion.

Basic building blocks of HCPL-

7723/0723 are a CMOS LED

driver IC, a high speed LED and a

CMOS detector IC. A CMOS logic

input signal controls the LED

driver IC, which supplies current

to the LED. The detector IC

incorporates an integrated

photodiode, a high speed

transimpedance amplifier, and a

voltage comparator with an

output driver.

Functional Diagram

SHIELD 5

**VDD1

GND1

VDD2**

GND2

VI, INPUT LED1

OFF

TRUTH TABLE

(POSITIVE LOGIC)

NC*

LED1

VO, OUTPUT

* PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT

UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE.

PIN 7 IS NOT CONNECTED INTERNALLY.

** A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN

PINS 1 AND 4, AND 5 AND 8.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of

this component to prevent damage and/or degradation, which may be induced by ESD.

•

Features

• +5 V CMOS compatibility

• High speed: 50 MBd min.

• 2 ns max. pulse width distortion

• 22 ns max. prop. delay

• 16 ns max. prop. delay skew

• 10 kV/µs min. common mode

rejection

• –40 to 85°C temperature range

• Safety and regulatory approvals

(Pending)

UL recognized

– 3750 V rms for 1 min. per UL1577

CSA component acceptance

notice #5

IEC/EN/DIN EN 60747-5-2

– Viorm = 630 Vpeak for HCPL-7723

option 060

– Viorm = 560 Vpeak for HCPL-0723

option 060

Applications

• Digital fieldbus isolation: CC-Link,

DeviceNet, Profibus, SDS

Isolated A/D or D/A conversion

• Multiplexed data transmission

• High Speed Digital Input/Output

• Computer peripheral interface

• Microprocessor system interface

Package Outline Drawings

HCPL-7723 8-Pin DIP Package

9.65 ± 0.25

(0.380 ± 0.010)

1.78 (0.070) MAX.

1.19 (0.047) MAX.

A XXXXV

YYWW

DATE CODE

1.080 ± 0.320

(0.043 ± 0.013) 2.54 ± 0.25

(0.100 ± 0.010)

0.51 (0.020) MIN.

0.65 (0.025) MAX.

4.70 (0.185) MAX.

2.92 (0.115) MIN.

DIMENSIONS IN MILLIMETERS AND (INCHES).

5678

4321

5° TYP. 0.254 + 0.076

- 0.051

(0.010+ 0.003)

- 0.002)

7.62 ± 0.25

(0.300 ± 0.010)

6.35 ± 0.25

(0.250 ± 0.010)

TYPE NUMBER

*OPTION 300 AND 500 NOT MARKED.

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.

OPTION 060 CODE*

3.56 ± 0.13

(0.140 ± 0.005)

HCPL-7723 Package with Gull Wing Surface Mount Option 300

HCPL-0723 Small Outline SO-8 Package

0.635 ± 0.25

(0.025 ± 0.010) 12° NOM.

9.65 ± 0.25

(0.380 ± 0.010)

0.635 ± 0.130

(0.025 ± 0.005)

7.62 ± 0.25

(0.300 ± 0.010)

9.65 ± 0.25

(0.380 ± 0.010)

6.350 ± 0.25

(0.250 ± 0.010)

1.016 (0.040)

1.27 (0.050)

10.9 (0.430)

2.0 (0.080)

LAND PATTERN RECOMMENDATION

1.080 ± 0.320

(0.043 ± 0.013)

3.56 ± 0.13

(0.140 ± 0.005)

1.780

(0.070)

MAX.

1.19

(0.047)

MAX.

2.54

(0.100)

BSC

DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.

0.254 + 0.076

- 0.051

(0.010+ 0.003)

- 0.002)

XXXV

YWW

8765

4321

5.994 ± 0.203

(0.236 ± 0.008)

3.937 ± 0.127

(0.155 ± 0.005)

0.406 ± 0.076

(0.016 ± 0.003) 1.270

(0.050)BSC

5.080 ± 0.127

(0.200 ± 0.005)

3.175 ± 0.127

(0.125 ± 0.005) 1.524

(0.060)

45° X 0.432

(0.017)

0.228 ± 0.025

(0.009 ± 0.001)

TYPE NUMBER

(LAST 3 DIGITS)

DATE CODE

0.305

(0.012)MIN.

TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)

5.207 ± 0.254 (0.205 ± 0.010)

DIMENSIONS IN MILLIMETERS (INCHES).

LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.

OPTION NUMBER 500 NOT MARKED.

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.

0.203 ± 0.102

(0.008 ± 0.004)

7°

PIN ONE

0 ~ 7°

7.49 (0.295)

1.9 (0.075)

0.64 (0.025)

LAND PATTERN RECOMMENDATION

Device Selection Guide

8-Pin DIP (300 mil) Small Outline SO-8

HCPL-7723 HCPL-0723

Ordering Information

Specify Part Number followed by Option Number (if desired)

Example:

HCPL-7723-XXXX

060 = IEC/EN/DIN EN 60747-5-2 Option.

300 = Gull Wing Surface Mount Option (HCPL-7723 only).

500 = Tape and Reel Packaging Option.

XXXE = Lead Free Option.

No Option and Option 300 contain 50 units (HCPL-7723), 100 units (HCPL-0723) per tube. Option 500

contain 1000 units (HCPL-7723), 1500 units (HCPL-0723) per reel. Option data sheets available. Contact

sales representative or authorized distributor.

Solder Reflow Temperature Profile Regulatory Information

The HCPL-7723/0723 have been

approved by the following

organizations:

Recognized under UL1577,

component recognition program,

File E55361.

CSA

Approved under CSA Component

Acceptance Notice #5, File

CA88324.

IEC/EN/DIN EN 60747-5-2

Approved under:

IEC 60747-5-2:1997+A1:2002/

EN 60747-5-2:2001+A1:2002/

DIN EN 60747-5-2 (VDE 0884

Teil 2): 2003-01.

(Option 060 only)

Insulation and Safety Related Specifications

Value

Parameter Symbol 7723 0723 Units Conditions

Minimum External Air Gap L(I01) 7.1 4.9 mm Measured from input terminals to output

(Clearance) terminals, shortest distance through air.

Minimum External Tracking L(I02) 7.4 4.8 mm Measured from input terminals to output

(Creepage) terminals, shortest distance path along body.

Minimum Internal Plastic Gap 0.08 0.08 mm Insulation thickness between emitter and

(Internal Clearance) detector; also known as distance through

insulation.

Tracking Resistance CTI ≥ 175 ≥ 175 Volts DIN IEC 112/VDE 0303 Part 1

(Comparative Tracking Index)

Isolation Group IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

TIME (SECONDS)

TEMPERATURE (°C)

200

100

50 150100 200 250

300

SEC.

50 SEC.

SEC.

160°C

140°C

150°C

PEAK

TEMP.

245°C

PEAK

TEMP.

240°C

PEAK

TEMP.

230°C

SOLDERING

TIME

200°C

PREHEATING TIME

150°C, 90 + 30 SEC.

2.5°C ± 0.5°C/SEC.

3°C + 1°C/–0.5°C

TIGHT

TYPICAL

LOOSE

ROOM

TEMPERATURE

PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.

REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.

Recommended Pb-Free IR Profile

217 °C

RAMP-DOWN

6 °C/SEC. MAX.

RAMP-UP

3 °C/SEC. MAX.

150 - 200 °C

260 +0/-5 °C

t 25 °C to PEAK

60 to 150 SEC.

20-40 SEC.

TIME WITHIN 5 °C of ACTUAL

PEAK TEMPERATURE

PREHEAT

60 to 180 SEC.

smax

smin

TIME

TEMPERATURE

NOTES:

THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.

smax

= 200 °C, T

smin

= 150 °C

All Agilent data sheets report the

creepage and clearance inherent

to the optocoupler component

itself. These dimensions are

needed as a starting point for the

equipment designer when

determining the circuit insulation

requirements. However, once

mounted on a printed circuit

board, minimum creepage and

clearance requirements must be

met as specified for individual

equipment standards. For

creepage, the shortest distance

path along the surface of a

printed circuit board between the

solder fillets of the input and

output leads must be considered.

There are recommended

techniques such as grooves and

ribs, which may be used on a

printed circuit board to achieve

desired creepage and clearances.

Creepage and clearance distances

will also change depending on

factors such as pollution degree

and insulation level.

IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060)

HCPL-7723 HCPL-0723

Description Symbol Option 060 Option 060 Units

Installation classification per DIN VDE 0110/1.89, Table 1

for rated mains voltage ≤ 150 V rms I-IV I-IV

for rated mains voltage ≤ 300 V rms I-IV I-III

for rated mains voltage ≤ 450 V rms I-III

Climatic Classification 55/85/21 55/85/21

Pollution Degree (DIN VDE 0110/1.89) 2 2

Maximum Working Insulation Voltage VIORM 630 560 V peak

Input to Output Test Voltage, Method b* VPR 1181 1050 V peak

VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,

Partial Discharge < 5 pC

Input to Output Test Voltage, Method a* VPR 945 840 V peak

VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec,

Partial Discharge < 5 pC

Highest Allowable Overvoltage* VIOTM 6000 4000 V peak

(Transient Overvoltage, tini = 10 sec)

Safety Limiting Values (maximum values allowed in the

event of a failure, also see Thermal Derating curve,

Figure 11)

Case Temperature TS175 150 °C

Input Current IS,INPUT 230 150 mA

Output Power PS,OUTPUT 600 600 mW

Insulation Resistance at TS, VIO = 500 V RIO ≥ 109≥ 109Ω

*Refer to the front of the optocoupler section of the

Isolation and Control Component Designer’s Catalog

, under Product Safety Regulations section

IEC/EN/DIN EN 60747-5-2, for a detailed description.

Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be

ensured by means of protective circuits.

Note: The surface mount classification is Class A in accordance with CECC 00802.

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units

Storage Temperature TS–55 125 °C

Ambient Operating Temperature[1] TA–40 85 °C

Supply Voltages VDD1, VDD2 0 6.0 Volts

Input Voltage VI –0.5 VDD1 +0.5 Volts

Output Voltage VO–0.5 VDD2 +0.5 Volts

Average Output Current IO10 mA

Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane

Solder Reflow Temperature Profile See Solder Reflow Temperature Profile Section

Recommended Operating Conditions

Parameter Symbol Min. Max. Units

Ambient Operating Temperature TA–40 85 °C

Supply Voltages VDD1, VDD2 4.5 5.5 V

Logic High Input Voltage VIH 2.0 VDD1 V

Logic Low Input Voltage VIL 0.0 0.8 V

Input Signal Rise and Fall Times tr, tf1.0 ms

Electrical Specifications

Test conditions that are not specified can be anywhere within the recommended operating range.

All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V.

Parameter Symbol Min. Typ. Max. Units Test Conditions

Logic Low Input Supply Current[2] IDD1L 710mAV

I = 0 V

Logic High Input Supply Current[2] IDD1H 1.8 3 mA VI = VDD1

Output Supply Current IDD2L 12.5 17.5 mA

IDD2H 12 16.5 mA

Input Current II–10 10 µA

Logic High Output Voltage VOH 4.4 5.0 V IO = –20 µA, VI = VIH

4.0 4.8 V IO = –4 mA, VI = VIH

Logic Low Output Voltage VOL 0 0.1 V IO = 20 µA, VI = VIL

0.5 1.0 V IO = 4 mA, VI = VIL

Switching Specifications

Test conditions that are not specified can be anywhere within the recommended operating range.

All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V.

Parameter Symbol Min. Typ. Max. Units Test Conditions

Propagation Delay Time to Logic tPHL 16 22 ns CL = 15 pF CMOS Signal Levels

Low Output[3]

Propagation Delay Time to Logic tPLH 16 22 ns CL = 15 pF CMOS Signal Levels

High Output[3]

Pulse Width PW 20 ns CL = 15 pF CMOS Signal Levels

Maximum Data Rate 50 MBd CL = 15 pF CMOS Signal Levels

Pulse Width Distortion[4] |tPHL - tPLH| |PWD| 1 2 ns CL = 15 pF CMOS Signal Levels

Propagation Delay Skew[5] tPSK 16 ns CL = 15 pF CMOS Signal Levels

Output Rise Time (10% – 90%) tR8nsC

L = 15 pF CMOS Signal Levels

Output Fall Time (90% - 10%) tF6nsC

L = 15 pF CMOS Signal Levels

Common Mode Transient Immunity |CMH| 10 15 kV/µsV

CM = 1000 V, TA = 25°C,

at Logic High Output[6] VI = VDD1, VO > 0.8 VDD2

Common Mode Transient Immunity |CML| 10 15 kV/µsV

CM = 1000 V, TA = 25°C,

at Logic Low Output[6] VI = 0 V, VO < 0.8 V

Package Characteristics

All Typical Specifications are at TA = 25°C.

Parameter Symbol Min. Typ. Max. Units Test Conditions

Input-Output Momentary –7723 VISO 3750 V rms RH ≤ 50%, t = 1 min,

–0723 3750 TA = 25°C

Input-Output Resistance[7] R I-O 10 12 ΩVI-O = 500 V dc

Input-Output Capacitance C I-O 0.6 pF f = 1 MHz

Input Capacitance[10] C I3.0 pF

Input IC Junction-to-Case –7723 θjci 145 °C/ W Thermocouple located at

Thermal Resistance center underside of package

Output IC Junction-to-Case –7723 θjco 145 °C/W

–0723 135

Package Power Dissipation PPD 150 mW

Notes:

1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not

guarantee functionality.

2. The LED is ON when VI is low and OFF when VI is high.

3. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal.

tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal.

4. PWD is defined as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.

5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within

the recommended operating conditions.

6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common

mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising and

falling common mode voltage edges.

7. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.

8. In accordance with UL1577, each HCPL-0723 is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detection

current limit, II-O ≤ 5 µA). Each HCPL-7723 is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (leakage detection

current limit. II-O ≤ 5 µA.)

9. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous

voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Agilent Application Note 1074 entitled

“Optocoupler Input-Output Endurance Voltage.”

10. CI is the capacitance measured at pin 2 (VI).

Withstand Voltage[7,8,9]

–0723 160

Thermal Resistance

Application Information

Bypassing and PC Board Layout

The HCPL-7723/0723

optocouplers are extremely easy

to use. No external interface

circuitry is required because the

HCPL-7723/0723 use high-speed

CMOS IC technology allowing

CMOS logic to be connected

directly to the inputs and outputs.

As shown in Figure 1, the only

external components required for

proper operation are two bypass

capacitors. Capacitor values

Figure 3. Timing diagram to illustrate propagation delay, tplh and tphl.

INPUT

tPLH tPHL

OUTPUT

VO10%

90%90%

10%

VOH

VOL

0 V

50%

5 V CMOS

2.5 V CMOS

Figure 1. Functional diagram.

should be between 0.01 µF and 0.1

µF. For each capacitor, the total

lead length between both ends of

the capacitor and the power-supply

pins should not exceed 20 mm.

Figure 2 illustrates the

recommended printed circuit

board layout for the HCPL-7723/

0723.

Propagation Delay, Pulse-Width

Distortion and Propagation Delay Skew

Propagation Delay is a figure of

merit which describes how quickly

a logic signal propagates through

Figure 2. Recommended printed circuit board layout.

a system as illustrated in Figure 3.

The propagation delay from low to

high (tPLH) is the amount of time

required for an input signal to

propagate to the output, causing

the output to change from low to

high. Similarly, the propagation

delay from high to low (tPHL) is

the amount of time required for

the input signal to propagate to

the output, causing the output to

change from high to low.

GND2

C1 C2

VDD2

NC VO

VDD1

HCPL-7723

HCPL-0723

C1, C2 = 0.01 µF TO 0.1 µF

GND1

DD2

C1 C2

HCPL-7723

HCPL-0723

GND

DD1

GND

C1, C2 = 0.01 µF TO 0.1 µF

Pulse-width distortion (PWD) is

the difference between tPHL and

tPHL and often determines the

maximum data rate capability of

a transmission system. PWD can

be expressed in percent by

dividing the PWD (in ns) by the

minimum pulse width (in ns)

being transmitted. Typically,

PWD on the order of 20-30% of

the minimum pulse width is

tolerable.

Propagation delay skew, tPSK, is

an important parameter to

consider in parallel data applica-

tions where synchronization of

signals on parallel data lines is a

concern. If the parallel data is

being sent through a group of

optocouplers, differences in

propagation delays will cause the

data to arrive at the outputs of

the optocouplers at different

times. If this difference in

propagation delay is large enough

it will determine the maximum

rate at which parallel data can be

sent through the optocouplers.

Propagation delay skew is defined

as the difference between the

minimum and maximum

propagation delays, either tPLH or

tPHL, for any given group of

optocouplers which are operating

under the same conditions (i.e.,

the same drive current, supply

voltage, output load, and

operating temperature). As

illustrated in Figure 4, if the

inputs of a group of optocouplers

are switched either ON or OFF at

the same time, tPSK is the

difference between the shortest

propagation delay, either tPLH or

tPHL, and the longest propagation

delay, either tPLH or tPHL.

As mentioned earlier, tPSK can

determine the maximum parallel

data transmission rate. Figure 5

is the timing diagram of a typical

parallel data application with

both the clock and data lines

being sent through the

optocouplers. The figure shows

data and clock signals at the

inputs and outputs of the

optocouplers. In this case the

data is assumed to be clocked off

of the rising edge of the clock.

Propagation delay skew

represents the uncertainty of

where an edge might be after

being sent through an

optocoupler. Figure 5 shows that

there will be uncertainty in both

the data and clock lines. It is

important that these two areas of

uncertainty not overlap,

otherwise the clock signal might

arrive before all of the data

outputs have settled, or some of

the data outputs may start to

change before the clock signal

has arrived. From these

considerations, the absolute

minimum pulse width that can be

sent through optocouplers in a

parallel application is twice tPSK.

A cautious design should use a

slightly longer pulse width to

ensure that any additional

uncertainty in the rest of the

circuit does not cause a problem.

The HCPL-7723/0723

optocouplers offer the advantage

of guaranteed specifications for

propagation delays, pulse-width

distortion, and propagation delay

skew over the recommended

temperature and power supply

ranges.

Figure 4. Timing diagram to illustrate propagation delay skew, tpsk.

50%

PSK

2.5 V,

CMOS

2.5 V,

CMOS

DATA

INPUTS

CLOCK

DATA

OUTPUTS

CLOCK

PSK

Figure 5. Parallel data transmission example.

www.agilent.com/semiconductors

For product information and a complete list of

distributors, please go to our web site.

For technical assistance call:

Americas/Canada: +1 (800) 235-0312 or

(916) 788-6763

Europe: +49 (0) 6441 92460

China: 10800 650 0017

Hong Kong: (+65) 6756 2394

India, Australia, New Zealand: (+65) 6755 1939

Japan: (+81 3) 3335-8152 (Domestic/Interna-

tional), or 0120-61-1280 (Domestic Only)

Korea: (+65) 6755 1989

Singapore, Malaysia, Vietnam, Thailand,

Philippines, Indonesia: (+65) 6755 2044

Taiwan: (+65) 6755 1843

Data subject to change.

Obsoletes 5989-0833EN

March 1, 2005

5989-2136EN