NMC9313B National Semiconductor NMC9313B 256-Bit Serial Electrically Erasable Programmable Memory General Description The NMC93138B is a 256-bit non-volatile sequential access memory fabricated using advanced floating gate N-channel E2PROM technology. It is a peripheral memory designed for data storage and/or timing and is accessed via the simple MICROWIRE serial interface. The device contains 256 bits of read/write memory divided into 16 registers of 16 bits each. Each register can be serially read or written by a COP400 series controller. Written information is stored in a floating gate cell with at least 10 years data retention and can be updated by an erase-write cycle. The NMC9313B has been designed to meet applications requiring up to 1 xX 104 erase/write cycles per register. A power down mode reduces power consumption by 67 percent. Features @ Low cost Single supply operation (6V + 10%) w TTL compatible @ 16X16 seria! read/write memory m MICROWIRE compatible serial |/O m Compatible with COP400 processors a 7 as Low standby power Non-volatile erase and write Reliable floating gate technology Block and Connection Diagrams PP vcc GENERATOR VPP EPROM 1/16 (16 x 16) 16 ADDRESS LATCHES R/W AMPS 16 DATA REGISTER (17 BITS) CLK INSTRUCTION REGISTER cLK (9 BITS) 2 INSTRUCTION DECODE. CONTROL AND CLOCK GENERATORS Dual-In-Line Package (N) cst1 YY 8}vcc sk4 2 7 hNC i{3 6 NE DO| 4 }GND TL/D/9145-2 Top View Order Number NMC9313B See NS Package Number NOSE Pin Names cs Chip Select SK Serial Data Clock 00 DI Serial Data Input DO Serial Data Output Vec Power Supply GND = Ground TL/D/9145=1 2-36Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage Relative to GND + 6V to 0.3V Ambient Operating Temperature NMC9313B/COP494 Ambient Storage Temperature with Data Retention OC to + 70C 65C to + 125C Lead Temperature (Soldering, 10 seconds) 300C ESD Rating 2000V Note: Stresses above those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicat- ed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics oc <tTa< 70c, Voc =5V + 10% untess otherwise specified Parameter Conditions Min Typ Max Units Operating Voltage (Vcc) 4.5 5.5 Vv Operating Current (Ic1) Voc =5.5V, CS=1 15 mA Standby Current (locz) Voc = 5.5V, CS=0 5 mA, Input Voltage Levels VIL 0.1 0.8 Vv VIH 2.0 Veco + 0.5 Vv Output Voltage Levels VoL loL=2.1 MA 0.4 Vv VOoH loH= 400 pA 2.4 Vv Input Leakage Current Vin = 5.5V 10 pA Output Leakage Current Vout=5.5V, CS=0 10 pA SK Frequency 0 200 kHz SK HIGH TIME tgxy (Note 2) 3 ps SK LOW TIME tex. (Note 2) 2 ps Input Set-Up and Hold Times cs tess 0.2 ps tcsH 9 BS DI tois 0.4 BS toi 0.4 ys Output Delay CL= 100 pF pO tp VoL =0.8V, VoH=2.0V 2 Bs tepo Vit = 0.45V, Vin=2.40V 2 ys Erase/Write Pulse Width (te;yw) (Note 1) 10 30 ms CS Low Time (tcg) (Note 3) 1 ps Note t: te;w measured to rising edge of SK or CS, whichever occurs last. Note 2: The SK frequency spec. specifies a minimum SK clock period of ps, therefore in an SK clock cycle, tgxH + tgk_ must be greater than or equal to 5 ys. og. if tsk. = 2 s then the minimum ts} = 3 48 in order to meat the SK frequency specification. Note 3: CS must be brought low for a minimum of 1 ws (tg) between consecutive instruction cycles. Instruction Set Instruction | SB | Op Code Address Data Comments READ 01 10xx A3A2A1A0 Read register A3A2A1A0 WRITE 01 O1xx A3A2A1A0 | D15DO | Write register AIA2A1A0 ERASE 01 11x A3A2A1A0 Erase register ASA2A1A0 EWEN 01 0011 OOK Erase/write enable EWDS 01 0000 XXX Erase/write disable ERAL 01 0010 XXXX Erase all registers WRAL 01 0001 XXXK Di5D0 | Write all registers NMC8313B has 7 instructions as shown. Note that MSB of any given instruction is a '1" and is viewad as a start bit in the interface sequence. The next 8 bits carry the op code and the 4-bit address for 1 of 16, 16-bit registers. X is a don't care state. 2-37 El E69iNNNMC9313B Functional Description The NMC93138B is a small peripheral memory intended for use with COPST controllers and other non-volatile memory applications. Its organization is sixteen registers and each register is sixteen bits wide. The input and output pins are controlled by separate serial formats. Seven 10-bit instruc- tions can be executed. The instruction format has a logical 0, 1. as start bits, four bits as an op code, and four bits of address. The on-chip programming-voltage generator al- lows the user to use a single power supply (Vcc). Only dur- ing the read mode is the serial output (DO) pin valid. During all other modes the DO pin is in TRI-STATE, eliminating bus contention. READ The read instruction is the only instruction which outputs serial data on the DO pin. After a READ instruction is re- ceived, the instruction and address are decoded, followed by data transfer from the memory register into a 16-bit seri- al-out shift register. A dummy bit (logical 0} precedes the 16-bit data output string. Output data changes are initiated by a low to high transition of the SK clock. ERASE/WRITE ENABLE AND DISABLE Programming must be preceded once by a programming enable (EWEN) instruction. Programming remains anabled until a programming disable (EWDS) instruction is executed. The programming disable instruction is provided to protect against accidental data disturb. Execution of a READ in- struction is independent of both EWEN and EWDS instruc- tions. ERASE (Note 4) Like most E2PROMS, the register must first be erased (all bits set to 1s) before the register can be written (certain bits Timing Diagrams set to Os). After an ERASE instruction is input, CS is dropped low. This falling edge of CS determines the start of programming. The register at the address specified in the instruction is then set entirely to 1s. When the erase/write programming time (tesyw) constraint has been satisfied, CS is brought up for at least one SK period. A new instruction may then be input, or a low-power standby state may be achieved by dropping CS iow. WRITE (Note 4) The WRITE instruction is followed by 16 bits of data which are written into the specified address. This register must have been previously erased. Like any programming mode, erase/write time is determined by the low state of CS fol- lowing the instruction. The on-chip high voltage section only generates high voltage during these programming modes, which prevents spurious programming during other modes. When CS rises to Vj}, the programming cycle ends. All pro- gramming modes should be ended with CS high for one SK period, or followed by another instruction. CHIP ERASE (Note 4) Entire chip erasing is provided for ease of programming. Erasing the chip means that all registers in the memory ar- ray have each bit set to a 1. Each register is then ready for a WRITE instruction. CHIP WRITE (Note 4) All registers must be erased before a chip write operation. The chip write cycle is identical to the write cycle, except for the different op code. All registers are simultaneously writ- ten with the data pattern specified in the instruction. Note 4: During a programming mode (write, erase, chip erase, chip write), SK clock is only needed while the actual instruction, i.e., start bit, op code, address and data, is being input. It can remain deactivated during the Erase/ Write pulse width (te sw). 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