2003-2013 Microchip Technology Inc. DS30498D-page 1
PIC16F7X7
Low-Power Features:
• Power-Managed modes:
- Primary Run (XT, RC oscillator, 76 A,
1MHz, 2V)
- RC_RUN (7 A, 31.25 kHz, 2V)
- SEC_RUN (9 A, 32 kHz, 2V)
- Sleep (0.1 A, 2V)
• Timer1 Oscillator (1.8 A, 32 kHz, 2V)
• Watchdog Timer (0.7 A, 2V)
• Two-Speed Oscillator Start-up
Oscillators:
• Three Crystal modes:
- LP, XT, HS (up to 20 MHz)
• Two External RC modes
• One External Clock mode:
- ECIO (up to 20 MHz)
• Intern al Os ci ll ator Block:
- 8 user-selectable frequencies (31 kHz,
125 kHz, 250 kHz, 500 kHz, 1 MHz, 2 MHz,
4MHz, 8MHz)
Analog Features:
• 10-bit, up to 14-channel Analog-to-Digital Converter:
- Programmable Acquisition Time
- Conversion available during Sleep mode
• Dual Analog Comparators
• Programmable Low-Current Brown-out Reset
(BOR) Circuitry and Programmable Low-Voltage
Detect (LVD)
Peripheral Feat ures:
• High Sink/Source Current: 25 mA
• Two 8-bit Timers with Prescaler
• Timer1/RTC module:
- 16-bit timer/counter with prescaler
- Can be incremented during Sleep via
external 32 kHz watch crystal
• Master Synchronous Serial Port (MSSP) with
3-wire SPI and I2CTM (Master and Slave) modes
• Addressable Universal Synchronous
Asynchronous Receiver Transmitter (AUSART)
• Three Captu r e, Com p are , PWM modu le s:
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10 bits
• Parallel Slave Port (PSP) – 40/44-pin devices only
S pecial Microcontroller Features:
• Fail-Safe Clock Monitor for protecting critical
applications against crystal failure
• Two-Speed Start-up mode for immediate code
execution
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Programmable Code Protection
• Processor Read Access to Program Memory
• Power-Saving Sleep mode
• In-Circuit Serial Programming(ICSP)via
two pins
• MPLAB® In-Circuit Debug (ICD) via two pins
•MCLR
pin function replaceable with input only pin
Device
Progra m
Memory
(# Single-Word
Instructions)
Data
SRAM
(Bytes) I/O
Interrupts
10-bit
A/D (ch)
Comparators
CCP
(PWM)
MSSP
AUSART Timers
8/16-bit
SPI I2C™
(Master)
PIC16F737 4096 368 25 16 11 2 3 Yes Yes Yes 2/1
PIC16F747 4096 368 36 17 14 2 3 Yes Yes Yes 2/1
PIC16F767 8192 368 25 16 11 2 3 Yes Yes Yes 2/1
PIC16F777 8192 368 36 17 14 2 3 Yes Yes Yes 2/1
28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with
10-Bit A/D and nanoWatt Technology
PIC16F7X7
DS30498D-page 2 2003-2013 Microchip Technology Inc.
Pin Diagrams
PIC16F737/767
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/LVDIN/SS/C2OUT
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RB7/PGD
RB6/PGC
RB5/AN13/CCP3
RB4/AN11
RB3/CCP2(1)/AN9
RB2/AN8
RB1/AN10
RB0/INT/AN12
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
PDIP, SOIC, SSOP (28-pin)
2
3
4
5
6
1
7
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/LVDIN/SS/C2OUT
15
16
17
18
19
20
21
RB0/INT/AN12
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
23
24
25
2627
28 22
RB7/PGD
RB6/PGC
RB5/AN13/CCP3
RB4/AN11
RB3/CCP2(1)/AN9
RB2/AN8
RB1/AN10
10 11
8912
13 14
QFN (28-pin)
PIC16F737
PIC16F767
Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.
2: Pin location of CCP2 is determined by the CCPM X bit in Configuration Word Register 1.
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC16F747
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
NC
RB7/PGD
RB6/PGC
RB5/AN13/CCP3
RB4/AN11
RB3/CCP2(2)/AN9 RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2(1)
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/LVDIN/SS/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT/AN12
RB1/AN10
RB2/AN8
PIC16F777
QFN (44-pin)(1)
VDD
VSS
NC
2003-2013 Microchip Technology Inc. DS30498D-page 3
PIC16F7X7
Pin Diagrams (Continued)
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC16F747
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
NC
RB7/PGD
RB6/PGC
RB5/AN13/CCP3
RB4/AN11
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2(1)
NC
NC
RC0/T1OSO/T1CKI
OSC1/CLKI/RA7
OSC2/CLKO/RA6
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/LVDIN/SS/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT/AN12
RB1/AN10
RB2/AN8
RB3/CCP2(1)/AN9
TQFP (44-pin)
PIC16F777
RB7/PGD
RB6/PGC
RB5/AN13/CCP3
RB4/AN11
RB3/CCP2(1)/AN9
RB2/AN8
RB1/AN10
RB0/INT/AN12
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/LVDIN/SS/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16F747/777
PDIP (40-pin)
Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
PIC16F7X7
DS30498D-page 4 2003-2013 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory O rganization................................................................................................................................................................. 15
3.0 Reading Program Memory .................................................. ............. ...... ...... ............. .... .......... ................................................... 31
4.0 Oscillator Configurations ............................................................................................................................................................ 33
5.0 I/O Ports ..... ..................... ..................................................................... ...................................................................................... 49
6.0 Timer0 Module ........................................................................................................................................................................... 73
7.0 Timer1 Module ........................................................................................................................................................................... 77
8.0 Timer2 Module ........................................................................................................................................................................... 85
9.0 Capture/Compare/PWM Modules .................... ......... .... .... .... ......... .... .... .. .... ........... .. .... .... ......... ... ............................................. 87
10.0 Master Synchronous Serial Port (M SSP ) Module .......................................... ............................................................................ 93
11.0 Addr essable Universal Synchronous Asynchronous Receiv er Transmitter (AUS ART ) . .......................................................... 133
12.0 Analog-t o-Digital Converter (A/D) Module................................................................................................................................ 151
13.0 Comparator Module................. .. .... ......... .... .. .... ......... .... .... .. .... ......... .... .... .. ......... .... .... .. ........................................................... 161
14.0 Comparator Voltage Reference Module...................... .. .... .... .. ......... .. .... .... .. ......... .... .. .... ......... .. .............................................. 167
15.0 Specia l Features of the CPU.................................................................................................................................................... 169
16.0 Instruction Set Summary.......................................................................................................................................................... 193
17.0 Development Support . .............................................................................................................................................................. 201
18.0 Electrical Characteristics.......................................................................................................................................................... 205
19.0 DC and AC Characteristics Graphs and Tables.................... ........... .... .... .... ......... .... ...... ......... .... .... ........................................ 235
20.0 Packagin g In fo rmation....... ....................................................................................................................................................... 249
Appendix A: Revision History. ............................................................................................................................................................ 265
Appendix B: Device Differences......................................................................................................................................................... 265
Appendix C: Conversion Considerations ............... .... .. ......... .... .. .... .. ......... .... .. .... ......... .. .... .. .... ......................................................... 266
The Micro chip Web Site... ..................................................... ................................. ............................................................................ 275
Customer Change Notification Service ........................ ................... ..................... ................... ........................................................... 275
Customer Support............................................................................................................... ............................................................... 275
Reader Response.............................................................................................................................................................................. 276
PIC16F7X7 Product Identification System......................................................................................................................................... 277
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2003-2013 Microchip Technology Inc. DS30498D-page 5
PIC16F7X7
1.0 DEVICE OVERVIEW
This document contains device specific information
about the following devices:
PIC16F737/767 devices are available only in 28-pin
packages, while PIC16F747/777 devices are available
in 40-pin and 44-pin packages. All devices in the
PIC16F7 X7 fami ly sha re com mon archi tecture with the
following differences:
• The PIC16 F73 7 and PIC16F7 67 have one-half of
the total on-chip memory of the PIC16F747 and
PIC16F777.
• The 28-pin devices have 3 I/O ports, whil e the
40/44-pin devices have 5.
• The 28-pin devices have 16 interrupts, while the
40/44-pin devices have 17.
• The 28-pin devices have 11 A/D input channels,
while the 40/44-pin devices have 14.
• The Parallel Slave Port is implemented only on
the 40/44-pin devices.
• Low-Powe r m od es : RC _ RU N al lows the core a nd
peripherals to be clocked from the INTRC, while
SEC_RUN allows the core and peripherals to be
clocked from the low-power Timer1. Refer to
Section 4.7 “Power-Managed Modes” for
further details.
• Interna l R C o sc il la to r wi th eight sele ctable
freq ue nc ie s , i nc lu di ng 3 1.2 5 kHz, 125 kHz ,
250kHz, 500kHz, 1MHz, 2 MHz, 4 MHz and
8 MHz. The INTRC can be configured as a primary
or secondary clock source. Refer to Section 4.5
“Inter nal Osci lla tor Bloc k” for further det ai ls.
• The Timer1 module current consumption has
been grea tly reduc ed from 20 A (pre vious PIC1 6
devi ces) to 1.8 A typical (32 kHz at 2V), which is
ideal for real-time clock applications. Refer to
Section 7.0 “Timer1 Module” for further details.
• Extended Watchd og Timer (WDT) that ca n hav e a
programmable period from 1 ms to 268s. The WDT
has its own 16-bit prescaler . Refer to Sectio n 1 5. 17
“Watchdog Timer (WDT)” f or fur the r d etails.
• Two- Speed Start-up: When the oscillator is
configu r ed for L P, XT or HS, this feature wi ll clock
the device from the INTRC while the oscillator is
warming up. This, in turn, will enable almost
immediate code execution. Refer to
Section 15.17.3 “Two-Speed Clock Start-up
Mode” for further details.
• Fail- Safe Clock Monitor: This feature will allow the
device to continue operation if the primary or
secondary clock source fails by switching over to
the INTRC.
The available features are summarized in Table 1-1.
Block diagrams of the PIC16F737/767 and
PIC16F7 47/777 devices are provided i n Figure 1-1 and
Figure 1-2, respectively. The pinouts for these device
families are listed in Table 1-2 and Table 1-3.
Additional information may be found in the “PIC® Mid-
Range MCU Family Reference Manual” (DS33023)
which may be o bta ined from your lo cal Mic rochip Sa les
Repres entative or d ow nl oa ded from the Mic r oc hip we b
site. The Reference Manual should be considered a
complementary document to this data sheet and is
highly recommended reading for a better understand-
ing of the device architecture and operation of the
peripheral modules.
TABLE 1-1: PIC16F7X7 DEVICE FEATURES
• PIC16F737 • PIC16F767
• PIC16F747 • PIC16F777
Key Features PIC16F737 PIC16F747 PIC16F767 PIC16F777
Operating Frequency DC – 20 MHz DC – 20 MHz DC – 20 MHz DC – 20 MHz
Resets (and Delays) POR, BOR
(PWRT, OST) POR, BOR
(PWRT, OST) POR, BOR
(PWRT, OST) POR, BOR
(PWRT, OST)
Flash Program Memory (14-b it words) 4K 4K 8K 8K
Data Memory (bytes) 368 368 368 368
Interrupts 16 17 16 17
I/O Ports Ports A, B, C Ports A, B, C, D, E Ports A, B, C Ports A, B, C, D, E
Timers 3 3 3 3
Capture/Compare/PWM Modules 3 3 3 3
Master Serial Communications MSSP, AUSART MSSP, AUSART MSSP, AUSART MSSP, AUSART
Parallel Communications — PSP — PSP
10-bit Analog-to-Digital Module 11 Input Channels 14 Input Channels 11 Input Channels 14 Input Channels
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
Packaging 28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin QFN
44-pin TQFP
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin QFN
44-pin TQFP
PIC16F7X7
DS30498D-page 6 2003-2013 Microchip Technology Inc.
FIGURE 1-1: PIC16F737 AND PIC16F767 BLOCK DIAGRAM
Standard
Program
Memory
4K/8K x 14
13 Data Bus 8
14
Program
Bus
Instruction Register
Progra m Counter
8-Level Stack
(13-bit)
RAM
File
Registers
368 x 8
Direct Addr 7
RAM Addr(1) 9
Addr MUX
Indirect
Addr
FSR reg
Status reg
MUX
ALU
WREG
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
VDD, VSS
PORTA
PORTB
PORTC
PORTE
RA4/T0CKI/C1OUT
RA5/AN4/LVDIN/
RB0/INT/AN12
RB7/PGD:RB6/PGC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
MCLR/VPP/RE3
8
8
Brown-out
Reset
Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
USART
CCP1, 2, 3 MSSP
10-bit A/DTimer0 Timer1 Timer2
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
8
3
BOR/LVD
Addressable
Comparators
Flash
RB1/AN10
RB2/AN8
RB3/CCP2(1)/AN9
RB4/AN11
RB5/AN13/CCP3
SS/C2OUT
OSC2/CLKO/RA6
OSC1/CLKI/RA7
RA3/AN3/VREF+
2003-2013 Microchip Technology Inc. DS30498D-page 7
PIC16F7X7
FIGURE 1-2: PIC16F747 AND PIC16F777 BLOCK DIAGRAM
Standard
Program
Memory
4K/8K x 14
13 Data Bus 8
14
Program
Bus
Instruction Register
Program Counter
8-Level Stack
(13-bit)
RAM
File
Registers
368 x 8
Direct Addr 7
RAM Addr(1) 9
Addr MUX
Indirect
Addr
FSR reg
Status reg
MUX
ALU
WREG
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
VDD, VSS
PORTA
PORTB
PORTC
PORTD
PORTE
RA4/T0CKI/C1OUT
RA5/AN4/LVDIN/
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD7/PSP7:RD0/PSP0
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
8
8
Brown-out
Reset
Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
USART
CCP1, 2, 3 MSSP
10-bit A/DTimer0 Timer1 Timer2
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
Parallel Slave Port
8
3
Comparators BOR/LVD
Addressable
RB0/INT/AN12
RB7/PGD:RB6/PGC
RB1/AN10
RB2/AN8
RB3/CCP2(1)/AN9
RB4/AN11
RB5/AN13/CCP3
MCLR/VPP/RE3
Flash
SS/C2OUT
OSC2/CLKO/RA6
OSC1/CLKI/RA7
PIC16F7X7
DS30498D-page 8 2003-2013 Microchip Technology Inc.
TABLE 1-2: PIC16F737 AND PIC16F767 PINOUT DESCRIPTION
Pin Name
PDIP
SOIC
SSOP
Pin #
QFN
Pin # I/O/P
Type Buffer
Type Description
OSC1/CLKI/RA7
OSC1
CLKI
RA7
96I
I
I/O
ST/CMOS(3)
ST
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input. ST
buffer when configured in RC m ode; otherwise CMO S.
External clock source input. Always associated with pin
function OSC1 (see OSC1/CLKI, OSC2/CLK O pins).
Digital I/O.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
10 7 O
O
I/O
—
ST
Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or resonator in Crystal Oscillator
mode.
In RC mode, OSC2 pin out put s CLKO whi ch has 1/ 4 the
frequency o f OSC1 and denote s the in struct ion cycle ra te.
Digital I/O.
MCLR/VPP/RE3
MCLR
VPP
RE3
126I
P
I
ST
ST
Master Clear (input) or programming voltage (output).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input only pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
227
I/O
I
TTL Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
328
I/O
I
TTL Digital I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
CVREF
41
I/O
I
I
0
TTL Digital I/O.
Analog input 2.
A/D reference voltage input (low).
Comparator voltage reference output.
RA3/AN3/VREF+
RA3
AN3
VREF+
52
I/O
I
I
TTL Digital I/O.
Analog input 3.
A/D reference volt age input (high).
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
63
I/O
I
O
ST Digital I/O – Open-drain when configured as output.
Timer0 external clock input.
Comparator 1 output bit.
RA5/AN4/LVDIN/SS/C2OUT
RA5
AN4
LVDIN
SS
C2OUT
74
I/O
I
I/O
I
O
TTL Digital I/O.
Analog input 4.
Low-Voltage Detect input.
SPI slave select input.
Comparator 2 output bit.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
4: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
2003-2013 Microchip Technology Inc. DS30498D-page 9
PIC16F7X7
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT/AN12
RB0
INT
AN12
21 18 I/O
I
I
TTL/ST(1)
Digital I/O.
External interrupt.
Analog input channel 12.
RB1/AN10
RB1
AN10
22 19 I/O
I
TTL Digital I/O.
Analog input channel 10.
RB2/AN8
RB2
AN8
23 20 I/O
I
TTL Digital I/O.
Analog input channel 8.
RB3/CCP2/AN9
RB3
CCP2(4)
AN9
24 21 I/O
I/O
I
TTL Digital I/O.
CCP2 capture input, compare output, PWM output.
Analog input channel 9.
RB4/AN11
RB4
AN11
25 22 I/O
I
TTL Digital I/O.
Analog input channel 11.
RB5/AN13/CCP3
RB5
AN13
CCP3
26 23 I/O
I
I/O
TTL Digital I/O.
Analog input channel 13.
CCP3 capture input, compare output, PWM output.
RB6/PGC
RB6
PGC
27 24 I/O
I/O
TTL/ST(2)
Digital I/O.
In-Circuit Debugger and ICSP™ programming clock.
RB7/PGD
RB7
PGD
28 25 I/O
I/O
TTL/ST(2)
Digital I/O.
In-Circuit Debugger and ICSP programming data.
TABLE 1-2: PIC16F737 AND PIC16F767 PINOUT DESCRIPTION (CONTINUED)
Pin Name
PDIP
SOIC
SSOP
Pin #
QFN
Pin # I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
4: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
PIC16F7X7
DS30498D-page 10 2003-2013 Microchip Technology Inc.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11 8 I/O
O
I
ST Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(4)
12 9 I/O
I
I/O
ST Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
CCP1
13 10 I/O
I/O
ST Digital I/O.
Capture1 input, Compare1 output, PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
14 11 I/O
I/O
I/O
ST Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI/SDA
RC4
SDI
SDA
15 12 I/O
I
I/O
ST Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO
RC5
SDO
16 13 I/O
O
ST Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
17 14 I/O
O
I/O
ST Digital I/O.
AUSART asynchronous transmit.
AUSART synchronous clock.
RC7/RX/DT
RC7
RX
DT
18 15 I/O
I
I/O
ST Digital I/O.
AUSART asynchronous receive.
AUSART synchronous data.
VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins.
VDD 20 17 P — Positive supply for logic and I/O pins.
TABLE 1-2: PIC16F737 AND PIC16F767 PINOUT DESCRIPTION (CONTINUED)
Pin Name
PDIP
SOIC
SSOP
Pin #
QFN
Pin # I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
4: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
2003-2013 Microchip Technology Inc. DS30498D-page 11
PIC16F7X7
TABLE 1-3: PIC16F747 AND PIC16F777 PINOUT DESCRIPTION
Pin Nam e PDIP
Pin # QFN
Pin # TQFP
Pin # I/O/P
Type Buffer
Type Description
OSC1/CLKI/RA7
OSC1
CLKI
RA7
13 32 30 I
I
I/O
ST/CMOS(4)
ST
Oscillator crystal or external clock input.
Osci llator crystal inpu t or external clock source inpu t.
ST buffer when configured in RC mode; otherwise
CMOS.
External clock source input. Always associated with
pin function OSC1 (see OSC1/CLKI, OSC2/CLKO
pins).
Bidirectional I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
14 33 31 O
O
I/O
—
ST
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
Bidirectional I/O pin.
MCLR/VPP/RE3
MCLR
VPP
RE3
11818I
P
I
ST
ST
Master Clear (input) or programming voltage (output).
Master Clear (Reset) input. This pin is an
active-low Reset to the device.
Programming voltage input.
Digital input only pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
21919
I/O
I
TTL Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
32020
I/O
I
TTL Digital I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
CVREF
42121
I/O
I
I
I
TTL Digital I/O.
Analog input 2.
A/D reference voltage input (low).
Comparator voltage reference output.
RA3/AN3/VREF+
RA3
AN3
VREF+
52222
I/O
I
I
TTL Digital I/O.
Analog input 3.
A/D reference voltage input (high).
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
62323
I/O
I
O
ST Digital I/O – Open-drain when configured as output.
Timer0 external clock input.
Comparator 1 output.
RA5/AN4/LVDIN/SS/C2OUT
RA5
AN4
LVDIN
SS
C2OUT
72424
I/O
I
I
I
I
TTL Digital I/O.
Analog input 4.
Low-Voltage Detect input.
SPI slave select input.
Comparator 2 output.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocesso r bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
5: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
PIC16F7X7
DS30498D-page 12 2003-2013 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
RB0/INT/AN12
RB0
INT
AN12
33 9 8 I/O
I
I
TTL/ST(1)
Digital I/O.
External interrupt.
Analog input channel 12.
RB1/AN10
RB1
AN10
34 10 9 I/O
I
TTL Digital I/O.
Analog input channel 10.
RB2/AN8
RB2
AN8
35 11 10 I/O
I
TTL Digital I/O.
Analog input channel 8.
RB3/CCP2/AN9
RB3
CCP2(5)
AN9
36 12 11 I/O
I/O
I
TTL Digital I/O.
CCP2 capture input, compare output, PWM output.
Analog input channel 9.
RB4/AN11
RB4
AN11
37 14 14 I/O
I
TTL Digital I/O.
Analog input channel 11
RB5/AN13/CCP3
RB5
AN13
CCP3
38 15 15 I/O
I
I
TTL Digital I/O.
Analog input channel 13.
CCP3 capture input, compare output, PWM output.
RB6/PGC
RB6
PGC
39 16 16 I/O
I/O
TTL/ST(2)
Digital I/O.
In-Circuit Debugger and ICSP™ programming
clock.
RB7/PGD
RB7
PGD
40 17 17 I/O
I/O
TTL/ST(2)
Digital I/O.
In-Circuit Debugger and ICSP programming
data.
TABLE 1-3: PIC16F747 AND PIC16F777 PINOUT DESCRIPTION (CONTINUED)
Pin Nam e PDIP
Pin # QFN
Pin # TQFP
Pin # I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Tri gger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocesso r bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
5: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
2003-2013 Microchip Technology Inc. DS30498D-page 13
PIC16F7X7
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
15 34 32 I/O
O
I
ST Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(5)
16 35 35 I/O
I
I/O
ST Digital I/O.
Timer1 oscillator input.
Capture 2 input, Compare 2 output, PWM 2 output.
RC2/CCP1
RC2
CCP1
17 36 36 I/O
I/O
ST Digital I/O.
Capture 1 input, Compare 1 output, PWM 1 output.
RC3/SCK/SCL
RC3
SCK
SCL
18 37 37 I/O
I/O
I/O
ST Digital I/O.
Synchronous serial clock input/output
for SPI mode.
Synchronous serial clock input/output
for I2C™ mode.
RC4/SDI/SDA
RC4
SDI
SDA
23 42 42 I/O
I
I/O
ST Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO
RC5
SDO
24 43 43 I/O
O
ST Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
25 44 44 I/O
O
I/O
ST Digital I/O.
AUSART asynchronous transmit.
AUSART synchronous clock.
RC7/RX/DT
RC7
RX
DT
26 1 1 I/O
I
I/O
ST Digital I/O.
AUSART asynchronous receive.
AUSART synchronous data.
TABLE 1-3: PIC16F747 AND PIC16F777 PINOUT DESCRIPTION (CONTINUED)
Pin Nam e PDIP
Pin # QFN
Pin # TQFP
Pin # I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocesso r bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
5: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
PIC16F7X7
DS30498D-page 14 2003-2013 Microchip Technology Inc.
PORTD is a bidirectional I/O port or Parallel Slave Port
when interfacing to a microprocessor bus.
RD0/PSP0
RD0
PSP0
19 38 38 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD1/PSP1
RD1
PSP1
20 39 39 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD2/PSP2
RD2
PSP2
21 40 40 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD3/PSP3
RD3
PSP3
22 41 41 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD4/PSP4
RD4
PSP4
27 2 2 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD5/PSP5
RD5
PSP5
28 3 3 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD6/PSP6
RD6
PSP6
29 4 4 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
RD7/PSP7
RD7
PSP7
30 5 5 I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
PORTE is a bidirectional I/O port.
RE0/RD/AN5
RE0
RD
AN5
82525
I/O
I
I
ST/TTL(3)
Digital I/O.
Read control for Parallel Slave Port.
Analog input 5.
RE1/WR/AN6
RE1
WR
AN6
92626
I/O
I
I
ST/TTL(3)
Digital I/O.
Write control for Parallel Slave Port.
Analog input 6.
RE2/CS/AN7
RE2
CS
AN7
10 27 27 I/O
I
I
ST/TTL(3)
Digital I/O.
Chip select control for Parallel Slave Port.
Analog input 7.
VSS — 31 — P — Analog ground reference.
VSS 12, 31 6, 30 6, 29 P — Ground reference for logic and I/O pins.
VDD — 8 — P — Analog positive supply.
VDD 11, 32 7, 28 7, 28 P — Positive supply for logic and I/O pins.
NC — 13, 29 12, 13,
33, 34 — — These pins are not internally connected. These pins
should be left unconnected.
TABLE 1-3: PIC16F747 AND PIC16F777 PINOUT DESCRIPTION (CONTINUED)
Pin Nam e PDIP
Pin # QFN
Pin # TQFP
Pin # I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Tri gger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocesso r bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
5: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
2003-2013 Microchip Technology Inc. DS30498D-page 15
PIC16F7X7
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these PIC®
MCUs. The program memory and data memory have
separate buses so that concurrent access can occur
and is detailed in this section. The program memory
can be read internally by user code (see Section 3.0
“Reading Program Memory”).
Addit ional informat ion on devi ce memory may be found
in th e “PIC® Mid-Range MCU Family Reference Man-
ual” (DS33023).
2.1 Program Memory Organization
The PIC16F7X7 dev ices have a 13-bit prog ram counter
capable of addressing an 8K word x 14-bit program
memory space. The PIC16F767/777 devices have
8K words of Flash program memory and the
PIC16F737/747 devices have 4K words. The program
memory maps for PIC16F7X7 devices are shown in
Figure 2-1. Accessing a location above the physically
implemented address will cause a wraparound.
The Res et vector is at 000 0h and the interru pt vector is
at 0004h.
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
whic h contain t he Genera l Purpos e Registe rs and t he
Special Function Registers. Bits RP1 (Status<6>) and
RP0 (Status<5>) are the bank select bits:
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE
REGISTER FILE
The register file (shown in Figure 2-2 and Figure 2-3)
can be accessed either directly, or indirectly, through
the File Select Register (FSR).
FIGURE 2-1: PROGRAM MEMORY MAPS AND STACKS FOR PIC16F7X7 DEVICES
RP1:RP0 Bank
00 0
01 1
10 2
11 3
PC<12:0>
13
0000h
0004h
0005h
S tack Level 1
Stack Level 8
Reset V ector
Interrupt Vector
On-Chip
CALL, RETURN
RETFIE, RETLW
1FFFh
Stack Level 2
Program
Memory
Page 0
0FFFh
1000h
07FFh
0800h
Page 1
17FFh
1800h
Page2
Page 3
Memory available on all
PIC16F7X7.
Memory available on PIC16F767
and PIC16F777. The memory
wraps to 000h through 0FFFh on
the PIC16F737 and PIC16F747.
PIC16F7X7
DS30498D-page 16 2003-2013 Microchip Technology Inc.
FIGURE 2-2: DATA MEMORY MAP FOR PIC16F737 AND THE PIC16F767
Indirect add r.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations read as ‘0’.
* Not a physical register.
File
Address
Indirect addr.(*) Indirect addr.(*)
PCL
STATUS
FSR
PCLATH
INTCON
PCL
STATUS
FSR
PCLATH
INTCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
Indirect addr.(*)
TMR0 OPTION_REG
PIR2 PIE2
ADRESH
ADCON0 ADCON1
General
Purpose
Register
Accesses
70h-7Fh
TRISB
PORTB
96 Bytes
10Ch
10Dh
10Eh
10Fh
110h
18Ch
18Dh
18Eh
18Fh
190h
PMDATA
PMADR PMCON1
PMDATH
PMADRH
17Fh 1FFh
Bank 2 Bank 3
19Fh
1A0h
11Fh
120h
CVRCON
OSCCON
CMCON
ADRESL
TMR1L
TMR1H
T1CON
TMR2
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
PR2
TXSTA
SPBRG
T2CON
OSCTUNE
WDTCON
EFh
F0h
General
Purpose
Register
80 Bytes 16Fh
170h
General
Purpose
Register
80 Bytes 1EFh
1F0h
General
Purpose
Register
80 Bytes
General
Purpose
Register
16 Bytes
General
Purpose
Register
16 Bytes
Accesses
70h-7Fh
Accesses
70h-7Fh
SSPBUF
SSPCON SSPADD
SSPSTAT
ADCON2
PORTC
PORTE
TRISC
TRISE
CCPR2L
CCPR2H
CCP2CON
SSPCON2
CCPR3L
CCPR3H
CCP3CON
LVDCON
File
Address
File
Address
File
Address
2003-2013 Microchip Technology Inc. DS30498D-page 17
PIC16F7X7
FIGURE 2-3: DATA MEMORY MAP FOR PIC16F747 AND THE PIC16F777
Indirect add r.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations read as ‘0’.
* Not a physical register.
File
Address
Indirect addr.(*) Indirect addr.(*)
PCL
STATUS
FSR
PCLATH
INTCON
PCL
STATUS
FSR
PCLATH
INTCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
Indirect addr.(*)
TMR0 OPTION_REG
PIR2 PIE2
ADRESH
ADCON0 ADCON1
General
Purpose
Register
Accesses
70h-7Fh
TRISB
PORTB
96 Bytes
10Ch
10Dh
10Eh
10Fh
110h
18Ch
18Dh
18Eh
18Fh
190h
PMDATA
PMADR PMCON1
PMDATH
PMADRH
17Fh 1FFh
Bank 2 Bank 3
19Fh
1A0h
11Fh
120h
CVRCON
OSCCON
CMCON
ADRESL
TMR1L
TMR1H
T1CON
TMR2
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
PR2
TXSTA
SPBRG
T2CON
OSCTUNE
WDTCON
EFh
F0h
General
Purpose
Register
80 Bytes 16Fh
170h
General
Purpose
Register
80 Bytes 1EFh
1F0h
General
Purpose
Register
80 Bytes
General
Purpose
Register
16 Bytes
General
Purpose
Register
16 Bytes
Accesses
70h-7Fh
Accesses
70h-7Fh
SSPBUF
SSPCON SSPADD
SSPSTAT
ADCON2
PORTC
PORTE
TRISC
TRISE
CCPR2L
CCPR2H
CCP2CON
SSPCON2
PORTD TRISD
CCPR3L
CCPR3H
CCP3CON
LVDCON
File
Address File
Address
File
Address
PIC16F7X7
DS30498D-page 18 2003-2013 Microchip Technology Inc.
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of thes e registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR Details
on page
Bank 0
00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180
01h TMR0 Timer0 Module Register xxxx xxxx 76, 180
02h(4) PCL Program Counter (PC) Least Signif icant Byte 0000 0000 29, 180
03h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 21, 180
04h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx 30, 180
05h PORTA PORTA Data Latch when written: POR TA pins when read xx0x 0000 55, 180
06h PORTB PORTB Data Latch when written: PORTB pins when read xx00 0000 64, 180
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx 66, 180
08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx 67, 180
09h(5) PORTE — — — — RE3 RE2 RE1 RE0 ---- x000 68, 180
0Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 29, 180
0Bh(4) INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 23, 180
0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 25, 180
0Dh PIR2 OSFIF CMIF LVDIF —BCLIF— CCP3IF CCP2IF 000- 0-00 27, 180
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 83, 180
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 83, 180
10h T1CON — T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 83, 180
11h TMR2 Timer2 Module Register 0000 0000 86, 180
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 86, 180
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 101, 180
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 101, 180
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx 90, 180
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx 90, 180
17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 88, 180
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 134, 180
19h TXREG AUSART Tr ansmit Dat a Register 0000 0000 139, 180
1Ah RCREG AUSART Receive Data Register 0000 0000 141, 180
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx 92, 180
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx 92, 180
1Dh CCP2CON —— CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 88, 180
1Eh ADRESH A/D Result Register High Byte xxxx xxxx 160, 180
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 152, 180
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’, r = reserved.
Shaded locat i ons are unimp lemented, read as ‘0’.
Note 1: The upper byt e of the pr ogra m coun ter is n ot dire ctly a ccess ibl e. PCLATH i s a h oldin g regis ter f or the P C<1 2:8 > bits, whose contents
are transferred to the upper byte of the program counter during branches (CALL or GOTO).
2: Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
3: Bits PS PIE and PSPIF are reserved on th e 28-pin devices; always maintain these bits clear.
4: These regi st ers can be addressed from any bank.
5: PORTD, PORTE, TR ISD and TRISE are not physically implemented on the 28 -pin devices (except for RE3), read as ‘0’.
6: This bit always reads as a ‘1’.
7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8: RE3 is an input only. The state of the TRISE3 bit has no eff ect and will always read ‘1’.
2003-2013 Microchip Technology Inc. DS30498D-page 19
PIC16F7X7
Bank 1
80h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180
81h
OPTION_REG
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 22, 180
82h(4) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 29, 180
83h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 21, 180
84h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx 30, 180
85h TRISA PORTA Data Direction Register 1111 1111 55, 181
86h TRISB PORTB Data Direction Register 1111 1111 64, 181
87h TRISC PORTC Dat a Direction Register 1111 1111 66, 181
88h(5) TRISD POR TD Data Direction Register 1111 1111 67, 181
89h(5) TRISE IBF(5) OBF(5) IBOV(5) PSPMODE(5) —(8) PORTE Data Direction bits 0000 1111 69, 181
8Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23, 180
8Bh(4) INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 25, 180
8Ch PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 24, 181
8Dh PIE2 OSFIE CMIE LVDIE —BCLIE— CCP3IE CCP2IE 000- 0-00 26, 181
8Eh PCON — — — — — SBOREN POR BOR ---- -1qq 28, 181
8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS(7) IOFS SCS1 SCS0 -000 1000 38, 181
90h OSCTUNE —— TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 36, 181
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 105
92h PR2 Timer2 Period Register 1111 1111 86, 181
93h SSP ADD Synchronous Serial Port (I2C™ mode) Address Register 0000 0000 101, 181
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 101, 181
95h CCPR3L Capture/Compare/PWM Register 3 (LSB) xxxx xxxx 92
96h CCPR3H Capture/Compare/PWM Register 3 (MSB) xxxx xxxx 92
97h CCP3CON —— CCP3X CCP3Y CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 92
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMTTX9D0000 -010 145, 181
99h SPBRG Baud Rate Generator Register 0000 0000 145, 181
9Ah —Unimplemented — —
9Bh ADCON2 —— ACQT2 ACQT1 ACQT0 — — — --00 0--- 154
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 55, 161
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 55, 167
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 180
9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 153, 181
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR Details
on page
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’, r = reserved.
Shaded locat i ons are unimp lemented, read as ‘0’.
Note 1: The upper byt e of t he progra m c oun ter is no t dire ctly a ccessi bl e. PCLATH i s a holdin g r egis ter f or the P C<1 2:8 > bit s, who s e con tents
are transferred to the upper byte of the program counter during branches (CALL or GOTO).
2: Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
3: Bits PS PIE and PSPIF are reserved on th e 28-pin devices; always maintain these bits clear.
4: These regi st ers can be addressed from any bank.
5: PORTD, PORTE, TR ISD and TRISE are not physically implemented on the 28 -pin devices (except for RE3), read as ‘0’.
6: This bit always reads as a ‘1’.
7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8: RE3 is an input only. The state of the TRISE3 bit has no eff ect and will always read ‘1’.
PIC16F7X7
DS30498D-page 20 2003-2013 Microchip Technology Inc.
Bank 2
100h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180
101h TMR0 Timer0 Module Register xxxx xxxx 76, 180
102h(4) PCL Program Counter (PC) Least Significant Byte 0000 0000 29, 180
103h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 21, 180
104h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx 30, 180
105h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 187
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx 64, 180
107h —Unimplemented — —
108h —Unimplemented — —
109h LVDCON —— IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 176
10Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23, 180
10Bh(4) INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 25, 180
10Ch PMDATA EEPROM Data Register Low Byte xxxx xxxx 32, 181
10Dh PMADR EEPROM Address Register Low Byte xxxx xxxx 32, 181
10Eh PMDATH —— EEPROM Data Register High Byte --xx xxxx 32, 181
10Fh PMADRH — — — — EEPROM Address Register High Byte ---- xxxx 32, 181
Bank 3
180h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 30, 180
181h
OPTION_REG
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 22, 180
182h(4) PCL Program Counter (PC) Least Significant Byte 0000 0000 29, 180
183h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 21, 180
184h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx 30, 180
185h —Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 64, 181
187h —Unimplemented — —
188h —Unimplemented — —
189h —Unimplemented — —
18Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 23, 180
18Bh(4) INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 25, 180
18Ch PMCON1 r(6) — — — — — —RD1--- ---0 32, 181
18Dh —Reserved, maintain clear — —
18Eh —Reserved, maintain clear — —
18Fh —Reserved, maintain clear — —
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR Details
on page
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’, r = reserved.
Shaded locat i ons are unimp lemented, read as ‘0’.
Note 1: The upper byt e of the pr ogra m coun ter is n ot dire ctly a ccess ibl e. PCLATH i s a h oldin g regis ter f or the P C<1 2:8 > bits, whose contents
are transferred to the upper byte of the program counter during branches (CALL or GOTO).
2: Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
3: Bits PS PIE and PSPIF are reserved on th e 28-pin devices; always maintain these bits clear.
4: These regi st ers can be addressed from any bank.
5: PORTD, PORTE, TR ISD and TRISE are not physically implemented on the 28 -pin devices (except for RE3), read as ‘0’.
6: This bit always reads as a ‘1’.
7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8: RE3 is an input only. The state of the TRISE3 bit has no eff ect and will always read ‘1’.
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2.2.2.1 Status Register
The Sta tus regis ter cont ains th e arithme tic st atus of th e
ALU, the Reset s tatus and the ba nk sel ec t bi t s fo r da t a
memory.
The Status register can be the destination for any
instruction, as with any other register. If the Status
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
Status register as destination may be different than
intended.
For exam pl e, CLRF STATUS, will c lea r the up per three
bits and set th e Z bit. Thi s leaves the Statu s register a s
000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
S t atus regis ter becaus e these inst ructions do not affec t
the Z, C or DC bits from the Status register. For othe r
instructions not affecting any Status bits, see
Section 16.0 “Instruction Set Summary”.
REGISTER 2-1: STATUS: ARITHMETIC STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)
Each bank is 128 bytes.
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power- u p or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the
two’s complement of the second operand. For rotate (RRF, RLF) instructions, this
bit is loaded with either the high or low-order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS30498D-page 22 2003-2013 Microchip Technology Inc.
2.2.2.2 OPTION_REG Register
The OPTION_REG register is a readable and writable
register whi ch con t ains various cont rol bi ts to c onfigu re
the TMR0 prescaler/WDT postscaler (single assign-
able register also known as the prescaler), the external
INT inte rrupt, TMR0 and the weak pull-u ps o n POR TB.
REGISTER 2-2: OPTION_REG: OPTION CONTROL REGISTER (ADDRESS 81h, 181h)
Note: To achieve a 1:1 prescaler assignment for
the TMR 0 re gis ter, as si gn the p r escaler to
the Watchdog Timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disab led
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruc tion cycle clock (CLK O)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
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PIC16F7X7
2.2.2.3 INTCON Register
The INTCON register is a readable and writable regis-
ter which contains various enable and flag bits for the
TMR0 register overflow, RB port change and external
RB0/INT pin interrupts.
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
Note: Interru pt flag bi ts are s et when an interrupt
conditi on occ urs regard les s of the sta te of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral inte rrupts
bit 5 TMR0IE: TMR0 Overflow Interr upt Enab le bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 i nter rupt
bit 4 INT0IE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INT0IF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared.
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS30498D-page 24 2003-2013 Microchip Technology Inc.
2.2.2.4 PIE1 Regi st er
The PIE1 regi ster cont ains the indivi dual enable b its for
the peripheral interrupts.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 PSPIE: Para llel Slave Port Read/Write Interrupt Enable bit(1)
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5 RCIE: AUSAR T Rece iv e Interru pt Enab le bit
1 = Enables the AUSART receive interrupt
0 = Disables the AUSART rece ive interrupt
bit 4 TXIE: AUSART Transmit Interrupt Enable bit
1 = Enables the AUSART transmit interrupt
0 = Disables the AUSART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 25
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2.2.2.5 PIR1 Register
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ADDRESS 0Ch)
Note: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of its
corresponding enable bit or the Global Inter-
rupt Enable bit, GIE (INTCON<7>). User
software should ensure the appropr iate inter-
rupt bits are clear prior to enabling an interrupt.
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
Note: PSPIF is reserved on 28-pin devices; always maintain this bit clear.
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion is completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RCIF: AUSART Receive Interrupt Flag bit
1 = The AUSART receive buffer is full
0 = The AUSART rec eive buffer is empty
bit 4 TXIF: AUSART Transmit Interrupt Flag bit
1 = The AUSART transmit buffer is empty
0 = The AUSART transmit buffer is full
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt co ndition has occurred and must be cleared in software befo re returning
from the Interrupt Service Routine. The conditions that will set this bit are:
SPI:
A transmission/reception has taken place.
I2 C Slave:
A transmission/reception has taken place.
I2 C Master:
A transmission/reception has taken place. The initiated Start condition was completed by
the SSP module. The initiated Stop condition was completed by the SSP module. The
initiated Restart condition was completed by the SSP module.The initiated Acknowledge
condition was completed by the SSP module. A Start condition occurred while the SSP
module was Idle (multi-master system). A Stop condition occurred while the SSP module
was Idle (multi-master system).
0 = No SSP interrupt condition has occurred
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in soft ware)
0 = TMR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F7X7
DS30498D-page 26 2003-2013 Microchip Technology Inc.
2.2.2.6 PIE2 Regi st er
The PIE2 regi ster cont ains the indivi dual enable b its for
the CCP2 and CCP3 peripheral interrupts.
REGISTER 2-6: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
OSFIE CMIE LVDIE —BCLIE— CCP3IE CCP2IE
bit 7 bit 0
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5 LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = LVD interrupt is enabled
0 = LVD interrupt is disabled
bit 4 Unimplemented: Read as ‘0’
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enable bus collision interrupt in the SSP when configured for I2C Master mode
0 = Disable bus collision interrupt in the SSP when configured for I2C Master mode
bit 2 Unimplemented: Read as ‘0’
bit 1 CCP3IE: CCP3 Interrupt Enable bit
1 = Enables the CCP3 interrupt
0 = Disables the CCP3 int errupt
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 int errupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 27
PIC16F7X7
2.2.2.7 PIR2 Register
The PIR2 register contains the flag bits for the CCP2
interrupt.
REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ADDRESS 0Dh)
Note: Interru pt flag bi ts are s et when an interrupt
conditi on occ urs regard les s of the sta te of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
OSFIF CMIF LVDIF —BCLIF— CCP3IF CCP2IF
bit 7 bit 0
bit 7 OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTRC (must be cleared in software)
0 = System clock operating
bit 6 CMIF: Comparator Interrupt Fl ag bi t
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 5 LVDIF: Low-Voltage Detect Interrupt Flag bit
1 = The supply vol tag e has fall en below th e specif ied LVD voltage (must be cleared in sof tware)
0 = The supply voltage is greater then the specified LVD voltage
bit 4 Unimplemented: Read as ‘0’
bit 3 BCLIF: Bus Collision Interrup t Flag bit
1 = A bus collision has occurred in the SSP when configured for I2C Mas ter mode
0 = No bus collision has occurred
bit 2 Unimplemented: Read as ‘0’
bit 1 CCP3IF: CCP3 Interrupt Flag bit
Capture mod e:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mod e:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F7X7
DS30498D-page 28 2003-2013 Microchip Technology Inc.
2.2.2.8 PCO N Register
The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR Reset.
REGISTER 2-8: PCON: POWER CONTROL/STATUS REGISTER (ADDRESS 8Eh)
Note: BOR is unknown on POR. It must be set
by the user and checked on subsequent
Resets to see if BOR is clear, indicating a
brown-out has occurred. The BOR status
bit is not predictable if the brown-out circuit
is disabled (by clearing the BOREN bit in
the Configuration Word register).
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-1
— — — — — SBOREN POR BOR
bit 7 bit 0
bit 7-3 Unimplemented: Read as ‘0’
bit 2 SBOREN: Software Brown-out Reset Enable bit
If BORSEN in Configuration Word 2 is a ‘1’ and BOREN in Configuration Word 1 is ‘0’:
1 = BOR enabled
0 = BOR disabled
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 29
PIC16F7X7
2.3 PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low
byte comes from the PCL register which is a readable
and writable register. The upper bits (PC<12:8>) are
not readable but are indirectly writable through the
PCLATH regi ster. On any Reset, the upper bits of the
PC will b e clea red. Fig ure 2-4 show s the two sit uation s
for the loading of the PC. The upper example in the
figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> PCH). The lower example in the
figure shows how the PC is loaded during a CALL or
GOTO instructi on (PCLATH<4:3> PCH).
FIGURE 2-4: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1 COM PU TED GO TO
A comput ed GOTO is a ccom pli shed by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be ex ercise d if th e t able loca tion c rosse s a PCL
memory boundary (each 256-byte bloc k). Refer to the
Application Note, AN556 “Implementing a Table Read”
(DS00556).
2.3.2 STACK
The PIC16F7X7 family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALL instruction is executed or an
interrupt causes a branch. The stack is POPed in the
event of a RETURN, RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP
operation.
The st ack operates as a circular buf fer . This means th at
af ter the st ack ha s be en PUSHed ei ght time s, th e nin th
push ove rwr ites the va lu e that was s tored fro m the firs t
push. The tenth push overw ri tes the se cond push (and
so on).
2.4 Program Memory Paging
PIC16F7X7 devices are capable of addressing a con-
tinuous 8K word block of program memory. The CALL
and GOTO instructions provide only 1 1 bit s of address to
allow bra nchi ng w ith in a ny 2K prog ram m em ory page .
When doing a CALL or GOTO instruction, the upper
2 bits of the address are provided by PCLATH<4:3>.
When doi ng a CALL or GOTO inst ruct ion, the user mus t
ensure that the page select bits are programmed so
that the de sired pr ogram memory page i s addressed . If
a return from a CALL instruction (or interrupt) is
executed, the entire 13-bit PC is POPed off the stac k.
Therefore, manipulation of the PCLATH<4:3> bits is
not required for the RETURN instructions (which POPs
the address from the stack).
Example 2-1 shows the calling of a subroutine in
page 1 o f the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routi ne (if interrupts are used).
EXAMPLE 2-1: CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU
GOTO,CALL
Opcode < 10:0 >
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interr upt add res s.
Note: The contents of the PCLATH are
unchanged after a RETURN or RETFIE
instruction is executed. The user must set
up the PCLA TH for any subsequent CALLs
or GOTOs.
ORG 0x500
BCF PCLATH, 4
BSF PCLATH, 3 ;Select page 1
;(800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 0x900 ;page 1 (800h-FFFh)
SUB1_P1
: ;called subroutine
: ;page 1 (800h-FFFh)
:
RETURN ;return to Call
;subroutine in page 0
;(000h-7FFh)
PIC16F7X7
DS30498D-page 30 2003-2013 Microchip Technology Inc.
2.5 Indirect Addressing, INDF and
FSR Registers
The INDF register is no t a physica l register. Add ressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself
indirectly (FSR = 0) will read 00h. Writing to the INDF
register indirectly results in a no operation (although
Status bit s m ay be a f fe cte d). An effective 9-bit address
is obt ained by concatena ting the 8-bit FSR regist er and
the IRP bi t (Status<7>) as shown in Fi gure 2-5.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: INDIR ECT ADDRESS ING
FIGURE 2-5: DIRECT/INDIRECT ADDRESSING
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR, F ;inc pointer
BTFSS FSR, 4 ;all done?
GOTO NEXT ;no clear next
CONTINUE
: ;yes continue
Note 1: For register file map detail, see Figure 2-2.
Data
Memory(1)
Indirect AddressingDirect Addressing
Bank Select Location Select
RP1:RP0 6 0
From Opcode IRP FSR Register
70
Bank Select Location Select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
2003-2013 Microchip Technology Inc. DS30498D-page 31
PIC16F7X7
3.0 READING PROGRAM MEMORY
The Flash program memory is readable during normal
operation over the entire VDD range. It is indirectly
addressed through Special Function Registers (SFR).
Up to 14-bit numbers can be stored in memory for use
as calib ration param eters, serial nu mbers, packe d 7-bit
ASCII, etc. Executing a program memory location
containing data that forms an invalid instruction results
in a NOP.
There are five SFRs used to read the program and
memory. These registers are:
•PMCON1
•PMDATA
•PMDATH
•PMADR
• PMADRH
The program memory allows word reads. Program
memory access allows for checksum calculation and
reading ca libration tables.
When interfacing to the program memory block, the
PMDATH:PMDATA registers form a two-byte word
which holds the 14-bit data for reads. The
PMADRH:PMADR registers form a two-byte word
which holds the 13-bit address of the Flash location
being accessed. These devices can have up to
8K words of program Flash, with an address range
from 0h to 3FFFh. The unused upper bits in both the
PMDATH and PMADRH registers are not implemented
and read as ‘0’s.
3.1 PMADR
The addres s registers can addr ess up to a maximum of
8K words of program Flash.
When selecting a program address value, the MSB of
the address is written to the PMADRH register and the
LSB is written to the PMADR register. The upper Most
Significant bits of PMADRH must always be clear.
3.2 PMCON1 Register
PMCON1 is the control register for memory accesses.
The control bit, RD, initiates read operations. This bit
cannot be cl eare d, onl y set, in softw a re. It is cl eare d in
hardware at the completion of the read operation.
REGISTER 3-1: PMCON1: PROGRAM MEMORY CONTROL REGISTER 1 (ADDRESS 18Ch)
R-1 U-0 U-0 U-0 U-x U-0 U-0 R/S-0
reserved — — — — — —RD
bit 7 bit 0
bit 7 Reserved: Read as ‘1’
bit 6-1 Unimplemented: Read as ‘0’
bit 0 RD: Read Control bit
1 = Initiates a Flash read, RD is cleared in hardware. The RD bit can only be set (not cleared)
in software.
0 = Flash read completed
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown
PIC16F7X7
DS30498D-page 32 2003-2013 Microchip Technology Inc.
3.3 Reading the Flash Program
Memory
A program me mory location may be read by wri ting two
bytes of t he add ress t o the PMADR and PMADRH re g-
isters and then setting control bit, RD (PMCON1<0>).
Once the read control bit is set, the microcontroller will
use the next two instruction cycles to read the data. The
data is available in the PMDATA and PMDATH
registers after the second NOP i nst ruc tio n; t he ref ore, it
can be read as two bytes in the following instructions.
The PMDATA and PMDATH registers will hold this
value until the next read operation.
3.4 Operation During Code-Protect
Flash program memory has its own code-protect
mechanism. External read and write operations by
programmers are disabled if this mechanism is
enabled.
The microcontroller can read and execute instructions
out of the internal Flash program memory, regardless
of the state of the code-protect configuration bits.
EXAMPLE 3-1: FLASH PROGRAM READ
TABLE 3-1: REGISTERS ASSOCIATED WITH PROGRAM FLASH
BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Bank 2
MOVF ADDRH, W ;
MOVWF PMADRH ; MSByte of Program Address to read
MOVF ADDRL, W ;
MOVWF PMADR ; LSByte of Program Address to read
BSF STATUS, RP0 ; Bank 3 Required
Required BSF PMCON1, RD ; EEPROM Read Sequence
Sequence NOP ; memory is read in the next two cycles after BSF PMCON1,RD
NOP ;
BCF STATUS, RP0 ; Bank 2
MOVF PMDATA, W ; W = LSByte of Program PMDATA
MOVF PMDATH, W ; W = MSByte of Program PMDATH
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
10Dh PMADR EEPROM Address Register Low Byte xxxx xxxx uuuu uuuu
10Fh PMADRH — — — — EE PROM Address Register High Byte ---- xxxx ---u uuuu
10Ch PMDATA EEPROM Data Register Low Byte xxxx xxxx uuuu uuuu
10Eh PMDATH —— EEPROM Data Register High Byte --xx xxxx --uu uuuu
18Ch PMCON1 reserved(1) — — — — — — RD 1--- ---0 1--- ---0
Legend: x = unkn own, u = unchanged, — = unimplemented, read as ‘0’. Shad ed ce lls a re not us ed d uring Fl ash acc ess .
Note 1: This bit always reads as a ‘1’.
2003-2013 Microchip Technology Inc. DS30498D-page 33
PIC16F7X7
4.0 OSCILLATOR
CONFIGURATIONS
4.1 Oscillator Types
The PIC16F7X7 c an b e op erated in eig ht different oscil-
lator modes. The user can program three configuration
bits (FOSC 2:FOSC0) to select one of thes e eight modes
(modes 5-8 are new PIC16 oscillator configurations):
1. LP Low-Power Crystal
2. XT Crystal/Resonator
3. HS High-Speed Crystal/Resonator
4. RC External Resistor/Capacitor with
FOSC/4 output on RA6
5. RCIO External Resistor/Capacitor with
I/O on RA6
6. INTIO1 Internal Oscillator with FOSC/4
output on RA6 and I/O on RA7
7. INTIO2 Internal Oscillator with I/O on RA6
and RA7
8. ECIO External Clock with I/O on RA6
4.2 Crystal Oscillator/Cera mic
Resonators
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKI and OSC2/CLKO pins
to est abl ish osci llatio n (see Fi gure 4-1 and Fi gure 4-2).
The PIC16F7X7 oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturer’s
specifications.
FIGURE 4-1: CRYSTAL OPERATION
(HS, XT OR LP OSC
CONFIGURATION)
T ABLE 4-1: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR (FOR
DESIGN GUIDANCE ONLY)
Note 1: See Table 4-1 for typical values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen (typically
between 2 M to 10 M.
C1(1)
C2(1)
XTAL
OSC2
RS(2)
OSC1
RF(3) Sleep
To Internal
Logic
PIC16F7X7
Osc Type Crystal
Freq
Typica l Cap acitor V alu es
Tested:
C1 C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 56 pF 56 pF
1 MHz 15 pF 15 pF
4 MHz 15 pF 15 pF
HS 4 MHz 15 pF 15 pF
8 MHz 15 pF 15 pF
20 MHz 15 pF 15 pF
Capacitor values are for design guidance only.
These capacito rs were tested with th e crystals listed
below for basic start-up and operation. These values
were not optimized.
Dif ferent capa citor values m ay be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information.
Note 1: Higher capacit ance inc reases the st abilit y
of oscillator but also increases the
start-up time.
2: Since each crystal has its own character-
istic s, th e use r shoul d cons ult th e crys tal
manufacturer for appropriate values of
external components.
3: Rs may be required in HS mode, as well
as XT mode, to av oid ove rdrivi ng cryst als
with low d rive l evel specification.
4: Always veri fy os ci lla tor performance over
the VDD and temperature range that is
expected for the application.
PIC16F7X7
DS30498D-page 34 2003-2013 Microchip Technology Inc.
FIGURE 4-2: CERAMIC RESONATOR
OPERATION (HS OR XT
OSC CONFIGURATION)
TABLE 4-2: CERAMIC RESONATORS (FOR
DESIGN GUIDANC E O NLY)
4.3 External Clock Input
The ECIO Oscillator mode requires an external clock
source to be connected to the OSC1 pin. There is no
oscill ator start -up time requi red after a Pow er-on Reset
or after an exit from Sleep mode.
In the ECIO Oscillator mode, the OSC2 pin becomes
an additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6). Figure 4-3 shows the
pin connections for the ECIO Oscillator mode.
FIGURE 4-3: EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
Typical Capacitor Values Used:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
56 pF
47 pF
33 pF
56 pF
47 pF
33 pF
HS 8.0 MHz
16.0 MHz 27 pF
22 pF 27 pF
22 pF
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values were not optimized.
Dif ferent cap acitor values ma y be required to prod uce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information.
Note: When using resonators with frequencies
above 3.5 MHz, the use of HS mode rather
than XT mode is recommend ed. HS mode
may be used at any VDD for which the
controller is rated. If HS is selected, it is
possible that the gain of the oscillator will
overdrive the resonator. Therefore, a
series resistor should be placed between
the OSC2 pin and the resonator. As a
good starting point, the recommended
value of RS is 330
Note 1: See Table 4-2 for typical values of C1 and C2.
2: A series resistor (RS) may be required.
3: RF varies with the resonator chosen (typically
between 2 M to 10 M.
C1(1)
C2(1)
RES
OSC2
RS(2)
OSC1
RF(3) Sleep
To Internal
Logic
PIC16F7X7
OSC1/CLKI
I/O (OSC2)
RA6
Clock from
Ext. System PIC16F7X7
2003-2013 Microchip Technology Inc. DS30498D-page 35
PIC16F7X7
4.4 RC Oscillator
For timing insensitive applic ations, the “RC” and “RCIO”
device options offer additional cost savings. The RC
oscillator frequency is a function of the supply voltage,
the resistor (REXT) and capacitor (CEXT) values and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
manufacturing variation. Furthermore, the difference in
lead frame cap acitance between p ackage types will also
affect the oscillation frequency, especially for low CEXT
values. The user also needs to take into account varia-
tion due to tolerance of external R and C components
used. Figure 4-4 shows how the R/C combination is
connected.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal may
be used for test purposes or to synchronize other logic.
FIGURE 4-4: RC OSCILLATOR MODE
The RCIO Oscillator mode (Figure 4-5) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 4-5: RCIO OSCILLATOR MODE
4.5 Internal Oscillator Block
The PIC16F7X7 devices include an internal oscillator
block which generates two different clock signals;
either can be used as the system’s clock source. This
can eliminate the need for external oscillator circuits on
the OSC1 and/or OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the system clock. It
also driv es the INT OSC postscal er which can prov ide a
range of s ix cl ock fre quenc ies, fro m 125 kHz to 4 MHz .
The other clock source is the internal RC oscillator
(INTRC) which provides a 31.25 kHz (32 s nominal
period) output. The INTRC oscillator is enabled by
selecting the INTRC as the system clock source or
when any of the following are enabled:
• Power-up Timer
• Watchdog Timer
• Two-Speed Start-up
• Fail- Safe C loc k Mo nito r
These features are discussed in greater detail in
Section 15.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTO SC post scaler) is select ed by con figuring
the IRCF bits of the OSCCON register (page 38).
OSC2/CLKO
CEXT
REXT
PIC16F7X7
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 k REXT 100 k
CEXT > 20 pF
CEXT
REXT
PIC16F7X7
OSC1 Internal
Clock
VDD
VSS
Recommended values: 3 k REXT 100 k
CEXT > 20 pF
I/O (OSC2)
RA6
Note: Throughout this data sheet, when referring
specifically to a generic clock source, the
term “INTRC” may als o be used to refer to
the clock modes using the internal
oscillator block. This is regardless of
whether the actual frequency used is
INTOSC (8 MHz), the INTOSC postscaler
or INTRC (31.25 kHz).
PIC16F7X7
DS30498D-page 36 2003-2013 Microchip Technology Inc.
4.5.1 INTRC MODES
Using the internal oscillator as the clock source can
elimin ate the ne ed for up t o two extern al oscil lator pins ,
after which it can be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 fu nc tio ns as RA 7 fo r dig it a l input and
output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
4.5.2 OSCTUNE REGISTER
The internal oscillator’s output has been calibrated at the
factory but can be adjusted in the application. This is
done by writing to the OSCTUNE register (Register 4-1).
The tuning sensitivity is constant throughout the tuning
range. The OSCTUNE register has a tuning range of
±12.5%.
When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8 clock cycles (approximately
8*32s = 256 s); the INTOSC clock will stabilize
within 1 ms. Code execution continues during this shift.
There is no indication that the shift has occurred. Oper-
ation of features that depend on the 31.25 kHz INTRC
clock source frequency, such as the WDT, Fail-Safe
Clock Monitor and peripherals, will also be affected by
the change in frequency.
REGISTER 4-1: OSCTUNE: OSCILLATOR TUNING REGISTER (ADDRESS 90h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
011110 =
•
•
•
000001 =
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111 =
•
•
•
100000 = Minimum frequency
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 37
PIC16F7X7
4.6 Clock Sources and Oscillator
Switching
The PIC16F7X7 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low-frequency clock source.
PIC16F7X7 devices off er three alternate clock sources.
When enabled, these give additional options for
switching to the various power-managed operating
modes.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary os cilla tors
• Internal oscillator block (INTRC)
The primary oscillators include the External Crystal
and Resonator modes, the External RC modes, the
External Clock mode and the internal oscillator block.
The par ticula r mode is defin ed on POR by the content s
of Configuration Word 1. The details of these modes
are covered earlier in this chapter.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC16F7X7 devices offer the Timer1 oscillator as a
secondary oscillator. This oscillator continues to run
when a SLEEP instruction is executed and is often the
time base for functions, such as a real-time clock.
Most often, a 32.768 kHz watch crystal is connected
betwee n the RC0 /T1OSO/T 1CKI and RC1 /T1OSI/CC P2
pins . Lik e the LP mod e osci llato r cir cuit , load ing c apaci-
tors are also connected from each pin to ground. The
Timer1 oscillator is discussed in greater detail in
Section 7.6 “Tim er1 O sc ill ato r”.
In addi tion to be ing a prim ary clock s ource, the internal
oscillator block is available as a power-managed
mode clock source. The 31.25 kHz INTRC source is
also used as the clock source for several special
features, such as the WDT, Fail-Safe Clock Monitor,
Powe r-up Timer and Two-Speed Start-up.
The clock sources for the PIC16F7X7 devices are shown
in Figure 4-6. See Section 7.0 “Timer1 Module” for
further details of the Timer1 oscillator. See Section 15.1
“Config urat ion Bits” for Configuration register details.
4.6.1 OSCCON REGIST ER
The OSCCON register (Register 4-2) controls several
aspects of the system clock’s operation, both in full
power ope ratio n and in pow e r-ma nag ed mo des .
The system clock select bits, SCS1:SCS0, select the
clock source that is used when the device is operating
in power-managed modes. When the bits are cleared
(SCS<1:0> = 00), the system clock source comes from
the main oscillator that is selected by the
FOSC2:FOSC0 configuration bits in Configuration
Register 1. When the bits are set in any other manner,
the system clock source is provided by the Timer1
oscillator (SCS1:SCS0 = 01) or from the internal
oscillator block (SCS1:SCS0 = 10). After a Reset,
SCS<1:0> are always set to ‘00’.
The internal oscillator select bits, IRCF2:IRCF0, select
the freque ncy o utput of the interna l oscill ator block th at
is use d to driv e th e syst em cl ock. T he choi ces ar e the
INTRC source (31.25 kHz), the INTOSC source
(8 MHz) or one of the six frequencies derived from the
INTOSC postsca ler (12 5 kHz to 4 MHz). Chan gin g t he
configu ration of these bit s has an i mmediate c hange on
the multiplexor’s frequency output.
The OSTS and IOFS bits indicate the status of the
primary oscillator and INTOSC source; these bits are
set when their respective oscillators are stable. In
particular, OSTS indicates that the Oscillator Start-up
Timer has timed out.
4.6.2 CLOCK SWITCHING
Clock switching will occur for the following reasons:
• The FCMEN (CONFIG2<0>) bit is set, the device
is running from the primary oscillator and the
primary oscillator fails. The clock source will be
the internal RC oscillator.
• The FCMEN bit is set, the device is running from
the Timer1 oscillator (T1OSC) and T1OSC fails.
The clock source will be the internal RC oscillator.
• Following a wake-up due to a Reset or a POR,
when the device is configured for Two-Speed
Start-up mode, switching will occur between the
INTRC and the system clock defined by the
FOSC<2:0> bits.
• A wake-up from Sleep occurs due to interrupt or
WDT wake-up and Two-Speed Start-up is
enabled. If the primary clock is XT, HS or LP, the
clock will switch between the INTRC and the
prim ary system clock after 102 4 cloc ks and
8 clocks of the primary oscillator. This is
conditional upon the SCS bits being set equal
to ‘00’.
• SCS bits are modified from their original value.
• IRCF bits are modified from their original value.
Note: Because the SCS bits are cleared on any
Reset, no clock switching will occur on a
Reset unless the Two-Speed Start-up is
enabled and the p rimary clock is XT, HS or
LP. The device will wait for the primary
clock to become stable before execution
begins (Two-Speed Start-u p disa ble d).
PIC16F7X7
DS30498D-page 38 2003-2013 Microchip Technology Inc.
4.6.3 CLOCK TRANSITION AND WDT
When clock switching is performed, the Watchdog
Timer is disabled because the Watchdog Ripple
Counter is used as the Oscillator S tart -up Timer (OST).
Once the clock transition is complete (i.e., new oscilla-
tor selection switch has occurred), the Watchdog
Counter is re-enabled with the Counter Reset. This
allows the user to synchronize the Watchdog Timer to
the start of execution at the new clock frequency.
REGISTER 4-2: OSCCON: OSCILLATOR CONTROL REGISTER (ADDRESS 8Fh)
Note: The OST is only used when switching to
XT, HS and LP Oscillator modes.
U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0
— IRCF2 IRCF1 IRCF0 OSTS(1) IOFS SCS1 SCS0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6-4 IRCF<2:0>: Internal RC Oscillator Frequency Select bits
000 = 31.25 kHz
001 = 125 kHz
010 = 250 kHz
011 = 500 kHz
100 = 1 MHz
101 = 2 MHz
110 = 4 MHz
111 = 8 MHz
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Device is running from the primary system cl ock
0 = Device is runni ng from the T imer1 oscil lator (T1OSC) or INTRC as a secondary sys tem clock
Note 1: Bit reset s to ‘0’ with Two-S peed Start-up and LP, XT or HS selected as the oscillator
mode.
bit 2 IOFS: INTOSC Frequency Stable bit
1 = Frequency is stable
0 = Frequency is not stable
bit 1-0 SCS<1:0>: Oscillator Mode Select bits
00 = Oscillator mode defined by FOSC<2:0>
01 = T1OSC is used for system clock
10 = Internal RC is used for system clock
11 = Reserved
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 39
PIC16F7X7
FIGURE 4-6: PIC16F7X7 CLOCK DIAGRAM
4.6.4 MODIFYING THE IR CF BITS
The IRCF bits can be modified at any time regardless of
which clock source is currently being used as the
system clock. The internal oscillator allows users to
change the frequency during run time. This is achieved
by modifying the IRCF bits in the OSCCON register.
The sequen ce of events tha t occur after the IRCF bits
are modified is dependent upon the initial value of the
IRCF bits before they are modified. If the INTRC
(31.25 kHz, IRCF<2:0> = 000) is running and the IRCF
bits are modified to any other va lue than ‘000’, a 4 ms
(approx. ) clock swit ch delay is turned o n. Code e xecu-
tion continues at a higher than expected frequency
while the new frequency stabilizes. Time sensitive code
should wait for the IOFS bit in the OSCCON register to
become set before continuing. This bit can be
monitored to ensure that t he frequency is stable before
using the system clock in time critical applications.
If the I RCF b its a re modif ied whi le the internal oscillator
is running at any other frequency than INTRC
(31.25 kHz, IRCF<2:0> 000), there is no need for a
4 ms (approx.) clock switch delay. The new INTOSC
frequency will be stable immediately after the eight
falling edges. The IOFS bit will remain set after clock
switching occurs.
Secondary Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
OSC1
OSC2
Sleep
Primary Oscillator
LP, XT, HS, RC, EC
T1OSC
CPU
Peripherals
Postscaler
MUX
MUX
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
OSCCON<6:4>
111
110
101
100
011
010
001
000
31.25 kHz
31.25 kHz
Source
Internal
Oscillator
Block
WDT, FSCM
31.25 kHz
8 MHz
Internal Oscillator
(INTRC)
(INTOSC)
CONFIG1 (FOSC2:FOSC0)
SCS<1:0> (T1OSC)
To Timer1
Note: Caution must be taken when mo difying the
IRCF bit s using BCF or BSF instructions. It
is possible to modify the IRCF bits to a
frequency that may be out of the VDD
specification range; for example:
VDD = 2.0V and IRCF = 111 (8 MHz).
PIC16F7X7
DS30498D-page 40 2003-2013 Microchip Technology Inc.
4.6.5 CLOCK TRANSITION SEQUENCE
The following are three different sequences for
switching the internal RC oscillator frequency:
• Clock before switch: 31.25 kHz
(IRCF<2:0> = 000)
1. IRCF bits are modified to an INTOSC/INTOSC
postscaler frequency.
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLK O to this ne w cl ock so ur ce.
4. The IOFS bit is cl ear to indicate t hat the clock is
unstable and a 4 ms (approx.) delay is started.
Time dependent code should wait for IOFS to
become set.
5. Switchover is complete.
• Clock before switch: One of INTOSC/INTOSC
postscaler (IRCF<2:0> 000)
1. IRCF bits are modified to INTRC
(IRCF<2:0> = 000).
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLK O to this ne w cl ock so ur ce.
4. Oscillator switchove r is complete .
• Clock before switch: One of INTOSC/INTOSC
postscaler (IRCF<2:0> 000)
1. IRCF bits are modified to a different INTOSC/
INTOSC postscaler frequency.
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for
eight falling edges of requested clock, after
which it switches CLKO to this new clock
source.
4. The IOFS bit is set.
5. Oscillator switchover is complete.
4.6.6 OSCILLATOR DELAY UPON
POWER-UP, WAKE-UP AND CLOCK
SWITCHING
Table 4-3 shows the different delays invoked for
various clock switching sequences. It also shows the
delays invoked for POR and wake-up.
TABLE 4-3: OSCILLATOR DELAY EXAMPLES
Clock Swi t ch Frequency Oscillator Delay Comments
From To
Sleep/POR
INTRC
T1OSC 31.25 kHz
32.768 kHz CPU Start-up(1)
Following a wake-up from Sleep mode
or POR, CPU start-up is invoked to
allow the CPU to become ready for
code execution.
INTOSC/INTOSC
Postscaler 125 kHz-8 MHz 4 ms (approx.) and
CPU Start-up(1)
INTRC/
Sleep EC, RC DC – 20 MHz
INTRC
(31.25 kHz) EC, RC DC – 20 MHz
Sleep LP, XT, HS 32.768 kHz-20 MHz 1024 Clock Cycles Following a change from INTRC, the
OST count of 1024 cycles must occur.
INTRC
(31.25 kHz) INTOSC/INTOSC
Postscaler 125 kHz-8 MHz 4 ms (approx.) Refer to Sectio n 4.6.4 “Modifying the
IRCF Bits” for further details.
Note 1: The 5 s-10 s start-up delay is based on a 1 MHz system clock.
2003-2013 Microchip Technology Inc. DS30498D-page 41
PIC16F7X7
4.7 Power-Managed Modes
4.7.1 RC_RUN MODE
When SCS bits are configured to run from the INTRC,
a clock tra nsition is generated if the system c lock is not
already using the INTRC. The event will clear the
OSTS bit and switch the system clock from the primary
system clock (if SCS<1:0> = 00) determined by the
value contained in the configuration bits, or from the
T1OSC (if SCS<1:0> = 01) to the INTRC clock option
and shut-down the primary system clock to conserve
power. Clock switching will not occur if the primary
system clock is already configured as INTRC.
If the system clock does not come from the INTRC
(31.25 kHz) when the SCS bits are changed and the
IRCF bit s in the OSC CO N regi ster are configured for a
frequency other than INTRC, the frequency may not be
stable immediately. The IOFS bit (OSCCON<2>) will
be set when the INTOSC or postscaler frequency is
stable, after 4 ms (approx.).
After a clock swi tch has b een exec uted, th e OSTS bit
is cleare d, indicati ng a low-powe r mode and the dev ice
does not run from the primary system clock. The inter-
nal Q clocks are held in the Q1 state until eight falling
edge clocks are counted on the INTRC oscillator. After
the eight cl ock peri ods hav e trans pi red , the clock inp ut
to the Q clo cks is released an d operation resu mes (see
Figure 4-7).
FIGURE 4-7: TIMING DIAGRAM FOR XT, HS, LP, EC, EXTRC TO RC_RUN MODE
Q4Q3Q2
OSC1
SCS<1:0>
Program PC + 1PC
Note 1: TINP = 32 s typical.
2: TOSC = 50 ns minimum.
3: TSCS = 8 TINP.
4: TDLY = 1 TINP.
Q1
INTOSC
Q1
TSCS(3)
Counter
Q1
TINP(1)
System
Clock
TOSC(2)
Q3Q2 Q4 Q1 Q2
PC + 2
PC + 3
Q3 Q4 Q1
TDLY(4)
PIC16F7X7
DS30498D-page 42 2003-2013 Microchip Technology Inc.
4.7.2 SEC_RUN MODE
The core and peripherals can be configured to be
clocked by T1OSC using a 32.768 kHz crystal. The
crystal must be connected to the T1OSO and T1OSI
pins. This is the same configuration as the low-power
timer circuit (see Section 7.6 “Timer1 Oscillator”).
When SCS bits are configured to run from T1OSC, a
clock transition is generated. It will clear the OSTS bit,
switch th e sys tem cl ock fro m eith er the pri mary sys tem
clock or INTRC, depending on the value of SCS<1:0>
and FOSC<2:0>, to the external low-power Timer1
oscillator input (T1OSC) and shut-down the primary
system clock to conserve power.
After a cloc k swit ch has been ex ec uted , the in ter nal Q
clocks are held in the Q1 state until eight falling edge
clocks are counted on the T1OSC. After the eight clock
periods have transp ired, t he clock i nput to th e Q clo cks
is relea se d a nd o pera tio n re su mes (s ee Fig ure 4-8). In
addition, T1RUN (in T1CON) is set to indicate that
T1OSC is being used as the system clock.
FIGURE 4-8: TIMING DIAGRAM FOR SWITCHING TO SEC_RUN MODE
Note 1: The T1OSC EN bi t must be enabl ed and i t
is the user’s responsibility to ensure
T1OSC is stable before clock switching to
the T 1OSC input clock can occur.
2: When T1OSCEN = 0, the following
possible effect s r esu lt.
Original
SCS<1:0> Modified
SCS<1:0> Final
SCS<1:0>
00 01 00 – no change
00 11 10 – INTRC
10 11 10 – no change
10 01 00 – Oscillator
defined by
FOSC<2:0>
A clock switching event will occur if the
final state of the SCS bits is different from
the original.
Q4Q3Q2
OSC1
SCS<1:0>
Program PC + 1PC
Note 1: TT1P = 30.52 s.
2: TOSC = 50 ns minimum.
3: TSCS = 8 TT1P
4: TDLY = 1 TT1P.
Q1
T1OSI
Q1
TSCS(3)
Counter
Q1
TT1P(1)
System
Clock TOSC(2)
Q3Q2 Q4 Q1 Q2
PC + 2
PC + 3
Q3 Q4 Q1
TDLY(4)
2003-2013 Microchip Technology Inc. DS30498D-page 43
PIC16F7X7
4.7.3 SEC_RUN/RC_RUN TO PRIMARY
CLOCK SOURCE
When switching from a SEC_RUN or RC_RUN mode
back to the primary syste m clock, foll owing a chang e of
SCS<1:0> to ‘00’, the sequence of events that take
place will depend upon the value of the FOSC bits in
the Conf iguration regis ter . If the primary clo ck sou rce is
configured as a crystal (HS, XT or LP), then the
transiti on will t ake pl ace aft er 1024 clo ck cycl es. This is
necessary because the crystal oscillator has been
powered down until the time of the transition. In order
to provide the system with a reliable clock when the
changeover has occurred, the clock will not be
released to the changeover circuit until the 1024 counts
have expired.
During the oscillator start-up time, the system clock
comes from the current system clock. Instruction
execution and/or peripheral operation continues using
the currently selected oscillator as the CPU clock
source, until the necessary clock count has expired, to
ensure that the primary system clock is stable.
To know when the OST has expired, the OSTS bit
should be monitored. OSTS = 1 indicates that the
Oscil la tor Start-up Timer has timed out and the system
cloc k comes from t he primary clock s ource.
Following the oscillator start-up time, the internal Q
clocks are held in the Q1 state until eight falling edge
clock s are coun ted from the prima ry sys tem cloc k. The
clock input to the Q clocks is then released and
operation resumes with the primary system clock
determined by the FOSC bits (see Figure 4-10).
When in SEC_RUN mode, the act of clearing the
T1OSCEN bit in the T1CON register will cause
SCS<0> to be cleared, which causes the SCS<1:0>
bits to revert to ‘00’ or ‘10’ depending on wh at SCS<1>
is. Althou gh the T1OSCEN bit was c leared, T1OSC will
be enabled and instruction execution w i ll c on tin ue until
the OST time-out for the main system clock is com-
plete. At th at time, the system cloc k will switc h from the
T1OSC to the primary clock or the INTRC. Following
this, the Timer1 oscillator will be shut-down.
4.7.3.1 Returning to Primary Clock Source
Sequence
Changing back to the primary oscillator from
SEC_RUN or RC_RUN can be accomplished by either
changing SCS<1:0> to ‘00’ or clearing the T1OSCEN
bit in th e T1CON register (i f T1OSC wa s the sec ondary
clock).
The sequence of events that follows is the same for
both modes :
1. If the primary system clock is configured as EC,
RC or IN TRC, then t he OST time-ou t is skip ped.
Skip to step 3.
2. If th e prim ary sys tem clo ck is confi gured as an
external oscillator (HS, XT, LP), then the OST
will be active, waiting for 1024 clocks of the
prim ary sy stem clock.
3. On the following Q1, the device holds the
system clock in Q1.
4. The device stays in Q1 while eight falling edges
of the primary system clock are counted.
5. Once the eight counts transpire, the device
begins to run from the primary oscillator.
6. If the secondary clock was INTRC and the
primary clock is not INTRC, the INTRC will be
shut-down to save current, providing that the
INTRC is not being used for any other function,
such as WDT or Fail-Safe Clock Monitoring.
7. If the secondary clock was T1OSC, the T1OSC
will continue to run if T1OSCEN is still set;
otherwise, the Timer1 oscillator will be shut-down.
Note: If the p r im ary sy s tem c loc k is ei t he r R C or
EC, an internal delay timer (5-10 s) will
suspen d oper ation a fte r exiti ng Sec ondary
Clock mode to allow the CPU to become
ready for code execution.
PIC16F7X7
DS30498D-page 44 2003-2013 Microchip Technology Inc.
FIGURE 4-9: TIMING FOR TRANSITION BETWEEN SEC_RUN/RC_RUN AND
PRIMARY CLOCK
Q4 Q1 Q3 Q4
OSC1
Program PC PC + 1
Secondary
Primary Clock
TOST(6)
Q1
PC + 3
TOSC(3)
TDLY(5)
TT1P(1) or TINP(2)
TSCS(4)
Q2
OSC2
Q3 Q4 Q1
OSTS
System Clock
PC + 2
Counter
Q2 Q2 Q3 Q4
SCS<1:0>
Note 1: TT1P = 30.52 s.
2: TINP = 32 s typical.
3: TOSC = 50 ns minimum .
4: TSCS = 8 TINP OR 8TT1P.
5: TDLY = 1 TINP OR 1TT1P.
6: Refer to parameter D032 in Section 18.0 “Electrical Characteristics”.
Oscillator
Q4 Q1 Q3 Q4
OSC1
Program PC PC + 1
Secondary
Primary Clock
TOST(6)
Q1
PC + 3
TOSC(3)
TDLY(5)
TT1P(1) or TINP(2)
TSCS(4)
Q2
OSC2
Q3 Q4 Q1
OSTS
System Clock
PC + 2
Counter
Q2 Q2 Q3 Q4
SCS<1:0>
Oscillator
2003-2013 Microchip Technology Inc. DS30498D-page 45
PIC16F7X7
4.7.3.2 Returning to Primary Oscillator with
a Reset
A Reset will clear SCS<1:0> back to ‘00’. The
sequence for starting the primary oscillator following a
Reset is the same for all forms of Reset, including
POR. There is no transition sequence from the
alte rnat e syst em clo ck to th e pri mary s ystem clock on
a Reset condition. Instead, the device will reset the
state of the OSCCON register and default to the
primary system clock. The sequence of events that
take place after this will depend upon the value of the
FOSC bits in t he Conf igur ation r egist er. I f the exter nal
osci llator is configured as a crystal (HS, X T or LP), the
CPU wi ll be h eld in th e Q1 st at e until 1024 clock cyc les
have transpired on the primary clock. This is
necessary because the crystal oscillator had been
powered down until the time of the transition.
During the oscillator start-up time, instruction
execution and/or peripheral operation is suspended.
If the primary system clock is either RC, EC or INTRC,
the CPU will begin operating on the first Q1 cycle
following the wake-up event. This means that there is
no oscillator start-up time required because the
primary clock is already stable; however, there is a
delay between the wake-up event and the following
Q2. An internal delay timer of 5-10 s will suspend
operation after the Reset to allow the CPU to become
ready for code execution. The CPU and peripheral
clock will be held in the first Q1.
The sequence of events is as follows:
1. A device Reset is asserted from one of many
sources (WDT, BOR, MCLR, etc.).
2. The device resets and the CPU start-up timer is
enabled if in Sleep mode. The device is held in
Reset until the CPU start-up time-out is
complete.
3. If th e prim ary sys tem clo ck is confi gured as an
external oscillator (HS, XT, LP), then the OST
will be activ e waiti ng for 102 4 clocks of the pri -
mary system clock. While waiting for the OST,
the device will be held in Reset. The OST and
CPU start-up timers run in parallel.
4. After both the CPU start-up timer and the
Oscillator Start-up Timer have timed out, the
device will wait for one additional clock cycle
and instruction execution will begin.
FIGURE 4-10: TIM ING LP CLOCK TO PRIMARY SYSTEM CLOCK AFTER RESET (HS, XT, LP)
Note: If Two-Speed Clock Start-up mode is
enabled, the INTRC will act as the system
clock until the Oscillat or Start-up T imer has
timed out.
Q4 Q1 Q3 Q4 Q1 Q2
OSC1
Peripheral
Sleep
Program PC 0000h
T1OSI
TOST(4)
Q3
TT1P(1)
Q4
OSC2
OSTS
System Clock
0001h
Q1 Q2 Q3 Q4 Q1 Q2
Clock
Counter 0004h 0005h
0003h
Q1 Q2 Q3 Q4
Reset
TEPU(3)
Note 1: TT1P = 30.52 s.
2: TOSC = 50 ns minimum .
3: TEPU = 5-10 s.
4: Refer to parameter D032 in Section 18.0 “Electrical Characteristics”.
CPU Start-up TOSC(2)
PIC16F7X7
DS30498D-page 46 2003-2013 Microchip Technology Inc.
FIGURE 4-11: TIMING LP CLOCK TO PRIMARY SYSTEM CLOCK AFTER RESET
(EC, RC, INTRC)
Q4 Q1 Q3 Q4 Q1 Q2
OSC1
Program PC 0000h
T1OSI
Q3
TT1P(1)
Q4
OSC2
OSTS
System Clock
0001h
Q1 Q2 Q3 Q4 Q1 Q2
Counter 0003h 0004h
0002h
Q1 Q2 Q3 Q4
MCLR
TCPU(2)
Note 1: TT1P = 30.52 s.
2: TCPU = 5-10 s.
CPU Start-up
2003-2013 Microchip Technology Inc. DS30498D-page 47
PIC16F7X7
TABLE 4-4: CLOCK SWITCHING MODES
Current
System
Clock
SCS bits<1:0>
Modified to: Delay OSTS
bit IOFS
bit T1RUN
bit
New
System
Clock Comments
LP, XT, HS,
T1OSC,
EC, RC
10
(INTRC)
FOSC<2:0> = LP,
XT or HS
8 Clocks of
INTRC 01
(1) 0INTRC
or
INTOSC
or
INTOSC
Postscaler
The internal R C oscillator
frequency is dependant upon
the IRCF bits.
LP, XT, HS,
INTRC,
EC, RC
01
(T1OSC)
FOSC<2:0> = LP,
XT or HS
8 Clocks of
T1OSC 0N/A 1T1O SC T1OSCEN bi t must be enabl ed.
INTRC
T1OSC 00
FOSC<2:0> = EC
or
FOSC<2:0> = RC
8 Clocks of
EC
or
RC
1N/A 0EC
or
RC
INTRC
T1OSC 00
FOSC<2:0> = LP,
XT, HS
1024 Clocks
+
8 Clocks of
LP, XT, HS
1N/A 0LP, XT, HS During the 1024 clocks,
program execution is clocked
from the secondary oscillator
until the primary oscillator
becomes stable.
LP, XT, HS 00
(Due to Reset)
LP, XT, HS
1024 Clocks 1N/A 0LP, XT, HS When a Reset occurs, there is
no clock transition sequence.
Instruction
execution and/or peripheral
operation is suspended unless
Two-Speed Start-up mode is
enabled, after which the INTRC
will act as t he system clock
until the Os ci ll ator Sta rt-u p
Ti mer has expired.
Note 1: If the new clock source is the INTOSC or INTOSC postscaler, then the IOFS bit will be set 4 ms (approx.)
after the clock change.
PIC16F7X7
DS30498D-page 48 2003-2013 Microchip Technology Inc.
4.7.4 EXITING SLEEP WITH AN
INTERRUPT
Any interru pt, such as WDT or INT0 , will cause the part
to leave the Sleep mode.
The SCS bits are unaffected by a SLEEP command and
are the same before and after entering and leaving
Sleep. The clock source used after an exit from Sleep
is determined by the SCS bits.
4.7.4.1 Sequence of Events
If SCS<1:0> = 00:
1. The device is held in Sleep until the CPU st art-up
time-out is complete.
2. If the primary system clock is configured as an
external oscillator (HS, XT, LP), then the OST will
be active waiting for 1024 clocks of the primary
system clock. While waiting for the OST, the
device will be held in Sleep unless Two-Speed
Start-up is enabled. The OST and CPU start-up
timers run in parallel. Refer to Section 15.17.3
“Two-Speed Clock Start-up Mode” for details
on Two-S p eed Start-up.
3. After both the CPU start-up timer and the
Oscillator Start-up Timer have timed out, the
device will exit Sleep and begin instruction
execution with the primary clock defined by the
FOSC bits.
If SCS<1:0> = 01 or 10:
1. The device is held in Sleep until the CPU st art-up
time-out is complete.
2. After the CPU start-up timer has timed out, the
device will exit Sleep and begin instruction
execution with the selected oscillator mode.
Note: If a user changes SCS<1:0> just before
entering Sleep mode, the system clock
used when exiting Sleep mode could be
different than the system clock used when
entering Sleep mode.
As an ex ample, i f SCS<1 :0> = 01, T 1OSC
is the system clock and the following
instructions are executed:
BCF OSCCON,SCS0
SLEEP
then a clock change event is executed. If
the primary oscillator is XT, LP or HS, the
core will continue to run off T1OSC and
execute the SLEEP comm and .
When Sleep is ex ited, the part will resume
operation with the primary oscillator after
the OST has expired.
2003-2013 Microchip Technology Inc. DS30498D-page 49
PIC16F7X7
5.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Addit ion al inf orm atio n o n I/O ports may be found in the
“PIC® Mid-Range MCU Family Reference Manual”
(DS33023).
5.1 PORTA and the TRISA Register
PORTA is a 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make th e corresponding PORT A pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the correspon ding POR TA pin an out put (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The RA4 pin is multiplexed with the Timer0 module
clock input and one of the comparator outputs to
become the RA4/T0CKI/C1OUT pin. Pins RA6 and
RA7 are multiplexed with the main oscillator pins; they
are enabled as oscillator or I/O pins by the selection of
the main oscillator in Configuration Register 1H (see
Section 15.1 “Configuration Bits” for details). When
they are not used as port pins, RA6 and RA7 and their
associated TRIS and LAT bits are read as ‘0’.
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs and the
comparator voltage reference output. The oper ation of
pins RA3:RA0 and RA5 as A/D converter inputs is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register 1). Pins RA0
through RA5 may also be used as comparator inputs or
outputs by setting the appropriate bits in the CMCON
register .
The R A4/T0C KI/C1O UT pin i s a Schm itt Trigger input
and an open-drain output. All other PORTA pins have
TTL input levels and full CMOS output drivers.
The TRISA register controls the direction of the RA pins
even when they are being used as analog inputs. The
user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 5-1: INITIA LIZI NG PORTA
Note: On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
BCF STATUS, RP0 ;
BCF STATUS, RP1 ; Bank0
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x0F ; Configure all pins
MOVWF ADCON1 ; as digital inputs
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6>are always
; read as '0'.
PIC16F7X7
DS30498D-page 50 2003-2013 Microchip Technology Inc.
FIGURE 5-1: BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS FIGURE 5-2: BLOCK DIAGRAM OF
RA3/AN3/VREF+ PIN
Data
Bus QD
Q
CK P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog VSS
VDD
I/O pin
QD
Q
CK
Input Mode
DQ
EN
To Comparator
TTL
Input Buffer
To A/D Module Channel Input
Data
Bus QD
Q
CK P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog VSS
VDD
I/O pin
QD
Q
CK
Input Mode
DQ
EN
To Comparator
TTL
Input Buffer
To A/D Module Channel Input
To A/D Module VREF+ Input
2003-2013 Microchip Technology Inc. DS30498D-page 51
PIC16F7X7
FIGURE 5-3: BLOCK DIAGRAM OF RA2/AN2/VREF-/CVREF PIN
FIGURE 5-4: BLOCK DIAGRAM OF RA4/T0CKI/C1OUT PIN
Data
Bus Q
D
Q
CK P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog
VSS
VDD
RA2/AN2/VREF-/
QD
Q
CK
DQ
EN
To Comparator
TTL
Input Buffer
Input Mode
To A/D Module Channel Input
CVROE
CVREF
To A/D Module VREF-
CVREF pin
Data
Bus QD
Q
CK
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
RA4/T0CKI/
QD
Q
CK
DQ
EN
TMR0 Clock Input
Comparator 1 Output
Comparator Mode = 011, 101, 001
1
0
Analog
Input Mode
Schmitt Trigger
Input Buffer
C1OUT pin
PIC16F7X7
DS30498D-page 52 2003-2013 Microchip Technology Inc.
FIGURE 5-5: BLOCK DIAGRAM OF RA5/AN4/LVDIN/SS/C2OUT PIN
Data
Bus QD
Q
CK
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
RA5/AN4/LVDIN/
QD
Q
CK
DQ
EN
Comparator 2 Output
Comparator Mode = 011, 101
1
0
Analog
Input Mode
To A/D Module Channel Input
P
VDD
SS Input
LVDIN
TTL
Buffer
SS/C2OUT pin
2003-2013 Microchip Technology Inc. DS30498D-page 53
PIC16F7X7
FIGURE 5-6: BLOCK DIAGRAM OF OSC2/CLKO/RA6 PIN
Data
Bus QD
Q
CK P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
VDD OSC2/CLKO
Q
D
Q
CK
DQ
EN
TTL
Buffer
Oscillator
Circuit
1
0
RA6 pin
From OSC1
(FOSC = 1x1)
EMUL
(FOSC = 1x0,011)
P
N
V
SS
VDD
EMUL + FOSC = 00x, 010
(FOSC = 1x0,011)
1
0
CLKO (FOSC/4) (FOSC = 1x1)
VDD
Note 1: CLKO signal is 1/4 of the FOSC frequency.
(FOSC = 1x1)
EMUL + FOSC = 00x,010
EMUL
PIC16F7X7
DS30498D-page 54 2003-2013 Microchip Technology Inc.
FIGURE 5-7: BLOCK DIAGRAM OF OSC1/CLKI/RA7 PIN
Data
Bus QD
Q
CK P
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
VDD OSC1/CLKI
Q
D
Q
CK
DQ
EN
Oscillator
Circuit
1
0RA7 pin
(FOSC = 10x) EMUL
NEMUL
(FOSC = 10x)
P
N
V
SS
VDD
(FOSC = 10x) EMUL
(FOSC = 10x)
VDD
(FOSC = 011)
TTL
Buffer
2003-2013 Microchip Technology Inc. DS30498D-page 55
PIC16F7X7
TABLE 5-1: PORTA FUNCTIONS
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0 bit 0 TTL Input/output or analog input.
RA1/AN1 bit 1 TTL Input/output or analog input.
RA2/AN2/VREF-/CVREF bit 2 TTL Input/output or analog input or VREF-.
RA3/AN3/VREF+ bit 3 TTL Input/output or analog input or VREF+.
RA4/T0CKI/C1OUT bit 4 ST Input/output or external clock input for Timer0. Output is
open-drain type.
RA5/AN4/LVDIN/SS/C2OUT bit 5 TTL Input/output or slave select input for synchronous serial port or
analog inp ut.
OSC2/CLKO/RA6 bit 6 ST Input/output, connects to crystal or resonator, oscillator output or
1/4 the frequency of OSC1 and denotes the instruction cycle in
RC mode.
OSC1/CLKI/RA7 bit 7 ST/CMOS(1) Input/output, connects to crystal or resonator or oscillator input.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 uu0u 0000
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
Legend: x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes, where PCFG2:PCFG0 = 100, 101, 11x.
PIC16F7X7
DS30498D-page 56 2003-2013 Microchip Technology Inc.
5.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make th e corresp onding POR TB pi n an out put (i.e .,
put the contents of the output latch on the selected pin).
Each of th e POR TB pins has a we ak inte rnal pul l-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION_REG<7>).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
PORTB pins are multiplexed with analog inputs. The
operat ion of eac h pin is selected by clear ing/settin g the
appropri ate con t rol bit s in the ADC ON1 regist er.
Four of the PORTB pins (RB7:RB4) have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are ORed together to generate the RB port change
interrupt with flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
inter rupt in the following manne r:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt on mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Application
Note AN552 “Implementing Wake-up on Key Stroke”
(DS00552).
RB0/INT is an external interrupt input pin and is
configured using the INTEDG bit (OPTION_REG<6>).
RB0/IN T is d iscus sed i n det ai l in Section 15 .15.1 “ INT
Interrupt”.
PORTB i s multiplexed w ith several pe ripheral function s
(see Table 5-3). PORTB pins have Schmitt Trigger
input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pi n. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISB as
dest ination shoul d be avoided. The user sh ould refer to
the corresponding peripheral section for the correct
TRIS bit settings.
Note: On a Power-on Reset, these pins are
configured as analog inputs and read as
‘0’.
2003-2013 Microchip Technology Inc. DS30498D-page 57
PIC16F7X7
FIGURE 5-8: BLOCK DIAGRAM OF RB0/INT/AN12 PIN
FIGURE 5-9: BLOCK DIAGRAM OF RB1/AN10 PIN
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
Data Latch
RBPU(1) P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR PORTB
WR TRISB
RD TRISB
RD PORTB
Weak
Pull-up
RD PORTB
I/O pin
TRIS Latch
To INT
TTL
Input Buffer
Input Mode
Analog
Input Mode
Analog
To A/D Channel Input
Input Mode
Analog
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
Data Latch
RBPU(1) P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR PORTB
WR TRISB
RD TRISB
RD PORTB
Weak
Pull-up
RD PORTB
I/O pin
TRIS Latch
TTL
Input Buffer
Input Mode
Analog
To A/D Channel Input
Input Mode
Analog
PIC16F7X7
DS30498D-page 58 2003-2013 Microchip Technology Inc.
FIGURE 5-10: BLOCK DIAGRAM OF RB2/AN8 PIN
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
Data Latch P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR PORTB
WR TRISB
RD TRISB
RD PORTB
Weak
Pull-up
RD PORTB
I/O pin
TRIS Latch
TTL
Input Buffer
Input Mode
Analog
To A/D Channel Input
RBPU(1)
2003-2013 Microchip Technology Inc. DS30498D-page 59
PIC16F7X7
FIGURE 5-11: BLOCK DIAGRAM OF RB3/CCP2(1)/AN9 PIN
Data Latch
P
VDD
Q
D
CK
QD
CK
QD
EN
Data Bus
WR PORTB
WR TRISB
RD TRISB
RD PORTB
Weak
Pull-up
RD PORTB
To A/D Channel Input
I/O pi n
Schmitt Trigger
Buffer(3)
TRIS Latch
Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
3: The SDA Schmitt Trigger conforms to the I2C™ specification.
1
0
CCP2 Output
P
N
VSS
VDD
Q
CCP2 Output Select and CCPMX
TTL
Input Buffer
Input Mode
Analog
Input Mode
Analog
Input Mode
Analog
To CCP Module Input
RBPU(2)
PIC16F7X7
DS30498D-page 60 2003-2013 Microchip Technology Inc.
FIGURE 5-12: BLOCK DIAGRAM OF RB4/AN11 PIN
Data Latch
From other
P
VDD
I/O pin
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR PORTB
WR TRISB
Set RBIF
TRIS Latch
RD TRISB
RD PORTB
RB7:RB4 pins
Weak
Pull-up
RD PORTB
Latch
Q3
Q1
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
To A/D channel input
P
N
VSS
VDD
Input Mode
Analog
TTL
Input Buffer
Input Mode
Analog
Input Mode
Analog
RBPU(1)
2003-2013 Microchip Technology Inc. DS30498D-page 61
PIC16F7X7
FIGURE 5-13: BLOCK DIAGRA M OF RB5/AN13/CCP3 PIN
Data Latch
From other
RBPU(1) P
VDD
I/O pin
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR PORTB
WR TRISB
Set RBIF
TRIS Latch
RD TRISB
RD PORTB
RB7:RB4 pins
Weak
Pull-up
RD PORTB
Latch
Q3
Q1
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
CCP3 Output 1
0
CCP3 Output Select
TTL
Input Buffer
Input Mode
Analog
Input Mode
Analog
Schmitt Trigger
Buffer Input Mode
Analog
To CCP Module Input
Input Mode
Analog
To A/D Channel Input
PIC16F7X7
DS30498D-page 62 2003-2013 Microchip Technology Inc.
FIGURE 5-14: BLOCK DIAGRAM OF RB6/PGC PIN
Data Latch
From other
RBPU(1) P
VDD
I/O pin
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR PORTB
WR TRISB
Set RBIF
TRIS Latch
RD TRISB
RD PORTB
RB7:RB4 pins
Weak
Pull-up
RD PORTB
Latch
Q3
Q1
Note 1: To enable weak pull-ups, set t he appropriate TRIS bit( s) and clear the RBPU bit.
TTL
Input Buffer
Schmitt Trigger
Buffer
PGC
Program Mode/ICD
Program Mode/ICD
2003-2013 Microchip Technology Inc. DS30498D-page 63
PIC16F7X7
FIGURE 5-15: BLOCK DIAGRAM OF RB7/PGD PIN
Data Latch
From other
RBPU(1)
P
VDD
I/O pin
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR PORTB
Set RBIF
TRIS Latch
RD TRISB
RD PORTB
RB7:RB4 pins
Weak
Pull-up
RD PORTB
Latch
Q3
Q1
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
PGD
PGD 1
0
Port/Program Mode/ICD
TTL
Input Buffer
1
0
PGD DRVEN
Program Mode/ICD
WR TRISB
PIC16F7X7
DS30498D-page 64 2003-2013 Microchip Technology Inc.
TABLE 5-3: PORTB FUNCTIONS
TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/INT/AN12 bit 0 TTL/ST(1) Input/output pin or external interrupt input. Internal software
programmable weak pull-up or analog input.
RB1/AN10 bit 1 TTL Input/output pin. Internal software programmable weak pull-up or
analog input.
RB2/AN8 bit 2 TTL Input/output pin. Internal software programmable weak pull-up or
analog input.
RB3/CCP2/AN9 bit 3 TTL Input/output pin or Capture 2 input/Compare 2 output/PWM 2 output.
Internal software programmable weak pull-up or analog input.
RB4/AN11 bit 4 TTL Input/output pin (with interrupt-on-change). In ternal software
programmable weak pull-up or analog input.
RB5/AN13/CCP3 bit 5 TTL Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up or analog input or Capture 2 in put/
Compare 2 output/PWM 2 output.
RB6/PGC bit 6 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Serial programming clock.
RB7/PGD bit 7 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when co nfig ured as the e xternal interrupt.
2: This buffe r is a Schmitt Trigger input w hen used in Serial Programming mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xx00 0000 uu00 0000
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
2003-2013 Microchip Technology Inc. DS30498D-page 65
PIC16F7X7
5.3 PORTC and the TRISC Register
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will mak e the correspo nding PORT C pin a n output (i.e.,
put the contents of the output latch on the selected pin).
PORT C is multip lexed with s everal periphe ral function s
(Table 5-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bit s for each PORT C pi n. Som e
peripherals override the TRIS bit to make a pin an
outp ut , whi le ot her pe ri ph e r al s ov err i d e the TR IS bi t to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instr uctions (BSF, BCF, XORWF) with TRISC as
dest ination shoul d be avoided. The user s hould refer to
the corresponding peripheral section for the correct
TRIS bit s ettings and to Section 16.1 “Read-Modify-
Write Operations” for additional information on
read-modify-write operations.
FIGURE 5-16: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<2:0>,
RC<7:5> PINS
FIGURE 5-17: PORTC BLOCK DIAGRAM
(PERIPHERA L OUTPUT
OVERRIDE) RC<4:3> PINS
Port/Peripheral Select(2)
Data Bus
WR
Port
WR
TRIS
RD
Data Latch
TRIS Latch
RD
Schmitt
Trigger
QD
Q
CK
QD
EN
Peripheral Data Out 0
1
QD
Q
CK
P
N
VDD
VSS
Port
Peripheral
OE(3)
Peripheral Input
I/O
pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between port
data and peripheral output.
3: Peripheral OE (Output Enable) is only activated if
Peripheral Select is active.
TRIS
Port/Peripheral Select(2)
Data Bus
WR
Port
WR
TRIS
RD
Data Latch
TRIS Latch
RD
Schmitt
Trigger
QD
Q
CK
QD
EN
Peripheral Data Out 0
1
QD
Q
CK
P
N
VDD
Vss
Port
Peripheral
OE(3)
SSPl Input
I/O
pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between port data
and peripheral output.
3: Peripheral OE (Output Enable) is only activated if
Peripheral Select is active.
0
1
CKE
SSPSTAT<6>
Schmitt
Trigger
with
SMBus
Levels
TRIS
PIC16F7X7
DS30498D-page 66 2003-2013 Microchip Technology Inc.
TABLE 5-5: PORTC FUNCTIONS
TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI bit 0 ST Input/output port pin or Ti mer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2 bit 1 ST Input/output port pin or Timer1 oscillator input or Capture 2 input/
Compare 2 output/PWM 2 output.
RC2/CCP1 bit 2 ST Input/outpu t port pin or Capture 1 inpu t/Compare 1 output/PWM 1
output.
RC3/SCK/SCL bit 3 ST RC3 can also be the synchronous serial clock for both SPI and
I2C™ modes.
RC4/SDI/SDA bit 4 ST RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode).
RC5/SDO bit 5 ST Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK bit 6 ST Input/output port pin or AUSART asynchronous transmit or
synchronous clock.
RC7/RX/DT bit 7 ST Input/output port pin or AUSART asynchronous receive or
synchro no us data.
Legend: ST = Schm itt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged
2003-2013 Microchip Technology Inc. DS30498D-page 67
PIC16F7X7
5.4 PORTD and TRISD Registers
This section is not applicable to the PIC16F737 or
PIC16F767.
PORTD is an 8-bit port with Schmitt Trigger input
buffers. Each pin is individually configureable as an
input or output.
PORTD can be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffe rs are TTL.
FIGURE 5-18: PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
TABLE 5-7: PORTD FUNCTIONS
TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
DataBus
WR Port
WR TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
QD
CK
QD
CK
EN
QD
EN
Name Bit# Buffer Type Function
RD0/PSP0 bit 0 ST/TTL(1) Inpu t/output port pin or Parallel Slave Port bit 0.
RD1/PSP1 bit 1 ST/TTL(1) Inpu t/output port pin or Parallel Slave Port bit 1.
RD2/PSP2 bit 2 ST/TTL(1) Inpu t/output port pin or Parallel Slave Port bit 2.
RD3/PSP3 bit 3 ST/TTL(1) Inpu t/output port pin or Parallel Slave Port bit 3.
RD4/PSP4 bit 4 ST/TTL(1) Inpu t/output port pin or Parallel Slave Port bit 4.
RD5/PSP5 bit 5 ST/TTL(1) Inpu t/output port pin or Parallel Slave Port bit 5.
RD6/PSP6 bit 6 ST/TTL(1) Inpu t/output port pin or Parallel Slave Port bit 6.
RD7/PSP7 bit 7 ST/TTL(1) Inpu t/output port pin or Parallel Slave Port bit 7.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
88h TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE IBF OBF IBOV PSPMODE —(1) PORTE Data Direction bits 0000 1111 0000 1111
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
PIC16F7X7
DS30498D-page 68 2003-2013 Microchip Technology Inc.
5.5 PORTE and TRISE Register
This section is not applicable to the PIC16F737 or
PIC16F767.
PORTE has four pins, RE0/RD/AN5, RE1/WR/AN6,
RE2/CS/AN7 and MCLR/VPP/RE3, which are individu-
ally configureable as inputs or outputs. These p ins have
Schmitt T rigger input buffers. RE3 is only available as an
input if MCLRE is ‘0’ in Configura tion W ord 1.
I/O PORTE becomes control inputs for the micro-
processor port when bit, PSPMODE (TRISE<4>), is
set. In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
input s). Ensure ADCO N1 is configure d for digital I/O. In
this mode, the input buffers are TTL.
Register 5-1 shows the TRISE register which also
controls the Parallel Slave Port operation.
PORTE pins are multiplexed with analog inputs. When
select ed as an analog input, these pins will read as ‘0’s.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
FIGURE 5-19: PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
TABLE 5-9: PORTE FUNCTIONS
TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Note: On a Power-on Reset, these pins are
configured as analog inputs and read as ‘0’.
Data Bus
WR Port
WR TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
QD
CK
QD
CK
EN
QD
EN
Name Bit# Buffe r Ty pe Function
RE0/RD/AN5 bit 0 ST/TTL(1) I nput/output port pin or read control input in Parallel Slave Port mode or analog input.
For RD (P SP m ode):
1 = Idle
0 = Read operation. Content s of PORTD register output to PORTD I/O pins (if chip selected).
RE1/WR/AN6 bit 1 ST/TTL (1) Input/output port pin or write control input in Parallel Slave Port mode or analog input.
For WR (PSP mode) :
1 =Idle
0 = Write operation. Value of PORTD I/O pins latched into PORTD register (if chip selected).
RE2/CS/AN7 bit 2 ST/TTL(1) Input/output port pin or chip select control input in Parallel Slave Port mode or analog input.
For CS (PSP mode):
1 = Device is not selected
0 = Device is selected
MCLR/VPP/RE3 bit 3 ST Input, Master Clear (Reset) or programming input voltage.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
09h PORTE — — — — RE3 RE2 RE1 RE0 ---- x000 ---- x000
89h TRISE IBF OBF IBOV PSPMODE —(1) PORTE Data Direction bits 0000 1111 0000 1111
9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
2003-2013 Microchip Technology Inc. DS30498D-page 69
PIC16F7X7
REGISTER 5-1: TRISE REGISTER (ADDRESS 89h)
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE —(1) TRISE2 TRISE1 TRISE0
bit 7 bit 0
bit 7 Parallel Slave Port Status/Control bits:
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6 OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The ou tput buffer has been read
bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in
software)
0 = No overflow occurred
bit 4 PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General Purpose I/O mode
bit 3 Unimplemented: Re ad as ‘1’(1)
Note 1: RE3 is an input only . The state of the TRISE3 bit has no effect and will always read ‘1’.
bit 2 PORTE Data Direction bits:
TRISE2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1 TRISE1: Direction Control bi t for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0 TRISE0: Direction Control bi t for pin RE0/RD/AN5
1 = Input
0 = Output
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F7X7
DS30498D-page 70 2003-2013 Microchip Technology Inc.
5.6 Parallel Slave Port
The Parallel Slave Port (PSP) is not implemented on
the PIC16F737 or PIC16F767.
PORT D operates as an 8-bit wide Parallel Slave Port or
microprocessor port when control bit, PSPMODE
(TRISE<4> ), is set. In Slave mode, it is a synchronousl y
readable and writable by an external system using the
read control input pin RE0/RD/AN5, the write control
input pin RE1/WR/AN6 and the chip select control input
pin RE2/CS/AN7.
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the POR TD latch a s an 8-bit latc h. Setting
bit PSPMODE enables port pin RE0/RD/AN5 to be the
RD input, RE1/WR/AN6 to be the WR input and
RE2/CS/AN7 to be the CS (Chip Select) input. For thi s
functionality, the corresponding data direction bits of
the TRISE register (TRISE<2:0>) must be configured
as inputs (i.e., set). The A/D port configuration bits,
PCFG3:PCFG0 (ADCON1<3:0>), must be set to
configure pins RE2:RE0 as digital I/O.
There a re act ually two 8-bit l atches, one for d ata o utput
(external reads) and one for data input (external
writes). The firmware writes 8-bit data to the PORTD
output data latch and reads data from the PORTD input
data latch (note that they have the same address). In
this mode, the TRISD register is ignored since the
external device is controlling the direction of data flow.
An external write to the PSP occurs when the CS and
WR lines are both detected low . Firmware can read the
actual data on th e PORTD pins during this time. W hen
either the CS or WR lines become high (level trig-
gered), the data on the PORTD pin s is latc he d and the
Input Buffer Full (IBF) status flag bit (TRISE<7>) and
interrupt flag bit, PSPIF (PIR1<7>), are set on the Q4
clock cycle following the next Q2 cycle to signal the
write is complete (Figure 5-21). Firmware clears the
IBF flag by readi ng the la tched PO RTD data a nd clea rs
the PSPIF bit.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if an external write to the PSP occurs
while the IBF flag is set from a previous external write.
The previous PORTD data is overwritten with the new
data. IBOV is cleared by reading PORTD and clearing
IBOV.
A read from t he PSP occurs when both the CS and RD
lines are detected low. The data in the PORTD output
latch is output to the PORTD pins. The Output Buffer
Full (OBF) status flag bit (TRISE<6>) is cleared imme-
diately (Figure 5-22), indicating that the PORTD latch is
being read or has been read by the external bus. If
firmwa re writes new dat a to t he o utp ut latc h during this
time, it is immediately output to the PORTD pins but
OBF will remain cleared.
When either the CS or RD pins are detected high, the
PORTD outputs are disabled and the interrupt flag bit
PSPIF is set on the Q4 clock cycle following the next
Q2 cycle, indicating that the read is complete. OBF
remains low until firmware writes new data to PORTD.
When not in PSP mode, t he I BF an d OBF b it s are hel d
clear . F lag bit IBOV rem ains unchange d. The PSPIF b it
must be cleared by the user in firmware; the interrupt
can be disabled by clearing the interrupt enable bit,
PSPIE (PIE1<7>).
FIGURE 5-20: PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Data Bus
WR
Port
RD
RDx pin
QD
CK
EN
QD
EN
Port
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR 1<7>)
Read
Chip Select
Write
RD
CS
WR
Note: I/O pin has protection diod es to VDD and VSS.
TTL
TTL
TTL
TTL
2003-2013 Microchip Technology Inc. DS30498D-page 71
PIC16F7X7
FIGURE 5-21: PARALLEL SLAVE PORT WRITE WAVEFORMS
FIGURE 5-22: PARALLEL SLAVE PORT READ W AVEFORMS
TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>
Add r e s s Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B i t 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
08h PORTD Port Data Latch when written: Port pins when read xxxx xxxx uuuu uuuu
09h PORTE — — — — RE3 RE2 RE1 RE0 ---- x000 ---- x000
89h TRISE IBF OBF IBOV PSPMODE —(2) PO RTE Data Direction bits 0000 1111 0000 1111
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserv ed on the PIC16F737/767; always maintain these bits clear.
2: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
PIC16F7X7
DS30498D-page 72 2003-2013 Microchip Technology Inc.
NOTES:
2003-2013 Microchip Technology Inc. DS30498D-page 73
PIC16F7X7
6.0 T IMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Additional information on the Timer0 module is
available in the “PIC® Mid-Range MCU Family Refer-
ence Manual” (DS330 23) .
Figure 6-1 i s a block diagram of th e Ti mer0 module and
the prescaler shared with the WDT.
6.1 Timer0 Operation
Timer0 operation is controlled through the
OPTION_REG register (se e Register 2-2). T imer mode
is selected by clearing bit T0CS (OPTION_REG<5>).
In T imer m ode, the T ime r0 module w ill incr ement eve ry
instruc tion cy cle (with out pr escal er). If the TMR0 regis-
ter is w ritten , the i ncrem ent is inhi bited f or the follow ing
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
Counter mode is selected by setting bit, T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment, either on every rising or falling edge of pin
RA4/T0CKI/C1OUT. The incrementing edge is
determined by the Timer0 Source Edge Select bit, T0SE
(OPTION_REG< 4>). Clearing bit T0SE selects the rising
edge. Restrictions on the external clock input are
discuss ed in de tail i n Section6.3 “Using Timer0 With
an External Clock”.
The prescaler is mutually, exclusively shared between
the Timer0 module and the Watchdog Timer. The
prescaler is not readable or writable. Section 6.4
“Prescaler” details the operation of the prescaler.
6.2 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
TMR0IF (INTCON<2>). The interrupt can be masked
by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF
must be cleared in software by the Timer0 module
Interrupt Service Routine before re-enabling this
interrupt. The TMR0 interrupt cannot awaken the
processor from Sleep since the ti mer is shut-off during
Sleep.
FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
RA4/T0CKI/C1OUT
T0SE
pin
M
U
X
CLKO (= FOSC/4)
Sync
2
Cycles TMR0 Reg
8-bit Prescaler
8-to-1 MUX
M
U
X
MUX
PSA
01
0
1
WDT Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA and PS2:PS0 are (OPTION_REG<5:0>).
PSA
M
U
X
0
10
1
Data Bus
Set Flag bit TMR0I F
on Overflow
8
PSA
T0CS
Prescaler
31.25 kHz
WDT Timer
WDT Enable bit
16-bit
Prescaler
PIC16F7X7
DS30498D-page 74 2003-2013 Microchip Technology Inc.
6.3 Using Timer0 With an
External Clock
When no pr escal er is used, t he ex ternal clo ck inp ut is
the same as the pre sc al er outp ut. Th e sy nch ron iz atio n
of T0CKI with the internal phase clocks is accom-
plishe d by sampling the prescale r output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 TOSC (and
a small RC delay of 20 ns) and low for at least 2 TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
6.4 Prescaler
There i s only one pres caler a vailable , whic h is mutu ally
exclus ively shar ed between th e T imer0 mod ule and the
Watchdog Timer. A prescaler assignment for the
Timer0 module means that the prescaler cannot be
used by the Watchdog Timer and vice versa. This
prescaler is not readable or writable (see Figu re 6-1).
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable .
Note: Althou gh the presca ler can be assi gned to
either the WDT or Timer0, but not both, a
new divide counter is implemented in the
WDT circui t to giv e m ul tipl e WDT tim e-o ut
selecti on s. T his al low s TM R0 an d WD T to
each have their own scaler. Refer to
Section 15.17 “W atchdog Timer (WDT)”
for further details.
Note: Writing to TMR0 when the prescaler is
assign ed to Timer0 will clear th e prescal er
count but will not change the prescaler
assignment.
2003-2013 Microchip Technology Inc. DS30498D-page 75
PIC16F7X7
REGISTER 6-1: OPTION_REG: OPTION CONTROL REGISTER (ADDRESS 181h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA(1) PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit(1)
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
Note 1: To avoid an uninte nd ed dev ice Res et, the in struct ion se quenc e sho wn in the ”PIC®
Mid-Range MCU Family Reference Manual” (DS33023) must be executed when
changing the prescaler assignment from Timer0 to the WD T. This sequence must
be followed even if the WDT is disabled.
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16F7X7
DS30498D-page 76 2003-2013 Microchip Technology Inc.
EXAMPLE 6-1: CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0
TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0
CLRWDT ; Clear WDT and prescaler
BANKSEL OPTION_REG ; Select Bank of OPTION_REG
MOVLW b'xxxx0xxx' ; Select TMR0, new prescale
MOVWF OPTION_REG ; value and clock source
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
01h,101h TMR0 T imer0 Module Register xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
2003-2013 Microchip Technology Inc. DS30498D-page 77
PIC16F7X7
7.0 T IMER1 MODULE
The Timer1 module is a 16 -bi t timer/c ou nter c ons is tin g
of two 8-bit registers (TMR1H and TMR1L) which are
readable and writable. The TMR1 register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rol ls over to 0000h. Th e TMR1 inter rupt, if e nabled,
is generated on overflow which is latched in interrupt
flag bit, TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit, TMR1IE (PIE1<0> ).
The T imer1 oscillator c an be used as a secondary clock
source in low-power modes. Whe n the T1RUN bit is set
along with SC S<1:0> = 01, the T imer1 osci llator is pro-
vidin g the syst em cloc k. If the F ail-Saf e Clock Mon itor
is enabled and the Timer1 oscillator fails while
providing the system clock, polling the T1RUN bit will
indicate whether the clock is being provided by the
Timer1 oscillator or another source.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
7.1 Timer1 Operation
Timer1 can operate in one of three modes:
•as a Timer
• as a Synchronous Counter
• as an Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
Timer1 can be enabled/disabled by setting/clearing
control bit, TMR1ON (T1CON<0>).
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP1 module as the special
event trigger (see Section 9.4 “Capture Mode”).
Register 7-1 shows the Timer1 Control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC0/T1OSO/T1CKI and RC1/T1OSI/CCP2
pins become inputs. That is, the TRISB<7:6> value is
ignored and these pins read as ‘0’.
Additional information on timer modules is available in
the “PIC® Mid-Range MCU Family Reference Manual”
(DS33023).
PIC16F7X7
DS30498D-page 78 2003-2013 Microchip Technology Inc.
REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 T1RUN: Timer1 System Clock Status bit
1 = System clock is derived from Ti mer1 oscillator
0 = System clock is d erived from anothe r source
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Pres cale value
10 = 1:4 Pres cale value
01 = 1:2 Pres cale value
00 = 1:1 Pres cale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Cloc k Sourc e Sele ct bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal cloc k (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 =Stops Timer1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 79
PIC16F7X7
7.2 Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit, T1SYNC
(T1CON<2>), has no effect since the internal clock is
always in sync.
7.3 Timer1 Counter Operation
Timer1 may operate in Asynchronous or Synchronous
mode depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After T imer1
is enab led in Coun ter mode, the module must first have
a falling edge before the counter begins to increment.
7.4 Timer1 Operation in Synchr onized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2 when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this con figuration during Sleep mode, T imer1 will not
increment even if the external clock is present, since
the synchronization circuit is shut-off. The prescaler,
however, will continue to increment.
FIGURE 7-1: TIMER1 INCREMENTING EDGE
FIGURE 7-2: TIMER1 BLOCK DIAGRAM
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
TMR1H TMR1L
T1OSC T1SYNC
TMR1CS
T1CKPS1:T1CKPS0 Q Clock
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
TMR1ON
On/Off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
T1OSI
T1OSO/T1CKI
Note 1: When the T1OSCEN bit is cleared, the inverter is turned of f. This eliminates power drain.
Set Flag bit
TMR1IF on
Overflow TMR1
PIC16F7X7
DS30498D-page 80 2003-2013 Microchip Technology Inc.
7.5 Timer1 Operation in
Asynchronous Counter Mode
If control bi t, T1SYNC (T1CON<2>), is set, the ext ernal
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt on overflow that will wake-up the
processor. However, special precautions in software
are needed to read/write the timer (Section 7.5.1
“Reading and Writing Timer1 in Asynchronous
Counter Mode”).
In Asynchronous Counter mode, Timer1 cannot be
used as a time base for capture or compare ope rations.
7.5.1 READING AND WR ITING T I MER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running
from an e xternal asyn chronous cl ock will ens ure a valid
read (taken care of in hardware). However, the user
should keep i n mind that rea ding t he 16-bi t ti mer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes , it is re commend ed that th e user s imply sto p
the timer and write the desired values. A write conten-
tion may occur by writing to the Timer registers while
the register is incrementing. This may produce an
unpredic table value in the Timer register.
Reading the 16-bit value requires some care. The
example codes provided in Example 7-1 and
Example 7-2 demonstrate how to write to and read
Timer1 while it is running in Asynchronous mode.
EXAMPLE 7-1: WRITING A 16-BIT FREE RUNNING TIMER
EXAMPLE 7-2: READING A 16-BIT FREE RUNNING TIMER
; All interrupts are disabled
CLRF TMR1L ; Clear Low byte, Ensures no rollover into TMR1H
MOVLW HI_BYTE ; Value to load into TMR1H
MOVWF TMR1H, F ; Write High byte
MOVLW LO_BYTE ; Value to load into TMR1L
MOVWF TMR1H, F ; Write Low byte
; Re-enable the Interrupt (if required)
CONTINUE ; Continue with your code
; All interrupts are disabled
MOVF TMR1H, W ; Read high byte
MOVWF TMPH
MOVF TMR1L, W ; Read low byte
MOVWF TMPL
MOVF TMR1H, W ; Read high byte
SUBWF TMPH, W ; Sub 1st read with 2nd read
BTFSC STATUS, Z ; Is result = 0
GOTO CONTINUE ; Good 16-bit read
; TMR1L may have rolled over between the read of the high and low bytes.
; Reading the high and low bytes now will read a good value.
MOVF TMR1H, W ; Read high byte
MOVWF TMPH
MOVF TMR1L, W ; Read low byte
MOVWF TMPL ; Re-enable the Interrupt (if required)
CONTINUE ; Continue with your code
2003-2013 Microchip Technology Inc. DS30498D-page 81
PIC16F7X7
7.6 Timer1 Oscillator
A crystal oscillator circuit is built between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON<3>). The oscil-
lator is a low-power oscillator, rated up to 32.768 kHz.
It will continue to run during all power-managed mo des.
It is primarily intended for a 32 kHz crystal. The circuit
for a typical LP oscillator is shown in Figure 7-3.
Table 7-1 shows the capacitor selection for the Timer1
oscillator.
The user m us t prov id e a so ftware time delay to en su re
proper oscillator start-up.
FIGURE 7-3: EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
TABLE 7-1: CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
7.7 Timer1 Oscillator Layout
Considerations
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 7-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-spee d c ircui t m us t b e l oc ate d n ear the os c ill a-
tor, a grounded guard ring around the oscillator circuit,
as shown in Figure 7-4, may be helpful when used on
a single sided PCB or in addition to a ground pl ane.
FIGURE 7-4: OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
7.8 Resetting Timer1 Using a CCP
Trigger Output
If the CCP1 module is configured in Compare mode to
generate a “special event trigger” signal
(CCP1M3:CCP1M0 = 1011), the signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
T imer 1 must be co nfigured fo r either T i mer or Synch ro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L
register pair effecti ve ly b ec ome s th e period register for
Timer1.
Osc Type Freq C1 C2
LP 32 kHz 33 pF 33 pF
Note 1: Microchip suggests this value as a starting
point in validating the oscillator circuit.
2: Highe r cap acita nce increase s the stabi lity
of the oscillator but also increases the
start - up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guidance
only.
PIC16F7X7
T1OSI
T1OSO
C2
33 pF
C1
33 pF
XTAL
32.768 kHz
Note: See the Notes with Table 7-1 for additional
information about capacitor selection.
Note: The special event triggers from the CCP1
module will not set interrupt flag bit,
TMR1IF (PIR1<0>).
OSC1
VSS
OSC2
RC0
RC1
RC2
PIC16F7X7
DS30498D-page 82 2003-2013 Microchip Technology Inc.
7.9 Resetting Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H an d TMR1L reg isters are not rese t to 00h on a
POR, or any other Reset, except by the CCP1 special
event triggers.
T1CON re gister is re set to 00h o n a Power-on Re set or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other Resets, the register
is unaffected.
7.10 Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
7.1 1 Using Timer1 as a Real-T ime Clock
Adding an extern al LP os cilla tor to Timer1 (such a s the
one described in Section 7.6 “Timer1 Oscillator”)
gives users the option to include RTC functionality in
their applications. This is accomplished with an inex-
pensiv e watc h cry sta l to p rovide a n accura te tim e base
and several lines of application code to calculate the
time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 7-3, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1 reg-
ister p air to overflow, triggers the in terrupt and ca lls th e
routine which increments the seconds counter by one;
additional counters for minutes and hours are
inc remen ted as the previo us counter overflows.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to
preload it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this m ethod to be a ccurate, T imer 1 must o perate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
EXAMPLE 7-3: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit BANKSEL TMR1H
MOVLW 0x80 ; Preload TMR1 register pair
MOVWF TMR1H ; for 1 second overflow
CLRF TMR1L
MOVLW b’00001111’ ; Configure for external clock,
MOVWF T1CON ; Asynchronous operation, external oscillator
CLRF secs ; Initialize timekeeping registers
CLRF mins
MOVLW .12
MOVWF hours
BANKSEL PIE1
BSF PIE1, TMR1IE ; Enable Timer1 interrupt
RETURN
RTCisr BANKSEL TMR1H
BSF TMR1H, 7 ; Preload for 1 sec overflow
BCF PIR1, TMR1IF ; Clear interrupt flag
INCF secs, F ; Increment seconds
MOVF secs, w
SUBLW .60
BTFSS STATUS, Z ; 60 seconds elapsed?
RETURN ; No, done
CLRF seconds ; Clear seconds
INCF mins, f ; Increment minutes
MOVF mins, w
SUBLW .60
BTFSS STATUS, Z ; 60 seconds elapsed?
RETURN ; No, done
CLRF mins ; Clear minutes
INCF hours, f ; Increment hours
MOVF hours, w
SUBLW .24
BTFSS STATUS, Z ; 24 hours elapsed?
RETURN ; No, done
CLRF hours ; Clear hours
RETURN ; Done
2003-2013 Microchip Technology Inc. DS30498D-page 83
PIC16F7X7
TABLE 7-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh, 18Bh INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserv ed on the PIC16F737/767 devices; always maintain these bits clear.
PIC16F7X7
DS30498D-page 84 2003-2013 Microchip Technology Inc.
NOTES:
2003-2013 Microchip Technology Inc. DS30498D-page 85
PIC16F7X7
8.0 T IMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
post scaler . It can be used as the PWM tim e base for the
PWM mode of the CCP module(s). The TMR2 register
is readable and writable and is cleared on any device
Reset.
The in put cloc k (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits,
T2CKPS1:T2CKPS0 (T2CON<1: 0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt, latched in flag bit,
TMR2IF (PIR1<1>).
T imer2 can b e shut-of f by clearing control bit, T MR2ON
(T2CON<2> ), to minimize power consumption.
Register 8-1 shows the Timer2 Control register.
Additional information on timer modules is available in
the “PIC® Mid-Range MCU Family Reference Manual”
(DS33023).
8.1 Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (POR, MCLR Reset, WDT
Reset or BOR)
TMR2 is not cleared when T2CON is written.
8.2 Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSP module which optionally uses it to generate the
shift clock.
FIGURE 8-1: TIMER2 BLOCK DIAGRAM
Comparator
TMR2
Sets Flag
TMR2 Reg
Output(1)
Reset
Postscaler
Prescaler
PR2 Reg
2
FOSC/4
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note 1: TMR2 register output can be software selected by the
SSP module as a baud cl ock.
1:1 to 1:16
TOUTPS3:
TOUTPS0
T2CKPS1:
T2CKPS0
PIC16F7X7
DS30498D-page 86 2003-2013 Microchip Technology Inc.
REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
TABLE 8-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
•
•
•
1111 = 1:16 P ostscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh,8Bh,
10Bh, 18Bh INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
11h TM R2 Timer2 Module Register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devices; always maintain these bits clear.
2003-2013 Microchip Technology Inc. DS30498D-page 87
PIC16F7X7
9.0 CAPTURE/COMPARE/PWM
MODULES
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
The CCP1, CCP2 and CCP3 modules are identical in
operatio n, with th e except ion being the operati on of the
specia l event trigger. Table 9-1 and Table 9-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 and CCP3
operate the same as CCP1, except where noted.
9.1 CCP1 Module
Capture/Compare/PWM Register 1 (CCPR1) is
comprised of two 8-bit registers: CCPR1L (low byte)
and C CPR1H (high byte). T he CCP1C ON register con-
trols the operation of CCP1. The special event trigger
is generated by a compare match and will clear both
TMR1H and TMR1L registers.
9.2 CCP2 Module
Capture/Compare/PWM Register 2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is gen-
erated by a compare match; it will clear both TMR1H and
TMR1L registers and s tart an A/D conversion (if the A/D
module is enabled).
Additional information on CCP modules is available in
the “PIC® Mid-Range MCU Family Reference Manual”
(DS33023) and in Application Note AN594 “Using the
CCP Module(s)” (DS005 94).
9.3 CCP3 Module
Capture/Compare/PWM Register 3 (CCPR3) is com-
prised of two 8-bit registers: CCPR3L (low byte) and
CCPR3H (high byte). The CCP3CON register controls
the operation of CCP3.
TABLE 9-1: CCP MODE – TIMER
RESOURCES REQUIR ED
TABLE 9-2: INTERACTION OF TWO CCP MODULES
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time base.
Capture Compare Same TMR1 time base.
Compare Compare Same TMR1 time base.
PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt).
The rising edges are aligned.
PWM Capture None.
PWM Compare None.
PIC16F7X7
DS30498D-page 88 2003-2013 Microchip Technology Inc.
REGISTER 9-1: CCPxCON: CCPx CONTROL REGISTER (ADDRESS 17h, 1Dh, 97h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 CCPxX:CCPxY: PWM Least Significant bits
Capture mo de:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits
0000 =Capture/Compare/PWM disabled (resets CCPx module)
0100 =Capture mode, every falling edge
0101 =Capture mode, every rising edge
0110 =Capture mode, every 4th rising edge
0111 =Capture mo de, ev ery 16th rising edge
1000 =Compare mode, set output on match (CCPxIF bit is set)
1001 =Compare mode, clear output on match (CCPxIF bit is set)
1010 =Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is
unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected);
CCP1 cle ars T i mer1; C CP2 clea rs Timer1 and st arts an A/D conv ersion (if A/D modul e
is enable d)
11xx =PWM mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 89
PIC16F7X7
9.4 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 r egister wh en an eve nt occurs
on pin RC2/CCP1. An event is defined as one of the
following and is configured by CCPxCON<3:0>:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
An even t is sel ected by c ontrol bit s, CCP1 M3:CCP1M 0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCP1IF (PIR1<2>), is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value is overwritten by the new
captured value.
9.4.1 CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC<2> bit.
FIGURE 9-1: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
9.4.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture ope ration may not wo rk.
9.4.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit,
CCP1IE (PIE1<2>), clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operati ng mode.
9.4.4 CCP PRESCALER
There are four prescaler settings specified by bits,
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any Reset will clear
the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleare d, therefore , the first cap ture may be from
a non-zero prescaler. Example 9-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 9-1: CHANGIN G BETWEEN
CAPTURE PRESCALERS
9.5 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC 2/CCP1 pin is:
• Driven high
•Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 9-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
capture co ndition.
CCPR1H CCPR1L
TMR1H TMR1L
Set Flag bit CCP 1IF
(PIR1<2>)
Capture
Enable
Q’s CCP1CON<3:0>
RC2/CCP1
Prescaler
1, 4, 16
and
Edge Detect
pin
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
;the new prescaler
;move value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
;value
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Event Trigger
Set Flag bit CCP1IF
(PIR1<2>)
Match
RC2/CCP1
TRISC<2>
CCP1CON<3:0>
Mode Select
Output Enable
pin
Special Event Trigger will:
• clear TMR1H and TMR1L registers
• NOT set interrupt flag bit, TMR1IF (PIR1<0>)
• (for CCP2 only) set the GO/DONE bit (ADCON0<2>)
PIC16F7X7
DS30498D-page 90 2003-2013 Microchip Technology Inc.
9.5.1 CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an
output by clearing the TRISC<2> bi t.
9.5.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
9.5.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not aff ect ed. The CCP1 IF or CCP 2IF bit is
set, causing a CCP interrupt (if enabled).
9.5.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 regi ste r pai r. Thi s al lows the CCPR 1 re gis ter to
ef fectively b e a 16-bit progra mmable pe riod registe r for
Timer1.
The special event trigger output of CCP2 resets the
TMR1 re gist e r p ai r and starts an A/D co nv ersi on (if th e
A/D module is ena bled).
TABLE 9-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
Note: The special event trigger from the CCP1
and CCP2 modules will not set interrupt
flag bit, TMR1IF (PIR1<0 >).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 OSFIF CMIF LVDIF —BCLIF— CCP3IF CCP2IF 000- 0-00 000- 0-00
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 OSFIE CMIE LVDIE —BCLIE—CCP3IECCP2IE000- 0-00 000- 0-00
87h TRISC PORTC D at a Dir ection Regist er 1111 1111 1111 1111
0Eh TMR1L Holding Register for the Lea st Signi fican t Byte of t he 16-bi t TMR1 Re giste r xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Re gist er fo r the Most Signi fica nt Byte of the 16-bit TMR1 Regist er xxxx xxxx uuuu uuuu
10h T1CON — T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
15h CCPR1L Capture/Compare/PWM Regist er 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compare/ PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
95h CCPR3L Capture/Compare/PWM Register 3 (LSB) xxxx xxxx uuuu uuuu
96h CCPR3H Capture/Compare/PWM Register 3 (MSB) xxxx xxxx uuuu uuuu
97h CCP3CON —— CCP3X CCP3Y CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16F737/767 devices; always maintain these bits clear.
2003-2013 Microchip Technology Inc. DS30498D-page 91
PIC16F7X7
9.6 PWM Mode (PWM)
In Pulse-Width Modulation mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC dat a latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an out put.
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a ste p-by-step proc edure on how t o set up the CC P
module for PWM operation, see Section 9.6.3 “Setup
for PWM Operatio n”.
FIGURE 9-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 9-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 9-4: PWM OUTPUT
9.6.1 PWM PE RIO D
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 9-1:
PWM frequency is defined as 1/[PWM period].
When TM R2 is equal to PR2, t he following three event s
occur on the next increment cycl e:
•TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from C CPR1L into
CCPR1H
9.6.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10- b i t re so l uti on is av ai l ab le. T he CC PR 1L c on tai ns
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 9-2:
CCPR1L and CCP1CON<5:4> can be written to a t any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
Note: Clearing the CCP1CON register will force
the CCP1 PWM o utpu t la tch to th e de fau lt
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(1)
RQ
S
Duty Cycle Registers CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
(Note 1)
Note 1: The 8-bit timer is concatenated with the 2-bit
internal Q clock or 2 bits of the prescaler to create
the 10-bit time base.
Period
Duty Cycle
TMR2 = P R 2
TMR2 = Duty Cycle
TMR2 = PR2
TMR2
Reset TMR2
Reset
Note: The Timer2 postscaler (see Section 9.4
“Capture M ode”) is not used in the deter-
minatio n of th e PWM f requ ency. The post-
scaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Pres cale Value)
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
PIC16F7X7
DS30498D-page 92 2003-2013 Microchip Technology Inc.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
The ma ximum P WM res olut ion (b its) fo r a giv en PW M
frequenc y is given by the formula:
EQUATION 9-3:
9.6.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register .
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable T imer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 9-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
TABLE 9-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
log(FPWM
log(2)
FOSC )
bits
=
Resolution
PWM Frequency 1.22 kHz 4 .88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resol ution (bits) 10 10 1 0 8 7 6.6
A d d res s Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 OSFIF CMIF LVDIF —BCLIF —CCP3IF CCP2IF 000- 0-00 000- 0-00
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 OSFIE CMIE LVDIE —BCLIE —CCP3IE CCP2IE 000- 0-00 000- 0-00
87h TRISC PORTC Data Dire ction Reg ister 1111 1111 1111 1111
11h TMR2 Timer2 Module Register 0000 0000 0000 0000
92h PR2 T imer2 Period Register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON —— CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
95h CCPR3L Capture/Compare/PWM Register 3 (LSB) xxxx xxxx uuuu uuuu
96h CCPR3H Capture/Compare/PWM Register 3 (MSB) xxxx xxxx uuuu uuuu
97h CCP3CON —— CCP3X CCP3Y CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PW M and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F737/767 devi ces; always maintain these bits cl ear.
2003-2013 Microchip Technology Inc. DS30498D-page 93
PIC16F7X7
10.0 MASTER SYNCHRONOUS
SERIAL PORT (MS SP)
MODULE
10.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
periphera l or m icroc ontroll er dev ices. Th ese p eriphera l
devices may be serial EEPROMs, shift registers,
displa y drivers, A/D converte rs, etc. The MSSP modul e
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
•Master mode
• Multi-Master mode
• Slave mode
10.2 Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON and SSPCON2). The use
of the se registers and thei r ind iv idu al c on fig uration bits
differ significantly, depending on whether the MSSP
module is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
10.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and recei ved simult aneously. All four modes
of SPI are supported. To accomplish communication,
typically thre e pins are use d:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/LVDIN/SS/C2OUT
Figure 10-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 10-1: MSSP BLOCK DIAGRAM
(SPI MODE)
Read Write
Internal
Data Bus
SSPSR Reg
SSPM3:SSPM0
bit 0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
TOSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX in SSPSR
TRIS bit
2
SMP:CKE
RC4/SDI/
RC5/SDO
RA5/AN4/
( )
SSPBUF Reg
LVDIN/SS/
RC3/
SCK/
Peripheral OE
C2OUT
SDA
SCL
PIC16F7X7
DS30498D-page 94 2003-2013 Microchip Technology Inc.
10.3.1 REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register (SSPCON)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
SSPCON and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buff ered. A write to SSPBUF will write to bo th SSPBUF
and SSPSR.
REGISTER 10-1: SSPSTAT: MSSP STATUS (SPI MODE) REGISTER (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
bit 7 SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6 CKE: SPI Clock Edge Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>).
bit 5 D/A: Data/Address bit
Used in I2C mode only.
bit 4 P: Stop bit
Used in I2C mode onl y . This bit is cl eared when the MSSP module is disabled, SSPEN is cleared.
bit 3 S: Start bit
Used in I2C mode only.
bit 2 R/W: Read/Write bit Info rma t io n
Used in I2C mode only.
bit 1 UA: Update Address bit
Used in I2C mode only.
bit 0 BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 95
PIC16F7X7
REGISTER 10-2: SSPCON: MSSP CONTROL (SPI MODE) REGISTER 1 (ADDRESS 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word.
(Must be cleared in software.)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicato r bit
SPI Slave mode:
1 = A new by te is re ceived whil e the SSPBUF register i s still holding the previous data . In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if on ly transmitting data, to avoid setting overflow.
(Must be cleared in software.)
0 = No overflow
Note: In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: When enabled, these pins must be properly configured as input or output.
bit 4 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101 = SPI S lave mod e, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note: Bit combinations not specifically listed here are either reserved or implemented in
I2C mo de onl y.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F7X7
DS30498D-page 96 2003-2013 Microchip Technology Inc.
10.3.2 OPERATION
When initializing the SPI, several options need to be
specif ied. This is done by progra mming the ap propriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a Transmit/Receive Shift register
(SSPSR) and a Buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full detect bit, BF
(SSPSTAT<0>) and the interrupt flag bit, SSPIF, are set.
This double-buffering of the received data (SSPBUF)
allows the next byte to start recep tion before reading the
data that was just received. Any write to the SSPBUF
register during transmission/reception of data will be
ignored and the Write Collision detect bit, WCOL
(SSPCON<7>), will be set. User sof tware must clear the
WCOL bit so that it can be determined if the following
write(s) to the SSPBUF register completed successfully .
When the application software is expecting to receive
valid da ta, the SSPBUF shoul d be read before th e next
byte of dat a to transfer is writ ten to the SSPBUF. Buffer
Full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the MSSP interrupt is used to
determine when the transmission/reception has com-
pleted. T he SSPBUF must be rea d and/or written. If the
interrupt method is not goi ng to b e u se d, then s of tw a re
polling can be d one to ensure that a write co llision d oes
not occur. Example 10-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
The SSPSR is n ot directly re adable or wri table and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 10-1: LOADING TH E SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?
BRA LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
2003-2013 Microchip Technology Inc. DS30498D-page 97
PIC16F7X7
10.3.3 ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed. That is:
• SDI is a uto matically control led by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• SCK (Slave mode) must have TRISC<3> bit set
•SS
must have TRISA<5> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
10.3.4 TYPICAL CO NNEC TI ON
Figure 10-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock e dge and l atched on the oppos ite edge
of the cloc k. Both processors should be prog rammed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master send s data–Slave sends dummy d ata
• Master send s data–Slave sends data
• Master sends dummy data–Slave sends data
FIGURE 10-2: SPI MASTE R/S LAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROC ES SOR 1
SCK
SPI Master SS PM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slave SSPM3:SSPM0 = 010xb
Serial Clock
PIC16F7X7
DS30498D-page 98 2003-2013 Microchip Technology Inc.
10.3.5 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 10-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF registe r is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will co ntinue to shift in the sign al present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if it is a n orm al re ce iv ed b yte (interrupts and st a t us bits
appropriately set). This could be useful in receiver
applications, such as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately program-
ming the CKP bi t (SSPCON<4>). This then, would give
waveforms for SPI communication as shown in
Figure 10-3, Figure 10-5 and Figure 10-6, where the
MSB is t rans m itte d f irst. In Master mode, the SPI cl oc k
rate (bit rate) is user programmable to be one of the
following:
•F
OSC/4 (or TCY)
•FOSC/16 (or 4 • TCY)
•F
OSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 10-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
dat a is shown.
FIGURE 10-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit 7 bit 6 bi t 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
Next Q4 Cycl e
after Q2
bit 0
2003-2013 Microchip Technology Inc. DS30498D-page 99
PIC16F7X7
10.3.6 SLAVE MODE
In Slave m ode , the data is transmitted and rece iv ed a s
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF inte rrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times, as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCK pin. The Idle
state is determined by the CKP bit (SSPCON1<4>).
10.3.7 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode wit h SS pin control ena bled
(SSPCON<3:0> = 4h). The pin must not be driven low
for the SS pin to function as an input. The data latch
must be high. When the SS pin is low , tran smission and
receptio n are enab led and the SDO pin is driven. When
the SS pin goes hi gh , th e SD O pin is no lo n ge r dr iv en ,
even if in the middle of a tran smitted byte an d becomes
a floating output. External pull-up/pull-down resistors
may be desirable, depending on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an in put. This d isables transmissi ons from th e SDO.
The SDI can always be left as an input (SDI function)
since it cann ot cre ate a bus con flict.
FIGURE 10-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Slave mode with SS pin
control enabled ( SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
2: If the SPI is us ed in Slave mo de with CK E
set, then the SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit 7
SDO bit 7 bit 6 bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7 bit 0
Next Q4 Cycle
after Q 2
PIC16F7X7
DS30498D-page 100 2003-2013 Microchip Technology Inc.
FIGURE 10-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 10-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit 7
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Wr i te t o
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Optional
Next Q4 Cycle
after Q 2
bit 0
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit 7 bit 0
SDO bit 6 bit 5 b i t 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPS R to
SSPBUF
SS
Flag
Not Optional
Next Q4 Cycle
after Q2
bit 7
2003-2013 Microchip Technology Inc. DS30498D-page 101
PIC16F7X7
10.3.8 SLEEP OPERATION
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI T ransmit/Receive Shift register
operat es asy nchron ously to the devi ce. Th is al lows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bit s have been received , the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
10.3.9 EFFECTS OF A RESET
A Reset disable s the MSSP module and termina tes the
current transfer.
10.3.10 BUS MODE COMPATIBILITY
Table 10-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 10-1: SPI BUS MODES
There is also an SMP bit which controls when the data
is sampled.
TABLE 10-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Standard SPI Mode
Terminology
Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA PORTA Dat a Direction Register 1111 1111 1111 1111
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF and PSPI E bits are reserved on 28-pin devices; always maintain these bits clear.
PIC16F7X7
DS30498D-page 102 2003-2013 Microchip Technology Inc.
10.4 I2C Mode
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs or output s
through the TRISC<4:3> bits.
FIGURE 10-7: MSSP BLOCK DIAGRAM
(I2C™ MODE)
10.4.1 REGISTERS
The MSSP module has six registers for I2C oper ation .
These are:
• MSSP Control Register (SSPCON)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address when
the SSP is configured in I2C Slave mode. When the
SSP is configured in Master mode, the lower seven bits
of SSPADD act as the Baud Rate Generator reload
value.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buff ered. A write to SSPBUF will write to bo th SSPBUF
and SSPSR.
Read Write
SSPSR Reg
Match Detect
SSPADD Reg
Start and
Stop bit Detect
SSPBUF Reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT Reg)
RC3/SCK/
RC4/
Shift
Clock
MSb
SDI/ LSb
SDA
SCL
2003-2013 Microchip Technology Inc. DS30498D-page 103
PIC16F7X7
REGISTER 10-3: SSPSTAT: MSSP STATUS (I2C MODE) REGISTER (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
bit 7 SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected las t
0 = Stop bit was not detected last
Note: This bit is cleared on Reset and when SSPEN is cleared.
bit 3 S: Start bit
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
Note: This bit is cleared on Reset and when SSPEN is cleared.
bit 2 R/W: Read/Write bit Info rma tio n bit (I2C mode only)
In Slave mode:
1 = Read
0 = Write
Note: This bit holds the R/W bit information following the last address match. This bit is
only valid from the address match to the next Start bit, Stop bit or not ACK bit.
In Master mo de:
1 = Transmit is in progress
0 = Transmit is not in progress
Note: ORing this b it with SEN, RSEN, PEN, RCEN o r ACKEN will i ndicate i f the MSSP i s
in Idle mode.
bit 1 UA: Update Address bit (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
In Receive mode:
1 = Data tr ansmit in progress (does n ot include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F7X7
DS30498D-page 104 2003-2013 Microchip Technology Inc.
REGISTER 10-4: SSPCON: MSSP CONTROL (I2C MODE) REGISTER 1 (ADDRESS 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for
a transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6 SSPOV: Receive Overflow Indicato r bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be
cleared in software)
0 = No overflow
In Transmit mode:
This is a “don’ t care” bit in Transmit mode.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: When enabled, the SDA an d SCL pins must be properly co nfigured a s input o r output.
bit 4 CKP: SCK Release Control bit
In Slave mode:
1 = Release c lock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In Master mode:
Unused in this mode.
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Fi rmware Controlled Master mode (slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Note: Bit combinations not specifically listed here are either reserved or implemented in
SPI mode only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 105
PIC16F7X7
REGISTER 10-5: SSPCON2: MSSP CONTROL (I2C MODE) REGISTER 2 (ADDRESS 91h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
bit 7 GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabl ed
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from s lave
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowle dge
0 = Acknowledge
Note: Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
bit 3 RCEN: Receive Enable bit (Master mode only)
1 = Enables Receive mode for I2C
0 = Re ceive Id le
bit 2 PEN: Stop Condition Enable bit (Master mode only)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only)
1 = Initiate Repeated S tart condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is enabled for slave transmit only (PIC16F87X compatibility)
Note: For bit s ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F7X7
DS30498D-page 106 2003-2013 Microchip Technology Inc.
10.4.2 OPERATION
The MSSP module functions are enabled by setting
MSSP enable bit, SSPEN (SSPCON<5>).
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
•I
2C M a st er mode, cloc k = O s cil la tor /4 (SSPADD + 1 )
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Slave mode (7-bit address), with Start and
Stop bit interrupts enabled
•I
2C Slave mode (10-bit address), with Start and
Stop bit interrupts enabled
•I
2C Firmware Controlled Master mode, slave is Idle
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain, pro-
vided these pins are programmed to inputs by setting
the appro priate TRISC b its. To ensure pro per operation
of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.
10.4.3 SL AV E MODE
In Slave mod e, the SCL and SDA pin s must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (sl ave-tran smit ter).
To ensure proper communication of the I2C Slave
mode, the TRIS bits (TRISx [SDA, SCL]) correspond-
ing to the I2C pins must be set to ‘1’. If any TRIS bits
(TRISx<7:0>) of the port containing the I2C pins
(PORTx [SDA, SCL]) are changed in software, during
I2C communication using a Read-Modify-Write
instruction (BSF, BCF), then the I2C mode may stop
functioning properly and I2C communication may
suspend. Do not change any of the TRISx bits (TRIS
bits of the port containing the I2C pins) using the
instruction BSF or BCF during I2C communication. If it
is absolutely necessary to change the TRISx bits
during communication, the following method can be
used:
The I2C Slave m od e h ardware will always ge nera te an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits.
When an add ress is matched, or the data transfer af ter
an add res s mat ch i s rece ived , th e ha rdw are au tom ati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
• The overflow bi t, SSPOV (SSPCON<6>), was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by readi ng the SSPBUF register , while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low fo r pro per op eration. Th e h igh and low times o f th e
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
10.4.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a S t art conditio n to occur. Follow ing the S t art condi tion,
the 8 bits are shifted in to the SSPSR register . All incom-
ing bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
MOVF TRISC, W ; Example for a 40-pin part such as the PIC16F877A
IORLW 0x18 ; Ensures <4:3> bits are ‘11’
ANDLW B’11111001’ ; Sets <2:1> as output, but will not alter other bits
; User can use their own logic here, such as IORLW, XORLW and ANDLW
MOVWF TRISC
2003-2013 Microchip Technology Inc. DS30498D-page 107
PIC16F7X7
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) o f the firs t address b yte spec ify if t his is a 1 0-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for
10-bit address is as follows, with steps 7 through 9 for
the slave-transmitter:
1. Receive first (high) byte of address (bits SSPIF,
BF and UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
5. Update the SSPADD regi ster with the first (hig h)
byte of address. If match releases SCL line, this
will clear bit UA .
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
10.4.3.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleare d. The re ceived ad dre ss is loa ded in to
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Ack no w led ge (ACK) pulse is given. An ov erfl ow
condition is defined as either bit BF (SSPSTAT<0>) is
set or bit SSPOV (SSPCON<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF (PIR1<3>), must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON<0> = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting bit,
CKP (SSPCON<4>). See Section 10.4.4 “Clock
Stretching” for more detai l.
10.4.3.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPST A T register is set. The received address is loaded
into the SSPBUF register . The ACK puls e will be sent on
the ninth bit and pin RC3/SCK/SCL is held low regard-
less of SEN (see Section 10.4.4 “Clock Stretching”
for more detail). By stretching the clock, the master will
be unable to asse rt another cl ock pulse u ntil the slave is
done preparing the transmit data. The transmit data
must be loaded into the SSPBUF register, which also
loads the SSPSR register. Then pin RC3/SCK/SCL
should be enabled by setting bit CKP (SSPCON<4>).
The eight data bits are shifted out on the falling edge of
the SCL input. This ensures that the SDA signal is valid
during the SCL high time (Figure 10-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the nin th SCL input pu lse. If the SDA
line is high (not ACK), then the data transfer is com-
plete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT regis-
ter) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit da ta must be loaded into the SSPBUF r egister .
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
PIC16F7X7
DS30498D-page 108 2003-2013 Microchip Technology Inc.
FIGURE 10-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S1 234 567891 234567891 2345 789 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W = 0
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
CKP (CKP does not reset to ‘0’ wh e n S E N = 0)
2003-2013 Microchip Technology Inc. DS30498D-page 109
PIC16F7X7
FIGURE 10-9: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9
SSPBUF is written in software
Cleared in software
Data in
sampled
S
ACK
Transmitting Data
R/W =
1
ACK
Receiving Address
A7 D7
9 1
D6 D5 D4 D3 D2 D1 D0
2 3 4 5 6 7 8 9
SSP BUF is writte n in s of tw are
Cleared in software From SSPIF ISR
Transmitting Data
D7
1
CKP
P
ACK
CK P is s e t in so ftware CK P is s e t in so ftware
while CPU
SCL held low
From SSPIF ISR
responds to SSPIF
PIC16F7X7
DS30498D-page 110 2003-2013 Microchip Technology Inc.
FIGURE 10-10 : I2C™ SLAV E MO DE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3> )
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
11110A9A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in softw are
D2
6
Cleared in software
Receive Second Byte of Address
Cleared by hardw are
when SSPADD is updated
with low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON<6>)
SSPOV is set
because SSPB UF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
2003-2013 Microchip Technology Inc. DS30498D-page 111
PIC16F7X7
FIGURE 10-11: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 1 1 1 1 0 A8
R/W = 1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus master
terminates
transfer
A9
6
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address.
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address.
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1
ACK
D2
6
Tran smitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Cleared in softw are
Completion of
clears BF flag
CKP (SSPCON<4>)
CKP is set in software
CKP is automatically cleared in hardware holding SCL low
Clock is held low until
update of SSPADD has
taken place
data transmission
Clock is held low until
CKP is set to ‘1’
BF flag is clear
third address sequence
at the end of the
PIC16F7X7
DS30498D-page 112 2003-2013 Microchip Technology Inc.
10.4.4 CLOCK STRETCHING
Both 7-bit and 10-bit Slave modes implement
automatic clock stre tch ing during a transmit sequence.
The SEN bit (SSPCON2<0>) al lows clock stretch ing to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
10.4.4.1 Clock Stretching for 7-bit Slave
Receive Mo de (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock, at the end of the ACK sequence if the BF bit
is set, the CKP bit in the SSPCON register is auto-
matically cleared, forcing the SCL outpu t to be held low.
The CKP being cleared to ‘0’ will assert the SCL line
low. The CKP bit must be set in the user’s ISR before
reception is allowed to continue. By holding the SCL
line low, the user has time to service the ISR and read
the contents of the SSPBUF before the master device
can initiate another receive sequence. This will prevent
buffer overruns from oc curring (see Figure 10 -13).
10.4.4.2 Clock Stretching for 10-bit Slave
Receive Mo de (SEN = 1)
In 10-bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not c lea red . Duri ng t his time, if th e UA b it i s
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address, with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
10.4.4.3 Clock Stretching for 7-bit Slave
Transmit Mode
7-bit Sl ave Transmit mode i mplem ent s clo ck str etchin g
by clearing the CKP bit after the falling edge of the
ninth clock, if the BF bit is clear. This occurs
regardless of the state of the SEN bit.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 10-9).
10.4.4.4 Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is
controlled during the first two address sequences by
the state of the UA bit, just as it is in 10-bit Slave
Receive mode. The first two addresses are followed
by a third address sequence, which contains the high-
order bits of the 10-bit address and the R/W bit set to
‘1’. After the third address sequence is performed, the
UA bit is not set, the module is now configured in
Transmit mode and clock stretching is controlled by
the BF flag as in 7-bit Slave Transmit mode (see
Figure 10-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Note: If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling ed ge of the ni nth c lock oc curs and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
Note 1: If the u ser lo ads the co nten t s of SSPBUF,
setting the BF bit bef ore the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretchin g will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
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10.4.4.5 Clock Synchronization
and the CKP Bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’; however, setting the CKP bit will not assert the
SCL output low until the SCL output is already
sampled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 10-12).
FIGURE 10-12: CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX – 1DX
Write
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock
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DS30498D-page 114 2003-2013 Microchip Technology Inc.
FIGURE 10-13 : I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3> )
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S123456789 123456789 12345 789 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W = 0
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
CKP
CKP
written
to ‘1’ in
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
software
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock Clock is not held low
because ACK = 1
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
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FIGURE 10-14 : I2C™ SLAV E MO DE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
11110A9A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
Cleared in software
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
UA (S SP ST AT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON<6>)
CKP written to ‘1’
Note: An update of the SSPADD register before the falling edge of
the ninth clock will have no effect on UA and UA will remain
set.
Note: An up da te of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set. in software
Clock is held low until
update of SSPADD has
taken place
of ninth clock
of ninth clock
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
Dummy read of SSPBUF
to clear BF flag
Clock is held low until
CKP is set to ‘1’Clock is not held low
because ACK = 1
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DS30498D-page 116 2003-2013 Microchip Technology Inc.
10.4.5 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed b y
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General Call Enable bit (GCEN) is enabled
(SSPCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPSR and the address is
compared against the SSPADD. It is also compared to
the general call address and fixed in hardware.
If the general call address matches, the SSPSR is
transferre d to the S SPBUF, the BF flag bi t is set (ei ghth
bit) and on the falling edg e of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
When the i nterrupt is serviced, the s ou rce f or the int er-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the seco nd half of the addre ss to match an d the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set and while the slave
is configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 10-15).
FIGURE 10-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
SDA
SCL S
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
Cleared in software
SSPBUF is read
R/W = 0
ACK
General Call Address
Address is compared to general call address
GCEN (SSPCON2<7>)
Receiving Data ACK
123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interru pt
‘0’
‘1’
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10.4.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I 2C bus may be taken when the P bit is
set or the bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options:
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register, initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated Start
FIGURE 10-16: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Note: The MSSP module, when configured in
I2C Mast er mode, does n ot allow que ueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediatel y write the SSPBUF register to
initiate transmi ssion before the S tart condi-
tion is complet e. In th is ca se, the SSPBUF
will not be wri tten to an d the WCO L bi t will
be set, indicating that a write to the
SSPBUF did not occur.
Read Write
SSPSR
Start bit, Stop bit,
Start bit Detect
SSPBUF
Internal
Data Bus
Set/Reset S, P, WCOL (SSPSTAT)
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL
SCL In
Bus Collision
SDA In
Receive Enable
Clock Cntl
Clock Arbitrate/WCOL Detect
(hold off clock sourc e)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM3:SSPM0
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DS30498D-page 118 2003-2013 Microchip Technology Inc.
10.4.6.1 I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the S tart and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer , the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
recei vin g dev ice ( 7 bits) and the Rea d/Writ e (R/W) bit.
In this case, the R/W bit wi ll be lo gic ‘0’ . Se ri al da ta is
transmitted 8 bits at a tim e. After each byte is tr ansm it-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R /W bit. In this cas e, the R/W bit wil l be
logic ‘ 1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate a receive bit. Serial
data is rece ived via S DA, while SCL o utp uts the se ri al
clock. Se rial dat a is received 8 bit s at a time. Aft er each
byte is received, an Acknowledge bit is transmitted.
Start and Stop conditions indicate the beginning and
end of transmission.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 10.4.7 “Baud Rate Generator” for more
detail.
A typical transmit sequence would go as follows:
1. The user generates a Start condition by setting
the Start enable bit, SEN (SSPCON2<0>).
2. SSPIF is set. The MSSP module will wait the
required Start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is s hi f ted out the SDA p in un til al l 8 bits
are transmitted.
5. The MSSP module shif t s in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP mo dule g enerate s an interrup t at th e
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data i s sh ifte d out the SD A pin until all 8 bit s a re
transmitted.
9. The MSSP module shif t s in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP modul e gene rates an int errupt a t the
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
11. The user generates a Stop condition by setting
the Stop enable bit, PEN (SSPCON2<2>).
12. Interrupt is ge nerated once the Stop condition i s
complete.
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10.4.7 BAUD RATE GENERATOR
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 10-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until an other re load h as t aken pl ace. Th e BRG c ount i s
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of th e last dat a bit is followed by ACK), the int ernal
clock wi ll aut omatica lly st op count ing and t he SCL pin
will rema in in it s last state.
Table 10-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 10-17: BAUD RATE GENER ATOR BLOCK DIAGRAM
TABLE 10-3: I2C™ CLOC K RATE w/BRG
FOSC FCY FCY*2 BRG Value FSCL
(2 Rollovers of BRG)
40 MHz 10 MHz 20 MHz 18h 400 kHz(1)
40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz
40 MHz 10 MHz 20 MHz 63h 100 kHz
16 MHz 4 MHz 8 MHz 09h 400 kHz(1)
16 MHz 4 MHz 8 MHz 0Ch 308 kHz
16 MHz 4 MHz 8 MHz 27h 100 kHz
4 MHz 1 MHz 2 MHz 02h 33 3 kHz(1)
4 MHz 1 MHz 2 MHz 09h 100 kHz
4 MHz 1 MHz 2 MHz 00h 1 MHz (1)
Note 1: The I2C ™ in terface d oes n ot conform to the 400 k Hz I 2C s pec ifi ca tio n (w h ic h a ppl ie s to rates g r ea ter tha n
100 kHz) in all details, but may be used with care where higher rates are required by the application.
SSPM3:SSPM0
BRG Down Counter
CLKO FOSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control Reload
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DS30498D-page 120 2003-2013 Microchip Technology Inc.
10.4.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 10-18).
FIGURE 10-18: BAUD RATE GENER ATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
SCL deasserted but slave holds
DX – 1DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration) SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
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10.4.8 I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Condition Ena ble bi t, SEN (SSPCON2< 0>). If th e SDA
and SCL pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPADD<6: 0> and st arts it s count . If SCL an d SDA are
both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit (SSPSTAT<3>) to
be set. Following this, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
resumes its count. When the Baud Rate Generator
times out (TBRG), the SEN bit (SSPCON2<0>) will be
automatically cleared by hardware, the Baud Rate
Generat or is susp ended , leavin g the SDA line hel d low
and the Start condition is complete.
10.4.8.1 WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 10-19: FIRST START BIT TIMING
Note: If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low , or if during the S tart condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
conditi on is complete.
SDA
SCL
S
TBRG
1st bit 2nd bit
TBRG
SDA = 1, At completion of Start bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
hardware clears SEN bit
TBRG
Write to SEN bit occurs here Set S bit (SSPSTAT<3>)
and sets SSPIF bit
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10.4.9 I2C MASTER MODE REP EA TED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPADD<5:0> and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<6:0> and begins count-
ing. SDA and SCL mu st be sampled high for one TBRG.
This ac tion is the n followed by assertio n of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held lo w. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
10.4.9.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buf fer are un ch anged (th e write doesn ’t
occur).
FIGURE 10-20: REPEATED START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus col lis ion dur ing th e Rep eat ed Start
conditi on oc curs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
SDA
SCL
Sr = Repeat ed Start
Write to SSPCON2
Write to SSPBUF occurs here
Falling edge of ninth clock.
End of Xmit.
At completion of St art bit,
hardware clears RSEN bit
1st bit
Set S (SSPSTAT<3>)
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change). SCL = 1
occurs here.
TBRG TBRG TBRG
and sets SSPIF
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10.4.10 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address, is accomplished by
simply writing a value to the SSPBUF register. This
action will set the Buffer Full flag bit, BF and allow the
Baud Rate Generator to begin counting and start the
next transmission. Each bit of address/data will be
shifted out onto the SDA pin after the falling edge of
SCL is asserted (see data hold time specification
parameter #106). SCL is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCL is released high (see data setup time
specification parameter #107). When the SCL pin is
release d hi gh , it is hel d that way for TBRG. The data on
the SDA pin must remain stable for that duration and
some ho ld time afte r the nex t falling e dge of SC L. Af ter
the eigh th bit is shif ted out (the falling edg e of the eighth
cloc k), the BF f lag is cle ared an d th e master releases
SDA. This allows the slave device being addressed to
respond with an ACK bit, during the ninth bit time, if an
address match occurred or if data was received
properly. The status of ACK is written into the ACKDT
bit on the falling edge of the ninth clock. If the master
receive s an Ack now ledge, the Acknow ledg e Status bi t,
ACKSTAT, is cleared. If no t, the bit is set. After t he ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 10-21).
After the write to the SSPBUF, each bit of address will
be shifted out on the fall ing edge of SC L un til a ll s eve n
address bits and the R/W bit are completed. On the
falling edge of the ei ghth clock , the master wil l deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On th e falling edge o f the ninth clock, the
master will sample the SDA pin to see if the address
was rec ognized by a sla ve. The st atus of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falli ng edge of the ninth clock transmis-
sion of the address, the SSPIF is set, The BF flag Is
cleared and th e Baud Ra te Genera tor is t urned o ff until
another write to the SSPBUF takes place, ho ldi ng SCL
low and allowing SDA to float.
10.4.10.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
10.4.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
10.4.10.3 ACKSTAT Status Flag
In T ran smit mod e, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK =0) and is set when the slav e does not Acknowl-
edge (ACK =1). A slave sends an Acknowledge when
it has recognized its address (including a general call)
or when the slave has properly received its data.
10.4.11 I2C MASTER MODE RECEP TION
Master mode recepti on is enabl ed by pro grammin g th e
Receive Enable bit, RCEN (SSPCON2<3>).
The Baud Rate Generator begins counting and on each
rollove r, the st a te of the SC L pin ch ang es (high -to-l ow /
low-to-high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bi t is set and the Baud Ra te Gener-
ator is s uspen ded from countin g, hold ing SC L low. The
MSSP is now in Idle st ate, awaiti ng the next comm and.
When the buffer is read by the CPU, the BF flag bit is
automatically cleared. The user can then send an
Acknowledge bit at the end of reception by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>).
10.4.11.1 BF Status Flag
In receiv e op eration, the BF bit is s et whe n an add r es s
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
10.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
10.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a dat a
byte), th e WCOL bi t is set an d the conte nts of th e buffer
are unchanged (the write doesn’t occur).
Note: The MSSP module must be in an Idle state
before the RCEN bit is set or t he RCEN bit
will be disregarded.
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DS30498D-page 124 2003-2013 Microchip Technology Inc.
FIGURE 10-21 : I2C™ MASTER MODE WAVEFORM (T RANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0
ACK
Transmitting Data or Second Half of 10-bit Address
R/W = 0Transmit Address to Slave
123456789 123456789 P
Cleared in software service routine
SSPBUF is written in software
from SSP interrup t
After Start condit ion, SEN clea red by hardware
S
SSPBUF written with 7-bit address and R/W
starts transmit
SCL held low
while CPU
responds to SSPIF
SEN = 0
Write to SSPCON2<0> (SEN = 1),
Start condition begins From Slave, clear ACKSTAT bit (SSPCON2<6>)
ACKSTAT in
SSPCON2 = 1
Cleared in software
SSPBUF written
PEN
R/W
Cleared in software
2003-2013 Microchip Technology Inc. DS30498D-page 125
PIC16F7X7
FIGURE 10-22 : I2C™ MASTER M ODE WAVEFORM (RECEPTION, 7-BI T ADDRESS)
P
98765
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 123456789 12345678 9 1234
Bus master
terminates
transfer
ACK Receiving Data from Slave
Receiving Data from Slave D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 1
Transmit Address to Slave
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1),
Write to SSPBUF occurs here. ACK from Slav e
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared in software
S t art XM IT.
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Cleared in software
Cleared in software
Set SSPIF interrupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
Cleared in
software
ACK from Master
Set SS PIF at end
Set SSPIF interrupt
at end of Acknowledge
sequence
Set SSPIF interrupt
at end of Acknow-
ledge sequence
of receive
Set ACKEN, start Acknowledge sequence
SDA = ACK D T = 1
RCEN cleared
automatically
RCEN = 1, start
next receive
Write to SSPCON2<4>
to start Acknowledge sequence,
SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared
automatically
responds to SSPIF
ACKEN
begin Start condition
Cleared in software
SDA = ACKDT = 0
SSPOV is set because
SSPBUF is still full
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
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DS30498D-page 126 2003-2013 Microchip Technology Inc.
10.4.12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the use r wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low . Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 10-23).
10.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buf fer are un chang ed (th e write doe sn ’t
occur).
10.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is
sample d low , th e Baud Rate G enerator is re loaded an d
counts down to ‘0’. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deass erted. Wh en the SDA pin is sam-
pled hi gh whil e SCL is high, the P bi t (SSPSTAT<4>) is
set. A TBRG la ter, the PEN bit is c leared and the SSPIF
bit is set (Figure 10-24).
10.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buf fer are un ch anged (th e write doesn ’t
occur).
FIGURE 10-23: ACKNOW LEDGE SEQUEN CE WAVEFORM
FIGURE 10-24: STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: TBRG = one Baud Rate Generator period.
SDA
SCL
Set SSPIF at the end
Acknowledge sequence starts here,
write to SSPCON2 ACKEN automatically cleared
Cleared in
TBRG TBRG
of receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software Set SSPIF at the end
of Acknowledge sequence
Cleared in
software
ACK
SCL
SDA
SDA asserted low before rising edge of clock to setup Stop condition
Write to SSPCON2,
set PEN
Falling edge of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
9th clock
SCL brought high after TBRG
Note: TBRG = one Baud Rate Generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
TBRG
ACK
P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
2003-2013 Microchip Technology Inc. DS30498D-page 127
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10.4.14 SLEEP OPERATION
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
10.4.15 EFFECT OF A RESET
A Reset disable s the MSSP module and termina tes the
current transfer.
10.4.16 MULTI-M AST ER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
deter mination of when the bus i s free. The S top (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPSTAT<4>) is set or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is at
the expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
10.4.17 MULTI-MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA by letting SDA float high and
another ma ste r assert s a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the da t a s am ple d on th e SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 10-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can b e written to. When the us er servic es th e
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condi-
tion was in progress when the bus collision occurred,
the condition is aborted, the SDA and SCL lines are
deasserted and the respective control bits in the
SSPCON2 register are cleared. When the user
servic es the b us collis ion Interru pt Service Routine and
if the I2C bus is free, the user can resume
communication by asserting a Start condition.
The master will continue to monitor the SDA and SCL
pins . I f a Stop c on d iti o n occ urs , th e SSPIF bit will be s e t.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detec tion of S t art and S to p conditio ns allows the determi -
nation of when the bus is fr ee. Contro l of the I2C bus can
be t aken when the P bit is set in the SSPSTAT registe r or
the bu s is Idle and th e S an d P b its are cle are d.
FIGURE 10-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source Sample SDA. While SCL is high,
data doesn’t match what is driven
Set bus collision
interrupt (BCLIF)
by the master. Bus collision has occurred.
by master
Data changes
while SCL = 0
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DS30498D-page 128 2003-2013 Microchip Technology Inc.
10.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA o r SCL are sampl ed low at the b eginning of
the Start condition (Figure 10-26).
b) SCL is s am pl ed l ow be fore SD A is asserted low
(Figure 10-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its Idle state
(Figure 10-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘ 1’ during the Start condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 10-28). If, h owever, a ‘1’ is sampled on the SDA
pin, the SD A pin is asser ted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
count s dow n to 0 an d dur ing this tim e, if the SCL pin i s
sampled as ‘0’, a bus collision does not occur. At the
end of t he BRG co unt , the SCL pin is a ss erte d lo w.
FIGURE 10-26: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that b us collision is not a factor
duri ng a Start cond iti on is that no t wo bus
masters can assert a S tart condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus
collis ion because the two masters must be
allowed to arbitrate the first address
follow ing the S tar t condit ion. If the addr ess
is the sam e, arbitr ation must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module resets into Idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SDA = 0, SCL = 1.
BCLIF
S
SSPIF
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF and BCLIF are
cleared in software
Set BCLIF,
Start condition. Set BCLIF.
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FIGURE 10-27: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 10-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN bus collision occurs. Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupt cleared
in software
bus collision occurs. Set BCLIF.
SCL = 0 before BRG time-out,
‘0’‘0’
‘0’‘0’
SDA
SCL
SEN
Set S
Less th an TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
in software
set SS PIF
SDA = 0, SCL = 1,
SCL pulled low after BRG
time-out
Set SS PIF
‘0’
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SDA pulled low by other master.
Reset BRG and assert SDA.
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DS30498D-page 130 2003-2013 Microchip Technology Inc.
10.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occu rs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user dea sserts SDA and the pin is a llowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision ha s occurred (i.e ., another
master is attempting to transmit a data ‘0’, see
Figure 10-29). If SDA is sampled high, the BRG is
reloaded and begins counting. If SDA goes from high-
to-low before the BRG times out, no bus collision
occurs because no two masters can assert SDA at
exactly the same time.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
tran smit a data ‘1’ during the Repeated Start condition
(Figure 10-30).
If at the end of the BR G time-out, both SCL and SDA are
still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SC L pin is
driven low and the Repeated S tart condition is complete.
FIGURE 10-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 10-30: BUS COLLISION DURING A REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared in software
‘0’
‘0’
S
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
in software
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG TBRG
‘0’
2003-2013 Microchip Technology Inc. DS30498D-page 131
PIC16F7X7
10.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) Af ter the SCL pin is deassert ed, SCL is sampled
low before SDA goes high.
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
floa t. Wh en t he p in i s sa mpled hig h (c loc k arbi tr atio n),
the Baud R ate Generator is load ed with SSPADD <6:0>
and cou nt s d own to 0. After the BRG times o ut, SDA i s
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 10-31). If the SCL pin is
sample d lo w befo re SD A is all owed to flo at hi gh , a bu s
collis ion occ urs. Thi s is anoth er case of a nother m aster
attempting to drive a data ‘ 0’ (Figure 10-32).
FIGURE 10-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 10-32: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sam pled
low after TBRG,
set BCLIF
‘0’
‘0’
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high,
set BCLIF
‘0’
‘0’
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DS30498D-page 132 2003-2013 Microchip Technology Inc.
NOTES:
2003-2013 Microchip Technology Inc. DS30498D-page 133
PIC16F7X7
11.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
The Addressable Universal Synchronous Asynchronous
Receiver Transmitter (AUSART) module is one of the
two serial I/O modules. (AUSART is also known as a
Serial Communications Interface or SCI.) The AUSART
can be configured as a full-duplex asynchronous system
that can communicate with peripheral devices, such as
CRT terminals and personal computers, or it can be
configured as a half-duplex synchronous system that
can communicate with peripheral devices, such as A/D
or D/A integrated circuit s , serial EEPROMs, etc.
The AUSART can be configured in the following
modes:
• Asynchronous (full-duplex)
• Synchro nous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have
to be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter.
The AUSART module also has a multi-processor
communication capability using 9-bit address detection.
REGISTER 11-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D
bit 7 bit 0
bit 7 CSRC: C loc k Source S ele ct bit
Asynchro nous mo de:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in Sync mode.
bit 4 SYNC: AUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 Unimplemented: Re ad as ‘0’
bit 2 BRGH: High Baud Rate Select bit
Asynchro nous mo de:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data, can be Parity bit
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS30498D-page 134 2003-2013 Microchip Technology Inc.
REGISTER 1 1-2: RCST A: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchro nous mo de:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchro nous mo de:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchro nous mo de 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and load of the receive buffer when
RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bi t can be used as parity bit
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receiving next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data
Can be parity bit but must be calcul ated by user firmware.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 135
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11.1 AUSART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and
Synchronous modes of the AUSART. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free running 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA<2>) also
controls the baud rate. In Synchronous mode, bit
BRGH is ignored. Table 11-1 shows the formula for
computation of the baud rate for different AUSART
modes which only apply in Master mode (internal
clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculate d
using the formula in Table 11-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
becaus e the FOSC/(16(X + 1 )) eq uat ion c an red uce th e
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
11.1.1 SAMPLING
The dat a on the RC7/RX/D T pin is sa mpled three time s
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
TABLE 11-1: BAUD RATE FORMULA
TABLE 11-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0
1
(Asynchronous ) Baud Rate = FOSC/(64(X + 1))
(Synchronous) Baud Rate = FOSC/(4(X + 1)) Ba ud Rate = FOSC/ (16(X + 1))
N/A
Legend: X = value in SPBRG (0 to 255).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
PIC16F7X7
DS30498D-page 136 2003-2013 Microchip Technology Inc.
TABLE 11-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
Baud
Rate
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
Kbaud %
Error
SPBRG
Value
(decimal) Kbaud %
Error
SPBRG
Value
(decimal) Kbaud %
Error
SPBRG
Value
(decimal)
0.3—————————
1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129
2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64
9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15
19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7
28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4
33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4
57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2
HIGH 1.221 — 255 0.977 — 255 0.610 — 255
LOW 312.500 — 0 250.000 — 0 156.250 — 0
Baud
Rate
(K)
FOSC = 4 MHz FOSC = 3.6864 MHz
Kbaud %
Error
SPBRG
Value
(decimal) Kbaud %
Error
SPBRG
Value
(decimal)
0.3 0.300 0 207 0.3 0 191
1.2 1.202 0.17 51 1.2 0 47
2.4 2.404 0.17 25 2.4 0 23
9.6 8.929 6.99 6 9.6 0 5
19.2 20.833 8.51 2 19.2 0 2
28.8 31.250 8.51 1 28.8 0 1
33.6 — — — — — —
57.6 62.500 8.51 0 57.6 0 0
HIGH 0.244 — 255 0.225 — 255
LOW 62.500 — 0 57.6 — 0
TABLE 11-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
Baud
Rate
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
Kbaud %
Error
SPBRG
Value
(decimal) Kbaud %
Error
SPBRG
Value
(decimal) Kbaud %
Error
SPBRG
Value
(decimal)
0.3—————————
1.2—————————
2.4 — — — — — — 2.441 1.71 255
9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64
19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31
28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21
33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18
57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10
HIGH 4.883 — 255 3.906 — 255 2.441 — 255
LOW 1250.000 — 0 1000.000 — 0 625.000 — 0
Baud
Rate
(K)
FOSC = 4 MHz FOSC = 3.6864 MHz
Kbaud %
Error
SPBRG
Value
(decimal) Kbaud %
Error
SPBRG
Value
(decimal)
0.3 — — — — — —
1.2 1.202 0.17 207 1.2 0 191
2.4 2.404 0.17 103 2.4 0 95
9.6 9.615 0.16 25 9.6 0 23
19.2 19.231 0.16 12 19.2 0 11
28.8 27.798 3.55 8 28.8 0 7
33.6 35.714 6.29 6 32.9 2.04 6
57.6 62.500 8.51 3 57.6 0 3
HIGH 0.977 — 255 0.9 — 255
LOW 250.000 — 0 230.4 — 0
2003-2013 Microchip Technology Inc. DS30498D-page 137
PIC16F7X7
TABLE 11-5: INTRC BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
Baud
Rate
(K)
FOSC = 8 MHz FOSC = 4 MHz FOSC = 2 MHz FOSC = 1 MHz
Kbaud %
Error
SPBRG
Value
(decimal) Kbaud %
Error
SPBRG
Value
(decimal) Kbaud %
Error
SPBRG
Value
(decimal) Kbaud %
Error
SPBRG
Value
(decimal)
0.3 NA — — 0.300 0 207 0.300 0 103 0.300 0 51
1.2 1.202 +0.16 103 1.202 +0.16 51 1.202 +0.16 25 1.202 +0.16 12
2.4 2.404 +0.16 51 2.404 +0.16 25 2.404 +0.16 12 2.232 -6.99 6
9.6 9.615 +0.16 12 8.929 -6.99 6 10.417 +8.51 2 NA — —
19.2 17.857 -6.99 6 20.833 +8.51 2 NA — — NA — —
28.8 31.250 +8.51 3 31.250 +8.51 1 31.250 +8.51 0 NA — —
38.4 41.667 +8.51 2 NA — — NA — — NA — —
57.6 62.500 +8.51 1 62.500 8.51 0 NA — — NA — —
TABLE 11-6: INTRC BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
Baud
Rate
(K)
FOSC = 8 MHz FOSC = 4 MHz FOSC = 2 MHz FOSC = 1 MHz
Kbaud %
Error
SPBRG
Value
(decimal) Kbaud %
Error
SPBRG
Value
(decimal) Kbaud %
Error
SPBRG
Value
(decimal) Kbaud %
Error
SPBRG
Value
(decimal)
0.3 NA — — NA — — NA — — 0.300 0 207
1.2 NA — — 1.202 +0.16 207 1.202 +0.16 103 1.202 +0.16 51
2.4 2.404 +0.16 207 2.404 +0.16 103 2.404 +0.16 51 2.404 +0.16 25
9.6 9.615 +0.16 51 9.615 +0.16 25 9.615 +0.16 12 8.929 -6.99 6
19.2 19.231 +0.16 25 19.231 +0.16 12 17.857 -6.99 6 20.833 +8.51 2
28.8 29.412 +2.12 16 27.778 -3.55 8 31.250 +8.51 3 31.250 +8.51 1
38.4 38.462 +0.16 12 35.714 -6.99 6 41.667 +8.51 2 NA — —
57.6 55.556 -3.55 8 62.500 +8.51 3 62.500 +8.51 1 62.500 +8.51 0
PIC16F7X7
DS30498D-page 138 2003-2013 Microchip Technology Inc.
11.2 AUSART Asynchronous Mode
In this mode, the AUSART uses standard Non-Return-
to-Zero (NRZ) format (one Start bit, eight or nine data
bits and one Stop bit). The most common data format
is 8 bits. An on-chip, dedicated, 8-bit Baud Rate
Generator can be used to derive standard baud rate
frequenc ies fr om the osci llator. The AUSART tran smit s
and rece ives the LSb first. Th e transmitter a nd receiv er
are fu nctionally inde pendent but us e the same d ata for-
mat and baud rate. The Baud Rate Gen erator produces
a clock , either x16 or x64 of the bi t shift rate, de pending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardw are but can be im pleme nted in so ftware (and
stored as the ninth data bit). Asynchronous mode is
stopped during Sleep.
Asynchronous mode is selected by clearing bit, SYNC
(TXSTA<4>).
The AUSART asynchronous module consists of the
following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
11.2.1 AUSART ASYNCHRONOUS
TRANSMITTER
The AUSART transmitter block diagram is shown in
Figure 11-1 . The heart of the tra nsmitter is the T ransmit
(Serial) Shift Regis ter (TSR). The Shi f t regi st er obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
softw are . Th e TSR re gi st e r is not lo ad e d un ti l t he Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
Once the TXR EG register trans fers the dat a to the TSR
register (occurs in one TCY), the TXREG register is
empty and flag bit, TXIF (PIR1<4>), is set. This
interrupt can be enabled/disabled by setting/clearing
enable bit, TXIE (PIE1<4>). Flag bit TXIF will be set
regardless of the state of enable bit TXIE and cannot be
cleared in software. It will reset only when new data is
loaded into the TXREG register. While flag bit TXIF
indica tes th e s t atus of the TXREG regi ste r, ano ther bit,
TRMT (TXSTA<1>), shows the status of the TSR
register. Status bit TRMT is a read- only bit which is set
when the TSR register is empty. No interrupt logic is
tied to thi s b it, s o th e us er h as to po ll t his bi t in o rder to
determine if the TSR register is empty.
Transmission is enabled by setting enable bit, TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the Baud Rate Generator (BRG) has produced a
shift clock (Figure 11-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 11-3).
Clearing enable bit TXEN during a transmission will
cause the tra nsm is s ion to be ab orte d and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to high-impedance.
In order to select 9-bit transmission, transmit bit, TX9
(TXSTA<6>), should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG
register can result in an immediate transfer of the data
to the TSR register (if the TSR is empty). In such a
case, an incorrect ninth data bit may be loaded in the
TSR registe r.
FIGURE 11-1: AUSART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit T XIF is set whe n enable bit TXEN
is set. TXIF is cle ared by loadi ng TXRE G.
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG Register
TSR Register
(8) 0
TX9
TRMT SPEN
RC6/TX/CK pin
Pin Buffer
and Control
8
2003-2013 Microchip Technology Inc. DS30498D-page 139
PIC16F7X7
When setting up an Asynchronous Transmission,
follow these steps:
1. Initialize th e SPBRG re gis te r for the ap propriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (see Section 11.1 “AUSART
Baud Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupt s are desired, then set enable bit TXIE.
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
FIGURE 11-2: ASYNCHRONOUS MASTER TRANSMISSION
FIGURE 11-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
TABLE 11-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Addr e s s N a m e Bit 7 Bit 6 Bit 5 B it 4 Bi t 3 B it 2 B it 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG AUSART Transmit Data Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
Word 1 Stop bit
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG
BRG O u tp ut
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
S tart bit Stop bit S t art bi t
Transmit Shift Reg.
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: T his tim ing diagram shows two consecut ive transmissions.
PIC16F7X7
DS30498D-page 140 2003-2013 Microchip Technology Inc.
11.2.2 AUSART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 11-4.
The data is received on the R C7/R X/DT pin and dri ve s
the data recovery block. The data recovery block is
actuall y a high-spee d shifter , operating at x16 times th e
baud rate; whereas, the main receive serial shifter
operates at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit, CREN (RCSTA<4>).
The heart of the receiver is the Receive (Serial) Shift
Register (RSR). After sampling the Stop bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit, R CIF (PIR1<5>), is set. The actual interr upt can be
enabled/disabled by setting/clearing enable bit, RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit which is
cleared by the hardware. It is clea red when the RCREG
register has been read and is empty. The RCREG is a
double-buffered register (i.e., it is a two-deep FIFO). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the Stop bit of the third byte, if the RCREG register is
still full, the Overrun Error bit, OERR (RCSTA<1>), will
be set. The word in the RSR will be lost. The R CREG
register can be read twice to retrieve the two bytes in
the FIFO. Ove rrun bit, OERR, ha s to be clea red in sof t-
ware. Th is is done by re setting the re ceive logi c (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhib-
ited and no further dat a will be rec eived. It is , therefore,
essential to clear error bit OERR if it is set. Framing
Error bit, FERR (RCSTA<2>), is set if a Stop bit is
detected as cle ar. Bit FERR and the 9th re cei ve bit a re
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values ; the refo r e, it is ess ent ial for the us er to re ad th e
RCSTA regis ter bef ore read ing the RCREG register in
order not to lose the old FERR and RX9D inform ation .
FIGURE 11-4: AUSART RECEIVE BLOCK DIAGRAM
FIGURE 11-5: ASYNCHRON OUS RECEPTION
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
64
16
or Stop Start(8) 7 1 0
RX9
FOSC
Start
bit bit 7/8
bit 1bit 0 bit 7/8 bit 0
Stop
bit
Start
bit bit 7/8
RX (pin)
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Inte rru pt Flag )
OERR bit
CREN
Word 1
RCREG Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (Overrun Error) bit to be set.
bit
Stop
bit
Start
2003-2013 Microchip Technology Inc. DS30498D-page 141
PIC16F7X7
When setting up an Asynchronous Reception, follow
these steps:
1. Initialize th e SPBRG re gis te r for the ap propriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (see Section 11.1 “AUSART
Baud Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit
RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bi t RCIE is set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 11-8: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG AUSART Receive Data Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
PIC16F7X7
DS30498D-page 142 2003-2013 Microchip Technology Inc.
11.2.3 SETTING UP 9-BIT MODE WITH
ADDRES S DETE CT
When setting up an Asynchronous Reception with
Address Detect enabled:
• Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
• Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
• Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
• Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
• Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
• If any error occurred, clear the error by clearing
enable bit CREN.
• If the device has been addressed, clear the
ADDEN bi t to al low da t a b yte s and address bytes
to be read into the receive buffer and interru pt the
CPU.
FIGURE 11-6: AUSART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
64
16
or Stop Start(8) 7 1 0
RX9
RX9
ADDEN
RX9
ADDEN
RSR<8>
Enable
Load of
Receive
Buffer
8
8
FOSC
2003-2013 Microchip Technology Inc. DS30498D-page 143
PIC16F7X7
FIGURE 11-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
FIGURE 11-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
TABLE 11-9: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit bit 1bit 0 bit 8 bit 0
Stop
bit
Start
bit bit 8 Stop
bit
RC7/RX/DT (pin)
Load RSR
Read
RCIF
Word 1
RCREG
bit 8 = 0, Data Byte bit 8 = 1, Address Byte
Note: This ti ming d iagram shows a data b yte fol lowed by an addr ess byte . The data b yte is n ot rea d i nto the R CREG (Recei ve Bu ffer)
because ADDEN = 1.
Start
bit bit 1bit 0 bit 8 bit 0
Stop
bit
Start
bit bit 8 Stop
bit
RC7/RX/DT (pin)
Load RSR
Read
RCIF
Word 1
RCREG
bit 8 = 1, Address Byte bit 8 = 0, Data Byte
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN was not updated and still = 0.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG AUSART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
PIC16F7X7
DS30498D-page 144 2003-2013 Microchip Technology Inc.
11.3 AUSART Synchronous
Master Mode
In Sync hronous Ma ster mode, the data is trans mitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the sa me time). When tran smitting dat a,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit, SYNC (TXSTA<4>). In
additio n, enabl e bit, SPEN (RCSTA<7>), is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode ind icates t hat the process or transmit s th e
master clock on the CK line. The Master mode is
entered by setting bit, CSRC (TXSTA<7>).
11.3.1 AUSART SYNCHRONOUS MASTER
TRANSMISSION
The AUSART transmitter block diagram is shown in
Figure 11-6 . The heart of the tra nsmitter is the T ransmit
(Serial) Shift Regis ter (TSR). The Shi f t regi st er obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
softw are. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXR EG is em pty an d inter-
rupt bit, TXIF (PIR1<4>), is set. The interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in
soft ware. It wi ll res et onl y when new data is loaded into
the TXREG register. While flag bit TXIF indicates the
status of the TXREG register, another bit, TRMT
(TXSTA<1>), shows the status of the TSR register.
TRMT is a read-only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit so the user
has to poll this bit in order to determine if the TSR
register is empty. The TSR is not mapped in data
memory so it is not available to the user.
Transmission is enabled by setting enable bit, TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first dat a bit will be shif ted out on the next av ailable
rising edge of the clock on the CK line. Data out is
stab le around the fal ling edge of the sync hronous cloc k
(Figure 11-9). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 11-10). This is advant ageous when slow
baud rates are selected since the BRG is kept in Reset
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR, resulting in an empty TXREG. Back-to-back
transfers are possible.
Clearing enable bit TXEN during a transmission will
cause the tra nsm is s ion to be ab orte d and will reset the
transmitter. The DT and CK pins will revert to high-
impeda nce. If ei ther bit C REN or bi t SREN is set durin g
a transmis sion , the transm issi on is abor ted and the DT
pin reverts to a high-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it i s disconnected from the pins. In order
to reset the tran sm itte r, th e user has to clear bit TXEN.
If bit SR EN is set (t o interrupt an on-goin g trans mission
and receive a single word) and after the single word is
received, bit SREN will be cleared and the serial port
will re vert back to transmittin g since bit TXEN is still set.
The DT line will immediately switch from High-
Impedan ce R eceiv e mod e to tra nsmit and st art d rivin g.
To avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” value
to TX9D, the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG re gister for the appropria te
baud rate (see Section 11.1 “AUSART Baud
Rate Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. S tart transmission by loading data t o the TXREG
register.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
2003-2013 Microchip Technology Inc. DS30498D-page 145
PIC16F7X7
TABLE 11-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
FIGURE 11-9: SYNCHRONOUS TRANSMISSION
FIGURE 11-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCO
NGIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG A USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
bit 0 bit 1 bit 7
Word 1
Q1Q2 Q3 Q4 Q1Q2Q3 Q4Q1Q2Q3 Q4Q1Q2Q3 Q4Q1 Q2 Q3 Q4 Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4Q1 Q2Q3Q4 Q1Q2Q3 Q4Q1Q2Q3 Q4
bit 2 bit 0 bit 1 bit 7
RC7/RX/DT
RC6/TX/CK
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
TXEN bit ‘1’ ‘1’
Word 2
TRMT bit
Write Word 1 Write Word 2
Note: Sync Master mode, SPBRG = 0. Continuous transmission of two 8-bit words.
pin
pin
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN b it
PIC16F7X7
DS30498D-page 146 2003-2013 Microchip Technology Inc.
11.3.2 AUSART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit, SREN
(RCST A<5>) or enable bit, CREN (RCSTA<4>). Dat a is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is c ontinuous until CREN is cleared. If bo th bits are
set, CREN takes precedence. After clocking the last bit,
the r eceived data in t he R eceive Sh ift Regist er (RS R)
is transferred to the RCREG register (if it is empty).
When the transfer is complete, interrupt flag bit, RCIF
(PIR1<5 >), is s et. The actual interrupt can be enabled/
disabled by setting/clearing enable bit, RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit which is
reset by the ha rdware . In thi s c as e, it i s r ese t whe n th e
RCREG register has been read and is empty. The
RCREG is a double-buffered register (i.e., it is a two-
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third by te to begi n shiftin g into the RSR register. On th e
clocking of the last bit of the third byte, if the RCREG
register is still full, then Overrun Error bit, OERR
(RCSTA<1>), is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The ninth
receive bit is buffered the same way as the receive
data. Reading the RCREG register will load bit RX9D
with a new value; therefore, it is essential for the user
to read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
When setting up a Sy nchronous Master Rece ption:
1. Initialize the SPBRG re gister for the appropria te
baud rate (see Section 11.1 “AUSART Baud
Rate Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt fla g bit RCIF will be se t when receptio n
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 11-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG A USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
2003-2013 Microchip Technology Inc. DS30498D-page 147
PIC16F7X7
FIGURE 11-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CREN bit
RC7/RX/DT pin
RC6/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Q1 Q2 Q3 Q4
PIC16F7X7
DS30498D-page 148 2003-2013 Microchip Technology Inc.
11.4 AUSART Synchronous Slave
Mode
Synchronous Slave mode diffe rs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/ CK pin (instead of being supplied in ternally
in Master mode). This allows the device to transfer or
receive data while in Sleep mode. Slave mode is
entered by clearin g bit, CSRC (TXS TA<7>).
11.4.1 AUSART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode .
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG
register.
c) Flag bit TXIF will not be set.
d) When the first word has b een sh ifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled , the p rog ram wil l bran ch to the in terrupt
vector (0004h).
When setting up a Synchronous Slave Transmission,
follow these steps:
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmis si on is des ired , then set bi t TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. S tart transmission by loading data t o the TXREG
register.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 11-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG AUSART T ransmit Data Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SP BRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
2003-2013 Microchip Technology Inc. DS30498D-page 149
PIC16F7X7
11.4.2 AUSART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
Bit SREN is a “don’t care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP inst ruction , then a w ord m ay be rec eived durin g
Sleep. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enabl e bit RCIE bit is set , the interrupt gene rated
will wake the chip from Sleep. If the global interrupt is
enabled , the pro gram w ill branc h to the interru pt vec tor
(0004h).
When setting up a Synchronous Slave Reception,
follow these steps:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 11-13: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Add r e s s Name Bi t 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG A USART Receive Data Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices, always maintain these bits clear.
PIC16F7X7
DS30498D-page 150 2003-2013 Microchip Technology Inc.
NOTES:
2003-2013 Microchip Technology Inc. DS30498D-page 151
PIC16F7X7
12.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has
11 inputs for the PIC16F737 and PIC16F767 devices
and 14 for the PIC16F747 AND PIC16F777 devices.
The A/D converter allo ws conversion of an analog inp ut
signal to a corresponding 10-bit digital number.
A new feature for the A/D converter is the addition of
programmable acquisition time. This feature allows the
user to select a new channel for conversion and to set
the GO/DONE b it immedia tely. W hen the GO /DONE bit
is set, the selected channel is sampled for the
programmed acquisition time before a conversion is
actually started. This removes the firmware overhead
required to allow for an acquisition (sampling) period
(see Register 12-3 and Section 12.2 “Selecting and
Configuring Automatic Acquisition Time”).
The module has five registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
The ADCON0 register, shown in Register 12-1, controls
the operation of the A/D module an d clock source. The
ADCON1 register, shown in Register 12-2, configures
the functions of the port pins, justification and voltage
reference sources. The ADCON2, shown in
Register 12-3, configures the programmed acquisition
time.
Addition al information on using the A/D modul e c an b e
found in the “PIC® Mid-Range M CU Family R eference
Manual” (DS33023) and in Application Note AN546
“Using the Analog-to-Digital (A/D) Converter”
(DS00546).
PIC16F7X7
DS30498D-page 152 2003-2013 Microchip Technology Inc.
REGISTER 12-1: ADCON0: A/D CONTROL REGISTER 0 (ADDRESS 1Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON
bit 7 bit 0
bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits
If ADCS2 = 0:
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock derived from an RC oscillation)
If ADCS2 = 1:
00 = FOSC/4
01 = FOSC/16
10 = FOSC/64
11 = FRC (clock derived from an RC oscillation)
bit 5-3 CHS<2:0>: Analog Channel Select bits
0000 = Channel 00 (AN0)
0001 = Channel 01 (AN1)
0010 = Channel 02 (AN2)
0011 = Channel 03 (AN3)
0100 = Channel 04 (AN4)
0101 = Channel 05 (AN5)(1)
0110 = Channel 06 (AN6)(1)
0111 = Channel 07 (AN7)(1)
1000 = Channel 08 (AN8)
1001 = Channel 09 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12)
1101 = Channel 13 (AN13)
111x =Unused
Note 1: Selecting AN5 through AN7 on the 28-pin product variant (PIC16F737 and
PIC16F767) will result in a full-scale conversion as unimplemented channels are
connected to VDD.
bit 2 GO/DONE: A/D Conversion Status bit
1 = A/D conversion c ycle in pro gress. Setting th is bit s tart s an A/D c onvers ion cycl e. This bit is
automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 1 CHS<3>: Analog Channel Select bit (see bit 5-3 for bit settings)
bit 0 ADON: A/D Convers io n Status bit
1 = A/D converter module is operating
0 = A/D converter is shut-off and consumes no operating current
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 153
PIC16F7X7
REGISTER 12-2: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. Six Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. Six Least Significant bits of ADRESL are read as ‘0’.
bit 6 ADCS2: A/D Clock Divide by 2 Select bit
1 = A/D clock source is divided by two when system clock is used
0 = Disabled
bit 5 VCFG1: Voltage Reference Configuration bit 1
0 = VREF- is connected to VSS
1 = VREF- is connected to external VREF- (RA2)
bit 4 VCFG0: Voltage Reference Configuration bit 0
0 = VREF+ is connected to VDD
1 = VREF+ is connected to external VREF+ (RA3)
bit 3-0 PCFG<3:0>: A/D Port Configuration bits
Note: AN5 through AN7 are only available on the 40-pin product variant (PIC16F747 and
PIC16F777).
Legend:
R = Re adable bit W = Writable b it U = Unimplement ed bit, rea d as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
0000 A A A A AAAAAAAAAA
0001 A A A A AAAAAAAAAA
0010 D A A A AAAAAAAAAA
0011 D D A A AAAAAAAAAA
0100 D D D A AAAAAAAAAA
0101 D D D D AAAAAAAAAA
0110 D D D DDAAAAAAAAA
0111 D D D DDDAAAAAAAA
1000 D D D DDDDAAAAAAA
1001 D D D D DDDDAAAAAA
1010 D D D D DDDDDAAAAA
1011 D D D D DDDDDDAAAA
1100 D D D D DDDDDDDAAA
1101 D D D D DDDDDDDDAA
1110 D D D D DDDDDDDDDA
1111 D D D D DDDDDDDDDD
Legend: A = Analog input, D = Digit al I/O
PIC16F7X7
DS30498D-page 154 2003-2013 Microchip Technology Inc.
REGISTER 12-3: ADCON2: A/D CONTROL REGISTER 2 (ADDRESS 9Bh)
The analog reference voltage is software selectable
to either the device’s positive and negative supply
voltage (VDD and VSS) or the voltage level on the
RA3/AN3/VREF+ and RA2/AN2/VREF-/CVREF pins.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter which generates the result via successive
approximation.
A device Reset forces all registers to thei r Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH/ADRESL
registers, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. Th e block
diagram of the A/D module is s hown in Figure 12-1.
U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
—— ACQT2 ACQT1 ACQT0 — — —
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits
000 =0
(1)
001 =2 TAD
010 =4 TAD
011 =6 TAD
100 =8 TAD
101 =12TAD
110 =16 TAD
111 =20 TAD
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D
clock starts. This allows the SLEEP instruction to be ex ecuted.
bit 2-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 155
PIC16F7X7
The value in the ADRESH/ADRESL registers is not
modified for a Power-on Reset. The ADRESH/
ADRESL registers will contain unknown data after a
Power-on Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 12.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur bet ween setting th e GO/DONE bit and the actual
start of the conversion.
The following steps should be followed to do an A/D
conversion:
1. Configure the A/D modul e:
• Config ure an alog pins, volt age refere nce and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D con ve rsi on clock (ADCON 0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF (if required).
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 12-1: A/D BLOCK DIAGRAM
(Input Voltage)
VIN
VREF+
(Reference
Voltage)
VDD
VCFG<1:0>
CHS<3:0>
AN3/VREF+
AN2/VREF-
AN1
AN0
0011
0010
0001
0000
A/D
Converter
VREF-
(Reference
Voltage) VSS
VCFG<1:0>
AN12
AN13
AN11
1101
1100
1011
S S
PIC16F7X7
DS30498D-page 156 2003-2013 Microchip Technology Inc.
12.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accurac y , the
charge holding capacitor (CHOLD) must be allowed to
fully charge to the input channel voltage level. The
analog input model is shown in Figure 12-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 12-2.
The maximum recommended impedance for analog
sources is 2.5 k. As the impedance is decreas ed, the
acquisition time may be decreased. After the analog
input channel is selected (changed), this acquisition
must be done before the convers ion can be started.
To calculate the minimum acquisition time,
Equation 12-1 may be used. This equation assumes
that 1/2 LS b error is used (1024 st eps for the A/D). The
1/2 LSb er ror is the ma ximu m error allow ed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the “PIC® Mid-Range MCU Family Reference Manual”
(DS33023).
EQUATION 12-1: ACQUISITION TIME
FIGURE 12-2: ANALOG INPUT MODEL
TACQ
TC
TACQ
=
=
=
=
=
=
=
=
Amplifier Settling Time + Hold Capacitor Charging Tim e + Temperature Coefficient
TAMP + TC + TCOFF
2 s + TC + [(Temperature – 25°C)(0.05 s/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
-120 pF (1 k + 7 k + 10 k) In(0.0004885)
16.47 s
2 s + 16.47 s + [(50°C – 25C)(0.05 s/C)
19.72 s
Note 1: The reference voltage (VREF) has no effect on the equation since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conve rsion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
CPIN
VA
RSANx
5 pF
VDD
VT = 0.6V
VT = 0.6V ILEAKAGE
RIC 1K
Sampling
Switch
SS RSS
CHOLD
= DAC Capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
567891011
(k)
VDD
= 120 pF
±500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold V oltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
various junctions
2003-2013 Microchip Technology Inc. DS30498D-page 157
PIC16F7X7
12.2 Selecting and Configuring
Auto matic A c q u is ition Time
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
When the GO/DON E bit is set, sampling is stopped an d
a conve rsion begins. Th e user is responsi ble for ens ur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT2:ACQT0
bits (ADCON2<5 :3>) remai n in their Re set state (‘000’)
and is compatible with devices that do not offer
progra mmable acqui si tion times .
If desired, the ACQT bits can be set to select a
programmable acquisition time for the A/D module.
When the GO/DONE bit is set, the A/D module con-
tinues to sample the input for the selected acquisition
time, th en automa tically begins a conversio n. Since the
acquis iti on time is programmed, there may be no nee d
to wait for an acquisition time between selecting a
channel and setting the GO/DONE bit.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
12.3 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D c onver sion requi res a mini mum 12 TAD pe r 10-bit
conversion. The source of the A/D conversion clock is
software selected. The seven possible options for TAD
are:
•2 T
OSC
•4 TOSC
•8 TOSC
•16 TOSC
•32 TOSC
•64 TOSC
• Internal A/D modu le, RC os cil la tor (2-6 s)
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
Table 12-1 shows the resultant TAD tim es de r ive d f r om
the device operating frequencies and the A/D clock
source selected.
TABLE 12-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (ST ANDARD DEVICES (F))
AD Clock Source (TAD)Maximum D evice Frequency
Operation ADCS2:ADCS1:ADCS0
2 TOSC 000 1.25 MHz
4 TOSC 100 2.5 MHz
8 TOSC 001 5 MHz
16 TOSC 101 10 MHz
32 TOSC 010 20 MHz
64 TOSC 110 20 MHz
RC(1,2,3) x11 (Note 1)
Note 1: The RC source has a typical TAD time of 4 s but can vary between 2-6 s.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only
recommended for Sleep operation.
3: For extended voltage devices (LF), please refer to Section 18.0 “Electrical Characteristics”.
PIC16F7X7
DS30498D-page 158 2003-2013 Microchip Technology Inc.
12.4 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and
A/D convers ion cl ock is determi ned in p ar t by the cl ock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT2:ACQT0
(ADCON2<5:3>) and ADCS2:ADCS0 (ADCON1<6>,
ADCON0<7:6>) bits should be updated in accordance
with the power-managed mode clock that will be used.
After the power-managed mode is entered (either of
the pow er-managed Run modes), an A/D a cquisition or
conversion may be started. Once an acquisition or
convers io n is started, the device should continu e to be
clocked by the same power-managed mode clock
sour ce unt il the con ve r si on has been co mpl eted.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires the A/D RC clock to
be sel ected. If bits ACQT2:ACQ T0 are set to ‘000’ and
a conv er s io n is s tart e d, t h e conv er s io n wi ll b e de la y ed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode.
12.5 Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers
control the operation of the A/D port pins. The port pin s
that are desired as analog inputs must have their
corresponding TRIS bits set (input). If the TRIS bit is
cleared (output), the digital output level (VOH or VOL)
will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the Port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins con-
figured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
2: Analog le vels on any pin that is defined as
a digit al inpu t, but not as an analog inpu t,
may cause the digital input buffer to
consume current that is out of the
device’s specification.
2003-2013 Microchip Technology Inc. DS30498D-page 159
PIC16F7X7
12.6 A/D Conversions
Figure 12-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 12-4 shows the operation of the A/D converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits are set to ‘010’ and a 4 TAD
acquisition time is selected before the conversion
starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair wil l NOT be upda ted w ith th e part ially comple ted
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2T
AD wait is required before the next acquisition ca n be
started. After this wait, acquisition on the selected
channel is automatically started.
FIGURE 12-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 12-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The GO/DONE bit should NOT be set in
the sam e inst ructio n that tu rns on the A/D.
TAD1TAD2TAD3TAD4 TAD5TAD6 TAD7TAD8 TAD11
Set GO/DO NE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10
TCY - TAD
Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9 b6 b5 b4 b3 b2 b1
b8 b7
1234567811
Set GO/DONE bit
(Holding capacitor is disconnected)
910
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
Conversion starts
1234
(Holding capacitor continues
acquiring input)
TACQT Cycles TAD Cycles
Automatic
Acquisition
Time
b0b9 b6 b5 b4 b3 b2 b1
b8 b7
PIC16F7X7
DS30498D-page 160 2003-2013 Microchip Technology Inc.
12.7 A/D Operation During Sleep
The A/D module can operate during Sleep mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed which eliminates all digital
switchi ng noise fro m the conv ersion. Whe n the conver-
sion i s comple ted, the GO /DONE bit will be cleared and
the result loaded into the ADRESH register. If the A/D
interrupt is enabled, the device will wake-up from
Sleep. If the A/D interrupt is not enabled, the A/D
modul e wil l then be t urned off, alt hough the A DON bi t
will remain set.
When the A/D clock sour ce is anoth er clock optio n (not
RC), a SLEEP instructi on will cause the present conver-
sion t o be aborte d and the A/D mod ule to be turned of f,
though the ADON bit will remain set.
Turning of f the A/D plac es the A/D m odu le in its lowest
current consumption state.
12.8 Effects of a Reset
A device Reset forces all registers to thei r Reset state.
The A/D module is disabled and any conversion in
progress is aborted. All A/D input pins are configured
as analog inputs.
The ADRESH register will contain unknown data after
a Power-on Rese t.
12.9 Use of the CCP Trigger
An A/D convers ion can be st arted by th e “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). Wh en the trigger occu rs, the
GO/DONE bit will be set, starting the A/D conversion
and the Timer1 counter will be reset to zero. Timer1 is
reset to au tomatical ly re peat th e A/D acquisi tion p eriod
with minimal software overhead (moving the ADRESH
to the desired location). The appropriate analog input
channel must be selected and an appropriate acquisi-
tion time sh oul d p as s befo re the “sp ec ial even t trigger”
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module but will still reset the Timer1 counter.
TABLE 12-2: SUMMARY OF A/D REGISTERS
Note: For the A/D module to operate in Sleep,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in Sleep, ensure the SLEEP
instruction immediately follows the
instruction that sets the GO/DONE bit.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh,8Bh,
10Bh, 18Bh INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 OSFIF CMIF LVDIF —BCLIF— CCP3IF CCP2IF 000- 0-00 000- 0-00
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 OSFIE CMIE LVDIE —BCLIE— CCP3IE CCP2IE 000- 0-00 000- 0-00
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 0000 0000
9Fh ADCON1 ADFM ADCS2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 000 0000 0000
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 uu0u 0000
85h TRISA PO RTA Data Direction Register 1111 1111 1111 1111
09h PORTE(2) — — — — RE3(3) RE2 RE1 RE0 ---- x000 ---- x000
89h TRISE(2) IBF OBF IBOV PSPMODE —(3) PORTE Data Direction bits 0000 1111 0000 1111
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserv ed on the PIC16F737/767 devices; always maintain these bits clear.
2: These registers are reserved on the PIC16F737/767 devices.
3: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
2003-2013 Microchip Technology Inc. DS30498D-page 161
PIC16F7X7
13.0 COMPARATOR MODULE
The comparator module contains two analog com-
parators. The inputs to the comparators are
multipl ex ed w ith I/O po rt pins , RA0 throu gh R A3, w hil e
the outputs are multiplexed to pins RA4 and RA5. The
on-chip volt age re ferenc e (Section 14. 0 “Comp a rator
Voltage Reference Module”) can also be an input to
the comparat ors.
The CMCON register (Register 13-1) controls the
comparator input and output multiplexers. A block
diagram of the various comparator configurations is
shown in Figure 13-1.
REGISTER 13-1: CMCON: COMPARATOR MODULE CONTROL REGISTER (ADDRESS 9Ch)
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7 bit 0
bit 7 C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN-
0 = C2 VIN+ < C2 VIN-
When C2INV = 1:
1 = C2 VIN+ < C2 VIN-
0 = C2 VIN+ > C2 VIN-
bit 6 C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VIN-
When C1INV = 1:
1 = C1 VIN+ < C1 VIN-
0 = C1 VIN+ > C1 VIN-
bit 5 C2INV: C omparator 2 Output Inver s ion bi t
1 = C2 output inverted
0 = C2 output not inverted
bit 4 C1INV: C omparator 1 Output Inver s ion bi t
1 = C1 output inverted
0 = C1 output not inverted
bit 3 CIS: Compara tor Input Switch bit
When CM2:CM0 = 110:
1 =C1 VIN- connects to RA3/AN3
C2 VIN- connects to RA2/AN2
0 =C1 V
IN- connects to RA0/AN0
C2 VIN- connects to RA1/AN1
bit 2-0 CM2:CM0: Comp arator Mode bits
Figure 13-1 shows the Comparator modes and CM2:CM0 bit settings.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F7X7
DS30498D-page 162 2003-2013 Microchip Technology Inc.
13.1 Comparator Configuration
There are eight modes of operation for the compara-
tors. The CMCON register is used to select these
modes. Figure 13-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the Comparator
mode is changed, the comp arator output leve l ma y n ot
be valid for the specified mode change delay shown in
the electrical specifications (Section 18.0 “Electrical
Characteristics”).
FIGURE 13-1: COMPAR ATOR I/O OPERATING MODES
Note: Compara tor in terr upts sh ould be disab led
during a Comparator mode change.
Otherwise, a false interrupt may occur.
C1
RA0/AN0 VIN-
VIN+
RA3/AN3/ Off (Read as ‘0’)
Comparators Reset
A
A
CM2:CM0 = 000
C2
RA1/AN1 VIN-
VIN+
RA2/AN2/ Off (Read as ‘0’)
A
A
C1
RA0/AN0 VIN-
VIN+C1OUT
Two Independent Comparators
A
A
CM2:CM0 = 010
C2
RA1/AN1 VIN-
VIN+C2OUT
A
A
C1
RA0/AN0 VIN-
VIN+C1OUT
Two Common Reference Comparators
A
A
CM2:CM0 = 100
C2
RA1/AN1 VIN-
VIN+C2OUT
A
D
C2
RA1/AN1 VIN-
VIN+Off (Read as ‘0’)
One Independent Comparator with Output
D
D
CM2:CM0 = 001
C1
RA0/AN0 VIN-
VIN+C1OUT
A
A
C1
RA0/AN0 VIN-
VIN+Off (Read as ‘0’)
Comparators Off (POR Default Mode)
D
D
CM2:CM0 = 111
C2
RA1/AN1 VIN-
VIN+Off (Read as ‘0’)
D
D
C1
RA0/AN0 VIN-
VIN+C1OUT
Four Inputs Multiplexed to Two Comparators
A
A
CM2:CM0 = 110
C2
RA1/AN1 VIN-
VIN+C2OUT
A
A
From Comparator
CIS = 0
CIS = 1
CIS = 0
CIS = 1
C1
RA0/AN0 VIN-
VIN+C1OUT
Two Common Reference Comparators with Outputs
A
A
CM2:CM0 = 101
C2
RA1/AN1 VIN-
VIN+C2OUT
A
D
A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON <3>) is the Comparator Input Switch
CVREF
C1
RA0/AN0 VIN-
VIN+C1OUT
Two Independent Comparators with Outputs
A
A
CM2:CM0 = 011
C2
RA1/AN1 VIN-
VIN+C2OUT
A
A
RA4/T0CKI/C1OUT
RA5/AN4/LVDIN/SS/C2OUT
RA4/T0CKI/C1OUT
RA5/AN4/LVDIN/SS/C2OUT
RA4/T0CKI/C1OUT
VREF Module
VREF+
VREF-/CVREF
RA3/AN3/
VREF+
RA3/AN3/
VREF+
RA3/AN3/
VREF+RA3/AN3/
VREF+
RA3/AN3/
VREF+
RA3/AN3/
VREF+
RA3/AN3/
VREF+
RA2/AN2/
VREF-/CVREF
RA2/AN2/
VREF-/CVREF
RA2/AN2/
VREF-/CVREF
RA2/AN2/
VREF-/CVREF
RA2/AN2/
VREF-/CVREF
RA2/AN2/
VREF-/CVREF
RA2/AN2/
VREF-/CVREF
2003-2013 Microchip Technology Inc. DS30498D-page 163
PIC16F7X7
13.2 Comparator Operation
A single comparator is shown in Figure 13-2, along wi th
the relationship between the analog input levels and
the digit al ou tput. When the an alog input a t VIN+ is les s
than the analog input VIN-, the outp ut of the co mparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital hi gh level. The shaded areas of
the output of the comparator in Figure 13-2 represent
the uncertainty due to input offsets and response time.
13.3 Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal present at VIN- is compar ed to the signal
at VIN+ and the digital output of the comparator is
adjusted accordingl y (Figure 13-2) .
FIGURE 13-2: SINGLE COMPARATOR
13.3.1 EXTERN AL REFE REN C E SIGNA L
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sour ces. How ever , th resho ld detecto r applica tions ma y
require th e s am e re fere nc e. Th e re fere nc e s ignal m us t
be between VSS and VDD and can be applied to either
pin of the comparator(s).
13.3.2 INTERNAL REFERENCE SIGNAL
The com p arator module al so al low s th e sel ec tion of an
internally generated voltage reference for the compar-
ators. Section 14.0 “Comparator Voltage Reference
Module” contains a detailed description of the com-
parator voltage reference module that provides this
signal. The internal reference signal is used when
comparators are in mo de CM<2:0> = 110 (Figure 13-1).
In this mode, the internal voltage reference is applied to
the VIN+ pin of both c omparators.
13.4 Comparator Response Time
Response time is the minimum time after selecting a
new reference voltage, or input source, before the
comparator output has a valid level. If the internal
reference is changed, the maximum delay of the inter-
nal voltage reference must be considered when using
the comparator outputs. Otherwise, the maximum
delay of the comparators should be used (Section 18.0
“Electrical Characteristics”).
13.5 Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
output s may al so be dire ctly output to the RA4 and RA5
I/O pins . When enab led, multipl exors in th e output p ath
of the RA4 and RA5 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 13-3 shows the comparator output block
diagram.
The TRISA bits will still function as an output enable/
disable for the RA4 and RA5 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<5:4:>).
–
+
VIN+
VIN-Output
VIN–
VIN+
Output
Output
VIN+
VIN-
Note 1: When reading the Port register, all pins
configu red a s anal og inp uts will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin defined as a
digital inpu t may cau se the in put bu ffer to
consume more current than is specified.
3: RA4 is an open collector I/O pin. When
used as an output, a pull-up resistor is
required.
PIC16F7X7
DS30498D-page 164 2003-2013 Microchip Technology Inc.
FIGURE 13-3: COMPARATOR OUTPUT BLOCK DIAGRAM
13.6 Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
stat us of the output b its, as rea d from CMCON<7:6> , to
determine the actual change that occurred. The CMIF
bit (PIR2 register) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it (‘0’). Since it is
also possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE2 register) and the PEIE bit (INTCON
register ) must be set to enable the interrupt. In additio n,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
The user , in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatc h co ndi tio n will co nti nue to set fla g bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
DQ
EN
To RA4 or
RA5 pin
Bus
Data
Read CMCON
Set
MULTIPLEX
CMIF
bit
-+
DQ
EN
CL
Port pins
Read CMCON
Reset
From
other
Comparator
CxINV
Note: If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2
register) interrupt flag may not get set.
2003-2013 Microchip Technology Inc. DS30498D-page 165
PIC16F7X7
13.7 Comparator Operation
During Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
While the comparator is powered up, higher Sleep
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current as shown in the com-
parat or specifi cations. To minimiz e power co nsumption
while in Sleep mode, turn off the comparators
(CM<2:0> = 111) before entering Sleep. If the device
wakes up from Sleep, the contents of the CMCON
register are not affected.
13.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator module to be in the
Comparator Off mode, CM<2:0> = 111. This ensures
compatibility to the PIC16F87X devices.
13.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 13-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. Th e analog input, th erefore, must be betw een
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 k is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 13-4: ANALOG INPUT MODEL
TABLE 13-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR
Value on
all other
Resets
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
0Dh PIR2 OSFIF CMIF LVDIF —BCLIF —CCP3IF CCP2IF 000- 0-00 000- 0-00
8Dh PIE2 OSFIE CMIE LVDIE —BCLIE —CCP3IE CCP2IE 000- 0-00 000- 0-00
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 uu0u 0000
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
VA
RS < 10K
AIN CPIN
5 pF
VDD
VT = 0.6V
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
Legend: CPIN = Input Capacitance
VT= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS= Source Impedance
VA = Analog Voltage
PIC16F7X7
DS30498D-page 166 2003-2013 Microchip Technology Inc.
NOTES:
2003-2013 Microchip Technology Inc. DS30498D-page 167
PIC16F7X7
14.0 COMPARATOR VOLTAGE
REFERENC E MODULE
The comparator voltage reference generator is a 16-tap
resistor ladder network that provides a fixed voltage
reference when the comparators are in mode ‘110’. A
programmable register controls the function of the
reference generator . Register 14-1 lists the bit functions
of the CVRCON register.
As shown in Figure 14-1, the resistor ladder is seg-
mented to provide tw o ranges of C VREF values and has
a power-down function to conserve power when the
reference is not bein g used. The comp arat or refer ence
supply voltage (also referred to as CVRSRC) comes
directly from VDD. It should b e noted, h owever, that th e
voltage at the top of the ladder is CVRSRC – VSAT,
where VSAT is the saturation voltage of the power
switch transistor. This reference will only be as
accurate as the values of CVRSRC and VSAT.
The output of the reference generator may be
connected to the RA2/AN2/VREF-/CVREF pin. This can
be us ed as a simp le D/A fun ction by the us er if a ve ry
high-impedance load is used. The primary purpose of
this function is to provide a test path for testing the
reference generator function.
REGISTER 14-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
(ADDRESS 9Dh)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down
bit 6 CVROE: Comparator VREF Output Enable bit
1 = CVREF voltage level is output on RA2/AN2/VREF-/CVREF pin
0 = CVREF voltage level is disconnected from RA2/AN2/VREF-/CVREF pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.625 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.72 CVRSRC, with CVRSRC/32 step size
bit 4 Unimplemented: Read as ‘0’
bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits 0 CVR3:CVR0 15
When CVRR = 1:
CVREF = (CVR<3:0>/24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (CVR3:CVR0/32) (CVRSRC)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Va lue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F7X7
DS30498D-page 168 2003-2013 Microchip Technology Inc.
FIGURE 14-1: COMPARATOR VOLTA GE REFERENCE BLOCK DIAGRAM
TABLE 14-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
CVRR
8R
CVR3
CVR0
16:1 Analog MUX
8R RRRR
CVREN
CVREF
16 Stages
Input to
Comparator
CVROE
RA2/AN2/VREF-/CVREF
VDD
CVR2
CVR1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR
Value on
all other
Resets
9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’.
Shaded cells are not used with the comp arator volt age reference.
2003-2013 Microchip Technology Inc. DS30498D-page 169
PIC16F7X7
15.0 SPECIAL FEATURES OF
THE CPU
These devices have a host of features intended to
maximize sys tem reliability, minimize cost through elimi-
nation of external components, provide power-saving
operating modes and offer code protection:
• Reset
- Power-o n Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
- Low-Voltage Detect (LVD)
• Interrupts
• Watchdog Timer (WDT)
• Two-Speed Start-up
• Fail-Safe Clock Monitor
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in Reset until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT) which provides a fixed delay of 72 ms
(nominal) on power-up only. It is designed to keep the
part in Reset while the power supply stabilizes and is
enabled or disabled using a configuration bit. With
these two timers on-chip, most applications need no
external Reset circuitry.
Sleep mode is designed to offer a very low-current
power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer wake-up or
through an interrupt.
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. Configuration bits are used to select the
desired oscillator mode.
Additional information on special features is available
in the “PIC® Mid-Range MCU Family Reference Man-
ual” (DS33023).
15.1 Configuration Bits
The con figuration bit s can be programme d (read as ‘0’)
or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped in
program memory locations 2007h and 2008h.
The user will note that address 2007h is beyond the
user program memory space which can be accessed
only during programming.
PIC16F7X7
DS30498D-page 170 2003-2013 Microchip Technology Inc.
REGISTER 15-1: CONFIGURATION WORD REGISTER 1 (ADDRESS 2007h)
R/P-1 R/P-1 R/P-1 U-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
CP CCPMX DEBUG —— BORV1 BORV0 BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0
bit 13 bit 0
bit 13 CP: Flash Program Memo ry Code Prote cti on bits
1 = Code protection off
0 = 0000h to 1FFFh code-protected for PIC16F767/777 and 0000h to 0FFFh for PIC16F737/747 (all protected)
bit 12 CCPMX: CCP2 Multiplex bit
1 = CCP2 is on RC1
0 = CCP2 is on RB3
bit 11 DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger
bit 10-9 Unimplemented: Read as ‘1’
bit 8-7 BORV<1:0>: Brown-out Reset Voltage bits
11 = VBOR se t to 2.0V
10 = VBOR se t to 2.7V
01 = VBOR se t to 4.2V
00 = VBOR se t to 4.5V
bit 6 BOREN: Brown-out Reset Enable bit
BOREN combines with BORSEN to control when BOR is enabled and how it is controlled.
BOREN:BORSEN:
11 = BOR enabled and always on
10 = BOR enabled during operation and disabled during Sleep by hardware
01 = BOR controlled by software bit SBOREN – refer to Register 2-8 (PCON<2>)
00 = BOR disabled
bit 5 MCLRE: MCLR/VPP/RE3 Pin Function Select bit
1 = MCLR/VPP/RE3 pin function is MCLR
0 = MCLR/VPP/RE3 pin function is digital input only, MCLR gated to ‘1’
bit 3 PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 2 WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 4, 1-0 FOSC2:FOSC0: Oscillator Selection bits
111 = EXTRC oscillator; CL KO functi on on OSC2 /C LKO /RA6
110 = EXTRC oscillator; port I/O function on OSC2/CLKO/RA6
101 = INTRC oscilla tor; CLKO functi on on OSC2 /CLKO/RA6 and port I/O function on OSC1/CLKI/RA7
100 = INTRC oscillator; port I/O function on OSC1/CLKI/RA7 and OSC2/CLKO/RA6
011 = EXTCLK; port I/O function on OSC2/CLKO/RA6
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 171
PIC16F7X7
REGISTER 15-2: CONFIGURATION WORD REGISTER 2 (ADDRESS 2008h)
U-1 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1
— — — — — — — BORSEN — — — — IESO FCMEN
bit 13 bit 0
bit 13-7 Unimplemented: Read as ‘1’
bit 6 BORSEN: Brown-out Reset Software Enable bit
Refer to Configuration Word Register 1, bit 6 for the function of this bit.
bit 5-2 Unimplemented: Read as ‘1’
bit 1 IESO: Internal External Switchover bit
1 = Internal External Switchover mode enabled
0 = Internal External Switchover mode disabled
bit 0 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F7X7
DS30498D-page 172 2003-2013 Microchip Technology Inc.
15.2 Reset
The PIC16F7X7 dif ferentiates between various kinds of
Reset:
• Power-on Reset (POR)
•MCLR
Reset during normal operation
•MCLR
Reset during Sleep
• WDT Reset during normal operation
• WDT Wake-up during Sleep
• Brown-out Reset (BOR)
Some regi sters a re not af fected in any Rese t condit ion.
Their st atus is unknown on POR and unchange d in an y
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCL R R ese t du ring Sle ep a nd Brown-
out Reset (BOR). They are not affected by a WDT
wake-up which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared
differently in different Reset situations, as indicated in
Table 15-3. These bits are used in software to
determine the nature of the Reset. Upon a POR, BOR
or wake-up from Sleep, the CPU requires approxi-
mately 5-10 s to become ready for code execution.
This delay runs in parallel with any other timers. See
Table 15-4 for a full description of Reset states of all
registers.
A simp lified block diagram of the On -Chip Re set Circ uit
is sh own in Figure 15-1.
FIGURE 15-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR/VPP/RE3 pin
VDD
OSC1/
WDT
Module
VDD Rise
Detect
OST/PWRT
INTRC(1)
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
11-bit Ripple Counter
Reset
Enable OST
Enable PWRT
Sleep
Brown-out
Detect BORSEN
BOREN
CLKI pin
Note 1: This is the 32 kHz INTRC oscillator. See Section 4.0 “Oscillator Configurations” for more infor ma ti on .
2003-2013 Microchip Technology Inc. DS30498D-page 173
PIC16F7X7
15.3 MCLR
PIC16F7X7 devices have a noise filter in the MCLR
Reset path. This filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Volta ges app lied to the pin th at exce ed it s s pecif icatio n
can result in both MCLR and excessive current, beyond
the devic e specifi cation, during the ESD event. For this
reason, Microchip recommends that the MCLR pin no
longer be tied directly to VDD. The use of an
RC network, as shown in Figure 15-2, is suggested.
The MCLR/VPP/RE3 pin can be configured for MCLR
(default) or as an input pin (RE3). This is configured
through the MCLRE bit in Configuration Word
Register 1.
FIGURE 15-2: RECOMMENDED MCLR
CIRCUIT
15.4 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the rang e of 1.2V -1.7V). To take
advantage of the POR, tie the MCLR pin to VDD as
described in Section 15.3 “MCLR”. A maximum rise
time fo r VDD is spec ified. Se e Section 18.0 “Electr ical
Characteristics” for details.
When the device starts normal operation (exits the
Reset condition), device operating parameters (volt-
age, fr equency, temp erature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in Reset until the operating conditions are
met. For more information, see Application Note
AN607 “Power-up Trouble Shooting” (DS00607).
15.5 Power-up Timer (PWRT)
The Power-up Timer (PWRT) of the PIC16F7X7 is a
counter that uses the INTRC oscillator as the clock
input. This yields a count of 72 ms. While the PWRT is
counting, the device is held in Reset.
The power-up time delay depends on the INTRC and
will vary from chip-to-chip due to temperature and
process variation. See DC parameter #33 for details.
The PWRT is enabled by clearing configuration bit
PWRTEN.
15.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (if enabled). This helps to ensure
that the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
15.7 Brown-out Reset (BOR)
Three c onfigurati on bit s (BOREN – Confi guration Word
Register 1, bit 6; BORSEN – Configuration Word
Register 2, bit 6; SBOREN – PCON register, bit 2)
together di sable or enable the Brown-out Reset circuit
in one of its three operating modes.
If VDD falls below VBOR (defined by BORV<1:0> bits in
Configuration Word Register 1) for longer than TBOR
(param eter #3 5, abou t 100 s), the brown-ou t situa tion
will reset the device. If VDD falls below VBOR for less
than TBOR, a Reset may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer (if enabled) will keep the device in
Reset for TPWRT (parameter #33, about 72 ms). If VDD
should fall below VBOR during TPWRT, the Brown-out
Reset process will restart when VDD rises above VBOR
with the Power-up Timer Reset. Unlike previous PIC16
devices, the PWRT is no longer automatically enabled
when the Brown-out Reset circuit is enabled. The
PWRTEN and BOREN configuration bits are
independent of each other.
C1
0.1 F
R1
1 k (or greater)
(optional, not critical)
VDD
MCLR
PIC16F7X7
PIC16F7X7
DS30498D-page 174 2003-2013 Microchip Technology Inc.
15.8 Low-Voltage Detect
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created where the application
software can do “housekeeping tasks” before the
device voltage exits the valid operating range. This can
be done using the Low-Voltage Detect module.
This module is a software programmable circuitry
where a device voltage trip point can be specified.
When the v oltage of the device be comes lower then the
specif ied poin t, an inter rupt flag is set. If the interrupt is
enabled, the program execution will branch to the
interrupt vector address and the software can then
respond to that interrupt source.
The Low-Voltage Detect circuitry is completely under
softw are control. This allows the circuitry to be turned
off by the software which minimizes the current
consum pt ion for the devic e.
Figure 15-3 s hows a po ssible a pplicati on volt age curv e
(typically for batteries). Over time, the device voltage
decreases. When the device voltage eq uals voltage V A,
the LVD logic generates an interrupt. This occurs at
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shut-down the sys tem. Voltag e point VB is the
minimum valid operating voltage specification. This
occur s at ti me TB. The difference, TB – TA, is the total
time for shutdown.
The block diagram for the LVD module is shown in
Figure 15-4. A comparator uses an internally gener-
ated reference voltage as the set point. When the
selected tap output of the device voltage crosses the
set point (is lower than ), the LVDIF bit is set.
Each node in the resistor divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate
before t he LVD module asserts an in terrupt. W hen the
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the 1.2V
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal setting the LVDIF bit. This voltage is
software programmable to any one of 16 values (see
Figure 15-4) . T h e t r i p po i n t is selec te d by p r o g ramming
the LVDL3:LVDL0 bits (LVDCON<3:0>).
FIGURE 15-3: TYPICAL LOW-VOLTAGE DETECT APPLICATION
Time
Voltage
VA
VB
TATB
VA = LVD trip point
VB = Minimum valid device
operating voltage
Legend:
2003-2013 Microchip Technology Inc. DS30498D-page 175
PIC16F7X7
FIGURE 15-4: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM
The LVD module has an additional feature that allows
the user to supply the sense voltage to the module
from an external source. This mode is enabled when
bits LVDL3:LVDL0 are set to ‘1111’. In this state, the
comp a rator input is mult ipl ex ed from the ext erna l inp ut
pin, LVDIN (Figure 15-5). This gives users flexibility
because it allows them to configure the Low-Voltage
Detect interrupt to occur at any voltage in the valid
operating range.
FIGURE 15-5: LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
LVDIF
VDD
16-to-1 MUX
LVDEN
LVD Control
Register
Internally Generated
Reference Voltage
LVDIN
1.2V
LVD
EN
LVD Control
16-to-1 MUX
BGAP
BODEN
LVDEN
LVDEN
LVDIN
Register
VDD VDD
Externally Generated
Trip Point
PIC16F7X7
DS30498D-page 176 2003-2013 Microchip Technology Inc.
15.9 Control Register
The Low-Voltage Detect Control register controls the
operation of the Low-Voltage Detect circuitry.
REGISTER 15-3: LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER (ADDRESS 109h)
U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
—— IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5 IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
bit 4 LVDEN: Low-Voltage Detect Power Enable bit
1 = Enables LVD, powers up LVD circuit
0 = Disables LVD, powers down LVD circuit
bit 3-0 LVDL3:LVDL0: Voltage Detection Limit bits
1111 = External analog input is used (input comes from the LVDIN pin)
1110 = Maximum setting
.
.
.
0001 = Minimum setting
Note: See Table 18-3 in Section 18.0 “Elec trical Characteris tics” for the specific ations.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2003-2013 Microchip Technology Inc. DS30498D-page 177
PIC16F7X7
15.10 Operation
Depen ding on the power s our ce for th e devi ce vol tag e,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be
constantly operating. To decrease the current require-
ments, the LVD circuitry only needs to be enabled for
short peri ods where the voltag e is check ed. After doing
the check, the LVD module may be disabled.
Each tim e that the LVD mo dule i s enab led, th e circ uitr y
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
The following steps are needed to set up the LVD
module:
1. Write the value to the LVDL3:LVDL0 bits
(LVDCON register) which selects the desired
LVD trip point.
2. Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or t he GIE bit is cleared).
3. Enable the LVD module (set the LVDEN bit in
the LVDCON register).
4. Wait for the LVD module to stabilize (the IRVST
bit to become set).
5. Clear the LVD interrupt flag, which may have
falsely become set, until the LVD module has
stabilized (clear the LVDIF bit).
6. Enable the LV D interru pt (set the LVDIE and th e
GIE bits).
Figure 15-6 shows the typical waveforms that the LVD
module may be used to detect.
FIGURE 15-6: LOW-VOLTAGE DETECT WAVEFORMS
VLVD
VDD
LVDIF
VLVD
VDD
Enable LVD
Inte rn a l l y Ge nerate d TIRVST
LVDIF may not be set
Enable LVD
LVDIF
LVDIF cleared in software
LVDIF cleared in software
LVDIF cleared in software,
CASE 1:
CASE 2:
LVDIF remains set since LVD condition still exists
Reference Stable
Inte rn a l l y Ge nerate d
Reference Stable TIRVST
PIC16F7X7
DS30498D-page 178 2003-2013 Microchip Technology Inc.
15.10.1 REFERENCE VOLTAGE SET POINT
The internal reference voltage of the LVD module may
be used by other internal circuitry (the Programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires a time to become stable before a low-voltage
condition can be reliably detected. This time is invariant
of system clock speed. This start-up time is specified in
electrical specification parameter #36. The low-voltage
interrupt flag w ill not be enabled until a stable reference
voltage is reached. Refer to the waveform in Figure 15-6.
15.10.2 CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static cur-
rent. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
15.11 Operation During Sleep
When enabled, the LVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the L VDIF bit will be set and the de vice will wake-
up from Sleep. Device execution will continue from the
inter rupt vecto r address if interru pts h ave been globall y
enabled.
15.12 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the LVD module to be turned off.
15.13 Time-out Sequence
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR occurs;
then , OST starts co unti ng 1024 o scilla tor cycl es when
PWRT ends (LP, XT, HS); when the OST ends, the
device comes out of Reset.
If MCLR is kept low long enough, all delays will expire.
Bringing MCLR high will begin execution immediately.
This is useful for testing purposes or to synchronize
more than one PIC16F7X7 device operating in parallel.
Table 15-3 shows the Reset conditions for the Status,
PCON and PC registers, while Table 15-4 shows the
Reset conditions for all the registers.
15.14 Power Control/Status Register
(PCON)
The Power C ontrol /S t atu s regis ter, PCON, has two bits
to indicate the type of Reset that last occurred.
Bit 0 is Brown-out Reset status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent Resets to see if
bit BOR cleared, indicating a Brown-out Reset
occurred. When the Brown-out Reset is disabled, the
state of the BOR bit is unpredictable.
Bit 1 is Po wer-on Reset S ta tus bit, POR. It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
Note: If the LVD i s enable d and the BOR modul e
is not enabl ed, the band gap will requ ire a
start -up time of no more than 50 s b efo re
the band gap reference is stable. Before
enabling the LVD interrupt, the user
should ensure that the band gap refer ence
voltage is stable by monitoring the IRVST
bit in the LV DCON regis ter. The LVD coul d
cause erroneous interrupts before the
band gap is stable.
2003-2013 Microchip Technology Inc. DS30498D-page 179
PIC16F7X7
TABLE 15-1: TIME-OUT IN VARIOUS SITUATIONS
TABLE 15-2: STATUS BITS AND THEIR SIGNIFICANCE
TABLE 15-3: RESET CONDITION FOR SPECIAL REGISTERS
Oscillator
Configuration Power-up Brown-out Reset Wake-up from
Sleep
PWRTE = 0PWRTE = 1PWRTE = 0PWRTE = 1
XT, HS, LP TPWRT + 1024 • TOSC 1024 • TOSC TPWRT + 1024 • TOSC 1024 • TOSC 1024 • TOSC
EXTRC, INTRC TPWRT 5-10 s(1) TPWRT 5-10 s(1) 5-10 s(1)
T1OSC — — — — 5-10 s(1)
Note 1: CPU s t art-up is always in vok ed on PO R , B OR and w ak e-u p f rom Sle ep. The 5 s-10 s delay is based on
a 1 MHz system clock.
POR BOR TO PD
0x11Power-on Reset
0x0xIllegal, TO is set on POR
0xx0Illegal, PD is set on POR
1011Brown-out Reset
1101WDT Reset
1100WDT Wake-up
11uuMCLR Reset during normal operation
1110MCLR Reset during Sleep or Interrupt Wake-up from Sleep
Legend: u = unchanged, x = unknown
Condition Program
Counter Status
Register PCON
Register
Power-on Reset 000h 0001 1xxx ---- -10x
MCLR Reset during normal operation 000h 000u uuuu ---- -uuu
MCLR Reset during Sleep 000h 0001 0uuu ---- -uuu
WDT Reset 000h 0000 1uuu ---- -uuu
WDT Wake- up PC + 1 uuu0 0uuu ---- -uuu
Brown-out Reset 000h 0001 1xxx ---- -1u0
Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- -uuu
Legend: u = unchanged, x = unknown, — = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
PIC16F7X7
DS30498D-page 180 2003-2013 Microchip Technology Inc.
TABLE 15-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Power-on Reset,
Brown-out Reset MCLR Reset,
WDT Reset Wake-up via WDT or
Interrupt
Wxxxx xxxx uuuu uuuu uuuu uuuu
INDF N/A N/A N/A
TMR0 xxxx xxxx uuuu uuuu uuuu uuuu
PCL 0000h 0000h PC + 1(2)
STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR xxxx xxxx uuuu uuuu uuuu uuuu
PORTA xx0x 0000 uu0u 0000 uuuu uuuu
PORTB xx00 0000 uu00 0000 uuuu uuuu
PORTC xxxx xxxx uuuu uuuu uuuu uuuu
PORTD xxxx xxxx uuuu uuuu uuuu uuuu
POR TE (PIC16F737/767)
POR TE (PIC16F747/777) ---- x---
---- x000
---- u---
---- u000
---- u---
---- uuuu
PCLATH ---0 0000 ---0 0000 ---u uuuu
INTCON 0000 000x 0000 000u uuuu uuuu(1)
PIR1 0000 0000 0000 0000 uuuu uuuu(1)
PIR2 000- 0-00 000- 0-00 uuu- u-uu
TMR1L xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H xxxx xxxx uuuu uuuu uuuu uuuu
T1CON -000 0000 -uuu uuuu -uuu uuuu
TMR2 0000 0000 0000 0000 uuuu uuuu
T2CON -000 0000 -000 0000 -uuu uuuu
SSPBUF xxxx xxxx uuuu uuuu uuuu uuuu
SSPCON 0000 0000 0000 0000 uuuu uuuu
SSPCON2 0000 0000 0000 0000 uuuu uuuu
CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON --00 0000 --00 0000 --uu uuuu
CCP2CON --00 0000 --00 0000 --uu uuuu
CCP3CON --00 0000 --00 0000 uuuu uuuu
CCPR2L xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2H xxxx xxxx uuuu uuuu uuuu uuuu
CCPR3L xxxx xxxx uuuu uuuu uuuu uuuu
CCPR3H xxxx xxxx uuuu uuuu uuuu uuuu
RCSTA 0000 000x 0000 000x uuuu uuuu
TXREG 0000 0000 0000 0000 uuuu uuuu
RCREG 0000 0000 0000 0000 uuuu uuuu
ADRESH xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 0000 0000 0000 0000 uuuu uuuu
OPTION_REG 1111 1111 1111 1111 uuuu uuuu
Legend: u = unchanged, x = unknown, — = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: One or more bits in INTCON, PIR1 and PR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 15-3 for Reset value for specific condition.
2003-2013 Microchip Technology Inc. DS30498D-page 181
PIC16F7X7
TRISA 1111 1111 1111 1111 uuuu uuuu
TRISB 1111 1111 1111 1111 uuuu uuuu
TRISC 1111 1111 1111 1111 uuuu uuuu
TRISD 1111 1111 1111 1111 uuuu uuuu
TRISE (PIC16F737/767)
TRISE (PIC16F747/777) ---- 1---
0000 1111
---- u---
0000 1111
---- 1---
uuuu uuuu
PIE1 0000 0000 0000 0000 -uuu uuuu
PIE2 000- 0-00 000- 0-00 uuu- u-uu
PCON ---- -1qq ---- -uuu ---- -uuu
OSCCON -000 1000 -000 1000 -uuu uuuu
OSCTUNE --00 0000 --00 0000 --uu uuuu
PR2 1111 1111 1111 1111 1111 1111
SSPADD 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 0000 0000 0000 0000 uuuu uuuu
TXSTA 0000 -010 0000 -010 uuuu -u1u
SPBRG 0000 0000 0000 0000 uuuu uuuu
CMCON 0000 0111 0000 0111 uuuu uuuu
CVRCON 000- 0000 000- 0000 uuu- uuuu
WDTCON ---0 1000 ---0 1000 ---u uuuu
ADRESL xxxx xxxx uuuu uuuu uuuu uuuu
ADCON1 0000 0000 0000 0000 uuuu uuuu
ADCON2 --00 0--- --00 0--- uuuu uuuu
PMDATA xxxx xxxx uuuu uuuu uuuu uuuu
PMADR xxxx xxxx uuuu uuuu uuuu uuuu
PMDATH --xx xxxx --uu uuuu --uu uuuu
PMADRH ---- xxxx ---- uuuu ---- uuuu
PMCON1 1--- ---0 1--- ---u 1--- ---u
LVDCON --00 0101 --00 0101 --uu uuuu
TABLE 15-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Power-on Reset,
Brown-out Reset MCLR Reset,
WDT Reset Wake-up via WDT or
Interrupt
Legend: u = unchanged, x = unknown, — = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: One or more bits in INTCON, PIR1 and PR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 15-3 for Reset value for specific condition.
PIC16F7X7
DS30498D-page 182 2003-2013 Microchip Technology Inc.
FIGURE 15-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH
PULL-UP RESISTOR)
FIGURE 15-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH
RC NETWORK): CASE 1
FIGURE 15-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH
RC NETWORK): CASE 2
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
TPWRT
TOST
2003-2013 Microchip Technology Inc. DS30498D-page 183
PIC16F7X7
FIGURE 15-10: SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK)
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
0V 1V
5V
TPWRT
TOST
PIC16F7X7
DS30498D-page 184 2003-2013 Microchip Technology Inc.
15.15 Interrupts
The PIC16 F7X7 ha s up to 17 sources of inte rrupt . The
Interrupt Control register (INTCON) records individual
interrupt requests in flag bits. It also has individual and
global interrupt enable bits.
A Global Interrupt Enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts or disables (if
cleared) all interr upts. When b it GIE is enable d and an
inter rupt’s flag bit and mask bit are s et, the int errupt will
vector immediately. Individual interrupts can be
disabled through their corresponding enable bits in
various registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on Reset.
The “return from interrupt” instruction, RETFIE, exits
the int errupt rout ine as well as sets the GIE bit which
re-ena ble s int er rup ts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the
Special Function Register, PIR1. The corresponding
interrupt enable bits are contained in Special Function
Register, PIE1 and the peripheral in terrupt enabl e bit is
contained in S p eci al Functi on R egi ste r, INTCON .
When an interrupt is serviced, the GIE bit is cleared to
disable any further interrupt, the return address is
pushed onto the stack and the PC is loaded with 0004h.
Once in the Interrupt Service Routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid
recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends on when the interrupt event occurs relative to
the current Q cycle. The latency is the same for one or
two-cycle instructions. Individual interrupt flag bits are
set regardless of the status of their corresponding
mask bit, PEIE bit or the GIE bit.
FIGURE 15-11: INTERRUPT LOGIC
Note: Indiv idual in terrupt flag b its are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
OSFIF
OSFIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
TMR0IF
TMR0IE
INT0IF
INT0IE
RBIF
RBIE
GIE
PEIE
Wake-up (If in Sleep mode)
Interrupt to CPU
PSPIF(1)
PSPIE(1)
CCP1IF
CCP1IE
CMIE
CMIF
BCLIF
BCLIE
CCP3IF
CCP3IE
CCP2IF
CCP2IE
Note 1: PSP interrupt is implemented only on PIC16F747/777 devices.
2003-2013 Microchip Technology Inc. DS30498D-page 185
PIC16F7X7
15.15.1 INT INTERRUPT
External interrupt on the RB0/INT pin is edge-triggered,
either ris ing if bit INTEDG (OPTION_REG<6> ) is set or
falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INT0IF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit, INT0IE (INTCON<4>). Flag bit
INT0IF must be cleared in software in the Interrupt
Service Routine before re-enabling this interrupt. The
INT interrupt can wake-up the processor from Sleep if
bit INT0I E w a s s et prio r to goi ng into Sleep. The status
of Global Interrupt Enable bit, GIE, decides whether or
not the processor branches to the interrupt vector
following wake-up. See Section 15.18 “Power-Down
Mode (Sleep)” for details on Sleep mode.
15.15.2 TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set
flag bit, TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>), see Section 6.0 “Timer0
Module”.
15.15.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by settin g/clearin g enable bit, RBIE (INTC ON<4>), se e
Section 2.2 “Data Memory Organization”.
15.16 Context Saving During Interr upts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (i.e., W, Status registers).
Since the upper 16 bytes of each bank are common in
the PIC16F7X7 devices, temporary holding registers,
W_TEMP, STATUS_TEMP and PCLATH_TEMP,
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for
context save and restore. The same code shown in
Example 15-1 can be used.
EXAMPLE 15-1: SAVING STATUS AND W REGISTERS IN RAM
MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS, W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
:
:(ISR) ;Insert user code here
:
SWAPF STATUS_TEMP, W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP, F ;Swap W_TEMP
SWAPF W_TEMP, W ;Swap W_TEMP into W
PIC16F7X7
DS30498D-page 186 2003-2013 Microchip Technology Inc.
15.17 Watchdog Timer (WDT)
For PIC16F7X7 devices, the WDT has been modified
from previous PIC16 devices. The new WDT is code
and functionally backward compatible with previous
PIC16 WDT modules and allows the user to have a
scaler value for the WDT and TMR0 at the same time.
In additio n, the WDT time-out valu e can be extende d to
268 seconds, using the prescaler with the postscaler
when the PSA bit is set to ‘1’.
15.17.1 WDT OS CIL LAT OR
The WDT derives its time base from the 31.25 kHz
INTRC; therefore, the a ccuracy of the 3 1.25 kHz will be
the same accuracy for the WDT time-out period.
The value of WDTCON is ‘---0 1000’ on a ll Re sets.
This gives a nominal time base of 16.38 ms which is
compatible with the time base generated with previous
PIC16 microcontroller versions.
A new presca ler ha s been added t o the pat h betw een
the internal RC and the multiplexors used to select the
path for the WDT. This pres caler is 16 bits and can be
programmed to divide the internal RC by 32 to 65536,
giving the time base used for the WDT a n ominal range
of 1 ms to 2.097s.
15.17.2 WDT CONTROL
The WDTEN bit is located in Configuration Word
Register 1 and when this bit is set, the WDT runs
continuously.
The SWD TEN bit is in the WDTC ON register . When the
WDTEN bit in the Confi guration W ord Regis ter 1 is set,
the SWDTE N bit has n o ef fect. I f WDTEN is cl ear, then
the SWDTEN bi t can be used to en able and disab le the
WDT. Setting the bit will enable it and clearing the bit
will disable it.
The PSA and PS<2:0> bits (OPTION_REG) have the
same function as in previous versions of the PIC16
family of microcontrollers.
FIGURE 15-12: WATCHDOG TIMER BLOCK DIAGRAM
Note: When the OST is invo ked, the WDT is held
in Reset because the WDT ripple counter
is us ed by the OS T to perf orm the osc ill a-
tor de lay coun t. When the OST co unt has
expired, the WDT will begin counting (if
enabled).
TABLE 15-5: PRESCALER/POSTSCALER BIT STATUS
Condition s Pr esc ale r Postsc ale r (PSA = 1)
WDTEN = 0
Cleared Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared at end of OST Cleared at end of OST
31.25 kHz
PSA
16-bit Programmable Prescaler WDT
From TMR0 Clock Source
Postscaler
8
PS<2:0>
PSA
WDT Time-out
To TMR0
WDTPS<3:0>
WDTEN from Configuration Word Register 1
1
10
0
SWDTEN from WDTCON Register
INTRC Clock
2003-2013 Microchip Technology Inc. DS30498D-page 187
PIC16F7X7
REGISTER 15-4: WDTCON: WATCHDOG TIMER CONTROL REGISTER (ADDRESS 105h)
TABLE 15-6: SUMMARY OF WATCHDOG TIMER REGISTERS
U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-1 WDTPS<3:0>: Watchdog Timer Peri od Select bits
0000 = 1:32 Prescale rate
0001 = 1:64 Prescale rate
0010 = 1:128 Prescale rate
0011 = 1:256 Prescale rate
0100 = 1:512 Prescale rate
0101 = 1:1024 Prescale rate
0110 = 1:2048 Prescale rate
0111 = 1:4096 Prescale rate
1000 = 1:8192 Prescale rate
1001 = 1:16394 Prescale rate
1010 = 1:32768 Prescale rate
1011 = 1:65536 Prescale rate
1100 = 1:1 Prescale rate
bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit(1)
1 = WDT is turned on
0 = WDT is turned off
Note 1: If WDTEN configuration bit = 1, then WDT is always enabled irrespective of this
control bit . If WDTEN confi guratio n bit = 0, then it is pos sible to t urn WDT on /of f with
this control bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Addr e s s N a me B it 7 Bit 6 Bit 5 B it 4 B it 3 Bit 2 B i t 1 B it 0 Value on
POR, BOR
Value on
all other
Resets
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
2007h Configuration
bits(1) BORV0 BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0 1111 1111 1111 1111
105h WDTCON — — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 15-1 for operation of these bits.
PIC16F7X7
DS30498D-page 188 2003-2013 Microchip Technology Inc.
15.17.3 TWO-SPEED CLOCK
START-UP MODE
Two-Speed Start-up minimizes the latency between
oscillator start-up and code execution that may be
selected with the IESO (Internal/External Switchover)
bit in Configuration Word Register 2. This mode is
achieved by initially using the INTRC for code
execution until the primary oscillator is stable.
If this mode is enabled and any of the following condi-
tions exist, the system will begin execution with the
INTRC oscillator. This results in almost immediate
code exec uti on with a min im um of dela y.
• POR and aft er the Power-u p T im er has expired (if
PWRTEN = 0)
• or following a wake-up from Sleep
• or a Reset, when running from T1OSC or INTRC
(after a Reset, SCS<1:0> are always set to ‘00’).
If the primary oscillator is configured to be anything
other than XT, LP or HS, then Two-Speed Start-up is
disabled because the primary oscillator will not require
any time to become stable after POR or an exit from
Sleep.
If the IRCF bits of the OSCCON register are configured
to a non-zero value prior to entering Sleep mode, the
secondary system clock frequency will come from the
output of the INTOSC. The IOFS bit in the OSCCON
register will be clear until the INTOSC is stable. This
will allow the user to determine when the internal
oscillator can be used for time critical applications.
Checking the state of the OSTS bit will confirm
whether the primary clock configuration is engaged. If
not, the OSTS bit will remain clear.
When the device is auto-configured in INTRC mode
following a POR or wake-up from Sleep, the rules for
entering other oscillator modes still apply, meaning the
SCS<1:0> bit s in OSC CON ca n be modif ied before the
OST time-out has occurred. This would allow the
application to wake-up from Sleep, perform a few
ins tru ctions using the IN TRC as t he clo ck sour ce and
go back to Sleep without waiting for the primary
oscillator to become stable.
15.17.3.1 Two-Speed Start-up Sequence
1. Wake-up from Sleep, Reset or POR.
2. OSCON bits configured to run from INTRC
(31.25 kHz).
3. Instructions begin execution by INTRC
(31.25 kHz).
4. OST enabled to count 1024 clock cycles.
5. OST timed out, wait for falling edge of INTRC.
6. OSTS is set.
7. System clock held low for eight falling edges of
new clock (LP, XT or HS).
8. System cloc k is sw i tch ed to prim ary sour ce (LP,
XT or HS).
The software may read the OSTS bit to determine
when the switchover takes place so that any software
timing edges can be adjusted.
FIGURE 15-13 : TWO-SPEED START -U P
Note: Following any Reset, the IRCF bits are
zeroed and the frequency selection is
forced to 31.25 kHz. The user can modify
the IRCF bits to select a higher internal
oscillator frequency.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit to remain clear.
Q4Q1 Q3 Q4 Q1 Q2
OSC1
Sleep
Program PC 0000h
INTRC
TOST
Q3 Q4
OSC2
OSTS
System Clock
0001h
Q1 Q2 Q3 Q4 Q1 Q2
Counter 0004h 0005h
0003h
Q1 Q2 Q3 Q4
CPU Start-up
2003-2013 Microchip Technology Inc. DS30498D-page 189
PIC16F7X7
15.17.4 FAIL-SAFE OPTION
The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate even in the
event of an oscillator failure.
FIGURE 15-14: FSCM BLOCK DIAGRAM
The FSCM function is enabled by setting the FCMEN
bit in Configuration Word R egister 2.
In the event of an oscillator failure, the FSCM will
generate an oscillator fail interrupt and will switch the
system clock over to the internal oscillator . The system
will continue to come from the internal oscillator until
the Fail-Safe condition is exited. The Fail-Safe
conditi on i s e xi ted w i th ei the r a R es et, the e xe cut ion of
a SLEEP instruction or a write to the SCS bits of a
different value .
The frequency of the internal oscillator will depend
upon the value contained in the IRCF bits. Another
clock source can be selected via the IRCF and the
SCS bits of the OSCCON register.
The FSCM sample clock is generated by dividing the
INTRC clock by 64. This will allow enough time
between FSCM sample clocks for a system clock edge
to occur.
On the rising edge of the postscaled clock, the
monitoring latch (CM = 0) will be cleared. On a falling
edge of the primary or secondary system clock, the
monitoring latch will be set (CM = 1). In the event that
a falling edge of the postscaled clock occurs and the
monitoring latch is not set, a clock failure has been
detected.
While in Fail-Safe mo de, a Reset will ex it the Fail-Safe
condition. If the primary clock source is configured for
a crystal, the OST timer will wait for the 1024 clock
cycles for the OST time-out and the device will
continue running from the internal oscillator until the
OST is complete. A SLEEP instruction, or a write to the
SCS bits (where SCS bits do not = 00), can be
performed to put the device into a low-power mode.
If Reset occurs while in Fail-Safe mode and the
primar y cl ock s ource i s EC or RC, t hen t he de vice will
immediately switch back to EC or RC mode.
15.17.4.1 Fail-Safe in Low-Power Mode
A change of SCS<1:0> or the SLEEP instruction will
end the Fail-Safe condition. The system clock will
default to the source selected by the SCS bits, which
is either T1OSC, INTRC or none (Sleep mode). How-
ever, the FSCM will continue to monitor the system
clock. If the secondary clock fails, the device will
immediately switch to the internal oscillator clock. If
OSFIE is set, an interru pt wi ll be gen erat ed.
FIGURE 15-15: FSCM TIMING DIAGRAM
Peripheral
INTRC ÷ 64
S
C
Q
31.25 kHz
(32 s) 488 Hz
(2.048 ms)
Clock Monitor
Latc h ( C M)
(edge-triggered)
Clock
Failure
Detected
Oscillator
Clock
Q
Note: Two-Speed Start-up is automatically
enabled when the Fail-Safe option is
enabled.
OSCFIF
CM Output
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The system clock is normally at a mu ch higher frequency than the sample clock. The relat ive frequencies in
this example have been chosen for clarity.
(Q)
CM Test CM Test CM Test
(488 Hz)
PIC16F7X7
DS30498D-page 190 2003-2013 Microchip Technology Inc.
15.17.4.2 FSCM and the Watchdog Timer
When a clock failure is detected, SCS<1:0> will be
forced to ‘10’ which will reset the WDT (if enabled).
15.17.4.3 POR or Wake from Sleep
The FS CM is designed to detect osc illator failu re at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
system clock is EC, RC or INTRC modes, monitoring
can begin immediately following these events.
For oscillator modes involving a crystal or resonator
(HS, LP or XT), the situation is somewhat different.
Since the osc il lat or ma y re quire a start-up ti me con si d-
erabl y longer than the FSCM sa mple clock ti me, a fals e
clock failure may be detected. To prevent this, the
internal oscillator block is automatically configured as
the system clock and functions until the primary clock
is sta ble (the OST and PLL timers have timed out). Thi s
is identical to Two-Speed Start-up mode. Once the
primary clock is stabl e, the INTRC returns to its role a s
the FSCM source.
15.18 Power-Down Mode (Sleep)
Power-Down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (Status<3>) is cleared, the
TO (Status<4>) bit is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or high -impedanc e).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external circuitry
is drawing current from the I/O pin, power-down the A/D
and disable external clocks. Pull all I/O pins that are
high-impedance inputs, high or low externally, to avoid
switching current s caused by floating inputs. The T0CKI
input should also be at VDD or VSS for lowest current
consumption. The contribution from on-chip pull-ups on
POR TB should als o be cons idered.
The MCLR pin must be at a logic high level (VIHMC).
15.18.1 W AKE-UP FROM SLEEP
The devi ce can wa ke-up from Sleep th rough one of th e
following events:
1. External Reset input on MCLR pin.
2. Watchdog Timer wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or a
peripheral interrupt.
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
executi on and ca us e a “w ake-up”. The TO and PD bit s
in the Status register can be used to determine the
cause of the device Reset. The PD bi t, wh ic h i s se t on
power-u p, is cleared when Sl eep is invok ed. The TO bit
is cleared if a WDT time-out occurred and caused
wake-up.
The follo wing periphe ral interrupt s can wake the device
from Sleep:
1. TMR1 inte rrupt. T imer1 must be o perating a s an
asynchronous counter.
2. CCP Capture mode interrupt.
3. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
4. SSP (Start/Stop) bit detect interrupt.
5. SSP transmit or receive in Slave mode (SPI/I2C).
6. A/D conversion (when A/D clock source is RC).
7. EEPROM write operation completion.
8. Comparator output changes state.
9. AUSART RX or TX (Synchronous Slave mode).
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up thro ugh an interrup t eve nt, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the inst ruction af ter the SLEEP ins truction. If the GIE b it
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the execu-
tion of the instruction following SLEEP is not desirable,
the user should have a NOP after the SLEEP instruction.
Note: The same logic that prevents false
oscillator failure interrupts on POR, or
wake from Sleep, will also prevent the
detection of the oscillator ’s failure to start
at all following these events. This can be
avoided by monitoring the OSTS bit and
using a timing routine to determine if the
oscillator is taking too long to start. Even
so, no oscillator failure interrupt will be
flagged.
2003-2013 Microchip Technology Inc. DS30498D-page 191
PIC16F7X7
15.18.2 WAKE-UP USIN G INTERR UPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit s et, one of the fo llowin g wil l occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT an d WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be clear ed.
• If the interrupt occurs during or after the
execution of a SLEEP ins truc ti on, the device will
immediately wake-up from Sleep. T he SLEEP
instruc t io n will be com pl etel y ex ec ute d befo re the
wake-up. The refore, the WDT and WDT pres caler
and pos tsc aler (i f enabl ed) wi ll be cle ared, the T O
bit will be set and the PD bit wil l be cl eared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP ins tructio n execut ed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT ins truction
should be executed before a SLEEP instruction.
FIGURE 15-16: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKO(4)
INT pin
INT F Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC – 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy Cycle
PC + 2 0004h 0005h
Dummy Cycle
TOST(2)
PC + 2
Note 1: XT, HS or LP Oscillator mode assume d.
2: TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Oscillator mode.
3: GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
4: CLKO is not available in these oscillator modes but shown here for timing reference.
PIC16F7X7
DS30498D-page 192 2003-2013 Microchip Technology Inc.
15.19 In-Circuit Debugger
When th e DEBU G bit i n t he C onfigu rat ion Word is pro-
grammed to a ‘0’, th e In-Circuit Debugger function ality
is enabled. This function allows simple debugging
functions when used with MPLAB® ICD. When the
microcontroller has this feature enabled, some of the
resources ar e no t avai labl e for ge ner al use . Table 15-7
shows which features are consumed by the background
debugger.
TABLE 15-7: DEBUGGER RESOURCES
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
15.20 Program Verification/Code
Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verificati on purp os es .
15.21 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during program/verify. It is
recommended that only the four Least Significant bits
of the ID lo cati on are used.
15.22 In-Circuit Seri al Programming
PIC16F7X7 microcontrollers can be serially
progra mmed w hile in t he en d appl icati on ci rcu it. Th is i s
simply done with tw o lines for cl ock and dat a and thre e
other lines for power, ground and the programming
volt age (see Figure 15-17 for an exa mp le) . Thi s al lo w s
customers to manufacture boards with unprogrammed
devices and then program the microcontroller just
before shipping the product. This also allows the most
recent firmware or a custom firmware to be
programmed.
For general information of serial programming, please
refer to the “In-Circuit Serial Programming™ (ICSP™)
Guide” (D S302 77).
FIGURE 15-17: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING™
CONNECTION
I/O pins RB6 , RB7
Stack 1 level
Program Memory Address 0000h must be NOP
Last 100h wor ds
Data Memory 0x070 (0x0F0, 0x170, 0x1F0)
0x165-0x16F
Note: In-Circuit Debugger operation must occur
between the operating voltage range
(VDD) of 4.75V-5.25V on PIC16F7X7
devices.
External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC16F7X7
VDD
VSS
MCLR/VPP/RE3
RB6
RB7
+5V
0V
VPP
CLK
Data I/O
VDD
* * *
*
* Isolation devices (as required).
2003-2013 Microchip Technology Inc. DS30498D-page 193
PIC16F7X7
16.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont rol operations
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type and one or
more operands, which further specify the operation of
the instruction. The formats for each of the categories
are presen ted in Fig ure 16-1, w hile the variou s opcod e
fields are sum m ariz ed in Table 16-1.
Table 13-2 lists the instructions recognized by the
MPASMTM Assembler. A complete description of each
instruction is also available in the “PIC® Mid-R ange MCU
Famil y Ref erenc e Manu al” (DS33023).
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W regis ter . If ‘d’ is one, the res ult is place d
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the bit affected by the opera-
tion, w hi le ‘f’ represent s th e a ddre ss of the file in which
the bit is located.
For literal and control operations, ‘k’ represents an
eight or eleven-bit constant or literal value
One instr uction cycle co nsists of four os cillator periods ;
for an oscillator frequency o f 4 MHz, t his gives a normal
instruction execution time of 1 s. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
change d as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
16.1 Read-Modify-Write Op erations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operatio n. The register is read, the data is modi fied and
the resul t is stored ac cording to e ither the ins truction or
the destination designator ‘d’. A read operation is
perfor me d on a regi st er ev en if the instruction wri tes to
that register.
For example, a “CLRF PORTB” instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the
unintended result that the condition that sets the RBIF
flag w oul d b e c le ared fo r pi ns configured as inp ut s an d
using the PORTB interrupt-on-change feature.
TABLE 16-1: OPCODE FIELD
DESCRIPTIONS
FIGURE 16-1: GENERAL FORMAT FOR
INSTRUCTIONS
Note: To maintain upward compatibility with
future PIC16F7X7 products, do not use
the OPTION and TRIS instructions.
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral field, constant data or label
xDon’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC Program Counter
TO Time-out bit
PD Power-Down bit
Byte-oriented file r egister op erations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriente d file register operations
13 10 9 7 6 0
OPCODE b (BIT # ) f (FIL E #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16F7X7
DS30498D-page 194 2003-2013 Microchip Technology Inc.
TABLE 16-2: PIC16F7X7 INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-OR I ENTED FILE R EGISTER OPE R ATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AN D W with f
Clear f
Clear W
Comp lement f
Decrement f
Decrement f, Skip if 0
Incr e ment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Mov e W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C, DC, Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1,2
1, 2
1, 2
1, 2
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip i f Clear
Bit Test f, Sk ip i f Se t
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1, 2
1, 2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from inter rupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C, DC, Z
Z
TO, PD
Z
TO, PD
C, DC, Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the “PIC® Mid-Range MCU Family
Reference Manual” (DS33023).
2003-2013 Microchip Technology Inc. DS30498D-page 195
PIC16F7X7
16.2 Instruction Descri ptions
ADDLW Add Literal and W
Syntax: [ label ] ADDLW k
Operands: 0 k 255
Operation: (W) + k (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are added to the eight-bi t literal ‘k’
and the result is placed in the W
register.
ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) + (f) (destination)
Status Affected: C, DC, Z
Desc ription: Add the conten ts of the W regis ter
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W registe r . I f
‘d’ is ‘1’, the result is stored back
in register ‘f’.
ANDLW AND Literal with W
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. (k) (W)
Status Affected: Z
Description: The contents of W register are
ANDed with the ei ght-bit literal ‘k’.
The result is placed in the
W register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .AND. (f) (destination)
Status Affected: Z
Description: AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is sto r ed bac k in regi ste r ‘f’.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 f 127
0 b 7
Operation: 0 (f<b>)
Status Af fe cte d: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 f 127
0 b 7
Operation: 1 (f<b>)
Status Af fe cte d: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 f 127
0 b < 7
Operation: skip if (f<b>) = 1
Status Af fe cte d: None
Descr iption: If bit ‘b’ in register ‘f’ is ‘0’, the next
instructi on is ex ecuted.
If bit ‘b’ is ‘1’, then the next
instructi on is discard ed an d a NOP
is exec ute d in stead, making thi s a
2 TCY instruction.
BTFSC Bit Test, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 f 127
0 b 7
Operation: skip if (f<b>) = 0
Status Af fe cte d: None
Descr iption: If bit ‘b’ in register ‘ f’ is ‘1’, the next
instruction is executed.
If bit ‘b’ in reg ister ‘f’ is ‘0’, the next
instr uct ion is discarded a nd a NOP
is exec uted ins tea d, m ak ing thi s a
2 TCY instruction.
PIC16F7X7
DS30498D-page 196 2003-2013 Microchip Technology Inc.
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 k 204 7
Operation: (PC) + 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Status Affected: None
Description: Call subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits<10:0>. The upper bits of
the PC are loa ded from PCLATH.
CALL is a two-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 f 127
Operation: 00h (f)
1 Z
Status Affected: Z
Desc ript ion : The content s of regi ste r ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W)
1 Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Af fe cte d: T O, PD
Description: CLRWDT instruction resets the
W atchdog T imer . It also resets the
prescaler of the WDT. S t a tus bits ,
TO and PD, are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination)
Status Af fe cte d: Z
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in regi ster ‘f’.
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) – 1 (desti nati on)
Status Af fe cte d: Z
Descr iption: D ecrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
2003-2013 Microchip Technology Inc. DS30498D-page 197
PIC16F7X7
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) – 1 (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
decrem ented. If ‘d’ is ‘ 0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
resu lt is ‘ 0’, then a NOP is
executed instead, making it a
2 TCY instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 2047
Operation: k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The e le ven -bi t im me dia t e v al ue i s
loaded into PC bits<10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination)
Status Affected: Z
Description: The contents of register ‘f’ are
incremen ted . If ‘ d ’ is ‘ 0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination),
skip if result = 0
Status Af fe cte d: None
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, th e result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, a NOP is executed
instead, making it a 2 TCY
instruction.
IORLW Inclusive OR Literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. k (W)
Status Af fe cte d: Z
Descr iption: The con tents of t he W register a re
ORed with the eight-bit literal ‘k’.
The result is placed in the W
register.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .OR. (f) (destinati on)
Status Af fe cte d: Z
Description: Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
PIC16F7X7
DS30498D-page 198 2003-2013 Microchip Technology Inc.
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination )
Status Affected: Z
Description: The contents of register ‘f’ are
moved to a destination dependant
upon the status of ‘d’. If d = 0,
the destination is W register . If
d = 1, the destination is file register
‘f’ it s e l f. d = 1 is useful to test a file
register since status flag Z is
affected.
MOVLW Move Literal to W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affected: None
Description: The eight-bit literal ‘k’ is loaded
into W register. The don’t cares
will assemble as ‘0’s.
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 f 127
Operation: (W) (f)
Status Affected: None
Description: Move data from W register to
register ‘f’.
NOP No Oper atio n
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Af fe cte d: None
Description: No operation.
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS PC,
1 GIE
Status Af fe cte d: None
RETLW Return with Literal in W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k (W);
TOS PC
Status Af fe cte d: None
Description: The W register is loaded with the
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
2003-2013 Microchip Technology Inc. DS30498D-page 199
PIC16F7X7
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the left through the
Carry fl ag. If ‘d’ is ‘0’, the result is
placed in the W register . If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS PC
Status Affected: None
Description: Return from subroutine. The stack
is POPed an d t he top o f th e s t a ck
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotat ed one bit to the r ight throug h
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed
back in register ‘f’.
Register fC
Register fC
SLEEP Enter Sleep mode
Syntax: [ label ] SLEEP
Operands: None
Operation: 00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Af fe cte d: T O, PD
Description: The Power-Down status bit, PD,
is cleared. Time-out status bit,
TO, is set. Watchdog Timer and
its prescaler are cleared.
The processor is put into Sleep
mode with th e oscillat or stopped.
SUBLW Subtract W from Literal
Syntax: [ label ] SUBLW k
Operands: 0 k 255
Operation: k – (W) W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) – (W) destination)
Status Affected: C, DC, Z
Description: Subtract (2’s complement method)
W register from register ‘f ’. If ‘d’ is
‘0’, the resu lt is sto red in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
PIC16F7X7
DS30498D-page 200 2003-2013 Microchip Technology Inc.
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 127
d [0,1]
Operation: (f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the resul t is
placed in register ‘f’.
XORLW Exclusive OR Literal with W
Syntax: [ label ]XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
Description: The contents of the W register
are XORed with the eight-bit
literal ‘k’. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .XOR. (f) destination)
Status Af fe cte d: Z
Description: Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the res ult is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
2003-2013 Microchip Technology Inc. DS30498D-page 201
PIC16F7X7
17.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Devi ce
Families
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Progra mmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Dev elopment Boards,
Evaluation Kits, and Starter Kits
17.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separatel y)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop vari ables from source to watch
windows
• Exten si ve on-l in e help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (eit her C or assembly)
• One-tou ch compile o r assemble , and downl oad to
emulator and simulator tools (automatically
updates all projec t information)
• Debug us ing :
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
PIC16F7X7
DS30498D-page 202 2003-2013 Microchip Technology Inc.
17.2 MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
17.3 HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of dig ital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
process or , and one-s tep driver , and can run on multipl e
platforms.
17.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
sour ce fil es
• Directives that allow complete control over the
assembly process
17.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLA B C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB O bject Li brarian manage s the cre ation an d
modification of library files of precompiled code. When
a rout in e from a l ibra ry is called fro m a so urc e f ile , only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacem ent, delet ion and extraction
17.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the asse mbler to pro duce i ts o bje ct file . The ass embl er
generates relocatable object files that can then be
archived or linked with other relocatable object files and
arch ives to c rea te an e xecu tabl e fil e. N otab le fe atu res
of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB IDE compatibility
2003-2013 Microchip Technology Inc. DS30498D-page 203
PIC16F7X7
17.7 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most periph erals and i nternal regi sters.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
developm ent tool .
17.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated D evelopment Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgrad able through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
17.9 MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
device s. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nect ed to t he des ign e nginee r's PC using a hig h-spee d
USB 2.0 i nte rfac e a nd is co nnected to the ta rget with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MP LAB ICD 3 supports al l
MPLAB ICD 2 headers.
17.10 PICkit 3 In-Cir cuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most af fordable price point using the powerful graphi cal
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller , hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
PIC16F7X7
DS30498D-page 204 2003-2013 Microchip Technology Inc.
17.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
The P ICkit™ 2 Develo pment Program mer/Debu gger i s
a low-cost development tool with an easy to use inter-
face fo r programmin g and debu gging Micr ochip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F, PIC12F5xx, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families o f 8 -bi t, 1 6-b it, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
produ cts . With Mic rochip ’s power ful MPL AB Integrate d
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file reg ist ers can be ex amin ed and m odifie d.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
17.12 MPLAB PM3 Device Progr ammer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64 ) for me nus an d err or messag es an d a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Devic e Programmer can rea d, verify an d program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or U SB cable.
The MPL AB PM3 has high-spe ed comm unications and
optimized algorithms for quick programming of large
memory devices and inc orporates an MMC card for file
storage and data applications.
17.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The board s support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory .
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience t he specified d evice. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2003-2013 Microchip Technology Inc. DS30498D-page 205
PIC16F7X7
18.0 ELECTRICAL CHARACTERIST ICS
Absolute Maximum Ratings †
Ambient temperature under bias .............................................................................................................-40°C to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) ..........................................-0.3V to (VDD + 0.3V)
Volta ge on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V
Volta ge on MCLR with respect to VSS (Note 2)..............................................................................................0 to +13.5V
Voltage on RA4 with respect to VSS...................................................................................................................0 to +12V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin...........................................................................................................................300 mA
Maximum current into VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk byPORTA, PORTB and PORTE (combined) (Note 3)....................................................200 mA
Maximum current sourced by PORTA, PORTB and PORTE (combined) (Note 3)...............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3) .................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3) ............................................................200 mA
Note 1: Power d issip ation is calcula ted as fol lows: Pdis = VDD x {IDD – IOH} + {(VDD – V OH) x IOH} + (VOL x IOL)
2: Voltage spikes at the MCLR pin may cause latch-up. A series resistor of greater than 1 k should be used
to pull MCLR to VDD, rather than tying the pin directly to VDD.
3: PORTD and PORTE are not implemented on the PIC16F737/767 devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC16F7X7
DS30498D-page 206 2003-2013 Microchip Technology Inc.
FIGURE 18-1: PIC16F7X7 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED)
FIGURE 18-2: PIC16LF7X 7 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
20 MHz
5.0V
3.5V
3.0V
2.5V
16 MHz
Frequency
Voltage
6.0V
5.5V
4.5V
4.0V
2.0V
5.0V
3.5V
3.0V
2.5V
FMAX = (12 MHz/V) (VDDAPPMIN – 2.5V) + 4 MHz
Note 1: VDDAPPMIN is the minim um voltage of the PIC® device in the app lic ati on .
4 MHz 10 MHz
Note 2: FMAX has a maximum frequency of 10 MHz.
2003-2013 Microchip Technology Inc. DS30498D-page 207
PIC16F7X7
18.1 DC Characteristics: PIC16F737/747/767/777 (Industr ial, Extended)
PIC16LF737/747/767/777 (Industria l)
PIC16LF737/747/767/777
(Industrial) Stand ard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F737/747/767/777
(Industrial, Extended)
Stand ard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
VDD Supply Voltage
D001 PIC16LF7X7 2.5
2.2
2.0
—
—
—
5.5
5.5
5.5
V
V
V
A/D in use, -40°C to +85°C
A/D in use, 0°C to +85°C
A/D not used, -40°C to +85°C
D001
D001A PIC16F7X7 4.0
VBOR*—
—5.5
5.5 V
VAll configurations
BOR enabled (Note 6)
D002* VDR RAM Data Retention
Voltage (Note 1) —1.5—V
D003 VPOR VDD Start Voltage to
ensure internal Power-on Reset
signal
—VSS — V See section on Power-on Reset for details
D004* SVDD VDD Rise Rate to ensure
internal Power-on Reset signal 0.05 — — V/ms See section o n Power-on Reset for details
VBOR Brow n-out Reset Voltage
PIC16LF7X7
D005 BORV1:BORV0 = 11 1.96 2.06 2.16 V 85C T 25C
BORV1:BORV0 = 10 2.64 2.78 2.92 V
BORV1:BORV0 = 01 4.11 4.33 4.55 V
BORV1:BORV0 = 00 4.41 4.64 4.87 V
D005 PIC16F7X7 Industrial
BORV1:BORV0 = 1x N.A. —N.A. VNot in operating voltage range of device
BORV1:BORV0 = 01 4.16 —4.5 V
BORV1:BORV0 = 00 4.45 —4.83 V
D005 PIC16F7X7 Extended
BORV1:BORV0 = 1x N.A. —N.A. VNot in operating voltage range of device
BORV1:BORV0 = 01 4.07 —4.59 V
BORV1:BORV0 = 00 4.36 —4.92 V
Legend: Shading of rows is to assist in readability of of the table.
* T hes e parameters are characte rized but not tested.
† Dat a in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from-rail to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the
part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS.
4: For RC oscillator configuration, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
5: The current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or I PD measurement.
6: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
PIC16F7X7
DS30498D-page 208 2003-2013 Microchip Technology Inc.
18.2 DC Characteristics: Power-Down and Supply Current
PIC16F737/747/767/777 (Industrial, Extended)
PIC16LF737/747/767/777 (Industrial)
PIC16LF737/747/767/777
(Industrial) St andard Operat ing Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F737/747/767/777
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Power-Down Current (IPD)(1)
PIC16LF7X7 0.1 0.4 A -40°C VDD = 2.0V0.1 0.4 A+25°C
0.4 1.5 A+85°C
PIC16LF7X7 0.3 0.5 A -40°C VDD = 3.0V0.3 0.5 A+25°C
0.7 1.7 A+85°C
All devices 0.6 1.0 A -40°C
VDD = 5.0V
0.6 1.0 A+25°C
1.2 5.0 A+85°C
Extended devices 6 28 A +125°C
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the os cillator type. Power-down current is mea sured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
2003-2013 Microchip Technology Inc. DS30498D-page 209
PIC16F7X7
Supply Current (IDD)(2,3)
PIC16LF7X7 9 20 A -40°C VDD = 2.0V
FOSC = 32 kHZ
(LP Oscillator)
715A+25°C
715A+85°C
PIC16LF7X7 16 30 A -40°C VDD = 3.0V14 25 A+25°C
14 25 A+85°C
All devices 32 40 A -40°C
VDD = 5.0V
26 35 A+25°C
26 35 A+85°C
Extended devices 35 53 A +125°C
PIC16LF7X7 72 95 A -40°C VDD = 2.0V
FOSC = 1 MHZ
(RC Oscillator)(3)
76 90 A+25°C
76 90 A+85°C
PIC16LF7X7 138 175 A -40°C VDD = 3.0V136 170 A+25°C
136 170 A+85°C
All devices 310 380 A -40°C
VDD = 5.0V
290 360 A+25°C
280 360 A+85°C
Extended devices 330 5 00 A +125°C
18.2 DC Characteristics: Power-Down and Supply Current
PIC16F737/747/767/777 (Industrial, Extended)
PIC16LF737/747/767/777 (Industrial) (Continued)
PIC16LF737/747/767/777
(Industrial) St andard Operat ing Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F737/747/767/777
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power- down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
PIC16F7X7
DS30498D-page 210 2003-2013 Microchip Technology Inc.
Supply Current (IDD)(2,3)
PIC16LF7X7 270 315 A -40°C VDD = 2.0V
FOSC = 4 MHz
(RC Oscillator)(3)
280 310 A+25°C
285 310 A+85°C
PIC16LF7X7 460 610 A -40°C VDD = 3.0V450 600 A+25°C
450 600 A+85°C
All devices 900 1060 A -40°C
VDD = 5.0V
890 1050 A+25°C
890 1050 A+85°C
Extended devices .920 1.5 mA +125°C
All devices 1.8 2.3 mA -40°C VDD = 4.0V
FOSC = 20 MHZ
(HS Oscillator)
1.6 2.2 mA +25°C
1.3 2.2 mA +85°C
All devices 3.0 4.2 mA -40°C
VDD = 5.0V
2.5 4.0 mA +25°C
2.5 4.0 mA +85°C
Extended devices 3.0 5.0 mA +125°C
18.2 DC Characteristics: Power-Down and Supply Current
PIC16F737/747/767/777 (Industrial, Extended)
PIC16LF737/747/767/777 (Industrial) (Continued)
PIC16LF737/747/767/777
(Industrial) St andard Operat ing Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F737/747/767/777
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the os cillator type. Power-down current is mea sured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
2003-2013 Microchip Technology Inc. DS30498D-page 211
PIC16F7X7
Supply Current (IDD)(2,3)
PIC16LF7X7 8 20 A -40°C VDD = 2.0V
FOSC = 31.25 kHz
(RC_RUN mode,
Internal RC Oscillator)
715A+25°C
715A+85°C
PIC16LF7X7 16 30 A -40°C VDD = 3.0V14 25 A+25°C
14 25 A+85°C
All devices 32 40 A -40°C
VDD = 5.0V
29 35 A+25°C
29 35 A+85°C
Extended devices 35 45 A +125°C
PIC16LF7X7 132 160 A -40°C VDD = 2.0V
FOSC = 1 MHz
(RC_RUN mode,
Internal RC Oscillator)
126 155 A+25°C
126 155 A+85°C
PIC16LF7X7 260 310 A -40°C VDD = 3.0V230 300 A+25°C
230 300 A+85°C
All devices 560 690 A -40°C
VDD = 5.0V
500 650 A+25°C
500 650 A+85°C
Extended devices 570 7 10 A +125°C
PIC16LF7X7 310 420 A -40°C VDD = 2.0V
FOSC = 4 MHz
(RC_RUN mode,
Internal RC Oscillator)
300 410 A+25°C
300 410 A+85°C
PIC16LF7X7 550 650 A -40°C VDD = 3.0V530 620 A+25°C
530 620 A+85°C
All devices 1.2 1.5 mA -40°C
VDD = 5.0V
1.1 1.4 mA +25°C
1.1 1.4 mA +85°C
Extended devices 1.3 1.6 mA +125°C
18.2 DC Characteristics: Power-Down and Supply Current
PIC16F737/747/767/777 (Industrial, Extended)
PIC16LF737/747/767/777 (Industrial) (Continued)
PIC16LF737/747/767/777
(Industrial) St andard Operat ing Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F737/747/767/777
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power- down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
PIC16F7X7
DS30498D-page 212 2003-2013 Microchip Technology Inc.
Supply Current (IDD)(2,3)
PIC16LF7X7 .950 1.3 mA -40°C VDD = 3.0V
FOSC = 8 MHz
(RC_RUN mode,
Internal RC Oscillator)
.930 1.2 mA +25°C
.930 1.2 mA +85°C
All devices 1.8 3.0 mA -40°C
VDD = 5.0V
1.7 2.8 mA +25°C
1.7 2.8 mA +85°C
Extended devices 2.0 4.0 mA +125°C
PIC16LF7X7 9 13 A -10°C VDD = 2.0V
FOSC = 32 kHz
(SEC_RUN mode,
Timer1 as Clock)
914A+25°C
11 16 A+70°C
PIC16LF7X7 12 34 A -10°C VDD = 3.0V12 31 A+25°C
14 28 A+70°C
All devices 20 72 A -10°C VDD = 5.0V20 65 A+25°C
25 59 A+70°C
18.2 DC Characteristics: Power-Down and Supply Current
PIC16F737/747/767/777 (Industrial, Extended)
PIC16LF737/747/767/777 (Industrial) (Continued)
PIC16LF737/747/767/777
(Industrial) St andard Operat ing Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F737/747/767/777
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the os cillator type. Power-down current is mea sured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
2003-2013 Microchip Technology Inc. DS30498D-page 213
PIC16F7X7
Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD)
D022
(IWDT)Watchdog T imer 1.5 3.8 A -40°C VDD = 2.0V2.2 3.8 A+25°C
2.7 4.0 A+85°C
2.3 4.6 A -40°C VDD = 3.0V2.7 4.6 A+25°C
3.1 4.8 A+85°C
3.0 10.0 A -40°C
VDD = 5.0V
3.3 10.0 A+25°C
3.9 13.0 A+85°C
Extended devices 5.0 21.0 A +125°C
D022A
(IBOR)Brown-out Reset 17 35 A-40C to +85CV
DD = 3.0V
47 45 A-40C to +85CV
DD = 5.0V
00A-40C to +85CV
DD = 2.0V
VDD = 3.0V
VDD = 5.0V
BOREN:BORSEN = 10
in Sleep mode
Extended devices 48 50 A-40C to +125CV
DD = 5.0V
D022B
(ILVD)Low-Voltage Detect 14 25 A-40C to +85CV
DD = 2.0V
18 35 A-40C to +85CV
DD = 3.0V
21 45 A-40C to +85CV
DD = 5.0V
Extended devices 24 50 A-40C to +125CV
DD = 5.0V
18.2 DC Characteristics: Power-Down and Supply Current
PIC16F737/747/767/777 (Industrial, Extended)
PIC16LF737/747/767/777 (Industrial) (Continued)
PIC16LF737/747/767/777
(Industrial) St andard Operat ing Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F737/747/767/777
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power- down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
PIC16F7X7
DS30498D-page 214 2003-2013 Microchip Technology Inc.
Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD)
D025
(IOSCB)T i mer1 Oscillator 1.7 2.3 A -40°C VDD = 2.0V
32 kHz on Ti mer1
1.8 2.3 A+25°C
2.0 2.3 A+85°C
2.2 3.8 A -40°C VDD = 3.0V2.6 3.8 A+25°C
2.9 3.8 A+85°C
3.0 6.0 A -40°C VDD = 5.0V3.2 6.0 A+25°C
3.4 7.0 A+85°C
D026
(IAD)A/D Converter 0.001 2.0 A-40C to +85CV
DD = 2.0V
A/D on, Sleep, not converting
0.001 2.0 A-40C to +85CV
DD = 3.0V
0.003 2.0 A-40C to +85CV
DD = 5.0V
Extended devices 4 8 mA -40C to +125CV
DD = 5.0V
18.2 DC Characteristics: Power-Down and Supply Current
PIC16F737/747/767/777 (Industrial, Extended)
PIC16LF737/747/767/777 (Industrial) (Continued)
PIC16LF737/747/767/777
(Industrial) St andard Operat ing Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F737/747/767/777
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Typ Max Units Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the os cillator type. Power-down current is mea sured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
2003-2013 Microchip Technology Inc. DS30498D-page 215
PIC16F7X7
18.3 DC Characteristics: Internal RC Accuracy
PIC16F737/747/767/777 (Industrial, Ex tended)
PIC16LF737/747/767/777 (Industrial)
PIC16LF737/747/767/777
(Industrial) St andard Operat ing Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F737/747/767/777
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Min Typ Max Units Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 M Hz, 500 kHz, 250 kHz, 125 kHz (1)
PIC16LF7X7 -2 ±1 2 % +25°C VDD = 2.7V-3.3V-5 — 5 % -10°C to +85°C
-10 — 10 % -40°C to +85°C
PIC16F7X7 -2 ±1 2 % +25°C
VDD = 4.5V-5.5V
-5 — 5 % -10°C to +85°C
-10 —10 %-40°C to +85°C
Extended devices -15 —15 %-40°C to +125°C
INTRC Accuracy @ Freq = 31 kHz(2)
PIC16LF7X7 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.7V-3.3V
PIC16F7X7 26.562 —35.938 kHz -40°C to +85°C VDD = 4.5V -5.5V
Legend: Shading of rows is to assist in readability of the table.
Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
2: INTRC is used to calibrate INTOSC.
PIC16F7X7
DS30498D-page 216 2003-2013 Microchip Technology Inc.
18.4 DC Characteristics: PIC16F737/747/767/777 (In dustrial, Extended)
PIC16LF737/747/767/777 (Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Operating voltage VDD range as described in
Section 18.1 “ DC C harac ter ist ics” .
Param
No. Sym Characteristic Min Typ† Max Units Conditions
VIL Input Low Voltage
I/O ports:
D030 with TTL buf fer VSS —0.15
VDD V For entire VDD range
D030A VSS — 0.8V V 4.5V VDD 5.5V
D031 with Schmitt Trigger buffer VSS — 0.2 VDD V
D032 MCLR, OSC1 (in RC mode) VSS — 0.2 VDD V
D033 OSC1 (in XT and LP modes) VSS —0.3VV(Note 1)
OSC1 (in HS mode) VSS — 0.3 VDD V
Ports RC3 and RC4: —
D034 with Schmitt Trigger buffer VSS — 0.3 VDD V For entire VDD range
D034A with SMBus -0.5 — 0.6 V For VDD = 4.5 to 5.5V
VIH Input High Voltage
I/O ports: —
D040 with TTL buffer 2.0 — VDD V4.5V VDD 5.5V
D04 0 A 0.25 VDD + 0.8V — VDD V For entire VDD range
D041 with Schmitt Trigger buffer 0.8 VDD —VDD V For entire VDD range
D042 MCLR 0.8 VDD —VDD V
D042A OSC1 (in XT and LP modes) 1.6V — VDD V(Note 1)
OSC1 (in HS mode) 0.7 VDD —VDD V
D043 OSC1 (in RC mode) 0.9 VDD —VDD V
Ports RC3 and RC4:
D044 with Schmitt Trigger buffer 0.7 VDD —VDD V For entire VDD range
D044A with SMBus 1.4 — 5.5 V For VDD = 4.5 to 5.5V
D070 IPURB PORTB Weak Pull-up
Current 50 250 400 AVDD = 5V, VPIN = VSS,
-40°C TO +85°C
* These parameters are characterized but not tested.
† D ata in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: In RC oscilla tor con figura tion, the OSC1/C LKI pin is a Schmitt Trigger inp ut. It is no t reco mmend ed tha t the
PIC16F7X7 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
2003-2013 Microchip Technology Inc. DS30498D-page 217
PIC16F7X7
IIL Input Leakage Current(2, 3)
D060 I/O ports — — 1AVSS VPIN VDD,
pin at high-impedance
D061 MCLR, RA4/T0CKI — — 5AVSS VPIN VDD
D063 OSC1 — — 5AVSS VPIN VDD,
XT, HS and LP oscillator
configuration
VOL Output Low Voltage
D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40C to +125C
D083 OSC2/CLKO
(RC oscillator configuration) —
—
—
—
0.6
0.6
V
V
IOL = 1.6 mA, VDD = 4.5V,
-40C to +125C
IOL = 1.2 mA, VDD = 4.5V,
-40C to +125C
VOH Output High Voltage
D090 I/O ports (Note 3) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V,
-40C to +125C
D092 OSC2/CLKO
(RC oscillator configuration) VDD – 0.7
VDD – 0.7
—
—
—
—
V
V
IOH = -1.3 mA, VDD = 4.5V,
-40C to +125C
IOH = -1.0 mA, VDD = 4.5V,
-40C to +125C
D150* VOD Open-Drain High Voltage — — 12 V RA4 pin
Capacitive Loading Specs
on Output Pins
D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes
when external clock is used
to drive OSC1
D101 CIO All I/O pins and OSC2
(in RC mode) — — 50 pF
D102 CBSCL, SDA in I2C™ mod e — — 400 pF
Program Flash Memory
D130 EPEndurance 100 1000 — E/W 25C at 5V
D131 VPR VDD for Read 2.0 — 5.5 V
18.4 DC Characteristics: PIC16F737/747/767/777 (In dustrial, Extended)
PIC16LF737/747/767/777 (Industrial) (Continued)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Operating voltage VDD range as described in
Section 18.1 “ DC Ch arac ter ist ics” .
Param
No. Sym Characteristic Min Typ† Max Units Conditions
* These parameters are characterized but not tested.
† D ata in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: In RC oscilla tor con figura tion, the OSC1/C LKI pin is a Schmitt Trigger inp ut. It is no t reco mmend ed tha t the
PIC16F7X7 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
PIC16F7X7
DS30498D-page 218 2003-2013 Microchip Technology Inc.
TABLE 18-1: COMPARA TOR SPECIFICATIONS
TABLE 18-2: VOLTAGE REFERENCE SPECIFICATIONS
Operating Condit ions : 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unl ess otherwise stated).
Param
No. Sym Characteristics Min Typ Max Units Comments
D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 mV
D301 VICM Input Common Mode Voltage* 0 — VDD – 1.5 V
D302 CMRR Common Mode Rejection Ratio* 55 — — dB
300
300A TRESP Response Time(1)* — 150 400
600 ns
ns PIC16F7X7
PIC16LF7X7
301 TMC2OV Comparato r Mode Change to
Output Valid* ——10s
* These parameters are characterized but not tested.
Note 1: Respo nse ti me m easure d wi th one comp ara tor inp ut at (V DD –1.5)/2, while t he other i nput tra nsitions from
VSS to VDD.
Operating Condit ions : 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless ot herwise stated).
Param
No. Sym Characteristics Min Typ Max Units Comments
D310 VRES Resolution VDD/24 — VDD/32 LSb
D311 VRAA Absolute Accuracy —
——
—1/4
1/2 LSb
LSb Low Range (CVRR = 1)
High Range (CVRR = 0)
D312 VRUR Unit Resistor Value (R)* — 2k —
310 TSET Settling Time(1)*— — 10 s
* These parameters are characterized but not tested.
Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transition from ‘0000’ to ‘1111’.
2003-2013 Microchip Technology Inc. DS30498D-page 219
PIC16F7X7
FIGURE 18-3: LOW-VOLTAGE DETECT CHARACTERISTICS
TABLE 18-3: LOW-VOLTAGE DETECT CHARACTERISTICS
VLVD
LVDIF
VDD
(LVDIF set by hardware)
(LVDIF can be
cleared in software)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
D420 VLVD LVD Voltage on VDD
Transition High-to-Low LVDL<3:0> = 0000 N/A N/A N/A V Reserved
LVDL<3:0> = 0001 1.96 2.06 2.16 V T 25C
LVDL<3:0> = 0010 2.16 2.27 2.38 V T 25C
LVDL<3:0> = 0011 2.35 2.47 2.59 V T 25C
LVDL<3:0> = 0100 2.43 2.56 2.69 V
LVDL<3:0> = 0101 2.64 2.78 2.92 V
LVDL<3:0> = 0110 2.75 2.89 3.03 V
LVDL<3:0> = 0111 2.95 3.1 3.26 V
LVDL<3:0> = 1000 3.24 3.41 3.58 V
LVDL<3:0> = 1001 3.43 3.61 3.79 V
LVDL<3:0> = 1010 3.53 3.72 3.91 V
LVDL<3:0> = 1011 3.72 3.92 4.12 V
LVDL<3:0> = 1100 3.92 4.13 4.34 V
LVDL<3:0> = 1101 4.11 4.33 4.55 V
LVDL<3:0> = 1110 4.41 4.64 4.87 V
Legend: Shading of rows is to assist in readability of the table.
† Production tested at TAMB = 25°C. Specificati ons over temperature limits ensured by characterization.
PIC16F7X7
DS30498D-page 220 2003-2013 Microchip Technology Inc.
18.5 Timing Parameter Symbology
The timing parameter symbols have been created
using one of the following formats:
FIGURE 18-4: LOA D CONDITIONS
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKO rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppe rcase letters and their meanings:
SFFall PPeriod
HHigh RRise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
I2C only
AA output ac cess High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO Stop condition
STA Start condition
VDD/2
CL
RL
pin pin
VSS VSS
CL
RL= 464
CL= 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as port s
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16F737/767 devices.
Load Condition 1 Load Condition 2
2003-2013 Microchip Technology Inc. DS30498D-page 221
PIC16F7X7
FIGURE 18-5: EXTER NAL CLOCK TIMING
TABLE 18-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
FOSC External CLKI Frequ ency
(Note 1) DC — 1 MHz XT Oscillator mode
DC — 20 MHz HS Oscillator mode
DC — 32 kHz LP Oscillator mode
Oscillator Frequency
(Note 1) DC — 4 MHz RC Osc illator mode
0.1 — 4 MHz XT Oscillator mode
4
5—
—20
200 MHz
kHz HS Oscillator mode
LP Oscillator mode
1T
OSC External CLKI Period
(Note 1) 1000 — — ns XT Oscillator mode
50 — — ns HS Oscillator mo de
5 — — ms LP Oscillator mode
Oscillator Period
(Note 1) 250 — — ns RC Oscillator mode
250 — 10,000 ns XT Oscillator mode
50 — 250 ns HS Oscillator mode
5 — — ms LP Oscillator mode
2T
CY Instruction Cycle Time
(Note 1) 200 TCY DC ns TCY = 4/FOSC
3T
OSL,
TOSHExternal Cloc k in (OSC1 )
High or Low Time 500 — — ns XT oscillator
2.5 — — ms LP oscillator
15 — — ns HS oscillator
4T
OSR,
TOSFExternal Cloc k in (OSC1 )
Rise or Fall Time — — 25 ns XT oscillator
— — 50 ns LP oscillator
— — 15 ns HS oscillator
† D ata in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type, under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time
limit is “DC” (no clock) for all devices.
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
PIC16F7X7
DS30498D-page 222 2003-2013 Microchip Technology Inc.
FIGURE 18-6: CLKO AND I/O TIMING
TABLE 18-5: CLKO AND I/O TIMING REQUIREMENTS
Note: Refer to Figure 18-4 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12 16
Old Va l u e New Value
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
10* TOSH2CKLOSC1 to CLKO — 75 200 ns (Note 1)
11* TOSH2CKHOSC1 to C LKO — 75 200 ns (Note 1)
12* TCKR CLKO Rise Time — 35 100 ns (Note 1)
13* TCKF CLKO Fall Time — 35 100 ns (Note 1)
14* TCKL2IOVCLKO to Port Out Valid — — 0.5 TCY + 20 ns (No te 1)
15* TIOV2CKH Por t In Valid before CLKO TOSC + 200 — — ns (Note 1)
16* TCKH2IOI Port In Hold after CLKO 0——ns(Note 1)
17* TOSH2IOVOSC1 (Q1 cycle) to Port Out Valid — 100 255 ns
18* TOSH2IOIOSC1 (Q2 cycle) to
Port Input Invalid (I/O in
hold time)
PIC16F7X7 100 — — ns
PIC16LF7X7 200 — — ns
19* TIOV2OSH Port Input Valid to OSC1 (I /O in setup time) 0 — — ns
20* TIOR Port Output Rise Time PIC16F7X7 — 10 40 ns
PIC16LF7X7 — — 145 ns
21* TIOF Port Output Fall Time PIC16F7X7 — 10 40 ns
PIC16LF7X7 — — 145 ns
22††* TINP INT pin High or Low Tim e TCY ——ns
23††* TRBP RB7:RB4 Change INT High or Low Time TCY ——ns
* T hes e parameters are characte rized but not tested.
† Dat a in “T yp” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measur ements are taken in RC mode, where CLKO output is 4 x TOSC.
2003-2013 Microchip Technology Inc. DS30498D-page 223
PIC16F7X7
FIGURE 18-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 18-8: BROWN-OUT RESET TIMING
TABLE 18-6: RESET, WATCHDOG TI MER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 18-4 for load conditions.
VDD VBOR
35
Param
No. Sym Characteristic Min Typ† Max Units Conditions
30 TMCLMCLR Pulse Width (low) 2 — — sVDD = 5V, -40°C to +85°C
31* TWDT Watchdog Timer Time-out Period
(no prescaler) 13.6 16 18.4 ms VDD = 5V, -40°C to +85°C
32 TOST Oscillation Start-up Timer Period — 1024 TOSC ——TOSC = OSC1 period
33* TPWRT Power-up Timer Period 61.2 72 82.8 ms VDD = 5V, -40°C to +85°C
34 TIOZ I/O High-Impedance from MCLR Low or
Watchdog Timer Reset ——2.1s
35 TBOR Brown-out Reset Pulse Width 100 — — sVDD VBOR (D005)
* T hes e parameters are characte rized but not tested.
† Dat a in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
PIC16F7X7
DS30498D-page 224 2003-2013 Microchip Technology Inc.
FIGURE 18-9: TIMER0 AND TIMER1 EX TERNAL CLOCK TIMINGS
TABLE 18-7: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
40* TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — — ns Must also meet
parameter 42
With prescaler 10 — — n s
41* TT0L T 0CK I Low Pulse Width No prescaler 0.5 TCY + 20 — — ns Must also meet
parameter 42
With prescaler 10 — — n s
42* TT0P T0CKI Period No prescaler TCY + 40 — — ns
With prescaler Great er of:
20 or TCY + 40
N
— — n s N = prescale
value (2, 4, ...,
256)
45* TT1H T1CKI High Time Synchronous, Prescaler = 1 0.5 TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler = 2, 4, 8 PIC16F7X7 15 — — ns
PIC16LF7X7 25 — — ns
Asynchronous PIC16F7X7 30 — — ns
PIC16LF7X7 50 — — ns
46* TT1L T 1CK I Low Time Synchronous, Pres caler = 1 0.5 TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler = 2, 4, 8 PIC16F7X7 15 — — ns
PIC16LF7X7 25 — — ns
Asynchronous PIC16F7X7 30 — — ns
PIC16LF7X7 50 — — ns
47* TT1P T1CKI Input
Period Synchronous PIC16F7X7 Greater of:
30 or TCY + 40
N
— — n s N = prescale
value (1, 2, 4, 8)
PIC16LF7X7 Greater of:
50 or TCY + 40
N
— — n s N = prescale
value (1, 2, 4, 8)
Asynchronous PIC16F7X7 60 — — ns
PIC16LF7X7 100 — — ns
FT1 Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz
48 TCKEZTMR1 Delay from External Clock Edge t o Timer Increment 2 TOSC —7 TOSC —
* T hes e parameters are characte rized but not tested.
† Dat a in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
Note: Refer to Figure 18-4 for load conditions.
46
47
45
48
41
42
40
RA4/T0CKI/C1OUT
RC0/T1OSO/T1CKI
TMR0 or TMR1
2003-2013 Microchip Technology Inc. DS30498D-page 225
PIC16F7X7
FIGURE 18-10: CAP TURE/ COMPARE/PWM TIMINGS (CCP1 AND CCP2)
TABLE 18-8: CAPTURE/COMP ARE/PWM REQUIREMENTS (ALL CCP MODULES)
Note: R efer to Figure 18-4 for load conditions.
and RC2/CCP1
(Capture Mode)
50 51
52
53 54
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
RC1/T1OSI/CCP2
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
50* TCCL CCP1, CCP2 and
CCP3 In put Low
Time
No prescaler 0.5 TCY + 20 — — ns
With pres caler PIC16F7X7 10 — — ns
PIC16LF7X7 20 — — ns
51* TCCH CCP1, CCP2 and
CCP3 In put H igh
Time
No prescaler 0.5 TCY + 20 — — ns
With pres caler PIC16F7X7 10 — — ns
PIC16LF7X7 20 — — ns
52* TCCP CCP1, C CP2 and CCP3 Input Period 3 TCY + 40
N— — ns N = prescale
value (1, 4 or 16)
53* TCCR CCP1, CCP2 and CCP3 Output
Rise T ime PIC16F7X7 — 10 25 ns
PIC16LF7X7 — 25 50 ns
54* TCCF CCP1, CCP2 and CCP3 Output
Fall Tim e PIC16F7X7 — 10 25 ns
PIC16LF7X7 — 25 45 ns
* These parameter s ar e characte rized but not test ed.
† Data in “T yp” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are no t teste d.
PIC16F7X7
DS30498D-page 226 2003-2013 Microchip Technology Inc.
FIGURE 18-11: PARALLEL SLAVE PORT TIMING (PIC16F747/777 DEVICES ONLY)
TABLE 18-9: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F747/777 DEVICES ONLY)
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
62 TDTV2WRH Data In Valid before WR or CS (set up time) 20
25 —
——
—ns
ns Extended range only
63* TWRH2DTIWR or CS to Data In Inv a lid
(hold time) PIC16F7X7 20 — — ns
PIC16LF7X7 35 — — ns
64 TRDL2DTVRD and CS to Data Out Valid —
——
—80
90 ns
ns Extended range only
65 TRDH2DTIRD or CS to Data Out Invalid 10 — 30 ns
* These parameter s ar e characte rized but not test ed.
† Data in “Typ” col um n is at 5V, 25°C unles s ot herwise stated . Th ese parameters are fo r de si gn guidance
only an d ar e not tested.
Note: Refer to Figure 18-4 for load conditions.
RE2/CS/AN7
RE0/RD/AN5
RE1/WR/AN6
RD7/PSP7:RD0/PSP0
62
63
64
65
2003-2013 Microchip Technology Inc. DS30498D-page 227
PIC16F7X7
FIGURE 18-12 : SPI MAST E R MODE TIMING (CKE = 0, SMP = 0)
FIGURE 18-13 : SPI MAST E R MODE TIMING (CKE = 1, SMP = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSb LSb
bit 6 - - - - - -1
LSb Inbit 6 - - - -1
Note: Refer to Figure 18-4 for load conditions.
MSb In
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
bit 6 - - - - - -1
LSb In
bit 6 - - - -1
LSb
Note: Refer to Figure 18-4 for load conditions.
MSb In
PIC16F7X7
DS30498D-page 228 2003-2013 Microchip Technology Inc.
FIGURE 18-14 : SPI SLAVE MODE TIMING (CKE = 0)
FIGURE 18-15 : SPI SLAVE MODE TIMING (CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
MSb LSb
bit 6 - - - - - -1
bit 6 - - - -1 LSb In
83
Note: Refer to Figure 18-4 for load conditions.
MSb In
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
74
75, 76
MSb bit 6 - - - - - -1 LSb
77
bit 6 - - - -1 LSb In
80
83
Note: Refer to Figure 18-4 for load conditions.
MSb In
2003-2013 Microchip Technology Inc. DS30498D-page 229
PIC16F7X7
TABLE 18-10: SPI MODE REQUIREMENTS
FIGURE 18-16 : I2C™ BUS START/STOP BITS TIM ING
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
70* TSSL2SCH,
TSSL2SCLSS to SCK or SCK Inpu t TCY ——ns
71* TSCH SCK Input High Time (Slave mode) TCY + 20 — — ns
72* TSCL SCK Input Low Time (Slave mode) TCY + 20 — — ns
73* TDIV2SCH,
TDIV2SCLSetup Time of SDI Data Input to SCK Edge 100 — — ns
74* TSCH2DIL,
TSCL2DILHold Time of SDI Data Input to SCK Edge 100 — — ns
75* TDOR SDO Data Output Rise Time PIC16F7X7
PIC16LF7X7 —
—10
25 25
50 ns
ns
76* TDOF SDO Data Output Fall Time — 10 25 ns
77* TSSH2DOZSS to SDO Output High-Impedance 10 — 50 ns
78* TSCR SCK Output Rise Time
(Master mode) PIC16F7X7
PIC16LF7X7 —
—10
25 25
50 ns
ns
79* TSCF SCK Output Fall Time (Master mode) — 10 25 ns
80* TSCH2DOV,
TSCL2DOVSDO Data Output Valid after
SCK Edge PIC16F7X7
PIC16LF7X7 —
——
—50
145 ns
ns
81* TDOV2SCH,
TDOV2SCLSDO Data Output Setup to SCK Edge TCY ——ns
82* TSSL2DOV SDO Data Output Valid after SS Edge — — 50 ns
83* TSCH2SSH,
TSCL2SSHSS after SCK Edge 1.5 TCY + 40 — — ns
* These parameters are characterized but not tested.
† D ata in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note: Refer to Figure 18-4 for load conditions.
91
92
93
SCL
SDA
Start
Condition Stop
Condition
90
PIC16F7X7
DS30498D-page 230 2003-2013 Microchip Technology Inc.
TABLE 18-11: I2C™ BUS START/STOP BITS REQUIREMENTS
FIGURE 18-17 : I2C™ BUS DATA TIMING
Param
No. Symbol Characteristic Min Typ Max Units Conditions
90* TSU:STA Start Condition 100 kHz mode 4700 — — ns Only relevant for Repeated
St art condition
Setup Time 400 kHz mode 600 — —
91* THD:STA Start Condition 100 kHz mode 4000 — — ns After this period, the first clock
pulse is genera ted
Hold Time 400 kHz mode 600 — —
92* TSU:STO Stop Condition 100 kHz mode 4700 — — ns
Setup Time 400 kHz mode 600 — —
93 THD:STO Stop Condition 100 kHz mode 4000 — — ns
Hold Time 400 kHz mode 600 — —
* These parameters are characterized but not tested.
Note: Ref er to Figure 18-4 for load conditions.
90
91 92
100 101
103
106 107
109 110
102
SCL
SDA
In
SDA
Out
109
2003-2013 Microchip Technology Inc. DS30498D-page 231
PIC16F7X7
TABLE 18-12: I2C™ BUS DATA REQUIREMENTS
Param.
No. Symbol Characteristic Min Max Units Conditions
100* THIGH Clock High Time 100 kHz mode 4.0 — s D evice must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5 TCY —
101* TLOW Clock Low Time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5 TCY —
102* TRSDA and SCL Rise
Time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from
10-400 pF
103* TFSDA and SCL Fall
Time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from
10-400 pF
90* TSU:STA Start Condition
Setup Time 100 kHz mode 4.7 — s Only relevant for Repeated
Start condition
400 kHz mode 0.6 — s
91* THD:STA Start Condition Hold
Time 100 kHz mode 4.0 — s After this period, the first
clock pulse is generated
400 kHz mode 0.6 — s
106* THD:DAT Data Input Hold
Time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
107* TSU:DAT Data Input Setup
Time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92* TSU:STO Stop Condition
Setup Time 100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
109* TAA Output Valid from
Clock 100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
110* TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — s
CBBus Capacitive Loading — 400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system but
the requireme nt, TSU:DAT 250 n s, mu st the n be m et. Thi s wi ll aut omatic ally be the ca se if the dev ice does
not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns
(according to the standard mode I2C bus specification), before the SCL line is released.
PIC16F7X7
DS30498D-page 232 2003-2013 Microchip Technology Inc.
FIGURE 18-18: AUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 18-13: AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 18-19: AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 18-14: AUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Note: Refer to Figure 18-4 for load conditions.
121 121
122
RC6/TX/CK
RC7/RX/DT
pin
pin
120
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
120 TCKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid PIC16F7X7 — — 80 ns
PIC16LF7X7 — — 100 ns
121 TCKRF Clock Out Rise Time and Fall Time
(Master mode) PIC16F7X7 — — 45 ns
PIC16LF7X7 — — 50 ns
122 TDTRF Data Out Rise Time and Fall Time PIC16F7X7 — — 45 ns
PIC16LF7X7 — — 50 ns
† D ata in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note: Refer to Figure 18-4 for load conditions.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
125 TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Setup before CK (DT setup time) 15 — — ns
126 TCKL2DTL Data Hold after CK (DT hold time) 15 — — ns
† D ata in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested .
2003-2013 Microchip Technology Inc. DS30498D-page 233
PIC16F7X7
TABLE 18-15: A/D CONVERTER CHARACTERISTICS: PIC16F7X7 (INDUSTRIAL, EXTENDED)
PIC16LF7X7 (INDUSTRIAL)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
A01 NRResolution — — 10 bits bit VREF = VDD = 5.12V,
VSS VAIN VREF
A03 EIL Integral Linearity Error — — <± 1 LSb VREF = VDD = 5.12V,
VSS VAIN VREF
A04 EDL Diff erentia l Linearity Error — — <±1 LSb VREF = VDD = 5.12V,
VSS VAIN VREF
A06 EOFF Offse t Error — — <±2 LSb VREF = VDD = 5.12V,
VSS VAIN VREF
A07 EGN Gain Error — — <±1 LSb VREF = VDD = 5.12V,
VSS VAIN VREF
A10 — Monotonicity — guaranteed(3) ——VSS VAIN VREF
A20 VREF Reference Voltage
(VREF+ – VREF-) 2.0 — VDD + 0.3 V
A21 VREF+ Ref erence Voltage High AVDD – 2.5V — AVDD + 0.3V V
A22 VREF- Reference Voltage Low AVSS – 0.3V — VREF+ – 2.0V V
A25 VAIN Anal og Input Voltage VSS – 0.3V — VREF + 0.3V V
A30 ZAIN Recommended Impedance of
Analog V oltage Source ——2.5k(Note 4)
A40 IAD A/D Conversion
Current (VDD)PIC16F7X7 — 220 — A Average current
consumption when A/D is on
(Not e 1)
PIC16LF7X7 — 90 — A
A50 IREF VREF Input Current (Note 2) —
—
—
—
5
150
A
A
During VAIN acquisition.
Based on dif ferential of VHOLD
to VAIN to charge CHOLD,
see Section 12.1 “A/D
Acquisition Requirements”.
During A/D conversion cycle
* T hes e parameters are characte rized but not tested.
† Dat a in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current specification
includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
4: Maximum allowed impedance for analog voltage source is 10 kThis requires higher acquisition time.
PIC16F7X7
DS30498D-page 234 2003-2013 Microchip Technology Inc.
FIGURE 18-20: A /D CONVERSION TIMING
TABLE 18-16: A/D CONVERSION REQUIREMENTS
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
(TOSC/2)(1)
987 210
Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
1 TCY
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
130 TAD A/D Clock Period PIC16F7X7 1.6 — — sTOSC based, VREF 3.0V
PIC16LF7X7 3.0 — — sT
OSC based, VREF 2.0V
PIC16F7X7 2.0 4.0 6.0 s A/D RC mode
PIC16LF7X7 3.0 6.0 9.0 s A/D RC mode
131 TCNV Conversion T ime (not including S/H time)
(Note 1) —12TAD
132 TACQ Acquisition Time (Note 2)
10*
40
—
—
—
s
s The minimum time is the
amplifier settling time. This may
be used if the “new” input
voltage has not changed by
more than 1 LSb (i.e., 5.0 mV @
5.12V) from the last sampled
voltage (as stated on CHOLD).
134 TGO Q4 to A/D Clock Start — TOSC/2 § — — I f the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
* T hes e parameters are characte rized but not tested.
† Dat a in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
§ This spec ification ensured by design.
Note 1: ADRE S register may be read on the following TCY cycle.
2: See Section 12.1 “A/D Acquisition Requirements” for minimum conditions.
2003-2013 Microchip Technology Inc. DS30498D-page 235
PIC16F7X7
19.0 DC AND AC CHARACTERIS TICS GRAPHS AND TABLES
“T ypical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean + 3) or (mean – 3)
respectively, w here is a st anda rd deviation, ov er the whol e temperature range .
FIGURE 19-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
FIGURE 19-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
Note: The g r ap hs and t ables provided following this no te a re a statistica l s um ma ry bas ed on a limited num ber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
0
1
2
3
4
5
6
7
4 6 8 10 12 14 16 18 20
FOSC (MHz)
IDD (mA)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0
1
2
3
4
5
6
7
8
4 6 8 10 12 14 16 18 20
FOSC (MHz)
IDD (mA)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F7X7
DS30498D-page 236 2003-2013 Microchip Technology Inc.
FIGURE 19-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
FIGURE 19-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0 500 1000 1500 2000 2500 3000 3500 4000
FOSC (MHz)
IDD (mA)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
0 500 1000 1500 2000 2500 3000 3500 4000
FOSC (MHz)
IDD (mA)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2003-2013 Microchip Technology Inc. DS30498D-page 237
PIC16F7X7
FIGURE 19-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE)
FIGURE 19-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)
0
10
20
30
40
50
60
70
20 30 40 50 60 70 80 90 100
FOSC (kHz)
IDD (A)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0
20
40
60
80
100
120
20 30 40 50 60 70 80 90 100
FOSC (kHz)
IDD (A)
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F7X7
DS30498D-page 238 2003-2013 Microchip Technology Inc.
FIGURE 19-7: TYPICAL IDD vs. VDD, -40C TO + 125C, 1 MHz TO 8 MHz
(RC_RUN MODE, ALL PERIPHERALS DISABLED)
FIGURE 19-8: MAXIMUM IDD vs. VDD, -40C TO +125C, 1 MHz TO 8 MHz
(RC_RUN MODE, ALL PERIPHERALS DISABLED)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.02.03.04.05.06.07.08.0
FOSC (MHz)
IDD (mA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1.02.03.04.05.06.07.08.0
FOSC (MHz)
IDD (mA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2003-2013 Microchip Technology Inc. DS30498D-page 239
PIC16F7X7
FIGURE 19-9: IDD vs. VDD, SEC_RUN MODE, -10C TO +125C, 32.768 kHz
(XTAL 2 x 22 pF, ALL PERIPHERALS DISABLED)
FIGURE 19-10 : IPD vs. VDD, -40C TO +125C (SLEEP MODE, ALL PERIPHERALS DISABLED)
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (A)
Max (+70°C)
Typ (+25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.001
0.01
0.1
1
10
100
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Typ (25°C)
Max (85°C)
Max (125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F7X7
DS30498D-page 240 2003-2013 Microchip Technology Inc.
FI GU R E 19 -11: AVERAGE FOSC vs. VDD FOR V ARIOUS VALUES OF R (RC MODE, C = 20 pF, +25C)
FIGURE 19-12: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 100 pF, +25C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Freq (MHz)
100 k O hm
10 kOhm
5.1 kO hm
Oper ation above 4 MHz is not r ecommend ed
0.0
0.5
1.0
1.5
2.0
2.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Freq (MHz)
100 k O hm
10 kOhm
5.1 kOhm
3.3 kOhm
2003-2013 Microchip Technology Inc. DS30498D-page 241
PIC16F7X7
FIGURE 19-13: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 300 pF, +25C)
FIGURE 19-14 : IPD TIMER1 OSCILLATOR, -10°C TO +70°C
(SLEEP MODE, TMR1 COUNTER DISABLED)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Freq (MHz)
100 kOhm
10 kOhm
5.1 kOhm
3.3 kOhm
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
2.02.53.03.54.04.55.05.5
VDD (V)
IPD (A)
Typ (+25°C)
Max (-10°C to +70°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F7X7
DS30498D-page 242 2003-2013 Microchip Technology Inc.
FIGURE 19-15 : IPD WDT, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED)
FIGURE 19-16 : IPD LVD vs. VDD (SLEEP MODE, LVD = 2.00V-2.12V)
0
2
4
6
8
10
12
14
16
18
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IWDT (A)
Max
(
-40°C to +125°C
)
Max (-40°C to +85°C)
Typ (25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0
5
10
15
20
25
30
35
40
45
50
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Typ ( +25°C)
Max (+85°C)
Max (+125°C)
Low-Voltage Detection Range
Normal Op erating Range
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2003-2013 Microchip Technology Inc. DS30498D-page 243
PIC16F7X7
FIGURE 19-17 : IPD BOR vs. VDD, -40°C TO +125°C
(SLEEP MODE, BOR ENABLED AT 2.00V-2.16V)
FIGURE 19-18 : IPD A/D, -40C TO +125C (SLEEP MODE, A/D ENABLED – NOT CONVERTING)
0
5
10
15
20
25
30
35
40
2.02.53.03.54.04.55.05.5
VDD (V)
IPD (A)
Max (+125°C)
Typ (+25°C)
Device may be in Reset
Device is Operating
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0
2
4
6
8
10
12
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Max
(
-40°C to +125°C
)
Max
(-40°C to +85°C)
Typ (+25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F7X7
DS30498D-page 244 2003-2013 Microchip Technology Inc.
FIGURE 19-19: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C)
FIGURE 19-20: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0 5 10 15 20 25
IOH (-mA)
VOH (V)
Max
Ty p ( 25 ° C)
Min
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-4 0° C to +125 °C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0 5 10 15 20 25
IOH (-mA)
VOH (V)
Max
Typ (25°C )
Min
Typical: statistical mean @ 25°C
Maximu m: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2003-2013 Microchip Technology Inc. DS30498D-page 245
PIC16F7X7
FIGURE 19-21: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C)
FIGURE 19-22: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25
IOL (-mA)
VOL (V)
Max (125°C)
Max ( 85°C)
Ty p ( 25 ° C)
Min (-40°C)
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25
IOL (-mA)
VOL (V)
Max (125°C)
Max (85°C)
Typ (25°C )
Min (-40°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
PIC16F7X7
DS30498D-page 246 2003-2013 Microchip Technology Inc.
FIGURE 19-23: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40C TO +125C)
FIGURE 19-24: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C)
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
VTH Max (-40°C)
VTH Min (125°C)
VTH Typ (25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
VIH Max (125°C)
VIH Min (-40°C)
VIL Max (-40°C)
VIL Min (125°C)
Typical: statisti cal mean @ 25°C
Maximu m: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2003-2013 Microchip Technology Inc. DS30498D-page 247
PIC16F7X7
FIGURE 19-25: MINIMUM AND MAXIMUM VIN vs. VDD (I2C™ INPUT, -40C TO +125C)
FIGURE 19-26: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
VIH Max
VIH Min
VILMax
VIL Min
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
VIL Max
0
0.5
1
1.5
2
2.5
3
3.5
4
22.533.544.555.5
VDD and VREFH (V)
Differential or Integral Nonlinearity (LSB)
-40C
25C
85C
125C
-40°C
+25°C
+85°C
+125°C
PIC16F7X7
DS30498D-page 248 2003-2013 Microchip Technology Inc.
FIGURE 19-27: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40C TO +125C)
0
0.5
1
1.5
2
2.5
3
22.533.544.555.5
VREFH (V)
Differential or Integral Nonlinearilty (LSB)
Max (-40C to 125C)
Typ (25C)
Typ (+25°C)
Max (-40°C to +125°C)
2003-2013 Microchip Technology Inc. DS30498D-page 249
PIC16F7X7
20.0 PACKAGING INFORMATION
20.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the ev ent the ful l Micro chip p art num ber can not be marke d on one li ne, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
28-Lead SPDIP (.300”) Example
28-Lead SOIC (7.50 mm) Example
YYWWNNN
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
28-Lea d SSOP (5.30 mm) Example
28-Lead QFN (6x6 mm) Example
XXXXXXXX
XXXXXXXX
YYWWNNN
PIN 1 PIN 1
PIC16F737-I/SP
0410017
PIC16F737-I/SO
0410017
PIC16F737
-I/SS
0410017
16F737
-I/ML
0410017
3
e
3
e
3
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3
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PIC16F7X7
DS30498D-page 250 2003-2013 Microchip Technology Inc.
Package Marking Information (Continued)
40-Lead PDIP (600 mil) Example
XXXXXXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
44-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX
XXXXXXXXXX
44-Lea d QFN (8x8x0.9 mm) Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
XXXXXXXXXXX
PIN 1 PIN 1
PIC16F777-I/P
0410017
PIC16F777
-I/PT
0410017
PIC16F777
-I/ML
0410017
3
e
3
e
3
e
2003-2013 Microchip Technology Inc. DS30498D-page 251
PIC16F7X7
20.2 Package Details
The follow ing sections give the technical details of the
packages.
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
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2003-2013 Microchip Technology Inc. DS30498D-page 253
PIC16F7X7
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DS30498D-page 254 2003-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2013 Microchip Technology Inc. DS30498D-page 255
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DS30498D-page 256 2003-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2013 Microchip Technology Inc. DS30498D-page 257
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2003-2013 Microchip Technology Inc. DS30498D-page 261
PIC16F7X7
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16F7X7
DS30498D-page 262 2003-2013 Microchip Technology Inc.
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2003-2013 Microchip Technology Inc. DS30498D-page 263
PIC16F7X7
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PIC16F7X7
DS30498D-page 264 2003-2013 Microchip Technology Inc.
NOTES:
2003-2013 Microchip Technology Inc. DS30498D-page 265
PIC16F7X7
APPENDIX A: RE VISION HISTORY
Revision A (June 2003)
This is a new data sheet. However, these devices are
similar to the PIC16C7X devices found in the
PIC16C7X Data Sheet (DS30390) or the PIC16F87X
devices (DS30292).
Revision B (November 2003)
This revi si on includes updates to th e E lec tric al Specifi-
cations in Section 18.0 “Electrical Characteristics”
and minor corrections to the data sheet text.
Revision C (October 2004)
This revision includes the DC and AC Characteristics
Graphs and Tables. The Electrical Specifications in
Section 19.0 “DC and AC Characteristics Graphs
and Tables” have been updated and there have been
minor corrections to the data sheet text.
Revision D (January 2013)
Added a note to each package drawing.
APPENDIX B: DEVICE
DIFFERENCES
The differences betwe en th e dev ic es in th is dat a she et
are listed in Table B-1.
TABLE B-1: DEVICE DIFFERENCES
Difference PIC16F737 PIC16F747 PIC16F767 PIC16F777
Flash Program M emory
(14-bit words ) 4K 4K 8K 8K
Data Memory (bytes) 368 368 368 368
I/O Ports 3 5 3 5
A/D 11 channels,
10 bits 14 channels,
10 bits 11 channels,
10 b i ts 14 channels,
10 bi ts
Parallel Slave Port No Yes No Yes
Interrupt Sources 16171617
Packages 28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin QFN
44-pin TQFP
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-p in PDIP
44-pin QFN
44-pin TQFP
PIC16F7X7
DS30498D-page 266 2003-2013 Microchip Technology Inc.
APPENDIX C: CONVERSION
CONSIDERATIONS
Considerations for converting from previous versions
of de vices to the one s listed in th is dat a sheet are liste d
in Table C-1.
TABLE C-1: CONVERSION CONSIDERATIONS
Characteristic PIC16C7X PIC16F87X PIC16F7X7
Pins 28/40 28/40 28/40
Timers 3 3 3
Interrupts 11 or 12 13 or 14 16 or 17
Communication PSP, USART, SSP
(SPI, I2C™ Master/ Slave) PSP, AUSART, MSSP
(SPI, I2C Master/Slave) PSP, AUSART, MSSP
(SPI, I2C Master/Slave)
Frequency 20 MHz 20 MHz 20 MHz
A/D 8-bit 10-bit 10-bit
CCP 2 2 3
Prog ram Memory 4K, 8K EPROM 4K, 8K Fl ash
(1,000 E/W cycles) 4K, 8K Flash
(100 E/W cycles)
RAM 192, 368 bytes 192, 368 bytes 368 bytes
EEPROM Data None 128, 256 bytes None
Other — In-Circuit Debugge r,
Low-Voltage Programming In-Circuit Debugger
2003-2013 Microchip Technology Inc. DS30498D-page 267
PIC16F7X7
INDEX
A
A/D A/D Converter Inte rrupt, Conf ig u r in g ...................... ..155
Acquisition Requirements ....... ......... .... .... .... ........... ..156
ADRESH Register.....................................................154
Analog Port Pins.........................................................68
Analog-to-Digital Converter.......................................151
Associ a te d Re g i sters.... ............................................160
Automatic Acquisition Time.......................................157
Calculating Acquisition Time.....................................156
Configuring Analog Port Pins....................................158
Configuring the Module.............................................155
Conversi o n Clo ck......................................................157
Conversi o n Re q uirements .. ......................................234
Conversion Status (GO/DONE Bit)...... ........... ..........154
Conversions..............................................................159
Delays.......................................................................156
Effects of a Reset......................................................160
Internal Sampling Switch (Rss) Impedance..............156
Operation During Sleep ............................................160
Operation in Power-Managed Modes.......................158
Source Impedance..................................... ........... ....156
Time Dela ys..............................................................156
Use of the CCP Trigger.............................................160
Absolute Maximum Ratings ..............................................205
ACKSTAT .........................................................................123
ACKSTAT Status Flag......................................................123
ADCON0 Register
GO/DONE Bit ............................................................154
Addressable Universal Synchronous Asynchronous
Receiver Transmitter. See AU SART
ADRESL Register.............................................................154
Application Notes
AN546 (Using the Analog-to-Digital (A/D)
Converter).........................................................151
AN552 (Implementing Wake-up on Key Stroke).........56
AN556 (Implementing a Table Read) .........................29
AN607 (Power-up Trouble Shooting)........................173
Assembler
MPASM Assembler...................................................202
AUSART
Address Detect Enable (ADDEN Bit)........................134
Addressable Universal Synchronous
Asynchronous Receiver Transmitter.................133
Asynchronous
Receiver
(9-Bit Mode)..............................................142
Asynchronous Mode.................................................138
Receiver............................................................140
Transmitter........................................................138
Asynchronous R eceive with Address Detec t.
SeeAsynchronous Receive (9-bit Mode).
Asynchronous Reception
Associated Registers................................141, 143
Setup ................................................................141
Asynchronous R eception with Address
Detect Setup.....................................................142
Asynchronous Transmission
Associ a te d Re g i sters...... ..................................139
Setup ................................................................139
Baud Rate Generator (BRG) .....................................135
Associ a te d Re g i sters...... ..................................135
Baud Rate Formula...........................................135
Baud Rates, Asynchronous Mode
(BRGH = 0)............................................... 136
Baud Rates, Asynchronous Mode
(BRGH = 1)............................................... 136
High Baud Rate Select (BRGH Bit).................. 133
INTRC Baud Rates, Asynchronous Mode
(BRGH = 0)............................................... 137
INTRC Baud Rates, Asynchronous Mode
(BRGH = 1)............................................... 137
Sampling .......................................................... 135
Clock Source Select (CSRC Bit) .............................. 133
Continuous Receive Enable (CREN Bit) .................. 134
Framing Er ror (FERR Bit)........ ................................. 134
Overrun Error (OERR Bit)......................................... 134
Receive Data, 9th Bit (RX9D Bit).............................. 134
Receive Enable, 9-Bit (RX9 Bit) ...... .... ............. .... .... 134
Serial Port Enable (SPEN Bit) .......................... 133, 134
Single Receive Enable (SREN Bit)........................... 134
Synchronous Master Mode....................................... 144
Reception ......................................................... 146
Transmission.................................................... 144
Synchronous Master Reception
Associ a te d Re gisters.................................... .... 146
Setup................................................................ 146
Synchronous Master Transmission
Associ a te d Re gisters.................................... .... 145
Setup................................................................ 144
Synchronous Slave Mode................................. .... .... 148
Reception ......................................................... 149
Transmit............................................................ 148
Synchronous Slave Reception
Associ a te d Re gisters.................................... .... 149
Setup................................................................ 149
Synchronous Slave Transmission
Associ a te d Re gisters.................................... .... 148
Setup................................................................ 148
Transmit Data, 9th Bit (TX9D).................................. 133
Transmit Enable (TXEN Bit)..................................... 133
Transmit Enable, 9-Bit (TX9 Bit)............................... 133
Transmit Shift Register Status (TRMT Bit) ............... 133
B
Bank i n g , D a ta M e mory.. .. ...... .. ........... .. ...... .. ........... .. ......... 15
Baud Rate Generator ....................................................... 119
BF..................................................................................... 123
BF Status Flag.................................................................. 123
Block Diagrams
A/D............................................................................ 155
Analog Input Model........................................... 156, 165
AUSART Receive............................................. 140, 142
AUSA R T Transm i t..... ...... . .. ...... .. ................. .. ........... 138
Baud Rate Generator ............................................... 119
Capture Mode Operation............... .... .. ....... .... .. .. .... .. .. 89
Comparator I/O Operating Modes............................ 162
Comparator Output................................................... 164
Comparator Voltage Reference... .. .... ....... .... .. .... .... .. 168
Compare..................................................................... 89
Fail-Safe Clock Monitor............................................ 189
In-Circuit Serial Programming Connections ............. 192
Interrupt Logic ........................................................... 184
Low-Voltage Detect (LVD)........................................ 175
Low-Voltage Detect (LVD) with External Input ......... 175
Low-Voltage Detect Characteristics ......................... 219
MSSP (I2C Master Mode)......................................... 117
PIC16F7X7
DS30498D-page 268 2003-2013 Microchip Technology Inc.
MSSP (I2C Mode) ...... ....... .. .. .... .. .. .. ....... .. .. .... .. .. .. .....102
MSSP (SPI Mode).......................................................93
On-Chip Reset Circuit....... ........................................172
OSC1/CLKI/RA7 Pin...................................................54
OSC2/CLKO/RA6 Pin.................................................53
PIC16F737 and PIC16F767..........................................6
PIC16F747 and PIC16F777..........................................7
PORTC (Peripheral Output Override)
RC<2:0>, RC<7:5> Pins........................ .............65
PORTC (Peripheral Output Override)
RC<4:3> Pins......................................................65
PORTD (In I/O Port Mode)..........................................67
PORTD and PORTE (Parallel Slave Port)........... .......70
PORTE (In I/O Port Mode)................ ..........................68
PWM Mode.................................................................91
RA0/AN0: RA1 /AN1 Pins... ..........................................50
RA2/AN2/VREF-/CVREF Pin.........................................51
RA3/AN3/VREF+ Pin........ ............................................50
RA4/T0CKI/C1OUT Pin ..............................................51
RA5/AN4/LVDIN/SS/C2OUT Pin ................................52
RB0/INT/AN12 Pin......................................................57
RB1/AN10 Pin........ .....................................................57
RB2/AN8 Pi n...............................................................58
RB3/CCP2/ AN9 Pin ...... ..............................................59
RB4/AN11 Pin........ .....................................................60
RB5/AN13/CCP3 Pin........ ..........................................61
RB6/PGC Pin..............................................................62
RB7/PGD Pin..............................................................63
Recommended MCLR Circuit....... ............................173
Syste m Cl o ck....... .......................................................39
Timer0/WDT Prescaler ...............................................73
Timer1.........................................................................79
Timer2.........................................................................85
Watchdog Timer (WDT)................ ........... .... .... .... .....186
BOR. See Brown-out Reset.
BRG. See Baud Rate Generator.
BRGH Bit...........................................................................135
Brown-out Reset (BOR) ....................169, 172, 173, 179, 180
C
C Compilers
MPLAB C18..... .........................................................202
Capture/Compare/PWM (CCP)...........................................87
Capture Mod e.... .........................................................89
CCP Pin Configuration........................................89
Prescaler.............................................................89
Compare Mode.... .......................................................89
CCP Pin Configuration........................................90
Softwa re In terrupt Mode .....................................90
Special Event Trigger..........................................90
Special Event Trigger Output..............................90
Timer1 Mode Selection.......................................90
Interaction of Two CCP Modules ................................87
PWM Mode.................................................................91
Duty Cycle...........................................................91
Example Frequencies and Resolutions ..............92
Period..................................................................91
Setup for Operation... ..........................................92
Registers Associated with Capture, Compare and
Timer1.................................................................90
Registers Associated with PWM and Timer2..............92
Timer Resources.........................................................87
CCP1 Module......................................................................87
CCP2 Module......................................................................87
CCP3 Module......................................................................87
CCPR1H Registe r.... ...........................................................87
CCPR1L Regist e r......... ...................................................... 87
CCPR2H Registe r.... ............................................ ............... 87
CCPR2L Regist e r......... ...................................................... 87
CCPR3H Registe r.... ............................................ ............... 87
CCPR3L Regist e r......... ...................................................... 87
CCPxM<3:0> Bits .. ............................................................. 88
CCPxX and CCPxY Bits ..................................................... 88
Cloc k So urces. ............ . .................. .. . ...... .. ............ . ............ . 37
Selection Using OSCCON Register............................ 37
Clock Switching .................................................................. 37
Modes (ta b l e).............................................................. 47
Transition and the Watchdog Timer............................ 38
Code Examples
Call of a Subroutine in Page 1 from Page 0 ............... 29
Changing Between Capture Prescalers...................... 89
Changing Prescaler Assignment from WDT
to Timer0 ............................................................ 76
Flash Program Read................................................... 32
Implementing a Real-Time Clock Using a
Time r 1 In t e r ru p t Servi c e... .. ............ .. ..... .. ...... .. ... 82
Indir ect Addressi n g.. ............ .. ..... .. ............ .. ........... .. ... 3 0
Initializing PORTA....................................................... 49
Loading the SSPBUF (SSPSR ) Register.................... 96
Reading a 16-bit Free Running Timer ...................... .. 80
Saving Status and W Registers in RAM................... 185
Writing a 16-bit Free Running Timer........................... 80
Code Protection........................................................ 169, 192
Comparator Module................................... .... .. .. ....... .... .. .. 161
Analog Input Connection Considerations ................. 165
Associated Registers................................................ 165
Configuration ............................................................ 162
Effects of a Reset ..................................................... 165
Interrupts .................................................................. 164
Operation.................................................................. 163
Operation During Sleep............................................ 165
Outputs..................................................................... 163
Reference................................................................. 163
External Signal ................................................. 163
Internal Signal................................................... 163
Response Time........................................ ............. ....163
Comparat o r Spe cifications................. .................. ............. 218
Comparator Voltage Reference........................................ 167
Associated Registers................................................ 168
Computed GOTO................................................................ 29
Configuration Bits ................................................. ............ 169
Conversion Considerations............................................... 266
Crystal and Ceramic Resonators........................................ 33
Customer Change Notification Service............................. 275
Customer Notification Service ............. ......................... .... 275
Custome r Support............................................................. 275
D
Data Memory ...................................................................... 15
Bank Select (RP1:RP0 Bits)....................................... 15
General Purpose Registers ........................................ 15
Map for PIC16F737 and PIC16F767.......................... 16
Map for PIC16F747 and PIC16F777.......................... 17
Spec i a l Function Re g i s t e r s....... .. ...... .. ...... .. ..... .. ...... .. . 18
DC and AC Characteristics
Graphs and Tables................................................... 235
DC Characteristics.................................................... 207, 216
Internal RC Accuracy ................................................ 215
Power-Down and Supply Current............................. 208
Development Support....................................................... 201
2003-2013 Microchip Technology Inc. DS30498D-page 269
PIC16F7X7
Device Differences............................................................265
Device Overview...................................................................5
Features........................................................................5
Direct Add ressing....... .........................................................30
E
Electrical Characteristics...................................................205
Errata ....................................................................................4
External Clock Input............................................................34
F
Fail-Safe Clock Monitor.............................................169, 189
FSR Register ......................................................................30
I
I/O Ports........................................................... ...................49
I2 Mode
Operation..................................................................106
I2 Slave Mode
Clock Stretching, 10-bit Receive
Mode (SEN = 1)................................................112
Clock Stretching, 10-bit Transmit Mode....................112
Clock Stretching, 7-bit Receive Mode (SEN = 1)......112
Clock Stretching, 7-bit Transmit Mode......................112
I2C Master Mode...............................................................117
Clock Arbitration........................................................120
Operation..................................................................118
Reception..................................................................123
Repeated Start Condition Timing............................ ..122
Start Condition Timing ...... .... ........... ...... .... ........... ....121
Transmission.............................................................123
I2C Mode...........................................................................102
ACK Pulse........................... .... ....... .... .. .... .... .....106, 107
Acknowledge Sequence Timing................................126
Baud Rate Generator................................................119
Bus Collision
Repeated Start Condition .............. .. .... ..... .... .. ..130
Start Condition........................... .... ...... ........... ..128
Stop Condition........ ..........................................131
Clock Synch r o n i zation and the CKP Bit..... ...............113
Effect of a Reset .......................................................127
General Call Address Support.. ................................116
Multi-Master Communication, Bus Collision
and Arbitration .. .... .. .. .. .. .. ....... .. .. .. .. .... .. ..... .. .. ....127
Multi-Master Mode....................................................127
Read/Write Bit Information (R/W Bit)........................107
Registers...................................................................102
Serial Clock (RC3/SCK/SCL)....................................107
Sleep Operation... .....................................................127
Stop Condition Timing...............................................126
I2C Slave Mode.................................................................106
Addressing................................................................106
Clock Stretching ........................................................112
Reception..................................................................107
Transmission.............................................................107
ID Locations..............................................................169, 192
In-Circuit Debugger...........................................................192
In-Circuit Serial Programming...........................................169
In-Circuit Serial Programming (ICSP)...............................192
INDF Register.....................................................................30
Indirect Addressing.............................................................30
FSR Register ..............................................................15
Instruction Set
Firm w a r e Instr u c ti o n s .... .. ..... .. ...... .. ........... .. ...... .. ..... 193
General Fo rmat ...... .................................................. 193
Opcode Field Descriptions ....................................... 193
Read-Modify-Write Operations................................. 193
ADDLW..................................................................... 195
ADDWF .................................................................... 195
ANDLW..................................................................... 195
ANDWF .................................................................... 195
BCF .......................................................................... 195
BSF........................................................................... 195
BTFSC...................................................................... 195
BTFSS...................................................................... 195
CALL......................................................................... 196
CLRF........................................................................ 196
CLRW....................................................................... 196
CLRWDT.................................................................. 196
COMF....................................................................... 196
DECF........................................................................ 196
DECFSZ................................................................... 197
GOTO....................................................................... 197
INCF......................................................................... 197
INCFSZ..................................................................... 197
IORLW...................................................................... 197
IORWF...................................................................... 197
MOVF....................................................................... 198
MOVLW.................................................................... 198
MOVWF.................................................................... 198
NOP.......................................................................... 198
RETFIE..................................................................... 198
RETLW..................................................................... 198
RETURN................................................................... 199
RLF........................................................................... 199
RRF.......................................................................... 199
SLEEP...................................................................... 199
SUBLW..................................................................... 199
SUBWF..................................................................... 199
SWAPF..................................................................... 200
XORLW .................................................................... 200
XORWF.................................................................... 200
Summary Table ........................................................ 194
INT Interrup t ( R B0/INT). See Interrupt Sources.
INTCON Register
GIE Bi t....... ................. ................. ........... ................ .... 23
INT0IE Bit................................................................... 23
INT0IF Bit ................................................................... 23
PEIE Bit................................... ................. .................. 23
RBIF Bit................................................................ 23, 56
TMR0IE Bit................................................................. 23
Inter-Integrated Circuit. See I2C.
Inte rn a l Oscillator Blo c k....... .. .. ..... .. ................. .. ............ .. ... 35
INTR C Mode s........ .. ........... .. ...... .. ...... .. ........... .. ...... .. . 36
Inter net Addres s................................................... ............ 275
Inte rr u p t So u r ces......... .. ...... .. ........... .. ........... .. ......... 169, 1 84
A/D Conversion Complete........................................ 155
Interrupt-on-Change (RB7:RB4)................................. 56
RB0/ INT Pin, Exte rn a l .............. .. .. ...... .. ................. .. . 185
TMR0 Overf low.... .. ...... .. ..... .. ............ .. ..... .. ...... .. ....... 18 5
Interrupts
Exiting Sleep with ..... .... .. ......... .. .... .... .. ......... .... .. .... .... 48
Synchronous Serial Port Interrupt .............................. 25
Inte rr u pts, Co n te x t Sa v i ng D u r i n g . .. ...... .. .......................... 185
PIC16F7X7
DS30498D-page 270 2003-2013 Microchip Technology Inc.
Interrupts, Enable Bits
Global Interrupt Enable (GIE Bit) ........................23, 184
Interrupt-on-Change (RB7:RB4) Enable
(RBIE Bit)..........................................................185
Peripheral Interrupt Enable (PEIE Bit) ........................23
RB0/INT Enable (INT0IE Bit) ......................................23
TMR0 Overflow Enable (TMR0IE Bit).........................23
Interrupts, Flag Bits
Interrupt-on Change (RB7:RB4 ) Flag (RBIF Bit).........23
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit)..............................................23, 56, 185
RB0/INT Flag (INT0IF Bit)...... .....................................23
TMR0 Overflow Flag (TMR0IF Bit) ...... .....................185
INTRC Modes
Adjustment..................................................................36
L
Load Conditions........................ .... .. .. .. .... ..... .... .. .. .. .. .... .....220
Loading of PC ............................. .. .. .... .. .. ..... .... .. .. .. .. .. ....... ..29
Low-Voltage Detect. ..........................................................174
Characteristics ..........................................................219
Effects of a Reset ......................................................178
Operation ..................................................................177
Curren t Cons u mption........................................178
Reference Voltage Set Point.............................178
Operation During Sleep ............................................178
Time-out Sequence............... .... .. .... ........... .. .... .... .....178
Low-Voltage Detect (LVD) ................................................169
LVD. See Low-Voltage Detect. .........................................174
M
Master Clear (MCLR)
MCLR Reset, Normal Operation...............172, 179, 180
MCLR Reset, Sleep............................... .. .172, 179, 180
Master Synchronous Serial Port (MSSP). See MS SP.
Master Synchronous Serial Port. See MSSP
MCLR/VPP/RE3 Pin........................................ .......................8
MCLRpp/RE3 Pin................................................................11
Memory Organization..........................................................15
Data Memor y ..... .........................................................15
Program Memory........................................................15
Program Memo ry and Stack Maps ........................ .....15
Microc h i p In ternet Web Site..............................................275
MPLAB ASM30 Assembler, Linker, Librarian ...................202
MPLAB Integrated Development
Environ ment Softwa re...............................................201
MPLAB PM3 Device Programmer.....................................204
MPLAB REA L IC E In -Circuit Emulator Sy stem.................203
MPLINK Object Linker/MP LIB Object Librar ia n ................202
MSSP..................................................................................93
I2C Mode. See I2C
SPI Mode. See SPI
MSSP Module
Control Registers (General)........................................93
Overview.....................................................................93
Multi-Master Mode ............................................................127
O
OPTION_REG Register
INTEDG Bi t.................................................................22
PS2:PS0 Bits ..............................................................22
PSA Bit........................................................................22
RBPU Bit.....................................................................22
T0CS Bit......................................................................22
T0SE Bit......................................................................22
OSC1/CLKI/RA7 Pin.......................................................8, 11
OSC2/CLKO/RA6 Pin.....................................................8, 11
Oscillato r Configurat ion .... ......................... ......................... 33
ECIO........................................................................... 33
EXTRC ..................................................................... 179
HS....................................................................... 33, 179
INTIO1........................................................................ 33
INTIO2........................................................................ 33
INTRC....................................................................... 179
LP....................................................................... 33, 179
RC ........................................................................ 33, 35
RCIO........................................................................... 33
XT....................................................................... 33, 179
Oscillator Control Register
Modifying IRCF Bits.................................................... 39
Clock Transition Sequence................................. 40
Oscillator Delay upon Power-up, Wake-up and
Clock Switching.......................................................... 40
Oscillator Start-up Timer (OST)................................ 169, 173
Oscillat o r Switching ...... ........................... ............... ............ 37
P
Packaging......................................................................... 249
Details....................................................................... 251
Marking Information.................................................. 249
Paging, Program Memory................................................... 29
Parallel Slave Port
Associated Registers.................................................. 71
Para ll e l Sl a ve Po r t (P SP)............... .. ....... ................. .. .. . 67, 70
RE0/RD/AN5 Pi n . ............ .. ........... .. .. ...... .. ........... .. ..... 68
RE1/WR/AN6 Pi n . ...... .. ............ . .................. .. ........... .. . 68
RE2/CS/AN7 Pin... .......... ............................................ 68
Select (PSPMODE Bit)......................................... 67, 68
PCL Re g i s t e r ...... .. ...... . .................. .. ........... .. ........... .. .. ...... . 29
PCLATH Register............................................................... 29
PCON Register................................................................. 178
POR Bit....... ...... .. ................. .. ........... .. ........... .. .. ...... .. . 28
Peripheral Interrupt (PEIE Bit)............................................ 23
Pinout Descriptions
PIC16F737/PIC16F767 .......................................... 8–10
PIC16F747/PIC16F777 ........................................ 11–14
PMADR Register ................................................................ 31
POP.................................................................................... 29
POR. See Power-on Reset.
PORTA ........................................................................... 8, 11
Associated Registers.................................................. 55
PORTA Register......................... ................................49
TRISA Register...........................................................49
PORTA Register................................................................. 49
PORTB ........................................................................... 9, 12
Associated Registers.................................................. 64
PORTB Register......................... ................................56
Pull-up Enable (RBPU Bit)................ .. ........... .. .. ...... .. . 22
RB0/INT Edge Select (INTEDG Bit) ........................... 22
RB0/ INT Pin, Exte r na l ...... .. ........... .. .. ...... .. ........... .. .. . 185
RB7:RB4 Interrupt-on-Change .......... .... .... ......... .... .. 185
RB7:RB4 Interrupt-on-Change Enable
(RBI E Bit).................... ........... .......... ........... ...... 185
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit).............................................. 23, 56, 185
TRISB Register...........................................................56
PORTB Register................................................................. 56
2003-2013 Microchip Technology Inc. DS30498D-page 271
PIC16F7X7
PORTC .........................................................................10, 13
Associ a te d Re g i sters.... ..............................................66
PORTC Register.........................................................65
RC3/SCK/SCL Pin .. ..................................................107
RC6/TX/ CK Pin..... ....................................................134
RC7/RX/DT Pin.................................................134, 135
TRISC Register...................................................65, 133
PORTC Register.................................................................65
PORTD ...............................................................................14
Associ a te d Re g i sters.... ..............................................67
Paral l e l Sla ve Port (PSP) Fu n ction.............................67
PORTD Register.........................................................67
TRISD Register...........................................................67
PORTD Register.................................................................67
PORTE................................................................................14
Analog Port Pins.........................................................68
Associ a te d Re g i sters.... ..............................................68
Input Buffer Full Status (IBF Bit).................................69
Input Buffer Overflow (IBOV Bit).................................69
PORTE Register.........................................................68
PSP Mode Select (PS PM ODE Bit) . ............... .......67, 68
RE0/RD/AN5 Pin .........................................................68
RE1/WR/AN6 Pin ........................................................68
RE2/CS/AN7 Pin.................................. .......................68
TRISE Register...........................................................68
PORTE Register.................................................................68
Postscaler, WDT
Assignment (PSA Bit ) . ................................................22
Rate Select (PS2:PS0 Bits) ........................................22
Power-Down Mode (Sleep)...............................................190
Power-Down Mode. See Sleep.
Power-Managed Modes........................... .... .. .... ......... .... ....41
RC_RUN.....................................................................41
SEC_RUN...................................................................42
SEC_RUN/RC_RUN to Primary Clock Source...........43
Power-on Reset (POR)......... .... .... ....169, 172, 173, 179, 180
POR Status (PO R Bit)....... ........... ........................... ....28
Power Control/Status (PCON) Register....................178
Power-Down (PD Bit)................................................172
Time-ou t (T O Bit)................................................21, 172
Power-up Timer (PWRT) ................ ........... .... .... .......169, 173
PR2 Register.......................................................................85
Prescaler, Timer0
Assignment (PSA Bit ) . ................................................22
Rate Select (PS2:PS0 Bits) ........................................22
Program Counter
Reset Conditions.......................................................179
Program Mem ory
FlashAssociated Re g i sters...... ....................................32
Inter rupt Vector........................................ ...................15
Memory and Stack Maps ............................................15
Operation During Code-Protect ..................................32
Organization................................................................15
Paging.........................................................................29
PMADR Register.........................................................31
PMADRH Registe r.... ..................................................31
Reading.......................................................................31
Reading Flash................... .... .. ....... .... .. .... .. ....... .... .. ....32
Reading, PMADR Register.........................................31
Reading, PMADRH Register .......................................31
Reading, PMCON1 Register.......................................31
Reading, PMDATA Register.......................................31
Reading, PMDATH Register.......................................31
Reset Vec tor.... ...........................................................15
Prog r a m Ve rifica tion................... .. .. ................. .. ............... 192
Prog r a mming , D ev i ce In stru cti o n s.... .. .. ...... .. .................... 193
PUSH.................................................................................. 29
R
RA0/AN0 Pin .................................................................. 8, 11
RA1/AN1 Pin .................................................................. 8, 11
RA2/AN2/VREF-/CVREF Pin ............................................ 8, 11
RA3/AN3/VREF+ Pin....................................................... 8, 11
RA4/ T0CKI /C 1OUT Pi n. .. ...... .. ........... .. .. ...... . ............ .. ... 8, 11
RA5/AN4/LVDIN/SS/C2OU T Pin.... .. ................. .. ........... 8, 11
RAM. See Data Me mory.
RB0/INT/AN12 Pin.......................................................... 9, 12
RB1/AN10 Pin ...... .......................................................... 9, 12
RB2/AN8 Pin .................................................................. 9, 12
RB3/CCP2/AN9 Pin........................................................ 9, 12
RB4/AN11 Pin ...... .......................................................... 9, 12
RB5/AN13/CCP3 Pin...................................................... 9, 12
RB6/PGC Pin.................................................................. 9, 12
RB7/PGD Pin.................................................................. 9, 12
RC0/T1OSO/T1CKI Pin................................................ 10, 13
RC1/T1OSI/CC P 2 Pi n . .. ...... .. ........... .. .. ...... .. ........... .. ... 10, 13
RC2/CCP1 Pin.............................................................. 10, 13
RC3/SCK/SCL Pin........................................................ 10, 13
RC4/SDI/SDA Pin....................................... .................. 10, 13
RC5/SDO Pin................................................................ 10, 13
RC6/TX/ CK Pin......... .................................................... 10, 13
RC7/RX/DT Pi n.. ........................................................... 10, 13
RCIO Oscillator................................................................... 35
RCSTA Register
ADDEN Bit............................................ .................... 134
CREN Bit... ............................................................... 13 4
FERR Bit................................................................... 134
OERR Bit.................................................................. 134
RX9 Bit ..................................................................... 134
RX9D Bit................................................................... 134
SPEN Bit ........................................................... 133, 134
SREN Bit .................................................................. 134
RD0/PSP0 Pin.................................................................... 14
RD1/PSP1 Pin.................................................................... 14
RD2/PSP2 Pin.................................................................... 14
RD3/PSP3 Pin.................................................................... 14
RD4/PSP4 Pin.................................................................... 14
RD5/PSP5 Pin.................................................................... 14
RD6/PSP6 Pin.................................................................... 14
RD7/PSP7 Pin.................................................................... 14
RE0/RD/AN5 Pi n . ...... .. .. ...... .. ..... .. .. ...... .. ........... .. ............ .. . 14
RE1/WR/AN6 Pi n . ...... .. ...... .. .. ..... .. ............ .. ........... .. ........... 14
RE2/CS/AN7 Pin... .......... .................................................... 14
Reader Response............................................................. 276
Register File........................................................................ 15
Registers
ADCON0 (A/D Control 0).......................................... 152
ADCON1 (A/D Control 1).......................................... 153
ADCON2 (A/D Control 2).......................................... 154
CCPxCON (CCPx Control)................................. ........ 88
CMCON (Comparator Control)................................. 161
CVRCON (Comparator Voltage
Reference Control)........................................... 167
Initialization Conditions (table).......................... 180–181
INTC ON (I n te rrupt C o n trol) .......... .. ...... . ...... .. . . ...... .. ... 23
LVDCON (Low-Voltage Detect Control) ................... 176
OPTION_R EG ( Op tio n Co ntrol) ......................... .. 22, 75
OSCC ON (O scilla tor Con t r o l ). .. ...... .. ..... .. ............ .. ..... 38
OSCTUNE (Oscillator Tunin g)..... ............. .................. 36
PCON (Powe r C o n tro l / Status ).. .. .. ............................. . 28
PIC16F7X7
DS30498D-page 272 2003-2013 Microchip Technology Inc.
PIE1 (Peripheral Interrupt Enable 1)...........................24
PIE2 (Peripheral Interrupt Enable 2)...........................26
PIR1 (Peripheral Interrupt Request (Flag) 1)..............25
PIR2 (Peripheral Interrupt Request (Flag) 2)..............27
PMCON1 (P ro g r am Memory C o n trol 1)........ .. ........... .31
RCSTA (Receive Status and Control).......................134
Special Function, Summary..................................18–20
SSPCON (MS SP Control Register 1,
I2C Mode)..........................................................104
SSPCON (MS SP Control Register 1,
SPI Mode)...........................................................95
SSPCON2 (MS SP Control Register 2,
I2C Mode)..........................................................105
SSPSTAT (MSSP Status, I2C Mode)............... .. .. .....103
SSPSTAT (MSSP Status, SPI Mode).........................94
Status..........................................................................21
T1CON (Timer1 Con tr o l)....... ........ ..............................78
T2CON (Timer2 Con tr o l)....... ........ ..............................86
TRISE .........................................................................69
TXSTA (Transmit Status and Control) ......... ...... .......133
WDTCON (Watchdog Tim er Contro l)........................187
Reset.........................................................................169, 172
Brown-out Reset (BOR). See Brown-out Reset (BOR).
MCLR Reset. See MC LR.
Power-on Reset (POR). See Powe r-on Reset (POR).
Reset Conditions for All Registers ....................180, 181
Rese t Condit i on s fo r PC ON Reg i s t e r...... .. ............ . ...17 9
Reset Conditions for Program Counter.....................179
Rese t Condit i on s fo r Statu s Registe r.. .. ............ .. ......179
WDT Reset. See Watchdog Timer (WDT).
Revision History................................................................265
S
SCI. See AUSAR T
SCK.....................................................................................93
SDI......................................................................................93
SDO ....................................................................................93
Serial Clock, SCK................................................................93
Serial Communication Interface. See AUS ART.
Serial Data In, SDI ..............................................................93
Serial Data Out, SDO..........................................................93
Serial Peripheral Interface. See SPI.
Slave Select, SS .................................................................93
Sleep.................................................................169, 172, 190
Softwa re Simulator (MPLAB SIM )..... ................................203
Speci a l Features of the CPU.............................................169
Special Function Registers .....................................18, 18–20
SPI Master Mode ................................................................98
SPI Mode ............................................................................93
Associ a te d Re gisters...... ..........................................101
Bus Mode Compatibilit y....................... .. .... .. .. .. .. .. .....101
Clock...........................................................................98
Effects of a Reset ......................................................101
Enabling SPI I/O .........................................................97
Master/Slave Connection..................................... .......97
Serial Clock.................................................................93
Serial Data In ..............................................................93
Serial Data Out ...........................................................93
Slave Select................................................................93
Slave Select Synchronization .....................................99
Sleep Operation........................................................101
Typica l Co nnection ......... ............................................97
SPI Slave Mode ..................................................................99
SS .......................................................................................93
SSPBUF..............................................................................98
SSPIF Bit.............................................................................25
SSPOV ............................................................................. 123
SSPOV Status Flag.......................................................... 123
SSPSR................................................................................ 98
SSPSTAT Register
R/W Bit ..... .. .. ...... . ............ .. .. ..... .. ............ .. ................ 107
Stack................................................................................... 29
Overflows.................................................................... 29
Underflows.................................................................. 29
Status Register
C Bit............................................................................ 21
DC Bit . .. ...... .. ................. .. ................. .. ........... .. ........... 21
IRP Bit .......................... ........................... ................. .. 21
PD Bit ... .. ...... .. ................. .. .. ..... .. ............ .. .......... 21, 172
TO Bit ................. . .................. .. ........... .. ........... .. . 21, 172
Z Bit....... .......... ............................. .......................... .... 21
Synchronous Serial Port Interrupt Flag Bit (SSPIF)............ 25
T
T1C KPS0 Bit. .. ............ . .................. .. ........... .. .. ...... . ............ . 78
T1C KPS1 Bit. .. ............ . .................. .. ........... .. .. ...... . ............ . 78
T1OSCEN Bi t...................................................................... 78
T1SYNC Bit ................................................. ................. ...... 78
T2C KPS0 Bit. .. ............ . .................. .. ........... .. .. ...... . ............ . 86
T2C KPS1 Bit. .. ............ . .................. .. ........... .. .. ...... . ............ . 86
TAD.................................................................................... 157
Timer0................................................................................. 73
Associated Registers.................................................. 76
Clock Source Edge Select (T0SE Bit) ........................ 22
Cloc k So urce Se l e ct (T0CS Bit) .. .................. . .. ........... 22
Interrupt ...................................................................... 73
Operation.................................................................... 73
Overflow Enable (TMR0IE Bit).................................... 23
Overflow Flag (TMR0IF Bit)...................................... 185
Overflow Interrupt..................................................... 185
Prescaler .................................................................... 74
T0CKI ......................................................................... 74
Use w i th Externa l C l oc k................ .. ............ .. .............. 7 4
Timer1................................................................................. 77
Associated Registers.................................................. 83
Asynchronous Counter Mode..................................... 80
Reading and Writing........................................... 80
Capacitor Selection..................................................... 81
Counter Operation.................. ..... .... .. .... .. .. ....... .... .. .. .. 79
Operation.................................................................... 77
Operation in Synchronized Counter Mode.................. 79
Operation in Timer Mode............................................ 79
Oscillator..................................................................... 81
Oscillator Layout Considerations........................ ........ 81
Prescaler .................................................................... 82
Resetting Timer1 Register Pair................................... 82
Resetting Using a CCP Trigger Output....................... 81
Use a s a Re al-Ti me Clock. .. ..... .. ...... .. ...... .. ........... .. ... 8 2
Timer2................................................................................. 85
Associated Registers.................................................. 86
Output......................................................................... 85
Postscaler................................................................... 85
Prescaler .................................................................... 85
Prescaler and Postscaler............................................ 85
Timing Diagrams
A/D Conver sion..... ....................................................234
Acknowledge Sequence........................................... 126
Asynchronous Mast er Transm ission. ........................ 139
Asynchronous Mast er Transm ission
(Ba ck to Ba ck). ...... .. ........... .. .. ...... .. ................. . 139
Asynchronous Receptio n. ......................................... 140
Asynchronous Recept ion with Address Byte First.... 143
2003-2013 Microchip Technology Inc. DS30498D-page 273
PIC16F7X7
Asynchronous Re ception with Address Dete ct.........143
AUSART Synchronous Receiv e (Mast er/ Slave).......232
AUSART Synchronous T ransm ission
(Master/Slave) ..................................................232
Baud Rate Generator with Clock Arbitration.............120
BRG Reset Due to SDA Arbitration During
Start Condition........................... .... ...... ........... ..129
Brown-out Reset.......................................................223
Bus Collision During a Repeated Start
Condition (Case 1)............................................130
Bus Collision During a Repeated Start
Condition (Case 2)............................................130
Bus Collision During a Stop Condition (Case 1) ... .. ..131
Bus Collision During a Stop Condition (Case 2) ... .. ..131
Bus Collision During Start Condition (SCL = 0) ........129
Bus Collision During Start Condition (SDA Only)......128
Bus Collision for Transmit and Acknowledge............127
Capture/Compare/PWM (CCP1 and CCP2).............225
CLKO and I/O ...........................................................222
Clock Synchronization ..............................................113
External Clock...........................................................221
Fail-Safe Clock Monitor.............................................189
First Start Bit.............................................................121
I2C Bus Data.............................................................230
I2C Bus Start/Stop Bits..............................................229
I2C Master Mode (Reception, 7-bit Address)............125
I2C Master Mode (Transmission, 7 or
10-bit Address) .................................................124
I2C Slave Mode (Transmission, 10-bit Address).......111
I2C Slave Mode (Transmission, 7-bit Address).........109
I2C Slave Mode with SEN = 0 (Reception,
10-bit Address) .................................................110
I2C Slave Mode with SEN = 0 (Reception,
7-bit Address) ...................................................108
I2C Slave Mode with SEN = 1 (Reception,
10-bit Address) .................................................115
I2C Slave Mode with SEN = 1 (Reception,
7-bit Address) ...................................................114
Low-Voltage Detect...................................................177
LP Clock to Primary System Clock after
Reset (EC, RC, INTRC)......................................46
LP Clock to Primary System Clock after
Reset (HS, XT, LP).............................................45
Paral l e l Sla ve Port ....................................................226
Paral l e l Sla ve Port Read....... ......................................71
Paral l e l Sla ve Port Write.............................................71
PWM Output......... ......................................................91
Repeated Start Condition................. .. .... .. .. ....... .. .... ..122
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer...............................223
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode)............................. ..116
Slave Synchronization (SP I Mode). ............................99
Slow Rise Time (MCLR Tied to VDD
Through RC Network)...................... .... ......... ....183
SPI Mast e r Mode (CKE = 0, SMP = 0) .. ................. ..227
SPI Mast e r Mode (CKE = 1, SMP = 1) .. ................. ..227
SPI Mode (Master Mode)............................................98
SPI Mode (Slave Mode with CKE = 0)......................100
SPI Mode (Slave Mode with CKE = 1)......................100
SPI Slave Mode (CKE = 0) .......................................228
SPI Slave Mode (CKE = 1) .......................................228
Stop Condition Receive or Transmit Mode...............126
Switching to SEC_RUN Mode ..................... ...............42
Synchronous Reception (Master Mode, SREN) .......147
Synchronous Transmission ..... ............ ..................... 145
Synchronous Transmiss ion (Through TXEN)........... 145
Time-out Sequence on Power-up (MCLR
Tied to VDD Through Pull-up Resistor)............. 182
Time-out Sequence on Power-up (MCLR
Tied to VDD Through RC Network): Case 1...... 182
Time-out Sequence on Power-up (MCLR
Tied to VDD Through RC Network): Case 2...... 182
Timer0 and Timer1 External Clock........................... 224
Time r 1 In creme n t i n g E d g e ..... ............ .. ..... .. ............ .. . 79
Transition Between SEC_RUN/RC_RUN
and Primary Clock.............................................. 44
Two-Speed Start-up ................................................. 188
Wake-up from Sleep via Interrupt............................. 191
XT, HS, LP, EC, EXTRC to RC_RUN Mode .......... .... 41
Timing Parameter Symbology .......................................... 220
Timing Requirements
AUSART Synchronous Receive............................... 232
AUSART Synchronous Transmi ssion. ...................... 232
Capture/Compare/PWM (All CCP Modules)............. 225
CLKO and I/O........................................................... 222
External Clock .......................................................... 221
I2C Bus Da t a...... .. ............ . ............ .. .. ..... .. ............ .. ... 231
I2C Bus Start/Stop Bits............................................. 230
Parallel Slave Port.................................................... 226
Reset, Watchdog Timer, Oscillator Start -up Time r,
Power-up Timer and Brown-out Reset............. 223
SPI Mode.................................................................. 229
Timer0 and Timer1 External Clock........................... 224
TMR1CS Bit........................................................................ 78
TMR1ON Bit....................................................................... 78
TMR2ON Bit....................................................................... 86
TOUTPS<3:0> Bits............................................................. 86
TRISA Register................................................................... 49
TRISB Register................................................................... 56
TRISC Regist e r................................................................... 65
TRISD Regist e r................................................................... 67
TRISE Register................................................................... 68
IBF Bit..................... ........................... ......................... 6 9
IBOV Bit...................................................................... 69
PSPM ODE Bit ....... .. ............. .............. .................. 67 , 6 8
Two-Speed Clock Start-up Mode...................................... 188
Two-Speed Start-up.......................................................... 169
TXSTA Register
BRGH Bit.................................................................. 133
CSRC Bit.................................................................. 133
TRMT Bit ... ............................................................... 133
TX9 Bit...................................................................... 133
TX9D Bit................................................................... 133
TXEN Bit....................... ............................ ................ 133
V
Voltage Refe rence Specif ications................... .............. .... 218
PIC16F7X7
DS30498D-page 274 2003-2013 Microchip Technology Inc.
W
Wake-up from Sleep .................................................169, 190
Interrupts...........................................................179, 180
WDT Reset ...............................................................180
Wake-up Using Interrupts .................................................191
Watchdog Timer (WDT)..................................... .. .... .169, 186
Associ a te d Re g i sters........ ........................................187
WDT Reset, Normal Operation.................172, 179, 180
WDT Reset, Sleep....................................172, 179, 180
WCOL .......................................................121, 122, 123, 126
WCOL Status Flag....................................121, 122, 123, 126
WWW Address..................................................................275
WWW, On-Line Support ........................................................4
2003-2013 Microchip Technology Inc. DS30498D-page 275
PIC16F7X7
THE MICROCHIP WEB SITE
Microc hip pro vides onl ine s upport v ia our W WW site at
www.microchip.com. This web si te i s used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
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Questions (FAQ), technical support requests,
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•Business of Microchip – Product selector and
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representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of interes t.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technic al suppo rt is avail able throug h the we b site
at: http://microchip.com/support
PIC16F7X7
DS30498D-page 276 2003-2013 Microchip Technology Inc.
READER RESP ONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
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DS30498DPIC16F7X7
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2003-2013 Microchip Technology Inc. DS30498D-page 277
PIC16F7X7
PIC16F7X7 P RODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC16F7X7(1), PIC16F7X7T(1); VDD range 4.0V to 5.5V
PIC16LF7X7(1), PIC16LF7X7T(1); VDD range 2.0V to 5.5V
Temperatu re R ang e I = - 40 C to +85C (Industrial)
E=-40C to +125C (Extended)
Package ML = QFN (Micro Lead Frame)
PT = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny Plastic DIP
P=PDIP
SS = SSOP
Pattern QTP, SQTP, Code or Special Requirements
(blank oth erwis e )
Examples:
a) PIC16F777-I/P 301 = Industrial temp., PDIP
package, normal VDD limits, QTP pattern #301.
b) PIC16LF767-I/SO = Industrial temp., SOIC
package, extended VDD limits.
c) PIC16F747-E/P = Extended temp., PDIP
packag e, norma l VDD limits.
Note 1: F = CMOS Flash
LF = Low-Power CMOS Flash
2: T = in tape and reel – SOIC, SSOP,
TQFP packages only.
PIC16F7X7
DS30498D-page 278 2003-2013 Microchip Technology Inc.
NOTES:
2003-2013 Microchip Technology Inc. DS30498D-page 279
Information contained in this publication regarding device
applications a nd t he lik e is provid ed only for your con venience
and may be su perseded by updates. I t is y our respo ns i bil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM ,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE , In-Circuit Seria l
Programm ing, ICSP, Mindi, MiWi, MPAS M, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Tec hnolo gy Germ any II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2003-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769386
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of t he most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS30498D-page 280 2003-2013 Microchip Technology Inc.
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Worldwide Sales and Service
11/29/12
