TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 FEATURES * * * * * * * * * * * * * * * (1) Controlled Baseline - One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of -40C to 125C (TLC2543Q) and -55C to 125C (TLC2543M) Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree (1) 12-Bit-Resolution Analog-to-Digital Converter (ADC) 10-s Conversion Time Over Operating Temperature 11 Analog Input Channels Three Built-In Self-Test Modes Inherent Sample-and-Hold Function Linearity Error . . . 1 LSB Max On-Chip System Clock End-of-Conversion (EOC) Output Unipolar or Bipolar Output Operation (Signed Binary With Respect to 1/2 the Applied Voltage Reference) Programmable Most Significant Bit (MSB) or Least Significant Bit (LSB) First Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. * * * * Programmable Power Down Programmable Output Data Length CMOS Technology Application Report Available (2) DW PACKAGE (TOP VIEW) AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 GND (2) 1 20 2 3 19 4 5 17 16 6 15 14 7 18 8 9 13 10 11 12 VCC EOC I/O CLOCK DATA INPUT DATA OUT CS REF + REF - AIN10 AIN9 Microcontroller Based Data Acquisition Using the TLC2543 12-bit Serial-Out ADC (SLAA012) DESCRIPTION/ORDERING INFORMATION The TLC2543 is a 12-bit, switched-capacitor, successive-approximation, analog-to-digital converter (ADC). This device, with three control inputs [chip select (CS), input-output clock (I/O CLOCK), and address input (DATA INPUT)], is designed for communication with the serial port of a host processor or peripheral through a serial 3-state output. The device allows high-speed data transfers from the host. In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel multiplexer that can select any 1 of 11 inputs or any 1 of 3 internal self-test voltages. The sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated in the device features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating temperature range. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2006, Texas Instruments Incorporated TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 ORDERING INFORMATION PACKAGE (1) TA ORDERABLE PART NUMBER TOP-SIDE MARKING -40C to 125C SOP - DW Tape and reel TLC2543QDWREP TLC2543QEP -55C to 125C SSOP - DB Tape and Reel TLC2543MDBREP TLC2543MEP (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTIONAL BLOCK DIAGRAM AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 1 2 3 4 5 6 7 8 9 11 12 Sample-andHold Function REF + REF - 14 13 12-Bit Analog-to-Digital Converter (Switched Capacitors) 14-Channel Analog Multiplexer 12 4 Input Address Register Output Data Register 12 12-to-1 Data Selector and Driver 16 DATA OUT 4 3 Self-Test Reference Control Logic and I/O Counters 19 DATA INPUT I/O CLOCK CS 2 17 18 15 Submit Documentation Feedback EOC TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 1 2 3 4 5 6 7 8 9 11 12 I Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should be less than or equal to 50 for 4.1-MHz I/O CLOCK operation, and be capable of slewing the analog input voltage into a capacitance of 60 pF. CS 15 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT, DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup time. I Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted next. The serial data is presented with the most significant bit (MSB) first and is shifted in on the first four rising edges of I/O CLOCK. After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order. DATA INPUT 17 DATA OUT 16 O The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the most significant bit/least significant bit (MSB/LSB) value of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB/LSB, and the remaining bits are shifted out in order. EOC 19 O End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until the conversion is complete and the data is ready for transfer. GND 10 Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. I/O CLOCK 18 I Input/output clock. I/O CLOCK receives the serial input and performs the following four functions: * It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK with the multiplexer address available after the fourth rising edge. * On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input begins charging the capacitor array and continues to do so until the last falling edge of the I/O CLOCK. * It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on the falling edge of I/O CLOCK. * It transfers control of the conversion to the internal state controller on the falling edge of the last I/O CLOCK. REF+ 14 I Positive reference voltage. The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is determined by the difference between the voltage applied to this terminal and the voltage applied to the REF- terminal. REF- 13 I Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF-. VCC 20 Positive supply voltage Submit Documentation Feedback 3 TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Supply voltage range (2) VCC MIN MAX -0.5 6.5 UNIT V V VI Input voltage range (any input) -0.3 VCC + 0.3 VO Output voltage range -0.3 VCC + 0.3 V Vref+ Positive reference voltage VCC + 0.1 V Vref- Negative reference voltage -0.1 V II Peak input current (any input) 20 mA II Peak total input current (all inputs) 30 mA TA Operating free-air temperature range Tstg Storage temperature range TLC2543Q -40 125 TLC2543M -55 125 -65 150 C 260 C Lead temperature 1,6 mm (1/16 in) from the case for 10 s (1) (2) C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the GND terminal with REF- and GND wired together (unless otherwise noted). Recommended Operating Conditions MIN VCC Supply voltage Vref+ Positive reference voltage (1) Vref- Negative reference voltage (1) Vref+ - Vref- Differential reference 4.5 voltage (1) 2.5 Analog input voltage (1) 0 VIH High-level control input voltage VCC = 4.5 V to 5.5 V VIL Low-level control input voltage VCC = 4.5 V to 5.5 V Clock frequency at I/O CLOCK Setup time, address bits at DATA INPUT before I/O CLOCK (see Figure 4) th(A) Hold time, address bits after I/O CLOCK (see Figure 4) th(CS) Hold time, CS low after last I/O CLOCK (see Figure 5) tsu(CS) Setup time, CS low before clocking in first address bit (2) (see Figure 5) twH(I/O) 5 5.5 UNIT V VCC V 0 V VCC VCC + 0.1 V VCC V V 0.8 V 4.1 MHz 100 ns 0 ns 0 ns 1.425 s Pulse duration, I/O CLOCK high 120 ns twL(I/O) Pulse duration, I/O CLOCK low 120 tt(I/O) Transition time, I/O CLOCK high to low (3) (see Figure 6) tt(CS) Transition time, DATA INPUT and CS TA Operating free-air temperature (1) (2) (3) 4 MAX 2 0 tsu(A) NOM ns 1 s 10 s TLC2543Q -40 125 TLC2543M -55 125 C Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied to REF- convert as all zeros (000000000000). To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 1 s for remote data acquisition applications where the sensor and the ADC are placed several feet away from the controlling microprocessor. Submit Documentation Feedback TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O (unless otherwise noted) PARAMETER TEST CONDITIONS CLOCK) = 4.1 MHz MIN TYP (1) MAX VCC = 4.5 V, IOH = -1.6 mA 2.4 VCC = 4.5 V to 5.5 V, IOH = -20 A VCC = 4.5 V, IOL = 1.6 mA 0.4 VCC = 4.5 V to 5.5 V, IOL = 20 A 0.1 UNIT VOH High-level output voltage VOL Low-level output voltage IOZ High-impedance off-state output current VO = VCC, CS at VCC 1 2.5 VO = 0, CS at VCC 1 -2.5 IIH High-level input current VI = VCC 1 10 IIL Low-level input current VI = 0 1 -10 A ICC Operating supply current CS at 0 V 1 2.5 mA ICC(PD) Power-down current For all digital inputs, 0 VI 0.5 V or VI VCC - 0.5 V 4 25 A Selected channel leakage current Maximum static analog reference current into REF+ Ci (1) Input capacitance V VCC - 0.1 Selected channel at VCC, Unselected channel at 0 V Selected channel at 0 V, Unselected channel at VCC Vref+ = VCC, Vref- = GND 10 -10 1 2.5 Analog inputs 30 60 Control inputs 5 15 V A A A A pF All typical values are at VCC = 5 V, TA = 25C. Submit Documentation Feedback 5 TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 Operating Characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O PARAMETER TEST CONDITIONS CLOCK) MAX UNIT EL Linearity See Figure 2 1 LSB ED Differential linearity error See Figure 2 1 LSB 2 (4) 1.5 LSB See Figure 2 (4) 1 LSB 1.75 LSB EO Offset EG Gain error (3) ET Total unadjusted error (5) See Figure DATA INPUT = 1011 Self-test output code (6) (see Table 3) t(conv) Conversion time 2048 DATA INPUT = 1100 0 DATA INPUT = 1101 4095 See Figure 9 through Figure 14 tc Total cycle time (access, sample, and conversion) (7) See Figure 9 through Figure 14 tacq Channel acquisition time (sample) (7) See Figure 9 through Figure 14 tv Valid time, DATA OUT remains valid after I/O CLOCK See Figure 6 td(I/O-DATA) Delay time, I/O CLOCK to DATA OUT valid See Figure 6 td(I/O-EOC) Delay time, last I/O CLOCK to EOC See Figure 7 td(EOC-DATA) Delay time, EOC to DATA OUT (MSB/LSB) See Figure 8 tPZH, tPZL Enable time, CS to DATA OUT (MSB/LSB driven) See Figure 3 tPHZ, tPLZ Disable time, CS to DATA OUT (high impedance) tr(EOC) 8 4 10 s 10 + total I/O CLOCK periods + td(I/O-EOC) s 12 10 I/O CLOCK periods ns 150 ns 2.2 s 100 ns 0.7 1.3 s See Figure 3 70 150 ns Rise time, EOC See Figure 8 15 50 ns tf(EOC) Fall time, EOC See Figure 7 15 50 ns tr(bus) Rise time, data bus See Figure 6 15 50 ns tf(bus) Fall time, data bus See Figure 6 15 50 ns td(I/O-CS) Delay time, last I/O CLOCK to CS to abort conversion (8) 5 s (1) (2) (3) (4) (5) (6) (7) (8) 6 TYP (1) error (2) error (3) MIN = 4.1 MHz 1.5 All typical values are at TA = 25C. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal midstep value at the offset point. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied to REF- convert as all zeros (000000000000). Total unadjusted error comprises linearity, zero-scale, and full-scale errors. Both the input address and the output codes are expressed in positive logic. I/O CLOCK period = 1 /(I/O CLOCK frequency) (see Figure 7) Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at 5 s of the tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5 s and 10 s, the result is uncertain as to whether the conversion is aborted or the conversion results are valid. Submit Documentation Feedback TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION 15 V 50 C1 10 F C2 0.1 F C3 470 pF VI C1 10 F TLC2543 10 _ U1 + AIN0-AIN10 C3 470 pF C2 0.1 F 50 -15 V LOCATION DESCRIPTION U1 C1 OP27 10-F 35-V tantalum capacitor C2 C3 0.1-F ceramic NPO SMD capacitor 470-pF porcelain Hi-Q SMD capacitor PART NUMBER -- -- AVX 12105C104KA105 or equivalent Johanson 201S420471JG4L or equivalent Figure 1. Analog Input Buffer to Analog Inputs AIN0-AIN10 VCC Test Point VCC Test Point RL = 2.18 k RL = 2.18 k EOC DATA OUT 12 k CL = 50 pF 12 k CL = 100 pF Figure 2. Load Circuits Data Valid 2V CS 0.8 V tPZH, tPZL DATA OUT tPHZ, tPLZ 2.4 V 90% 0.4 V 10% 2V 0.8 V DATA INPUT th(A) tsu(A) I/O CLOCK 0.8 V Figure 3. DATA OUT to Hi-Z Voltage Waveforms Submit Documentation Feedback Figure 4. DATA INPUT and I/O CLOCK Voltage Waveforms 7 TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 2V CS 0.8 V tsu(CS) I/O CLOCK A. th(CS) Last Clock 0.8 V 0.8 V To ensure full conversion accuracy, it is recommended that no input signal change occurs while a conversion is ongoing. Figure 5. CS and I/O CLOCK Voltage Waveforms tt(I/O) tt(I/O) I/O CLOCK 2V 2V 0.8 V 0.8 V 0.8 V I/O CLOCK Period td(I/O-DATA) tv DATA OUT 2.4 V 0.4 V 2.4 V 0.4 V tr(bus), tf(bus) Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms I/O CLOCK Last Clock 0.8 V td(I/O-EOC) 2.4 V EOC 0.4 V tf(EOC) Figure 7. I/O CLOCK and EOC Voltage Waveforms tr(EOC) EOC 2.4 V 0.4 V td(EOC-DATA) DATA OUT 2.4 V 0.4 V Valid MSB Figure 8. EOC and DATA OUT Voltage Waveforms 8 Submit Documentation Feedback TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B 7 8 11 Sample Cycle B III II II II II II II II II III II II II II II II II II III II II II II II II II II IIIIIIIIIIIIIIIIIII DATA OUT A11 A10 A9 A8 A7 A6 A5 A4 A1 Previous Conversion Data MSB 12 B7 B6 B5 B4 B3 B2 B1 1 Hi-Z State A0 LSB DATA INPUT MSB IIIIII IIIIII IIIIII IIIIII II II II II II II IIII B11 C7 B0 LSB EOC t(conv) Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value A/D Conversion Interval Initialize A. Initialize To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 9. Timing for 12-Clock Transfer Using CS With MSB First CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B DATA OUT 7 8 11 A10 A9 A8 A7 A6 A5 A4 Previous Conversion Data MSB 1 Sample Cycle B III II II II II II II II II III II II II II II II II II III II II II II II II II II IIIIIIIIIIIIIIIIIII A11 12 A1 A0 Low Level LSB DATA INPUT B7 MSB B6 B5 B4 B3 B2 B1 III II III II III II IIIII B11 C7 B0 LSB EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize A. t(conv) A/D Conversion Interval Initialize To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 10. Timing for 12-Clock Transfer Not Using CS With MSB First Submit Documentation Feedback 9 TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 CS (see Note A) 1 I/O CLOCK 2 3 IIIIII IIIIII IIIIII IIIIII IIII II II II IIIII III II II II II II IIIII III II IIII II II II IIIII III II IIIIIIIIIIIII III II 4 5 Access Cycle B DATA OUT II II II II A7 MSB DATA INPUT B7 MSB I I I I A6 I I I I A5 6 7 8 Sample Cycle B A4 A3 A2 A1 B5 B3 B4 Hi-Z A0 Previous Conversion Data B6 1 B7 LSB B2 B1 B0 C7 LSB EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value t(conv) A/D Conversion Interval Initialize A. Initialize To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 11. Timing for 8-Clock Transfer Using CS With MSB First CS (see Note A) 1 I/O CLOCK 2 3 4 5 Access Cycle B DATA OUT 7 8 1 Sample Cycle B II II II II II II II I III IIIIIIIIIIIIIIIIII II II II II II II II I III IIIIIIIIIIIIIIIIII A7 A6 A5 B7 MSB A4 A3 A2 A1 Previous Conversion Data MSB DATA INPUT 6 B6 B5 B4 B3 B2 A0 Low Level LSB B1 B0 III II IIIII III II IIIII B7 C7 LSB EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize A. t(conv) A/D Conversion Interval To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 12. Timing for 8-Clock Transfer Not Using CS With MSB First 10 Initialize Submit Documentation Feedback TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B 7 A15 A14 A13 A12 A11 A10 A9 Previous Conversion Data MSB DATA INPUT B7 B6 B5 B3 B4 MSB 15 16 Sample Cycle B III II II II II II I IIIIIIIIIIIIII III II II II II II I IIIIIIIIIIIIII DATA OUT 8 B2 B1 I I I I A8 B0 II II II II IIIIII IIIIII IIIIII IIIIII II II IIII II II IIII 1 Hi-Z State A1 A0 LSB B15 C7 LSB EOC t(conv) Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value A/D Conversion Interval Initialize A. Initialize To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 13. Timing for 16-Clock Transfer Using CS With MSB First CS (see Note A) I/O CLOCK 1 2 3 4 5 6 Access Cycle B 7 8 15 16 Sample Cycle B III II I II II II II II III III II I II II II II II III III II I II II II II II III IIIIIIIIIIIIIIIIIII DATA OUT A15 A14 A13 A12 A11 A10 A9 A8 A1 Previous Conversion Data MSB 1 A0 Low Level LSB DATA INPUT B7 MSB B6 B5 B4 B3 B2 B1 B0 IIII II IIII II IIII II IIIIII B15 C7 LSB EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize A. t(conv) A/D Conversion Interval To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed. Figure 14. Timing for 16-Clock Transfer Not Using CS With MSB First Submit Documentation Feedback 11 TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 PRINCIPLES OF OPERATION Initially, with chip select (CS) high, I/O CLOCK and DATA INPUT are disabled and DATA OUT is in the high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA INPUT and removes DATA OUT from the high-impedance state. The input data is an 8-bit data stream consisting of a 4-bit analog channel address (D7-D4), a 2-bit data length select (D3-D2), an output MSB or LSB first bit (D1), and a unipolar or bipolar output select bit (D0) that are applied to DATA INPUT. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the input data register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles long, depending on the data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The last falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion. Converter Operation The operation of the converter is organized as a succession of two distinct cycles: the I/O cycle and the actual conversion cycle. I/O Cycle The I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods, depending on the selected output data length. During the I/O cycle, the following two operations take place simultaneously: * An 8-bit data stream consisting of address and control information is provided to DATA INPUT. This data is shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after the first eight clocks during 12- or 16-clock I/O transfers. * The data output, with a length of 8, 12, or 16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising edge of EOC. When CS is negated between conversions, the first output data bit occurs on the falling edge of CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding bit is clocked out on the falling edge of each succeeding I/O CLOCK. Conversion Cycle The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to I/O CLOCK. During the conversion period, the device performs a successive-approximation conversion on the analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when conversion is complete and the output data register is latched. A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external digital noise on the accuracy of the conversion. 12 Submit Documentation Feedback www.ti.com TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 PRINCIPLES OF OPERATION (continued) Power Up and Initialization After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data register is set to all zeroes. The contents of the output data register are random, and the first conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low to begin the next I/O cycle. The first conversion after the device has returned from the power-down state may not read accurately due to internal device settling. Table 1. Operational Terminology Current (N) I/O cycle Entire I/O CLOCK sequence that transfers address and control data into the data register and clocks the digital result from the previous conversion from DATA OUT Current (N) conversion cycle The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into the output register when conversion is complete. Current (N) conversion result The current conversion result is serially shifted out on the next I/O cycle. Previous (N - 1) conversion cycle Conversion cycle just prior to the current I/O cycle Next (N + 1) I/O cycle I/O period that follows the current conversion cycle Example: In the 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this corrupts the output data from the previous conversion. The current conversion is begun immediately after the twelfth falling edge of the current I/O cycle. Submit Documentation Feedback 13 TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 Data Input The data input is internally connected to an 8-bit serial-input address and control register. The register defines the operation of the converter and the output data length. The host provides the data word with the MSB first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data input-register format). Table 2. Input-Register Format INPUT DATA BYTE ADDRESS BITS L1 L0 LSBF BIP D3 D2 D1 D0 (LSB) 8 bits 0 1 12 bits X (1) 0 16 bits 1 1 FUNCTION SELECT D7 (MSB) D6 D5 D4 AIN0 0 0 0 0 AIN1 0 0 0 1 AIN2 0 0 1 0 AIN3 0 0 1 1 AIN4 0 1 0 0 AIN5 0 1 0 1 AIN6 0 1 1 0 AIN7 0 1 1 1 AIN8 1 0 0 0 AIN9 1 0 0 1 AIN10 1 0 1 0 (Vref+ - Vref-)/2 1 0 1 1 Vref- 1 1 0 0 Vref+ 1 1 0 1 1 1 1 0 Select input channel Select test voltage Software power down Output data length Output data format MSB first 0 LSB first (LSBF) 1 Unipolar (binary) 0 Bipolar (BIP) 2s complement 1 (1) The four MSBs (D7-D4) of the data register address one of the 11 input channels, a reference-test voltage, or the power-down mode. The address bits affect the current conversion, which is the conversion that immediately follows the current I/O cycle. The reference voltage is nominally equal to Vref+- Vref-. Data Input Address Bits The four MSBs (D7-D4) of the data register address 1 of the 11 input channels, a reference-test voltage, or the power-down mode. The address bits affect the current conversion, which is the conversion that immediately follows the current I/O cycle. The reference voltage is nominally equal to Vref+- Vref-. 14 Submit Documentation Feedback www.ti.com TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 Data Output Length The next two bits (D3 and D2) of the data register select the output data length. The data-length selection is valid for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested. With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly 12 bits long for proper synchronization, even when this means corrupting the output data from a previous conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle. With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current I/O cycle. With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even when this means corrupting the output data from the previous conversion. The four LSBs of the conversion result are truncated and discarded. The current conversion is started immediately after the eighth falling edge of the current I/O cycle. Since D3 and D2 take effect on the current I/O cycle when the data length is programmed, there can be a conflict with the previous cycle when the data-word length is changed from one cycle to the next. This may occur when the data format is selected to be LSB first, since at the time the data length change becomes effective (six rising edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation, when different data lengths are required within an application and the data length is changed between two conversions, no more than one conversion result can be corrupted and only when it is shifted out in LSB-first format. Sampling Period During the sampling period, one of the analog inputs is internally connected to the capacitor array of the converter to store the analog input signal. The converter starts sampling the selected input immediately after the four address bits have been clocked into the input data register. Sampling starts on the fourth falling edge of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge of the I/O CLOCK depending on the data-length selection. After the EOC delay time from the last I/O CLOCK falling edge, the EOC output goes low indicating that the sampling period is over and the conversion period has begun. After EOC goes low, the analog input can be changed without affecting the conversion result. Since the delay from the falling edge of the last I/O CLOCK to EOC low is fixed, time-varying analog input signals can be digitized at a fixed rate without introducing systematic harmonic distortion or noise due to timing uncertainty. After the 8-bit data stream has been clocked in, DATA INPUT should be held at a fixed digital level until EOC goes high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the influence of external digital noise. Data Register, LSB First D1 in the input data register (LSB first) controls the direction of the output binary data transfer. When D1 is reset to 0, the conversion result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to another, the current I/O cycle is never disrupted. Submit Documentation Feedback 15 TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 Data Register, Bipolar Format D0 (BIP) in the input data register controls the binary data format used to represent the conversion result. When D0 is cleared to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result of an input voltage equal to Vref- is a code of all zeros (000 . . . 0), the conversion result of an input voltage equal to Vref+ is a code of all ones (111 . . . 1), and the conversion result of (Vref+ + Vref-)/2 is a code of a one followed by zeros (100 . . . 0). When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion of an input voltage equal to Vref- is a code of a one followed by zeros (100 . . . 0), conversion of an input voltage equal to Vref+ is a code of a zero followed by all ones (011 . . . 1), and the conversion of (Vref+ + Vref-)/2 is a code of all zeros (000 . . . 0). The MSB is interpreted as the sign bit. The bipolar data format is related to the unipolar format in that the MSBs are always each other's complement. Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the current I/O cycle is not affected. End of Conversion (EOC) Output The EOC signal indicates the beginning and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes low, the analog input signal can be changed without affecting the conversion result. The EOC signal goes high again after the conversion is completed and the conversion result is latched into the output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins. On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When CS is negated between conversions, the first bit of the current conversion result occurs at DATA OUT on the falling edge of CS. Data Format and Pad Bits D3 and D2 of the input data register determine the number of significant bits in the digital output that represent the conversion result. The LSB-first bit determines the direction of the data transfer while the BIP bit determines the arithmetic conversion. The numerical data is always justified toward the MSB in any output format. The internal conversion result is always 12 bits long. When an 8-bit data transfer is selected, the four LSBs of the internal result are discarded to provide a faster 1-byte transfer. When a 12-bit transfer is used, all bits are transferred. When a 16-bit transfer is used, four LSB pad bits are always appended to the internal conversion result. In the LSB-first mode, four leading zeros are output. In the MSB-first mode, the last four bits output are zeros. When CS is held low continuously, the first data bit of the newly completed conversion occurs on DATA OUT on the rising edge of EOC. When a new conversion is started after the last falling edge of I/O CLOCK, EOC goes low and the serial output is forced to a setting of 0 until EOC goes high again. When CS is negated between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit in the serial conversion result until the required number of bits has been output. 16 Submit Documentation Feedback TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 Chip-Select (CS) Input CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data transfer of several devices sharing the same bus. When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing its output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK is inhibited, thus preventing any further change in the internal state. When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low) for a minimum time before a new I/O cycle can start. CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough before the end of the current conversion cycle, the previous conversion result is saved in the internal output buffer and shifted out during the next I/O cycle. Power-Down Features When a binary address of 1110 is clocked into the input data register during the first four I/O CLOCK cycles, the power-down mode is selected. Power down is activated on the falling edge of the fourth I/O CLOCK pulse. During power down, all internal circuitry is put in a low-current standby mode. No conversions are performed, and the internal output buffer keeps the previous conversion cycle data results provided that all digital inputs are held above VCC - 0.5 V or below 0.5 V. The I/O logic remains active so the current I/O cycle must be completed, even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle, the converter normally begins in the power-down mode. The device remains in the power-down mode until a valid input address (other than 1110) is clocked in. Upon completion of that I/O cycle, a normal conversion is performed with the results being shifted out during the next I/O cycle. Analog Input, Test, and Power-Down Mode The 11 analog inputs, 3 internal voltages, and power-down mode are selected by the input multiplexer according to the input addresses shown in Table 3, Table 4, and Table 5. The input multiplexer is a break-before-make type to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the falling edge of the last I/O clock pulse. The three internal test inputs are applied to the multiplexer, then sampled and converted in the same manner as the external analog inputs. The first conversion after the device has returned from the power-down state may not read accurately due to internal device settling. Table 3. Analog-Channel-Select Address ANALOG INPUT SELECTED VALUE SHIFTED INTO DATA INPUT BINARY HEX AIN0 0000 0 AIN1 0001 1 AIN2 0010 2 AIN3 0011 3 AIN4 0100 4 AIN5 0101 5 AIN6 0110 6 AIN7 0111 7 AIN8 1000 8 AIN9 1001 9 AIN10 1010 A Submit Documentation Feedback 17 TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 Table 4. Test-Mode-Select Address INTERNAL SELF-TEST VOLTAGE SELECTED (1) (1) (2) VALUE SHIFTED INTO DATA INPUT BINARY HEX UNIPOLAR OUTPUT RESULT (HEX) (2) Vref + - Vref - 2 1011 B 800 Vref- 1100 C 000 Vref+ 1101 D FFF Vref+ is the voltage applied to REF+, and Vref- is the voltage applied to REF-. The output results shown are the ideal values and may vary with the reference stability and with internal offsets. Table 5. Power-Down-Select Address INPUT COMMAND Power down VALUE SHIFTED INTO DATA INPUT BINARY HEX 1110 E RESULT ICC 25 A Converter and Analog Input The CMOS threshold detector in the successive-approximation conversion system determines each bit by examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously. This action charges all the capacitors to the input voltage. In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-) voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks at the first capacitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF-. When the voltage at the summing node is greater than the trip point of the threshold detector (approximately one-half VCC), a bit 0 is placed in the output register and the 4096-weight capacitor is switched to REF-. When the voltage at the summing node is less than the trip point of the threshold detector, a bit 1 is placed in the register and this 4096-weight capacitor remains connected to REF+ through the remainder of the successive-approximation process. The process is repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth down the line until all bits are determined. With each step of the successive-approximation process, the initial charge is redistributed among the capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB. Reference Voltage Inputs The two reference inputs used with the device are the voltages applied to the REF+ and REF- terminals. These voltage values establish the upper and lower limits of the analog input to produce a full-scale and zero-scale reading, respectively. These voltages and the analog input should not exceed the positive supply or be lower than ground consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than REF+ terminal voltage, and at zero when the input signal is equal to or lower than REF- terminal voltage. 18 Submit Documentation Feedback TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 SC Threshold Detector 4096 2048 Node 4096 REF - 1024 REF+ REF+ REF - ST 16 REF - ST 8 REF+ REF - ST 4 REF+ REF - ST REF+ REF - ST 2 1 REF+ REF+ REF - ST REF - ST To Output Latches 1 REF - ST ST VI Figure 15. Simplified Model of the Successive-Approximation System Submit Documentation Feedback 19 TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 APPLICATION INFORMATION 4095 111111111111 VFS See Notes A and B 4094 111111111110 VFSnom 4093 VFT = VFS - 1/2 LSB 2049 100000000001 2048 100000000000 VZT = VZS + 1/2 LSB 2047 011111111111 VZS 000000000001 1 000000000000 0 0.0012 0.0024 2.4564 2.4576 2.4588 4.9128 4.9134 2 0.0006 000000000010 4.9140 0 4.9152 VI - Analog Input Voltage - V A. This curve is based on the assumption that Vref+ and Vref- have been adjusted so that the voltage at the transition from digital 0 to 1 (VZT) is 0.0006 V and the transition to full scale (VFT) is 4.9134 V. 1 LSB = 1.2 mV. B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is the step whose nominal midstep value equals zero. Figure 16. Ideal Conversion Characteristics TLC2543 1 2 3 4 5 Analog Inputs 6 7 8 9 11 12 AIN0 AIN1 AIN2 15 CS 18 I/O CLOCK 17 DATA INPUT Processor AIN3 AIN4 DATA OUT AIN5 EOC 16 19 AIN6 AIN7 AIN8 REF+ AIN9 AIN10 REF- 14 5-V DC Regulated 13 GND 10 To Source Ground Figure 17. Serial Interface 20 Submit Documentation Feedback Control Circuit Step Digital Output Code 111111111101 TLC2543-EP 12-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 ANALOG INPUTS www.ti.com SGLS125A - JULY 2002 - REVISED NOVEMBER 2006 APPLICATION INFORMATION (continued) Simplified Analog Input Analysis Using the equivalent circuit in Figure 18, the time required to charge the analog input capacitance from 0 V to VS within one-half LSB can be derived as follows: The capacitance charging voltage is given by: V C + VS 1 * e *t cRtC i (1) Where: Rt = Rs + ri The final voltage to 1/2 LSB is given by: VC (1/2 LSB) = VS - (VS /8192) (2) Equating equation 1 to equation 2 and solving for time tc gives V S * V S8192 + VS 1 * e *t cRtC i (3) and tc (1/2 LSB) = Rt x Ci x ln(8192) (4) Therefore, with the values given, the time for the analog input signal to settle is: tc (1/2 LSB) = (Rs + 1 k) x 60 pF x ln(8192) (5) This time must be less than the converter sample time shown in the timing diagrams. Driving Source(A) TLC2543 Rs VS VI ri VC 1 k Max Ci 60 pF Max VI = Input Voltage at AIN VS = External Driving Source Voltage Rs = Source Resistance ri = Input Resistance Ci = Input Capacitance VC = Capacitance Charging Voltage A. Driving source requirements: * Noise and distortion for the source must be equivalent to the resolution of the converter. * Rs must be real at the input frequency. Figure 18. Equivalent Input Circuit Including the Driving Source Submit Documentation Feedback 21 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC2543MDBREP ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC2543QDWREP ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/03614-01XE ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/03614-02YE ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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OTHER QUALIFIED VERSIONS OF TLC2543-EP : TLC2543 * Catalog: TLC2543-Q1 * Automotive: * Military: TLC2543M NOTE: Qualified Version Definitions: - TI's standard catalog product * Catalog - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Automotive * Military - QML certified for Military and Defense Applications Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC2543MDBREP SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 TLC2543QDWREP SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC2543MDBREP TLC2543QDWREP SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. 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