S i 3 2 1 0 / S i 3 2 11 P RO SLIC (R) P ROGRAMMABLE CMOS SLIC/C ODEC W I T H R INGING / B A TT E R Y V OLTA GE G ENERATION Features Applications Programmable audio processing DTMF encoding and decoding 12 kHz/16 kHz pulse metering Phase-continuous FSK (caller ID) Dual tone generators -Law/A-Law and linear PCM audio Extensive test and diagnostic features Multiple loopback test modes DC line V/I measurements Supports GR-909 MLT Comprehensive design tools Reference schematic and PCB layout ProSLIC API abstracts SLIC functions, minimizing software development RoHS-compliant packages SPI and PCM bus digital interfaces Fixed Wireless (cellular) Terminals Terminal Adapters PBX/IP-PBX/Key telephone systems Voice-over-IP Systems: DSL/EMTAs/FTTx WiMax/LTE Description ProSLIC(R) The Si3210/11 chipset provides a complete analog telephone interface ideal for customer premise equipment (CPE). It integrates a subscriber line interface circuit (SLIC), voice codec, and battery generation (Si3210) or battery selection (Si3211) into a single CMOS integrated circuit. The battery supply continuously adapts its output voltage to minimize power dissipation and enables the entire circuit to be powered from a single 3.3 or 5 V supply (Si3210). The CMOS ProSLIC interfaces to the line through either the Si3201 Line-feed IC or a discrete line-feed circuit. Si3210/11 features include software-configurable 5 REN internal ringing up to 90 VPK, DTMF generation and decoding, Caller ID generation, and a comprehensive set of telephony signaling capabilities for global operation with a single hardware solution. The Si3210/11 is packaged in a 38-pin QFN or TSSOP, and the Si3201 is packaged in a thermally-enhanced 16-pin SOIC. Ordering Information See page 130. QFN Pin Assignments Si3210/11 QFN DRX PCLK INT CS SCLK SDI SDO 100% programmable global solution Performs all BORSCHT functions DC-DC controller provides tracking battery from a 3.3-35V input (Si3210) Minimizes power in all modes Dynamic 0 to -94.5 V output Choice of inductor (low cost) or transformer (high efficiency) Programmable line-feed parameters 2-wire AC impedance and hybrid Constant current feed (20 to 41 mA) Loop closure and ring trip thresholds and filtering Internal balanced ringing up to 90VPK 5 REN up to 4 kft; 3 REN up to 8 kft Programmable frequency, amplitude, cadence, and wave shape DTX FSYNC RESET SDCH/DIO1 SDCL/DIO2 VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC 1 38 37 36 35 34 33 32 31 30 2 3 4 29 5 27 26 28 6 7 25 8 9 24 23 10 22 21 11 12 13 14 15 16 17 18 19 20 SDITHRU DCDRV/DCSW DCFF/DOUT TEST GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP STIPE SVBAT SRINGE STIPAC SRINGAC IGMN GNDA U.S. Patent #6,567,521 U.S. Patent #6,812,744 Functional Block Diagram INT RESET Si3210/11 Line Status CS SCLK SDO Control Interface Compression SDI DTX PCM Interface Expansion DRX FSYNC PCLK Rev. 1.61 1/12 DTMF Decode PLL Gain/ Attenuation/ Filter A/D Prog. Hybrid Tone Generators Gain/ Attenuation/ Filter TIP Line Feed Control Linefeed Interface RING D/A ZS DC-DC Converter Controller (Si3210 only) Discrete Components Copyright (c) 2012 by Silicon Laboratories Si3210 Si3210/Si3211 TABLE O F C ONTENTS 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.1. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.5. Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.6. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 2.7. Audio Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.8. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.9. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.10. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.11. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.12. PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.13. Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 4. Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 4.1. DTMF Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 4.2. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.3. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.4. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.5. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 5. Pin Descriptions: Si3210/11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8. Package Outlines and PCB Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.1. 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 8.2. 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8.3. 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 9.1. Ordering Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.2. Marking Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10. Package Marking (Top Mark) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.1. QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10.2. TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.3. SOIC (Si3201) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 2 Rev. 1.61 Si3210/Si3211 1. Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information1 Parameter Symbol Value Unit VDDD, VDDA1, VDDA2 -0.5 to 6.0 V IIN 10 mA VIND -0.3 to (VDDD + 0.3) V TA -40 to 100 C TSTG -40 to 150 C TSSOP-38 Thermal Resistance, Typical JA 70 C/W QFN-38 Thermal Resistance, Typical JA 35 C/W Continuous Power Dissipation2 PD 0.7 W DC Supply Voltage VDD -0.5 to 6.0 V Battery Supply Voltage VBAT -104 V Input Voltage: TIP, RING, SRINGE, STIPE pins VINHV (VBAT - 0.3) to (VDD + 0.3) V Input Voltage: ITIPP, ITIPN, IRINGP, IRINGN pins VIN -0.3 to (VDD + 0.3) V Operating Temperature Range2 TA -40 to 100 C TSTG -40 to 150 C SOIC-16 Thermal Resistance, Typical3 JA 55 C/W Continuous Power Dissipation2 PD Si3210/11 DC Supply Voltage Input Current, Digital Input Pins Digital Input Voltage Operating Temperature Range2 Storage Temperature Range Si3201 Storage Temperature Range 0.8 at 70 C 0.6 at 85 C W Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Operation above 125 C junction temperature may degrade device reliability. 3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad. Rev. 1.61 3 Si3210/Si3211 Table 2. Recommended Operating Conditions Parameter Symbol Test Condition Min* Typ Max* Unit Ambient Temperature TA F-grade 0 25 70 C Ambient Temperature TA G-grade -40 25 85 VDDD,VDDA1, VDDA2 3.13 3.3/5.0 5.25 V Si3201 Supply Voltage VDD 3.13 3.3/5.0 5.25 V Si3201 Battery Voltage VBAT -96 -- -10 V Si3210/11 Supply Voltage VBATH = VBAT C *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 C unless otherwise stated. Product specifications are only guaranteed for the typical application circuit (including component tolerances). Table 3. AC Characteristics (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter Test Condition Min Typ Max Unit THD = 1.5% 2.5 -- -- VPK 2-wire - PCM or PCM - 2-wire: 200 Hz-3.4 kHz -- -- -45 dB Signal-to-(Noise + Distortion) Ratio2 200 Hz to 3.4 kHz D/A or A/D 8-bit Active off-hook, and OHT, any ZAC Figure 1 -- -- Audio Tone Generator Signal-to-Distortion Ratio2 0 dBm0, Active off-hook, and OHT, any Zac 45 -- -- dB -- -- -45 dB 2-wire to PCM, 1014 Hz -0.5 0 0.5 dB PCM to 2-wire, 1014 Hz -0.5 0 0.5 dB Gain Accuracy over Frequency Figure 3,4 -- -- Group Delay over Frequency Figure 5,6 -- -- 3 to -37 dB -0.25 -- 0.25 dB -37 to -50 dB -0.5 -- 0.5 dB -50 to -60 dB -1.0 -- 1.0 dB Round-Trip Group Delay at 1000 Hz -- 1100 -- s Gain Step Accuracy -6 to +6 dB -0.017 -- 0.017 dB All gain settings -0.25 -- 0.25 dB VDDA = VDDA = 3.3/5 V 5% -0.1 -- 0.1 dB TX/RX Performance Overload Level Single Frequency Distortion1 Intermodulation Distortion Gain Accuracy 2 Gain Tracking3 Gain Variation with Temperature Gain Variation with Supply 4 1014 Hz sine wave, reference level -10 dBm signal level: Rev. 1.61 Si3210/Si3211 Table 3. AC Characteristics (Continued) (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter Test Condition Min Typ Max Unit 2-Wire Return Loss 200 Hz to 3.4 kHz 30 35 -- dB Transhybrid Balance 300 Hz to 3.4 kHz 30 -- -- dB C-Message Weighted -- -- 15 dBrnC Psophometric Weighted -- -- -75 dBmP 3 kHz flat -- -- 18 dBrn PSRR from VDDA RX and TX, DC to 3.4 kHz 40 -- -- dB PSRR from VDDD RX and TX, DC to 3.4 kHz 40 -- -- dB PSRR from VBAT RX and TX, DC to 3.4 kHz 40 -- -- dB 200 Hz to 3.4 kHz, Q1,Q2 150, 1% mismatch 56 60 -- dB Q1,Q2 60 to 2405 43 60 -- dB Q1,Q2 300 to 53 60 -- dB Using Si3201 53 60 -- dB 200 Hz to 3.4 kHz 40 -- -- dB -- -- -- 33 17 17 -- -- -- -- -- -- 4 8 12 -- -- -- mA mA mA Noise Performance Idle Channel Noise 4 Longitudinal Performance Longitudinal to Metallic or PCM Balance Metallic to Longitudinal Balance 8005 200 Hz to 3.4 kHz at TIP or RING Register selectable Longitudinal Impedance ETBO/ETBA 00 01 10 Active off-hook 200 Hz to 3.4 kHz Register selectable Longitudinal Current per Pin ETBO/ETBA 00 01 10 Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be -10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified. 2. Analog signal measured as VTIP - VRING. Assumes ideal line impedance matching. 3. The quantization errors inherent in the /A-law companding process can generate slightly worse gain tracking performance in the signal range of 3 to -37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate. 4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed -55 dBm. 5. Assumes normal distribution of betas. Rev. 1.61 5 Si3210/Si3211 Figure 1. Transmit and Receive Path SNDR 9 8 7 6 Fundamental Output Power 5 (dBm0) Acceptable Region 4 3 2.6 2 1 0 1 2 3 4 5 6 7 8 Fundamental Input Power (dBm0) Figure 2. Overload Compression Performance 6 Rev. 1.61 9 Si3210/Si3211 Typical Response Typical Response Figure 3. Transmit Path Frequency Response Rev. 1.61 7 Si3210/Si3211 Figure 4. Receive Path Frequency Response 8 Rev. 1.61 Si3210/Si3211 Figure 5. Transmit Group Delay Distortion Figure 6. Receive Group Delay Distortion Rev. 1.61 9 Si3210/Si3211 Table 4. Linefeed Characteristics (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70C for F-Grade, -40 to 85C for G-Grade) Parameter Symbol Test Condition Min Typ Max Unit RLOOP See *Note. 0 -- 160 ILIM = 29 mA, ETBA = 4 mA -10 -- 10 % Active Mode; VOC = 48 V, VTIP - VRING -4 -- 4 V RDO ILOOP < ILIM -- 160 -- DC Open Circuit Voltage-- Ground Start VOCTO IRING<ILIM; VRING wrt ground VOC = 48 V -4 -- 4 V DC Output Resistance-- Ground Start RROTO IRING<ILIM; RING to ground -- 160 -- DC Output Resistance-- Ground Start RTOTO TIP to ground 150 -- -- k Loop Closure/Ring Ground Detect Threshold Accuracy ITHR = 11.43 mA -20 -- 20 % Ring Trip Threshold Accuracy ITHR = 40.64 mA -10 -- 10 % User Programmable Register 70 and Indirect Register 36 -- -- -- VTR 5 REN load; sine wave; RLOOP = 160 VBAT = -75 V 44 -- -- Vrms ROS Programmable in Indirect Register 19 0 -- -- V Crest factor = 1.3 -.05 -- .05 1.35 -- 1.45 f = 20 Hz -1 -- 1 % Accuracy of ON/OFF Times -50 -- 50 ms CAL to CAL Bit -- -- 600 ms -25 -- 25 % Loop Resistance Range* DC Loop Current Accuracy DC Open Circuit Voltage Accuracy DC Differential Output Resistance Ring Trip Response Time Ring Amplitude Ring DC Offset Trapezoidal Ring Crest Factor Accuracy Sinusoidal Ring Crest Factor Ringing Frequency Accuracy Ringing Cadence Accuracy Calibration Time Power Alarm Threshold Accuracy RCF At Power Threshold = 300 mW *Note: DC resistance round trip; 160 corresponds to 2 kft, 26 gauge AWG. 10 Rev. 1.61 Si3210/Si3211 Table 5. Monitor ADC Characteristics (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter Symbol Min Typ Max Unit -1/2 -- 1/2 LSB -1 -- 1 LSB Gain Error (Voltage) -- -- 10 % Gain Error (Current) -- -- 20 % Min Typ Max Unit Differential Nonlinearity (6-bit resolution) DNLE Integral Nonlinearity (6-bit resolution) INLE Test Condition Table 6. Si321x DC Characteristics, VDDA = VDDD = 5.0 V (VDDA,VDDD = 4.75 to 5.25 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter Symbol Test Condition High Level Input Voltage VIH 0.7 x VDDD -- -- V Low Level Input Voltage VIL -- -- 0.3 x VDDD V DIO1,DIO2,SDITHRU: IO = -4 mA SDO, DTX:IO = -8 mA VDDD - 0.6 -- -- V DOUT: IO = -40 mA VDDD - 0.8 -- -- V DIO1,DIO2,DOUT,SDITHRU: IO = 4 mA SDO,INT,DTX:IO = 8 mA -- -- 0.4 V -10 -- 10 A High Level Output Voltage VOH Low Level Output Voltage VOL Input Leakage Current IL Table 7. Si321x DC Characteristics, VDDA = VDDD = 3.3 V (VDDA,VDDD = 3.13 to 3.47 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 0.7 x VDDD -- -- V Low Level Input Voltage VIL -- -- 0.3 x VDDD V DIO1,DIO2,SDITHRU: IO =-2 mA VDDD - 0.6 SDO, DTX:IO = -4 mA -- -- V DOUT: IO = -40 mA VDDD - 0.8 -- -- V DIO1,DIO2,DOUT,SDITHRU: IO = 2 mA SDO,INT,DTX:IO = 4 mA -- -- 0.4 V -10 -- 10 A High Level Output Voltage VOH Low Level Output Voltage VOL Input Leakage Current IL Rev. 1.61 11 Si3210/Si3211 Table 8. Power Supply Characteristics (Unless otherwise noted, VDDA, VDDD=3.13 to 5.25 V; TA=0 to 70C for F-grade, -40 to 85C for G-grade) Parameter Power Supply Current, Analog and Digital VDD Supply Current (Si3201) VBAT Supply Current3 VBAT Supply Slew Rate 12 Symbol IA + ID IVDD IBAT Test Condition Typ1 Typ2 Max Unit Sleep (RESET = 0), VDDA=VDDD=3.13 to 3.465 V 0.1 -- 0.3 mA Sleep (RESET = 0), VDDA=VDDD=4.75 to 5.25 V, TA=0 to 70C/F-grade -- 0.1 0.3 mA Sleep (RESET = 0), VDDA=VDDD=4.75 to 5.25 V, TA=-40 to 85C/G-grade -- 0.1 0.35 mA Open 33 42.8 49 mA Active on-hook ETBO = 4 mA, codec and Gm amplifier powered down 37 53 68 mA Active OHT ETBO = 4 mA 57 72 83 mA Active off-hook ETBA = 4 mA, ILIM = 20 mA 73 88 99 Ground Start 36 47 55 mA Ringing sinewave, REN = 1, VPK = 56 V 45 55 65 mA Sleep mode, RESET = 0 100 100 -- A Open (high impedance) 100 100 -- A Active on-hook standby 110 110 -- A Forward/reverse active off-hook, no ILOOP, ETBO = 4 mA, VBAT = -24 V 1 1 -- mA Forward/reverse OHT, ETBO = 4 mA, VBAT = -70 V 1 1 -- mA Sleep (RESET = 0) 0 0 -- mA Open (DCOF = 1) 0 0 -- mA Active on-hook VOC = 48 V, ETBO = 4 mA 3 3 -- mA Active OHT ETBO = 4 mA 11 11 -- mA Active off-hook ETBA = 4 mA, ILIM = 20 mA 30 30 -- mA Ground Start 2 2 -- mA Ringing: VPK_RING = 56 VPK, Sinewave ringing: REN = 1 5.5 5.5 -- mA When using Si3201 -- -- 10 V/s Rev. 1.61 mA Si3210/Si3211 Table 8. Power Supply Characteristics (Continued) (Unless otherwise noted, VDDA, VDDD=3.13 to 5.25 V; TA=0 to 70C for F-grade, -40 to 85C for G-grade) Parameter Symbol Test Condition Typ1 Max Typ2 Unit Notes: 1. VDDD, VDDA = 3.3 V. 2. VDDD, VDDA = 5.25 V. 3. IBAT = current from VBAT (the large negative supply). For a switched-mode power supply regulator efficiency of 71%, the user can calculate the regulator current consumption as IBAT x VBAT/(0.71 x VDC). Table 9. Switching Characteristics (General Inputs)1 VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade, CL = 20 pF) Parameter Rise Time, RESET RESET Pulse Width 2 Symbol Min Typ Max Unit tr -- -- 20 ns trl 100 -- -- ns Notes: 1. All timing (except rise and fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VD - 0.4 V, VIL = 0.4 V. Rise and fall times are referenced to the 20% and 80% levels of the waveform. 2. Additional initialization guidelines apply; see section 1.2 ProSLIC Initialization in AN35. Table 10. Switching Characteristics (SPI) VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade, CL = 20 pF Parameter Symbol Test Conditions Min Typ Max Unit Cycle Time SCLK tc 0.062 -- -- s Rise Time, SCLK tr -- -- 25 ns Fall Time, SCLK tf -- -- 25 ns Delay Time, SCLK Fall to SDO Active td1 -- -- 20 ns Delay Time, SCLK Fall to SDO Transition td2 -- -- 20 ns Delay Time, CS Rise to SDO Tri-state td3 -- -- 20 ns Setup Time, CS to SCLK Fall tsu1 25 -- -- ns Hold Time, CS to SCLK Rise th1 20 -- -- ns Setup Time, SDI to SCLK Rise tsu2 25 -- -- ns Hold Time, SDI to SCLK Rise th2 20 -- -- ns Delay Time between Chip Selects (Continuous SCLK) tcs 440 -- -- ns Delay Time between Chip Selects (Non-continuous SCLK) tcs 220 -- -- ns Rev. 1.61 13 Si3210/Si3211 Table 10. Switching Characteristics (SPI) VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade, CL = 20 pF SDI to SDITHRU Propagation Delay td4 -- 4 10 ns Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD -0.4 V, VIL = 0.4 V tthru tr tr tc SCLK tsu1 th1 CS tcs tsu2 th2 SDI td1 td3 td2 SDO Figure 7. SPI Timing Diagram Table 11. Switching Characteristics--PCM Highway Serial Interface VD = 3.13 to 5.25 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade, CL = 20 pF Parameter Symbol Test Conditions Min 1 Typ 1 Max 1 Units 0.256 0.512 0.7682 1.024 1.5362 2.048 4.096 8.192 -- -- -- -- -- -- -- -- MHz MHz MHz MHz MHz MHz MHz MHz PCLK Frequency 1/tc -- -- -- -- -- -- -- -- PCLK Duty Cycle Tolerance tdty 40 50 60 % PCLK-to-FSYNC Jitter Tolerance tjitter -120 -- 120 ns Rise Time, PCLK tr -- -- 25 ns Fall Time, PCLK tf -- -- 25 ns Delay Time, PCLK Rise to DTX Active td1 -- -- 20 ns Delay Time, PCLK Rise to DTX Transition td2 -- -- 20 ns Delay Time, PCLK Rise to DTX Tri-state3 td3 -- -- 20 ns Setup Time, FSYNC to PCLK Fall tsu1 25 -- -- ns Hold Time, FSYNC to PCLK Fall th1 20 -- -- ns 14 Rev. 1.61 Si3210/Si3211 Table 11. Switching Characteristics--PCM Highway Serial Interface VD = 3.13 to 5.25 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade, CL = 20 pF Setup Time, DRX to PCLK Fall tsu2 25 -- -- ns Hold Time, DRX to PCLK Fall th2 20 -- -- ns Notes: 1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH - VI/O -0.4V, VIL = 0.4 V. 2. Not a valid PCLK frequency for GCI mode. 3. Specification applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0). tr tc tf PCLK th1 tsu1 FSYNC tsu2 th2 DRX td1 td2 td3 DTX Figure 8. PCM Highway Interface Timing Diagram Rev. 1.61 15 Si3210/Si3211 VCC L2 47 H C31 C30 10 F 10 F C16 C15 20 C24 0.1 F VCC C3 220 nF STIPDC 0.1 F VDDD 30 27 VDDA2 10 23 31 GNDD VDDA1 15 GNDA TEST 32 0.1 F R1 200k C17 0.1 F SCLK SDI STIPAC R8 470 SDO IRINGN 13 25 IRINGN ITIPP 16 28 ITIPP IRINGP 14 26 IRINGP STIPE 11 SRINGE 10 RESET SRINGDC 33 VCC R281 DCFF GND PCM Bus 4 VCC 5 2 Note 2 7 24 IGMN 22 IREF 11 CAPP 12 CAPM 14 QGND 13 VDC Note 1 VBAT Rev. 1.61 3 DCFF 16 DCDRV SRINGAC SDCH 21 R3 200k Q9 2N2222 6 IGMP DC-DC Converter Circuit VDC Figure 9. Si3210/Si3210M Application Circuit Using Si3201 16 1 R262 10 k R15 243 SVBAT 34 R9 470 0.1 F R291 5 R6 4.02k INT DCDRV C26 Notes: 1. Values and configurations for these components can be derived from Table 19 or from "AN45: Design Guide for the SI3210 DC-DC Converter". 2. Only one component per system needed. R21 15 3. All circuit ground should have a single-point connection to the ground plane. 4. Si3201 bottom-side exposed pad should be electrically and thermally connected to bulk ground plane. 5. Pin numbers for TSSOP shown. SPI Bus 36 R322 10k R5 200k C4 220 nF 4 5 SRINGE 18 VBAT VBATH R7 4.02k 19 DTX 8 RING STIPE DRX SDCH RING R4 196k 17 SDCL 3 R2 196k ITIPN 9 C6 22nF PCLK 15 Si3210/Si3210M Si3201 Protection Circuit 29 FSYNC ITIPN TIP C5 22nF C19 4.7 F SDCL TIP C18 4.7 F 4 1 37 7 VDD GND 8 CS 38 C2 10 F C1 10 F R14 40.2k Si3210/Si3211 Table 12. Si3210/Si3210M + Si3201 External Component Values Component(s) Value Package Supplier C1,C2 10 F, 6 V Ceramic or 16 V Low Leakage Electrolytic, 20% Radial Murata, Nichicon URL1C100MD C3,C4 220 nF, 100 V, X7R, 20% 1812 Murata, Johanson, Novacap, Venkel C5,C6 22 nF, 100 V, X7R, 20% 1206 Murata, Johanson, Novacap, Venkel C15,C16,C17,C24 0.1 F, 6 V, Y5V, 20% 603 Murata, Johanson, Novacap, Venkel C18,C19 4.7 F, ceramic, 6 V, X7R, 20% 1206 Murata, Johanson, Novacap, Venkel C26 0.1 F, 100 V, X7R, 20% 1210 Murata, Johanson, Novacap, Venkel C30,C31 10 F, 10 V, Electrolytic, 20% Radial Panasonic L2 47 H, 150 mA SMD Coilcraft 200 k, 1/10 W, 1% 805 196 k, 1/10 W, 1% 805 R6,R7 4.02 k, 1/10 W, 1% 805 R8,R9 470 , 1/10 W, 1% 805 R14 40.2 k, 1/10 W, 1% 805 R15 243 , 1/10 W, 1% 805 R21 15 , 1/4 W, 5% 805 10 k, 1/10 W, 1% 805 R28,R29 1/10 W, 1% (See "AN45: Design Guide for the Si3210 DC-DC Converter" or Table 19 for value selection) 805 R322 10 k, 1/10 W, 5% 805 Q9 60 V, General Purpose Switching NPN SOT-23 R11,R31,R51 1 R2 ,R4 R26 1 2 ON Semi MMBT2222ALT1; Central Semi CMPT2222A; Zetex FMMT2222 Notes: 1. These resistors must be in an 0805 or larger package. 2. Only one component per system needed. Rev. 1.61 17 Si3210/Si3211 VDC F1 SDCH R191 R201 SDCL Si3210 C10 0.1 F DCFF DCDRV R16 200 C142 0.1 F C252 10 F Note 1 R181 Q7 FZT953 Q8 2N2222 R17 L1 D1 ES1D VBAT C9 10 F Note 1 GND Notes: 1. Values and configurations for these components can be derived from "AN45: Design Guide for the Si3210 DC-DC Converter" or Table 21. 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 10. Si3210 BJT/Inductor DC-DC Converter Circuit 18 Rev. 1.61 Si3210/Si3211 Table 13. Si3210 BJT/Inductor DC-DC Converter Component Values Component(s) Value Package Supplier C9 10 F, 100 V, Electrolytic, 20% Radial Panasonic C10 0.1 F, 50 V, X7R, 20% 1210 Murata, Johanson, Novacap, Venkel C14* 0.1 F, X7R, 20% 1210 Murata, Johanson, Novacap, Venkel C25* 10 F, Electrolytic, 20% Radial Panasonic R16 200 , 1/10 W, 5% 805 1/10 W, 5% (See AN45 or Table 21 for value selection) 1/4 W, 5% (See AN45 or Table 21 for value selection) 1/10 W, 1% (See AN45 or Table 21 for value selection) 1206 F1 Fuse SMD Belfuse SSQ Series D1 Ultra Fast Recovery 200 V, 1A Rectifier DO214AA L1 1 A, Shielded Inductor (See AN45 or Table 21 for value selection) SMD Q7 120 V, High Current Switching PNP SOT-223 Q8 60 V, General Purpose Switching NPN SOT-23 General Semi ES1D; Central Semi CMR1U-02 API Delevan SPD127 series, Sumida CDRH127 series, Datatronics DR3401 series, Coilcraft DS5022, TDK SLF12565 Zetex FZT953, FZT955, ZTX953, ZTX955; Sanyo 2SA1552 ON Semi MMBT2222ALT1, MPS2222A; Central Semi CMPT2222A; Zetex FMMT2222 R17 R18 R19,R20 805 805 *Note: Voltage rating of this device must be greater than VDC. Rev. 1.61 19 Si3210/Si3211 VDC F1 SDCH R191 Note 1 R18 C252 10 F 1 C142 0.1 F R201 SDCL Si3210M 1 C27 470 pF R22 22 2 3 DCFF M1 IRLL014N 6 D1 ES1D 4 10 T11 VBAT C9 10 F Note 1 R17 200 k DCDRV NC GND Notes: 1. Values and configurations for these components can be derived from AN45 or Table 20. 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 11. Si3210M MOSFET/Transformer DC-DC Converter Circuit 20 Rev. 1.61 Si3210/Si3211 Table 14. Si3210M MOSFET/Transformer DC-DC Converter Component Values Component(s) Value Package Supplier C9 10 F, 100 V, Electrolytic, 20% Radial Panasonic C14* 0.1 F, X7R, 20% 1210 Murata, Johanson, Novacap, Venkel C25* 10 F, Electrolytic, 20% Radial Panasonic C27 470 pF, 100 V, X7R, 20% 1206 Murata, Johanson, Novacap, Venkel R17 200 k, 1/10 W, 5% 805 R18 1/4 W, 5% (See "AN45: Design Guide for the Si3210 DC-DC Converter" or Table 20 for value selection) 1206 R19,R20 1/10 W, 1% (See AN45 or Table 20 for value selection) 805 R22 22 , 1/10 W, 5% 805 F1 Fuse SMD Belfuse SSQ Series D1 Ultra Fast Recovery 200 V, 1 A Rectifier D214-AA General Semi ES1D; Central Semi CMR1U-02 T1 Power Transformer SMD Coiltronic CTX01-15275; Datatronics SM76315; Midcom 31353R-02 M1 100 V, Logic Level Input MOSFET SOT-223 Intl Rect. IRLL014N; Intersil HUF76609D3S; ST Micro STD5NE10L, STN2NE10L *Note: Voltage rating of this device must be greater than VDC. Rev. 1.61 21 Si3210/Si3211 VCC L2 47 H C31 C30 10 F 10 F C16 C15 C3 220 nF VDDD 10 27 VDDA2 STIPAC VDDA1 23 31 STIPDC 20 GNDA TEST GNDD 32 C24 0.1 F VCC 15 0.1 F 30 0.1 F 0.1 F R1 200k C17 SCLK SDI R8 470 SDO 7 VDD GND 8 CS C18 4.7 F C19 4.7 F FSYNC ITIPN 15 29 ITIPN IRINGN 13 25 IRINGN ITIPP 16 28 IRINGP 14 26 STIPE 11 R2 196k 17 SRINGE 10 PCLK DRX TIP Si3201 C5 22 nF Protection Circuit C6 22 nF 3 RING RING R4 196k ITIPP IRINGP INT RESET STIPE SRINGE VBAT R6 4.02k 18 SVBAT R5 200k 9 NC NC Notes: 2. All circuit grounds should have a singlepoint connection to the ground plane. 3. Si3201 bottom-side exposed pad should be electrically and thermally connected to bulk ground plane. CAPM 14 QGND 13 NC R18 1.8k Note 1 7 12 VBATH Rev. 1.61 2 CAPP Figure 12. Si3211 Typical Application Circuit Using Si3201 22 VCC 5 11 4. Pin numbers for TSSOP shown. VBATL PCM Bus 4 IREF Q8 5551 Q7 5401 3 22 D1 4003 R16 200k 6 IGMN GND 1. Only one component per system needed. 1 24 DOUT R3 200k DCSW SRINGDC SPI Bus 36 IGMP 33 SRINGAC 16 DIO1 21 8 GND 34 R9 470 C4 220 nF DIO2 C9 0.1 F 37 R321 10k 4 5 VBATH R7 4.02k 19 Si32114 TIP 3 DTX 1 38 R261 10k R15 243 C2 10 F C1 10 F R14 40.2k Si3210/Si3211 Table 15. Si3211 + Si3201 External Component Values Component(s) Value Package Supplier C1,C2 10 F, 6 V Ceramic or 16 V, Low-Leakage Electrolytic, 20% Radial Murata, Nichicon URL1C100MD C3,C4 220 nF, 100 V, X7R, 20% 1812 Murata, Johanson, Novacap, Venkel C5,C6 22 nF, 100 V, X7R, 20% 1206 Murata, Johanson, Novacap, Venkel C9 0.1 F, 100 V, X7R, 20% 1210 Murata, Johanson, Novacap, Venkel C15,C16,C17,C24 0.1 F, 6 V, Y5V, 20% 1206 Murata, Johanson, Novacap, Venkel C18,C19 4.7 F Ceramic, 6 V, X7R, 20% 1206 Murata, Johanson, Novacap, Venkel C30,C31 10 F, 10 V, Electrolytic, 20% Radial Panasonic L2 47 H, 150 mA SMD Coilcraft D1 200 V, 1 A Rectifier MELF ON Semi: MRA4003, IN4003 Q7 120 V, PNP, BJT SOT-89 ON Semi: 2N5401 ON Semi: 2N5551 Q8 120 V, NPN, BJT SOT-223 R11,R31,R51,R161 200 k, 1/10 W, 1% 805 R21,R41 196 k, 1/10 W, 1% 805 R6,R7 4.02 k, 1/10 W, 1% 805 R8,R9 470 , 1/10 W, 1% 805 R14 40.2 k, 1/10 W, 1% 805 R15 243 , 1/10 W, 1% 805 R18 1.8 k, 1/10 W, 5% 805 R262 10 k, 1/10 W, 1% 805 R322 10 k, 1/10 W, 5% 805 Notes: 1. These resistors must be in an 0805 or larger package. 2. Only one component per system needed. Rev. 1.61 23 Si3210/Si3211 VCC L2 47 H C31 C30 10 F 10 F C16 C15 0.1 F 15 20 Q3 5401 R11 10 C34 4 R4 100k 0.1 F Q5 5551 R12 5.1k R5 100k C33 4 0.1 F 0.1 F 18 R105 (100k) R7 80.6 C4 220nF R9 470 21 16 IRINGN SRINGE SRINGDC 9 VCC R281 30 VDDD SPI Bus 36 1 6 3 4 PCM Bus 5 VCC R322 10k INT RESET IGMP SRINGAC Q9 2N2222 R291 DTX SVBAT R3 200k GND R21 15 IRINGP SDCL Notes: 1. Values and configurations for these components can be derived from Table 19 or from "AN45: Design Guide for the Si3210 DC-DC Converter". 2. Only one component per system needed. 3. All circuit grounds should have a single-point connection to the ground plane. 4. Optional components to improve idle channel noise. 5. The trace resistance between R6 and C26 should equal the trace resistance between R 7 and C26. 6. Pin numbers for TSSOP shown. 19 R104 (100k) C7 220nF C26 25 34 26 Q2 5401 DCDRV R6 80.6 RING STIPE R2 100k DRX 37 2 R26 2 10k 24 IGMN 22 IREF 11 CAPP 12 CAPM 14 QGND Note 2 7 R15 243 C2 10uF C1 10uF 13 DCFF 17 R102 (100k) Si3210/Si3210M6 R13 5.1k SDCH C6 22nF C8 220nF SDCL C5 22nF ITIPN 8 Protection Circuit 0.1 F DCDRV C32 4 Q6 5551 PCLK 38 33 29 FSYNC ITIPP SDCH TIP SDO STIPAC CS 28 R10 10 SDI R8 470 Q4 5401 Q1 5401 0.1 F SCLK STIPDC DCFF C3 220nF 27 10 VDDA1 R1 200k VDDA2 23 31 GNDA TEST GNDD 32 0.1 F GND C17 VDC Note 1 VBAT DC-DC Converter Circuit VDC Figure 13. Si3210/Si3210M Typical Application Circuit Using Discrete Components 24 Rev. 1.61 R14 40.2k Si3210/Si3211 Table 16. Si3210/Si3210M External Component Values--Discrete Solution Component(s) Value Package Supplier/Part Number C1,C2 10 F, 6 V Ceramic or 16 V Low-Leakage Electrolytic, 20% Radial Murata, Panasonic, Nichicon URL1C100MD C3,C4 220 nF, 100 V, X7R, 20% 1812 Murata, Johanson, Novacap, Venkel C5,C6 22 nF, 100 V, X7R, 20% 1206 Murata, Johanson, Novacap, Venkel C7,C8 220 nF, 50 V, X7R, 20% 1812 Murata, Johanson, Novacap, Venkel C15,C16,C17 0.1 F, 6 V, Y5V, 20% 603 Murata, Johanson, Novacap, Venkel C26 0.1 F, 100 V, X7R, 20% 1210 Murata, Johanson, Novacap, Venkel C30,C31 10 F, 10 V, Electrolytic, 20% Radial Panasonic C32,C33,C34 0.1 F, 50 V, 20% 805 Venkel L2 47 H, 150 mA SMD Coilcraft Q1,Q2,Q3,Q4 120 V, PNP, BJT SOT-23 Central Semi CMPT5401; ON Semi MMBT5401LT1, 2N5401; Zetex FMMT5401; Fairchild 2N5401; Samsung 2N5401 Q5,Q6 120 V, NPN, BJT SOT-223 Central Semi CZT5551, ON Semi 2N5551; Fairchild 2N5551; Phillips 2N5551 Q9 NPN General Purpose BJT SOT-23 ON Semi MMBT2222ALT1, MPS2222A; Central Semi CMPT2222A; Zetex FMMT2222 200 k, 1/10 W, 1% 805 R2 , R4 , R5 , R1021, R1041, R1051 100 k, 1/10 W, 1% 805 R6,R7 80.6 , 1/4 W, 1% 1210 R8,R9 470 , 1/10 W, 1% 805 R10,R11 10 , 1/10 W, 5% 805 R12,R13 5.1 k, 1/10 W, 5% 805 R14 40.2 k, 1/10 W, 1% 805 R15 243 , 1/10 W, 1% 805 R21 15 , 1/4 W, 1% 805 R26 10 k, 1/10 W, 1% 805 R28,R29 1/10 W, 1% (See "AN45: Design Guide for the Si3210/15/16 DC-DC Converter" or Table 19 for value selection) 805 R322 10 k, 1/10 W, 5% 805 R11, R31 1 1 1 2 Notes: 1. These resistors must be in 0805 or larger package. 2. Only one component per system needed. Rev. 1.61 25 Si3210/Si3211 VCC L2 47 H C31 C30 10 F 10 F C16 C15 C3 220nF 0.1F R4 100k 0.1F Q5 5551 C26 C34 4 ITIPN PCLK 17 STIPE DRX C7 220nF R12 5.1k IRINGP 25 IRINGN 19 R5 100k C33 4 18 R105 (100k) C4 220nF R9 470 21 SRINGAC 16 SRINGDC DIO2 NC NC Q7 5401 6 3 Rev. 1.61 PCM Bus 4 5 INT VCC 2 7 Note 1 RESET R261 10k 24 IGMN 22 IREF 11 CAPP 12 CAPM 14 QGND 13 NC R18 1.8k Figure 14. Si3211 Typical Application Circuit Using Discrete Solution 26 SPI Bus 36 1 R15 243 SVBAT 9 GND 37 R321 10k SRINGE R3 200k R16 200k DTX IGMP 0.1F R7 80.6 Notes: 1. Only one component per system needed. 2. All circuit grounds should have a single-point connection to the ground plane. Q8 5551 3. The trace resistance between R6 and C26 D1 should equal the trace resistance between 4003 R7 and C26. 4. Optional components to improve idle channel noise. 5. Pin numbers for TSSOP shown. VBATL VBATH 26 R104 (100k) 0.1 F 30 FSYNC Si32115 Q3 5401 VDDD ITIPP 29 R2 100k R11 10 27 28 R102 (100k) Q2 5401 VDDA2 10 GNDA VDDA1 23 31 CS DOUT R13 5.1k R6 80.6 RING SDO DCSW C6 22nF SDI 38 33 C5 22nF STIPAC DIO1 Protection Circuit 20 C32 4 Q6 5551 C8 220nF SCLK 8 TIP STIPDC 34 R10 10 0.1 F 15 R8 470 Q4 5401 Q1 5401 GNDD 32 TEST R1 200k GND C17 0.1 F 0.1 F C2 10uF C1 10uF R14 40.2k Si3210/Si3211 Table 17. Si3211 External Component Values--Discrete Solution Component(s) Value Package Supplier/Part Number C1,C2 10 F, 6 V Ceramic or 16 V Low Leakage Electrolytic, 20% Radial Murata, Panasonic, Nichicon URL1C100MD C3,C4 220 nF, 100 V, X7R, 20% 1812 Murata, Johanson, Novacap, Venkel C5,C6 22 nF, 100 V, X7R, 20% 1206 Murata, Johanson, Novacap, Venkel C7,C8 220 nF, 50 V, X7R, 20% 1812 Murata, Johanson, Novacap, Venkel C9 0.1 F, 100 V, X7R, 20% 1210 Panasonic C15,C16,C17 0.1 F, 6 V, Y5V, 20% 603 Murata, Johanson, Novacap, Venkel C30,C31 10 F, 10 V, X7R, 20% Radial Panasonic C32, C33, C34 0.1 F, 50 V, X7R, 20% 805 Venkel Coilcraft L2 47 H, 150 mA SMD R11,R31,R161 200 k, 1/10 W, 1% 805 R21, R41, R51, R1021, R1041, R1051 100 k, 1/10 W, 1% 805 R6,R7 80.6 , 1/4 W, 1% 1210 R8,R9 470 , 1/10 W, 1% 805 R10,R11 10 , 1/10 W, 5% 805 R12,R13 5.1 k, 1/10 W, 5% 805 R14 40.2 k, 1/10 W, 1% 805 R15 243 , 1/10 W, 1% 805 R18 1.8 k, 1/10 W, 5% 805 R262 10 k, 1/10 W, 1% 805 2 R32 10 k, 1/10 W, 5% 805 D1 200 V 1A Rectifier MELF ON Semi MRA4003, 1N4003 Q1,Q2,Q3,Q4,Q7 120 V, PNP, BJT SOT-23 Central Semi CMPT5401; ON Semi MMBT5401LT1, 2N5401; Zetex FMMT5401 Q5,Q6 120 V, NPN, BJT SOT-223 Central Semi CZT5551, ON Semi 2N5551 Q8 120 V, NPN, BJT SOT-223 Central Semi CMPT5551, ON Semi 2N5551 Notes: 1. These resistors must be in an 0805 or larger package. 2. Only one component per system needed. Rev. 1.61 27 Si3210/Si3211 QRDN QTDN Q3 Q4 5401 5401 R23 RRBN0 3.0k R24 RTBN0 3.0k QTN QRP Q6 Q5 5551 R7 RRE 80.6 C8 CTBN 100 nF 5551 C7 CRBN 100 nF R12 RRBN 5.1k R6 RTE 80.6 R13 RTBN 5.1k Figure 15. Si321x Optional Equivalent Q5, Q6 Bias Circuit Table 18. Si321x Optional Bias Component Values Component Value Package Supplier/Part Number C7,C8 100 nF, 100 V, X7R, 20% 1210 Murata, Johanson, Venkel R23,R24 3.0 k, 1/10 W, 5% 805 The subcircuit above can be substituted into any of the ProSLIC solutions as an optional bias circuit for Q5 and Q6. For this optional subcircuit, C7 and C8 differ in voltage and capacitance from the standard circuit. R23 and R24 are additional components. Table 19. Component Value Selection for Si3210/Si3210M 28 Component Value Package Comments R28 1/10 W, 1% resistor For VDD = 3.3 V: 26.1 k For VDD = 5.0 V: 37.4 k 805 R28 = (VDD + VBE)/148 A where VBE is the nominal VBE for Q9 R29 1/10 W, 1% resistor For VCLAMP = 80 V: 541 k For VCLAMP = 85 V: 574 k For VCLAMP = 100 V: 676 k 805 R29 = VCLAMP/148 A where VCLAMP is the clamping voltage for VBAT Rev. 1.61 Si3210/Si3211 Table 20. Component Value Selection Examples for Si3210M MOSFET/Transformer DC-DC Converter1 VDC Maximum Ringing Load/ Loop Resistance Winding Connections2 Transformer Ratio R18 R19, R20 3.3 V 3 REN/117 1-2 1-2 0.06 7.15 k 5.0 V 5 REN/117 1-2 1-2 0.10 16.5 k 12 V 5 REN/117 1-3 1-3 0.6 56.2 k 24 V 5 REN/117 1-4 1-4 2.1 121 k Notes: 1. There are other system and software conditions that influence component value selection. Refer to "AN45: Design Guide for the Si3210 DC-DC Converter" for detailed guidance. 2. Applies to transformer specified in Table 14; other transformers may vary. Table 21. Component Value Selection Examples for Si3210 BJT/Inductor DC-DC Converter VDC Maximum Ringing Load/Loop Resistance L1 R17 R18 R19, R20 5V 3 REN/117 67 H 150 0.15 16.5 k 12 V 5 REN/117 150 H 162 0.56 56.2 k 24 V 5 REN/117 220 H 175 2.0 121 k Note: There are other system and software conditions that influence component value selection. Refer to "AN45: Design Guide for the Si3210 DC-DC Converter" for detailed guidance. Rev. 1.61 29 Si3210/Si3211 2. Functional Description 2.1.1. DC Feed Characteristics The ProSLIC(R) is a single, low-voltage CMOS device that provides all the SLIC, codec, DTMF detection, and signal generation functions needed for a complete analog telephone interface. The ProSLIC performs all battery, overvoltage, ringing, supervision, codec, hybrid, and test (BORSCHT) functions. Unlike most monolithic SLICs, the Si3210 does not require externally-supplied high-voltage battery supplies. Instead, it generates all necessary battery voltages from a positive dc supply using its own dc-dc converter controller. Two fullyprogrammable tone generators can produce DTMF tones, phase continuous FSK (caller ID) signaling, and call progress tones. DTMF decoding and pulse metering signal generation are also integrated. The Si3201 linefeed interface IC performs all high-voltage functions. As an option, the Si3201 can also be replaced with lowcost discrete components as shown in the typical application circuits in Figures 12, 13, and 14. The ProSLIC has programmable constant voltage and constant current zones as shown in Figure 16. Opencircuit TIP-to-RING voltage (VOC) defines the constant voltage zone and is programmable from 0 V to 94.5 V in 1.5 V steps. The loop current limit (ILIM) defines the constant current zone and is programmable from 20 mA to 41 mA in 3 mA steps. The ProSLIC has an inherent dc output resistance (RO) of 160 . V (TIP-RING ) (V) V OC R O =160 The ProSLIC is ideal for short loop applications, such as terminal adapters, cable telephony, PBX/key systems, wireless local loop (WLL), and voice over IP solutions. The linefeed provides programmable on-hook voltage, programmable off-hook loop current, reverse battery operation, loop or ground start operation, and on-hook transmission ringing voltage. Loop current and voltage are continuously monitored using an integrated A/D converter. Balanced 5 REN ringing with or without a programmable dc offset is integrated. The available offset, frequency, waveshape, and cadence options are designed to ring the widest variety of terminal devices and to reduce external controller requirements. A complete audio transmit and receive path is integrated, including DTMF decoding, ac impedance, and hybrid gain. These features are softwareprogrammable, allowing for a single hardware design to meet international requirements. Digital voice data transfer occurs over a standard PCM bus. Control data is transferred using a standard SPI. The device is available in a 38-pin QFN or TSSOP package. 30 Constant Current Zone I LIM I LOOP (m A) Figure 16. Simplified DC Current/Voltage Linefeed Characteristic The TIP-to-RING voltage (VOC) is offset from ground by a programmable voltage (VCM) to provide voltage headroom to the positive-most terminal (TIP in forward polarity states and RING in reverse polarity states) for carrying audio signals. Table 22 summarizes the parameters to be initialized before entering an active state. Table 22. Programmable Ranges of DC Linefeed Characteristics Parameter Programmable Range Default Value Register Bits Location* ILIM 20 to 41 mA 20 mA ILIM[2:0] Direct Register 71 VOC 0 to 94.5 V 48 V VOC[5:0] Direct Register 72 VCM 0 to 94.5 V 3V VCM[5:0] Direct Register 73 2.1. Linefeed Interface The ProSLIC's linefeed interface offers a rich set of features and programmable flexibility to meet the broadest applications requirements. The dc linefeed characteristics are software-programmable. Key current, voltage, and power measurements are acquired in real time and provided in software registers. Constant Voltage Zone *Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. Rev. 1.61 Si3210/Si3211 2.1.2. Linefeed Architecture The ProSLIC is a low-voltage CMOS device that uses either an Si3201 linefeed interface IC or low-cost external components to control the high voltages required for subscriber line interfaces. Figure 17 is a simplified illustration of the linefeed control loop circuit for TIP or RING and the external components used. The ProSLIC uses both voltage and current sensing to control TIP and RING. DC and ac line voltages on TIP and RING are measured through sense resistors RDC and RAC. The ProSLIC uses linefeed transistors QP and QN to drive TIP and RING. QDN isolates the high-voltage base of QN from the ProSLIC. The ProSLIC measures voltage at various nodes in order to monitor the linefeed current. RDC, RSE, and RBAT provide access to these measuring points. The sense circuitry is calibrated on-chip to guarantee measurement accuracy with standard external component tolerances. See "2.1.9. Linefeed Calibration" on page 36 for details. 2.1.3. Linefeed Operation States The ProSLIC linefeed has eight states of operation as shown in Table 23. The state of operation is controlled using the Linefeed Control register (direct Register 64). The open state turns off all currents into the external bipolar transistors and can be used in the presence of fault conditions on the line and to generate Open Switch Intervals (OSIs). TIP and RING are effectively tri-stated with a dc output impedance of about 150 k. The ProSLIC can also automatically enter the open state if it detects excessive power being consumed in the external bipolar transistors. See "2.1.5. Power Monitoring and Line Fault Detection" for more details. In the forward active and reverse active states, linefeed circuitry is on, and the audio signal paths are powered down. In the forward and reverse on-hook transmission states, audio signal paths are powered up to provide data transmission during an on-hook loop condition. The TIP Open state turns off all control currents to the external bipolar devices connected to TIP and provides an active linefeed on RING for ground start operation. The RING Open state provides similar operation with the RING drivers off and TIP active. The ringing state drives waveforms onto the line. programmable ringing 2.1.4. Loop Voltage and Current Monitoring The ProSLIC continuously monitors the TIP and RING voltages and external BJT currents. These values are available in registers 78-89. Table 24 on page 33 lists the values that are measured and their associated registers. An internal A/D converter samples the measured voltages and currents from the analog sense circuitry and translates them into the digital domain. The A/D updates the samples at a rate of 800 Hz. Two derived values are also reported: loop voltage and loop current. The loop voltage, VTIP - VRING, is reported as a 1-bit sign, 6-bit magnitude format. For ground start operation, the reported value is the RING voltage. The loop current, (IQ1 - IQ2 + IQ5 -IQ6)/2, is reported in a 1bit sign, 6-bit magnitude format. In RING open and TIP open states, the loop current is reported as (IQ1 - IQ2) + (IQ5 -IQ6). Rev. 1.61 31 Si3210/Si3211 Audio Codec Monitor A/D A/D A/D DSP D/A D/A SLIC DAC On-Chip External Components Battery Sense AC Control DC Control AC Sense Emitter Sense DC Sense RAC CAC AC Control Loop Si3201 QP QDN RBP TIP or RING DC Control Loop RDC RSE RBAT QN RE VBAT Figure 17. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown) Table 23. ProSLIC Linefeed Operations LF[2:0]* Linefeed State 000 Open 001 Forward Active 010 Forward On-Hook Transmission 011 TIP Open 100 Ringing 101 Reverse Active 110 Reverse On-Hook Transmission 111 Ring Open Description TIP and RING tri-stated VTIP > VRING VTIP > VRING; audio signal paths powered on TIP tri-stated, RING active; used for ground start Ringing waveform applied to TIP and RING VRING > VTIP VRING > VTIP; audio signal paths powered on RING tri-stated, TIP active Note: The linefeed register (LF) is located in direct Register 64. 32 Rev. 1.61 Si3210/Si3211 Table 24. Measured Real-Time Linefeed Interface Characteristics Parameter Measurement Range Resolution Register Bits Location* Loop Voltage Sense (VTIP - VRING) -94.5 to +94.5 V 1.5 V LVSP, LVS[6:0] Direct Register 78 Loop Current Sense -78.75 to +78.5 mA 1.25 mA LCSP, LCS[5:0] Direct Register 79 TIP Voltage Sense 0 to -95.88 V 0.376 V VTIP[7:0] Direct Register 80 RING Voltage Sense 0 to -95.88 V 0.376 V VRING[7:0] Direct Register 81 Battery Voltage Sense 1 (VBAT) 0 to -95.88 V 0.376 V VBATS1[7:0] Direct Register 82 Battery Voltage Sense 2 (VBAT) 0 to -95.88 V 0.376 V VBATS2[7:0] Direct Register 83 Transistor 1 Current Sense 0 to 81.35 mA 0.319 mA IQ1[7:0] Direct Register 84 Transistor 2 Current Sense 0 to 81.35 mA 0.319 mA IQ2[7:0] Direct Register 85 Transistor 3 Current Sense 0 to 9.59 mA 37.6 A IQ3[7:0] Direct Register 86 Transistor 4 Current Sense 0 to 9.59 mA 37.6 A IQ4[7:0] Direct Register 87 Transistor 5 Current Sense 0 to 80.58 mA 0.316 mA IQ5[7:0] Direct Register 88 Transistor 6 Current Sense 0 to 80.58 mA 0.316 mA IQ6[7:0] Direct Register 89 *Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. 2.1.5. Power Monitoring and Line Fault Detection In addition to reporting voltages and currents, the ProSLIC continuously monitors the power dissipated in each external bipolar transistor. Real-time output power of any one of the six linefeed transistors can be read by setting the Power Monitor Pointer (direct Register 76) to point to the desired transistor and then reading the Line Power Output Monitor (direct Register 77). The real-time power measurements are low-pass filtered and compared to a maximum power threshold. Maximum power thresholds and filter time constants are software-programmable and should be set for each transistor pair based on the characteristics of the transistors used. Table 25 describes the registers associated with this function. If the power in any external transistor exceeds the programmed threshold, a power alarm event is triggered. The ProSLIC sets the Power Alarm register bit, generates an interrupt (if enabled), and automatically enters the Open state (if AOPN = 1). This feature protects the external transistors from fault conditions and, combined with the loop voltage and current monitors, allows diagnosis of the type of fault condition present on the line. The value of each thermal low-pass filter pole is set according to the equation: 4096 3 Thermal LPF register = ------------------ 2 800 where is the thermal time constant of the transistor package, 4096 is the full range of the 12-bit register, and 800 is the sample rate in hertz. Generally = 3 seconds for SOT223 packages and = 0.16 seconds for SOT23, but check with the manufacturer for the package thermal constant of a specific device. For example, the power alarm threshold and low-pass filter values for Q5 and Q6 using a SOT223 package transistor are computed as follows: Thus, indirect Register 34 should be set to 150Dh. Rev. 1.61 33 Si3210/Si3211 P MAX 1.28 7 7 PPT56 = ------------------------------- 2 = ------------------ 2 = 5389 = 150Dh Resolution 0.0304 Note: The power monitor resolution for Q3 and Q4 is different from that of Q1, Q2, Q5, and Q6. Table 25. Associated Power Monitoring and Power Fault Registers Parameter Description/ Range Resolution Register Bits Location* Power Monitor Pointer 0 to 5 points to Q1 to Q6, respectively n/a PWRMP[2:0] Direct Register 76 Line Power Monitor Output 0 to 7.8 W for Q1, Q2, Q5, Q6 0 to 0.9 W for Q3, Q4 30.4 mW PWROM[7:0] Direct Register 77 Power Alarm Threshold, Q1 & Q2 0 to 7.8 W 30.4 mW PPT12[7:0] Indirect Register 32 Power Alarm Threshold, Q3 & Q4 0 to 0.9 W 3.62 mW PPT34[7:0] Indirect Register 33 Power Alarm Threshold, Q5 & Q6 0 to 7.8 W 30.4 mW PPT56[7:0] Indirect Register 34 3.62 mW Thermal LPF Pole, Q1 & Q2 See equation above. NQ12[7:0] Indirect Register 37 Thermal LPF Pole, Q3 & Q4 See equation above. NQ34[7:0] Indirect Register 38 Thermal LPF Pole, Q5 & Q6 See equation above. NQ56[7:0] Indirect Register 39 Power Alarm Interrupt Pending Bits 2 to 7 correspond to Q1 to Q6, respectively n/a QnAP[n+1], where n = 1 to 6 Direct Register 19 Power Alarm Interrupt Enable Bits 2 to 7 correspond to Q1 to Q6, respectively n/a QnAE[n+1], where n = 1 to 6 Direct Register 22 Power Alarm Automatic/Manual Detect 0 = manual mode 1 = enter open state upon power alarm n/a AOPN Direct Register 67 *Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31). 34 Rev. 1.61 Si3210/Si3211 LCS LVS Input Signal Processor ISP_OUT Digital LPF + Debounce Filter LCR Interrupt Logic LCIP - NCLR LCDI LFS LCVE HYSTEN LCIE Loop Closure Threshold LCRT LCRTL Figure 18. Loop Closure Detection 2.1.6. Loop Closure Transition Detection A loop closure transition event signals that the terminal equipment has gone from on-hook to off-hook or from offhook to on-hook; detection occurs while the ProSLIC linefeed is in its on-hook transmission or active states. The ProSLIC performs loop closure detection digitally using its on-chip monitor A/D converter. The functional blocks required to implement loop closure detection are shown in Figure 18. The primary input to the system is the Loop Current Sense value provided in the LCS register (direct Register 79). The LCS value is processed in the Input Signal Processor when the ProSLIC is in the on-hook transmission or active linefeed state, as indicated by the Linefeed Shadow register, LFS[2:0] (direct Register 64). The data then feeds into a programmable digital low-pass filter, which removes unwanted ac signal components before threshold detection. The output of the low-pass filter is compared to a programmable threshold, LCRT (indirect Register 28). The threshold comparator output feeds a programmable debouncing filter. The output of the debouncing filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, LCDI (direct Register 69). If the debounce interval has been satisfied, the LCR bit will change state to indicate that a valid loop closure transition has occurred. A loop closure transition interrupt is generated if enabled by the LCIE bit (direct Register 22). Table 26 lists the registers that must be written or monitored to correctly detect a loop closure condition. 2.1.7. Loop Closure Threshold Hysteresis Silicon revisions C and higher support the addition of programmable hysteresis to the loop closure threshold, which can be enabled by setting HYSTEN = 1 (direct Register 108, bit 0). The hysteresis is defined by LCRT (indirect Register 28) and LCRTL (indirect Register 43), which set the upper and lower bounds, respectively. 2.1.8. Voltage-Based Loop Closure Detection Silicon revisions C and higher also support an optional voltage-based loop closure detection mode, which is enabled by setting LCVE = 1 (direct Register 108, bit 2). In this mode, the loop voltage is compared to the loop closure threshold register (LCRT), which represents a minimum voltage threshold instead of a maximum current threshold. If hysteresis is also enabled, LCRT represents the upper voltage boundary, and LCRTL represents the lower voltage boundary for hysteresis. Although voltage-based loop closure detection is an option, the default current-based loop closure detection is recommended. Rev. 1.61 35 Si3210/Si3211 2.1.9. Linefeed Calibration Table 26. Register Set for Loop Closure Detection Parameter Loop Closure Interrupt Pending Loop Closure Interrupt Enable Loop Closure Threshold Loop Closure Threshold--Lower Loop Closure Filter Coefficient Loop Closure Detect Status (monitor only) Loop Closure Detect Debounce Interval Hysteresis Enable Voltage-Based Loop Closure Register An internal calibration algorithm corrects for internal and external component errors. The calibration is initiated by setting the CAL bit in direct Register 96. Upon completion of the calibration cycle, this bit is automatically reset. Location LCIP Direct Reg. 19 LCIE Direct Reg. 22 LCRT[5:0] Indirect Reg. 28 LCRTL[5:0] Indirect Reg. 43 NCLR[12:0] Indirect Reg. 35 LCR Direct Reg. 68 LCDI[6:0] Direct Reg. 69 HYSTEN Direct Reg. 108 LCVE Direct Reg. 108 It is recommended that a calibration be executed following system powerup. Upon release of the chip reset, the Si3210 will be in the open state. The calibration can be initiated after powering up the dc-dc converter and allowing it to settle for time (tsettle). Additional calibrations may be performed, but only one calibration should be necessary as long as the system remains powered up. During calibration, VBAT, VTIP, and VRING voltages are controlled by the calibration engine to provide the correct external voltage conditions for the algorithm. Calibration should be performed in the on-hook state. RING or TIP must not be connected to ground during the calibration. When using the Si3201, automatic calibration routines for RING gain mismatch and TIP gain mismatch should not be performed. Instead of running these two calibrations automatically, follow the instructions for manual calibration in "AN35: Si321x User's Quick Reference Guide". 2.2. Battery Voltage Generation and Switching The ProSLIC supports two modes of battery supply operation. First, the Si3210 integrates a dc-dc converter controller that dynamically regulates a single output voltage. This mode eliminates the need to supply large external battery voltages. Instead, it converts a single positive input voltage into the real-time battery voltage needed for any given state according to programmed linefeed parameters. Second, the Si3211 supports switching between high and low battery voltage supplies, as would a traditional monolithic SLIC. For single to low channel count applications, the Si3210 proves to be an economical choice, as the dc-dc converter eliminates the need to design and build highvoltage power supplies. For higher channel count applications where centralized battery voltage supply is economical or for modular legacy systems where battery voltage is already available, the Si3211 is recommended. 2.2.1. DC-DC Converter General Description (Si3210/Si3210M Only) The dc-dc converter dynamically generates the large negative voltages required to operate the linefeed interface. The Si3210 acts as the controller for a buck- 36 Rev. 1.61 Si3210/Si3211 boost dc-dc converter that converts a positive dc voltage into the desired negative battery voltage. In addition to eliminating external power supplies, this allows the Si3210 to dynamically control the battery voltage to the minimum required for any given mode of operation. Two different dc-dc circuit options are offered: a BJT/ inductor version and a MOSFET/transformer version. Due to the differences on the driving circuits, there are two different versions of the Si3210. The Si3210 supports the BJT/inductor circuit option, and the Si3210M version supports the MOSFET solution. The only difference between the two versions is the polarity of the DCFF pin with respect to the DCDRV pin. For the Si3210, DCDRV and DCFF are of opposite polarity. For the Si3210M, DCDRV and DCFF are the same polarity. Table 27 summarizes these differences. Table 27. Si3210 and Si3210M Differences Device DCFF Signal Polarity DCPOL Si3210 Si3210M = DCDRV = DCDRV 0 1 Notes: 1. DCFF signal polarity with respect to DCDRV signal. 2. Direct Register 93, bit 5; This is a read-only bit. Extensive design guidance on each of these circuits can be obtained from "AN45: Design Guide for the Si3210 DC-DC Converter" and from an interactive dc-dc converter design spreadsheet. Both of these documents are available on the Silicon Laboratories website (www.silabs.com). 2.2.2. BJT/Inductor Circuit Option Using Si3210 The BJT/Inductor circuit option shown in Figure 10 on page 18 offers a flexible, low-cost solution. Depending on selected L1 inductance value and the switching frequency, the input voltage (VDC) can range from 5 V to 30 V. Because of the nature of a dc-dc converter's operation, peak and average input currents can become large with small input voltages. Consider this when selecting the appropriate input voltage and power rating for the VDC power supply. For this solution, a PNP power BJT (Q7) switches the current flow through low ESR inductor L1. The Si3210 uses the DCDRV and DCFF pins to switch Q7 on and off. DCDRV controls Q7 through NPN BJT Q8. DCFF is ac-coupled to Q7 through capacitor C10 to assist R16 in turning off Q7. Therefore, DCFF must have opposite polarity to DCDRV, and the Si3210 (not Si3210M) must be used. Rev. 1.61 37 Si3210/Si3211 2.2.3. MOSFET/Transformer Circuit Option Using the Si3210M The MOSFET/transformer circuit option (shown in Figure 11 on page 20) offers higher power efficiencies across a larger input voltage range. Depending on the transformer's primary inductor value and the switching frequency, the input voltage (VDC) can range from 3.3 V to 35 V. Therefore, it is possible to power the entire ProSLIC solution from a single 3.3 V or 5 V power supply. By nature of a dc-dc converter's operation, peak and average input currents can become large with small input voltages. Consider this when selecting the appropriate input voltage and power rating for the VDC power supply (number of REN supported). For this solution, an N-channel power MOSFET (M1) switches the current flow through a power transformer, T1. T1 is specified in "AN45: Design Guide for the Si3210 DC-DC Converter" and includes several taps on the primary side to facilitate a wide range of input voltages. The Si3210M version of the Si3210 must be used for the application circuit depicted in Figure 11 because the DCFF pin is used to drive M1 directly and, therefore, must be the same polarity as DCDRV. DCDRV is not used in this circuit option; connecting DCFF and DCDRV together is not recommended. 2.2.4. DC-DC Converter Architecture (Si3210/Si3210M Only) The control logic for a pulse-width-modulated (PWM) dc-dc converter is incorporated in the Si3210. Output pins DCDRV and DCFF are used to switch a bipolar transistor or MOSFET. The polarity of DCFF is opposite that of DCDRV. The dc-dc converter circuit is powered on when the DCOF bit in the Powerdown Register (direct Register 14, bit 4) is cleared to 0. The switching regulator circuit within the Si3210 is a highperformance, pulse-width modulation controller. The control pins are driven by the PWM controller logic in the Si3210. The regulated output voltage (VBAT) is sensed by the SVBAT pin and is used to detect whether the output voltage is above or below an internal reference for the desired battery voltage. The dc monitor pins, SDCH and SDCL, monitor input current and voltage to the dc-dc converter external circuitry. If an overload condition is detected, the PWM controller will turn off the switching transistor for the remainder of a PWM period to prevent damage to external components. It is important that the proper value of R18 be selected to ensure safe operation. Guidance is given in AN45. 38 The PWM controller operates at a frequency set by the dc-dc Converter PWM register (direct Register 92). During a PWM period, the outputs of the control pins, DCDRV and DCFF, are asserted for a time given by the read-only PWM Pulse Width register (direct Register 94). The dc-dc converter must be off for some time in each cycle to allow the inductor or transformer to transfer its stored energy to the output capacitor, C9. This minimum off time can be set through the dc-dc Converter Switching Delay register, (direct Register 93). The number of 16.384 MHz clock cycles that the controller is off is equal to DCTOF (bits 0 through 4) plus 4. If the dc Monitor pins detect an overload condition, the dc-dc converter interrupts its conversion cycles regardless of the register settings to prevent component damage. These inputs should be calibrated by writing the DCCAL bit (bit 7) of the dc-dc Converter Switching Delay register, direct Register 93, after the dc-dc converter has been turned on. Because the Si3210 dynamically regulates its own battery supply voltage using the dc-dc converter controller, the battery voltage, VBAT, is offset from the negative-most terminal by a programmable voltage, VOV, to allow voltage headroom for carrying audio signals. As mentioned previously, the Si3210 dynamically adjusts VBAT to suit the particular circuit requirement. To illustrate this, the behavior of VBAT in the active state is shown in Figure 19. In the active state, the TIP-to-RING open circuit voltage is kept at VOC in the constant voltage region while the regulator output voltage VBAT = VCM + VOC + VOV. When the loop current attempts to exceed ILIM, the dc line driver circuit enters constant current mode allowing the TIP to RING voltage to track RLOOP. As the TIP terminal is kept at a constant voltage, it is the RING terminal voltage that tracks RLOOP and, as a result, the |VBAT| voltage will also track RLOOP. In this state, |VBAT| = ILIM x RLOOP + VCM +VOV. As RLOOP decreases below the VOC/ILIM mark, the regulator output voltage can continue to track RLOOP (TRACK = 1), or the RLOOP tracking mechanism is stopped when |VBAT| = |VBATL| (TRACK = 0). The former case is the more common application and provides the maximum power dissipation savings. In principle, the regulator output voltage can go as low as |VBAT| = VCM+ VOV, offering significant power savings. When TRACK = 0, |VBAT| will not decrease below VBATL. The RING terminal voltage, however, continues to decrease with decreasing RLOOP. Rev. 1.61 Si3210/Si3211 The power dissipation on the NPN bipolar transistor driving the RING terminal can become large and may require a higher power rating device. The non-tracking mode of operation is required by specific terminal equipment that, in order to initiate certain data transmission modes, goes briefly on-hook to measure the line voltage to determine whether there is any other off-hook terminal equipment on the same line. TRACK = 0 mode is desired since the regulator output voltage has long settling time constants (on the order of tens of milliseconds) and cannot change rapidly for TRACK = 1 mode. Therefore, the brief on-hook voltage measurement would yield approximately the same voltage as the off-hook line voltage and cause the terminal equipment to incorrectly sense another offhook terminal. VOC ILIM Constant I Region Constant V Region RLOOP VCM VTIP TR AC K= VBATL TRACK=0 VOC |VTIP - VRING| 1 VOV VRING VOV VBAT V Figure 19. VTIP, VRING, and VBAT in the Forward Active State Table 28. Associated Relevant DC-DC Converter Registers Parameter Range Resolution Register Bit Location DC-DC Converter Power-off Control N/A N/A DCOF Direct Register 14 DC-DC Converter Calibration Enable/Status N/A N/A DCCAL Direct Register 93 DC-DC Converter PWM Period 0 to 15.564 s 61.035 ns DCN[7:0] Direct Register 92 DC-DC Converter Min. Off Time (0 to 1.892 s) + 4 ns 61.035 ns DCTOF[4:0] Direct Register 93 High Battery Voltage--VBATH 0 to -94.5 V 1.5 V VBATH[5:0] Direct Register 74 Low Battery Voltage--VBATL 0 to -94.5 V 1.5 V VBATL[5:0] Direct Register 75 VOV 0 to -9 V or 0 to -13.5 V 1.5 V VMIND[3:0] VOV Indirect Register 41 Direct Register 66 Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31). Rev. 1.61 39 Si3210/Si3211 2.2.5. DC-DC Converter Enhancements Silicon revisions C and higher support two enhancements to the dc-dc converter. The first is a multi-threshold error control algorithm that enables the dc-dc converter to adjust more quickly to voltage changes. This option is enabled by setting DCSU = 1 (direct Register 108, bit 5). The second enhancement is an audio band filter that removes audio band noise from the dc-dc converter control loop. This option is enabled by setting DCFIL = 1 (direct Register 108, bit 1). 2.2.6. DC-DC Converter During Ringing When the ProSLIC enters the ringing state, it requires voltages well above those used in the active mode. The voltage to be generated and regulated by the dc-dc converter during a ringing burst is set using the VBATH register (direct Register 74). VBATH can be set between 0 and -94.5 V in 1.5 V steps. To avoid clipping the ringing signal, VBATH must be set larger than the ringing amplitude. At the end of each ringing burst, the dc-dc converter adjusts back to active state regulation as described above. 2.2.7. External Battery Switching (Si3211 Only) The Si3211 supports switching between two battery voltages. The circuit for external battery switching is defined in Figure 14. Typically, a high-voltage battery (e.g., -70 V) is used for on-hook and ringing states, and a low-voltage battery (e.g., -24 V) is used for the offhook condition. The ProSLIC uses an external transistor to switch between the two supplies. When the ProSLIC changes operating states, it automatically switches battery supplies if the automatic/ manual control bit, ABAT (direct Register 67, bit 3), is set. 40 For example, the ProSLIC will switch from high battery to low battery when it detects an off-hook event through either a ring trip or loop closure event. If automatic battery selection is disabled (ABAT = 0), the battery is selected by the Battery Feed Select bit, BATSL (direct Register 66, bit 1). Silicon revisions C and higher support the option to add a 60 ms debounce period to the battery switching circuit when transitioning from high battery to low battery. This option is enabled by setting SWDB = 1 (direct Register 108, bit 3). This debounce minimizes battery transitions in the case of pulse dialing or other quick onhook to off-hook transitions. 2.3. Tone Generation Two digital tone generators are provided in the ProSLIC. They allow the generation of a wide variety of single- or dual-tone frequency and amplitude combinations and spare the user the effort of generating the required POTS signaling tones on the PCM highway. DTMF, FSK (caller ID), call progress, and other tones can all be generated on-chip. The tones can be sent to either the receive or transmit paths (see Figure 25 on page 50). 2.3.1. Tone Generator Architecture A simplified diagram of the tone generator architecture is shown in Figure 20. The oscillator, active/inactive timers, interrupt block, and signal routing block are connected to give the user flexibility in creating audio signals. Control and status register bits are placed in the figure to indicate their association with the tone generator architecture. These registers are described in more detail in Table 29. Rev. 1.61 Si3210/Si3211 8 kHz Clock 8 kHz Clock OZn Zero Cross OnE 16-Bit Modulo Counter OAT Expire Zero Cross Logic OSSn Load Logic OIT Expire to TX Path Enable Two-Pole Resonance Register Oscillator Signal Routing Load to RX Path OSCn OATn INT Logic OATnE OITn OnIP REL* OnSO OSCnX OnIE OITnE INT Logic OnAP OSCnY OnAE *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively Figure 20. Simplified Tone Generator Diagram OSC1Y = 0 2.3.2. Oscillator Frequency and Amplitude Each of the two tone generators contains a two-pole resonate oscillator circuit with a programmable frequency and amplitude, which are programmed via indirect registers OSC1, OSC1X, OSC1Y, OSC2, OSC2X, and OSC2Y. The sample rate for the two oscillators is 8000 Hz. The equations are as follows: coeffn = cos(2fn/8000 Hz), 21336 coeff 2 = cos -------------------- = 0.49819 8000 OSC2 = 0.49819 (215) = 16324 = 3FC4h 1 15 OSC2X = --- 0.50181 --------------------- 2 - 1 0.5 = 2370 = 942h 4 1.49819 OSC2Y = 0 where fn is the frequency to be generated; The above computed values would be written to the corresponding registers to initialize the oscillators. Once the oscillators are initialized, the oscillator control registers can be accessed to enable the oscillators and direct their outputs. OSCn = coeffn x (215); Desired V rms 1 1 - coeff- 2 15 - 1 -----------------------------------OSCnX = --- ----------------------1.11 V rms 4 1 + coeff where desired Vrms is the amplitude to be generated; OSCnY = 0, n = 1 or 2 for oscillator 1 or oscillator 2, respectively. For example, in order to generate a DTMF digit of 8, the two required tones are 852 Hz and 1336 Hz. Assuming the generation of half-scale values (ignoring twist) is desired, the following values are calculated: 2852 coeff 1 = cos ----------------- = 0.78434 8000 15 OSC1 = 0.78434 2 = 25701 = 6465h 15 1 OSC1X = --- 0.21556 --------------------- 2 - 1 0.5 = 1424 = 590h 4 1.78434 2.3.3. Tone Generator Cadence Programming Each of the two tone generators contains two timers, one for setting the active period and one for setting the inactive period. The oscillator signal is generated during the active period and suspended during the inactive period. Both the active and inactive periods can be programmed from 0 to 8 seconds in 125 s steps. The active period time interval is set using OAT1 (direct registers 36 and 37) for tone generator 1 and OAT2 (direct registers 40 and 41) for tone generator 2. To enable automatic cadence for tone generator 1, define the OAT1 and OIT1 registers and then set the O1TAE bit (direct Register 32, bit 4) and O1TIE bit (direct Register 32, bit 3). This enables each of the timers to control the state of the Oscillator Enable bit, O1E (direct Register 32, bit 2). The 16-bit counter will begin counting until the active timer expires, at which Rev. 1.61 41 Si3210/Si3211 time the 16-bit counter will reset to zero and begin counting until the inactive timer expires. The cadence continues until the user clears the O1TAE and O1TIE control bits. The zero crossing detect feature can be implemented by setting the OZ1 bit (direct Register 32, bit 5). This ensures that each oscillator pulse ends without a dc component. The timing diagram in Figure 21 is an example of an output cadence using the zero crossing feature. One-shot oscillation can be achieved by enabling O1E and O1TAE. Direct control over the cadence can be achieved by controlling the O1E bit (direct Register 32, bit 2) directly if O1TAE and O1TIE are disabled. The operation of tone generator 2 is identical to that of tone generator 1 using its respective control registers. Note: Tone Generator 2 should not be enabled simultaneously with the ringing oscillator due to resource sharing within the hardware. Continuous phase frequency-shift keying (FSK) waveforms may be created using tone generator 1 (not available on tone generator 2) by setting the REL bit (direct Register 32, bit 6), which enables reloading of the OSC1, OSC1X, and OSC1Y registers at the expiration of the active timer, OAT1. Table 29. Associated Tone Generator Registers Tone Generator 1 Parameter Description / Range Register Bits Location Oscillator 1 Frequency Coefficient Sets oscillator frequency OSC1[15:0] Indirect Register 13 Oscillator 1 Amplitude Coefficient Sets oscillator amplitude OSC1X[15:0] Indirect Register 14 Oscillator 1 initial phase coefficient Sets initial phase OSC1Y[15:0] Indirect Register 15 Oscillator 1 Active Timer 0 to 8 seconds OAT1[15:0] Direct Registers 36 & 37 Oscillator 1 Inactive Timer 0 to 8 seconds OIT1[15:0] Direct Register 38 & 39 Oscillator 1 Control Status and control registers OSS1, REL, OZ1, O1TAE, O1TIE, O1E, O1SO[1:0] Direct Register 32 Tone Generator 2 Parameter Description/Range Register Location Oscillator 2 Frequency Coefficient Sets oscillator frequency OSC2[15:0] Indirect Register 16 Oscillator 2 Amplitude Coefficient Sets oscillator amplitude OSC2X[15:0] Indirect Register 17 Oscillator 2 initial phase coefficient Sets initial phase OSC2Y[15:0] Indirect Register 18 Oscillator 2 Active Timer 0 to 8 seconds OAT2[15:0] Direct Registers 40 & 41 Oscillator 2 Inactive Timer 0 to 8 seconds OIT2[15:0] Direct Register 42 & 43 Oscillator 2 Control Status and control registers OSS2, OZ2, O2TAE, O2TIE, O2E, O2SO[1:0] Direct Register 33 42 Rev. 1.61 Si3210/Si3211 O1E 0,1 ... ... , O AT1 0,1 ... ... , OIT1 0,1 ... ... , O AT1 0,1 ... ... ... OSS1 Tone Gen. 1 Signal Output Figure 21. Tone Generator Timing Diagram 2.3.4. Enhanced FSK Waveform Generation 2.4. Ringing Generation Silicon revisions C and higher support enhanced FSK generation capabilities, which can be enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REN = 1 (direct Register 32, bit 6). In this mode, the user can define mark (1) and space (0) attributes once during initialization by defining indirect registers 99-104. The user need only indicate 0-to-1 and 1-to-0 transitions in the information stream. By writing to FSKDAT (direct Register 52), this mode applies a 24 kHz sample rate to tone generator 1 to give additional resolution to timers and frequency generation. "AN32: Si321x Frequency Shift Keying (FSK) Modulation" gives detailed instructions on how to implement FSK in this mode. Additionally, sample source code is available from Silicon Laboratories upon request. The ProSLIC provides fully-programmable internal balanced ringing with or without a dc offset to ring a wide variety of terminal devices. All parameters associated with ringing (ringing frequency, waveform, amplitude, dc offset, and ringing cadence) are softwareprogrammable. Both sinusoidal and trapezoidal ringing waveforms are supported, and the trapezoidal crest factor is programmable. Ringing signals of up to 88 V peak or more can be generated, enabling the ProSLIC to drive a 5 REN (1380 + 40 F) ringer load across loop lengths of 2000 feet (160 ) or more. 2.3.5. Tone Generator Interrupts Both the active and inactive timers can generate their own interrupt to signal "on/off" transitions to the software. The timer interrupts for tone generator 1 can be individually enabled by setting the O1AE and O1IE bits (direct Register 21, bits 0 and 1, respectively). Timer interrupts for tone generator two are O2AE and O2IE (direct Register 21, bits 2 and 3, respectively). A pending interrupt for each of the timers is determined by reading the O1AP, O1IP, O2AP, and O2IP bits in the Interrupt Status 1 register (direct Register 18, bits 0 through 3, respectively). 2.4.1. Ringing Architecture The ringing generator architecture is nearly identical to that of the tone generator. The sinusoidal ringing waveform is generated using an internal two-pole resonance oscillator circuit with programmable frequency and amplitude. However, since ringing frequencies are very low compared to the audio band signaling frequencies, the ringing waveform is generated at a rate of 1 kHz instead of 8 kHz. The ringing generator has two timers that function the same as the tone generator timers. They allow on/off cadence settings of up to 8 seconds on and 8 seconds off. In addition to controlling ringing cadence, these timers control the transition into and out of the ringing state. Table 30 summarizes the list of registers used for ringing generation. Note: Tone generator 2 should not be enabled concurrently with the ringing generator due to resource sharing within the hardware. Rev. 1.61 43 Si3210/Si3211 Table 30. Registers for Ringing Generation Parameter Range/ Description Ringing Waveform Ringing Voltage Offset Enable Sine/Trapezoid Enabled/ Disabled Enabled/ Disabled Enabled/ Disabled Enabled/ Disabled 0 to 8 seconds 0 to 8 seconds Ringing State = 100b 0 to -94.5 V 0 to 94.5 V 15 to 100 Hz 0 to 94.5 V Sets initial phase for sinewave and period for trapezoid 0 to 22.5 V Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) High Battery Voltage Ringing dc voltage offset Ringing frequency Ringing amplitude Ringing initial phase Common Mode Bias Adjust During Ringing Register Bits TSWS RVO Location Direct Register 34 Direct Register 34 RTAE Direct Register 34 RTIE Direct Register 34 ROE Direct Register 34 RAT[15:0] RIT[15:0] LF[2:0] VBATH[5:0] ROFF[15:0] RCO[15:0] RNGX[15:0] RNGY[15:0] Direct Registers 48 and 49 Direct Registers 50 and 51 Direct Register 64 Direct Register 74 Indirect Register 19 Indirect Register 20 Indirect Register 21 Indirect Register 22 VCMR[3:0] Indirect Register 40 Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31). When the ringing state is invoked by writing LF[2:0] = 100 (direct Register 64), the ProSLIC will go into the ringing state and start the first ring. At the expiration of RAT, the ProSLIC will turn off the ringing waveform and will go to the on-hook transmission state. At the expiration of RIT, ringing will again be initiated. This process will continue as long as the two timers are enabled and the Linefeed Control register is set to the ringing state. 2.4.2. Sinusoidal Ringing To configure the ProSLIC for sinusoidal ringing, the frequency and amplitude are initialized by writing to the following indirect registers: RCO, RNGX, and RNGY. The equations for RCO, RNGX, RNGY are as follows: 15 Desired V PK 0 to 94.5 V 1 1 - coeff- 2 15 ----------------------------------------------------------------------RNGX = --- ----------------------96 V 4 1 + coeff RNGY = 0 The minimum allowed peak TIP-to-RING ringing voltage depends on the linefeed state. In the forward active linefeed state, the selected ringing amplitude (RNGX, Indirect Register 21) plus the selected ringing dc voltage offset (ROFF, Indirect Register 19) must be greater than the selected on-hook line voltage setting (VOC, direct Register 72). In the reverse active linefeed state, the selected ringing amplitude (RNGX, Indirect Register 21) minus the selected ringing dc voltage offset (ROFF, Indirect Register 19) must be greater than the selected on-hook line voltage setting (VOC, direct Register 72). RCO = coeff 2 Using a 70 VPK 20 Hz ringing signal as an example, the equations are as follows: 2f coeff = cos ----------------------- 1000 Hz 2 20 coeff = cos ----------------------- = 0.99211 1000 Hz where and f = desired ringing frequency in Hertz. 44 Rev. 1.61 Si3210/Si3211 For example, to generate a 71 VPK, 20 Hz ringing signal, the equations are as follows: 15 RCO = 0.99211 2 = 32509 = 7EFDh 15 70 1 RNGX = --- 0.00789 --------------------- 2 ------ = 376 = 0177h 4 96 1.99211 1 1 RNGY 20 Hz = --- ---------------- 8000 = 200 = C8h 2 20 Hz RNGY = 0 In addition, the user must select the sinusoidal ringing waveform by writing TSWS = 0 (direct Register 34, bit 0). 2.4.3. Trapezoidal Ringing In addition to the sinusoidal ringing waveform, the ProSLIC supports trapezoidal ringing. Figure 22 illustrates a trapezoidal ringing waveform with offset VROFF. 15 71 RNGX 71 V PK = ------ 2 = 24235 = 5EABh 96 For a crest factor of 1.3 and a period of 0.05 seconds (20 Hz), the rise time requirement is 0.0153 seconds. RCO 20 Hz, 1.3 crest factor 2 24235 = -------------------------------------- = 396 = 018Ch 0.0153 8000 In addition, the user must select the trapezoidal ringing waveform by writing TSWS = 1 in direct Register 34. 2.4.4. Ringing DC voltage Offset VTIP-RING A dc offset can be added to the ac ringing waveform by defining the offset voltage in ROFF (indirect Register 19). The offset, VROFF, is added to the ringing signal when RVO is set to 1 (direct Register 34, bit 1). The value of ROFF is calculated as follows: VROFF T=1/freq V ROFF 15 ROFF = ------------------ 2 96 tRISE time 2.4.5. Linefeed Considerations During Ringing Figure 22. Trapezoidal Ringing Waveform To configure the ProSLIC for trapezoidal ringing, the user should follow the same basic procedure as in the Sinusoidal Ringing section, but using the following equations: 1 RNGY = --- Period 8000 2 Desired V PK 15 RNGX = ----------------------------------- 2 96 V 2 RNGX RCO = --------------------------------t RISE 8000 RCO is a value added or subtracted from the waveform to ramp the signal up or down in a linear fashion. This value is a function of rise time, period, and amplitude, where rise time and period are related through the following equation for the crest factor of a trapezoidal waveform. Care must be taken to keep the generated ringing signal within the ringing voltage rails (GNDA and VBAT) to maintain proper biasing of the external bipolar transistors. If the ringing signal nears the rails, a distorted ringing signal and excessive power dissipation in the external transistors results. To prevent this invalid operation, set the VBATH value (direct Register 74) to a value higher than the maximum peak ringing voltage. The discussion below outlines the considerations and equations that govern the selection of the VBATH setting for a particular desired peak ringing voltage. First, the required amount of ringing overhead voltage, VOVR, is calculated based on the maximum value of current through the load, ILOAD,PK, the minimum current gain of Q5 and Q6, and a reasonable voltage required to keep Q5 and Q6 out of saturation. For ringing signals up to VPK = 87 V, VOVR = 7.5 V is a safe value. However, to determine VOVR for a specific case, use the equations below. 3 1 t RISE = --- T 1 - ----------2- 4 CF V AC , PK N REN I LOAD , PK = ------------------- + I OS = V AC , PK ------------------ + I OS R LOAD 6.9 k where T = ringing period, and CF = desired crest factor. Rev. 1.61 45 Si3210/Si3211 ringing to a dc linefeed state. This mode is enabled by setting ILIMEN = 1 (direct Register 108, bit 7). where: NREN is the ringing REN load (max value = 5), IOS is the offset current flowing in the line driver circuit (max value = 2 mA), and VAC,PK = amplitude of the ac ringing waveform. It is good practice to provide a buffer of a few more milliamperes for ILOAD,PK to account for possible line leakages, etc. The total ILOAD,PK current should be smaller than 80 mA. +1 V OVR = I LOAD , PK ------------- 80.6 + 1 V where is the minimum expected current gain of transistors Q5 and Q6. The minimum value for VBATH is therefore given by the following: VBATH = V AC , PK + V ROFF + V OVR The ProSLIC is designed to create a fully-balanced ringing waveform, meaning that the TIP and RING common mode voltage, (VTIP + VRING)/2, is fixed. This voltage is referred to as VCM_RING and is automatically set to the following: VBATH - VCMR VCM_RING = ---------------------------------------------2 VCMR is an indirect register, which provides the headroom by the ringing waveform with respect to the VBATH rail. The value is set as a 4-bit setting in indirect Register 40 with an LSB voltage of 1.5 V/LSB. Register 40 should be set with the calculated VOVR to provide voltage headroom during ringing. Silicon revisions C and higher support the option to briefly increase the maximum differential current limit between the voltage transition of TIP and RING from LCS Input Signal Processor ISP_OUT Digital LPF + 2.4.6. Ring Trip Detection A ring trip event signals that the terminal equipment has gone off-hook during the ringing state. The ProSLIC performs ring trip detection digitally using its on-chip A/ D converter. The functional blocks required to implement ring trip detection are shown in Figure 23. The primary input to the system is the loop current sense (LCS) value provided by the current monitoring circuitry and reported in direct Register 79. LCS data is processed by the input signal processor when the ProSLIC is in the ringing state as indicated by the Linefeed Shadow register (direct Register 64). The data then feeds into a programmable digital low-pass filter that removes unwanted ac signal components before threshold detection. The output of the low-pass filter is compared to a programmable threshold, RPTP (indirect Register 29). The threshold comparator output feeds a programmable debouncing filter. The output of the debouncing filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the ring trip debounce interval, RTDI[6:0] (direct Register 70). If the debounce interval has been satisfied, the RTP bit of direct Register 68 will be set to indicate that a valid ring trip has occurred. A ring trip interrupt is generated if enabled by the RTIE bit (direct Register 22). Table 31 lists the registers that must be written or monitored to correctly detect a ring trip condition. The recommended values for RPTP, NRTP, and RTDI vary according to the programmed ringing frequency. Register values for various ringing frequencies are given in Table 32. DBIRAW Debounce Filter RTP Interrupt Logic - NRTP RTDI LFS Ring Trip Threshold RPTP Figure 23. Ring Trip Detector 46 Rev. 1.61 RTIE RTIP Si3210/Si3211 Table 31. Associated Registers for Ring Trip Detection Parameter Register Location Ring Trip Interrupt Pending RTIP Direct Register 19 Ring Trip Interrupt Enable RTIE Direct Register 22 Ring Trip Detect Debounce Interval RTDI[6:0] Direct Register 70 Ring Trip Threshold RPTP[5:0] Indirect Register 29 Ring Trip Filter Coefficient NRTP[12:0] Indirect Register 36 RTP Direct Register 68 Ring Trip Detect Status (monitor only) Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31). Table 32. Recommended Ring Trip Values for Ringing Ringing Frequency NRTP RPTP RTDI Hz decimal hex decimal hex decimal hex 16.667 64 0200 34 mA 3600 15.4 ms 0F 20 100 0320 34 mA 3600 12.3 ms 0B 30 112 0380 34 mA 3600 8.96 ms 09 40 128 0400 34 mA 3600 7.5 ms 07 50 213 06A8 34 mA 3600 5 ms 05 60 256 0800 34 mA 3600 4.8 ms 05 2.5. Pulse Metering Generation There is an additional tone generator suitable for generating tones above the audio frequency. This oscillator is provided for the generation of billing tones that are typically 12 kHz or 16 kHz. The generator follows the same algorithm as described in "2.3. Tone Generation" on page 40 with the exception that the sample rate for computation is 64 kHz instead of 8 kHz. The equations are as follows: 2f coeff = cos -------------------------- 64000 Hz PLSCO = coeff 2 15 Desired V rms 1 1 - coeff 15 PLSX = --- ----------------------- 2 - 1 -------------------------------------------4 1 + coeff Full Scale V rms where full scale Vrms = 0.85 Vrms for a matched load. The initial phase of the pulse metering signal is set to 0 internally; so, there is no register to serve this purpose. The pulse metering generator timers and associated pulse metering timer registers are similar to those of the tone generators. These timers count 8 kHz sample periods like the other tones even though the sinusoid is generated at 64 kHz. - 1 Rev. 1.61 47 Si3210/Si3211 Table 33. Associated Pulse Metering Generator Registers Parameter Description / Range Register Bits Location Pulse Metering Frequency Coefficient Sets oscillator frequency PLSCO[15:0] Indirect Register 25 Pulse Metering Amplitude Coefficient Sets oscillator amplitude PLSX[15:0] Indirect Register 24 Pulse Metering Attack/Decay Ramp Rate 0 to PLSX (full amplitude) PLSD[15:0] Indirect Register 23 Pulse Metering Active Timer 0 to 8 seconds PAT[15:0] Direct Registers 44 & 45 Pulse Metering Inactive Timer 0 to 8 seconds PIT[15:0] Direct Register 46 & 47 Status and control registers PSTAT, PMAE, PMIE, PMOE Direct Register 35 Pulse Metering Control Note: The ProSLIC uses registers that are both directly and indirectly mapped. A direct register is one that is mapped directly. An indirect register is one that is accessed using the indirect access registers (direct registers 28 through 31). The pulse metering oscillator has a volume envelope (linear ramp) on the on/off transitions of the oscillator. The volume value is incremented by the value in the PLSD register (indirect Register 23) at an 8 kHz rate. The sinusoidal generator output is multiplied by this volume before being sent to the DAC. The volume will ramp from 0 to 7FFF in increments of PLSD; so, the value of PLSD will set the slope of the ramp. When the pulse metering signal is turned off, the volume will ramp to 0 by decrementing according to the value of PLSD. Pulse Metering Oscillator X To DAC Volum e 8 Khz +/- PLSD Clip to 7FFF or 0 Figure 24. Pulse Metering Volume Envelope 48 Rev. 1.61 Si3210/Si3211 2.6. DTMF Detection The dual-tone multi-frequency (DTMF) tone signaling standard is also known as touch tone. It is an in-band signaling system used to replace the pulse-dial signaling standard. In DTMF, two tones are used to generate a DTMF digit. One tone is chosen from four possible row tones, and one tone is chosen from four possible column tones. The sum of these tones constitutes one of 16 possible DTMF digits. 2.6.1. DTMF Detection Architecture DTMF detection is performed using a modified Goertzel algorithm to compute the dual frequency tone (DFT) for each of the eight DTMF frequencies as well as their second harmonics. At the end of the DFT computation, the squared magnitudes of the DFT results for the eight DTMF fundamental tones are computed. The row results are sorted to determine the strongest row frequency; the column frequencies are sorted as well. At the completion of this process, a number of checks are made to determine whether the strongest row and column tones constitute a DTMF digit. filter is available in the transmit path: THPF. THPF implements the high-pass attenuation requirements for signals below 65 Hz. The linear PCM data stream output from THPF is amplified by the transmit-path programmable gain amplifier, ADCG, which can be programmed from - dB to 6 dB. The DTMF decoder can receive the linear PCM data stream at this point to perform the digit extraction when enabled by the user. The final step in transmit path signal processing is the user-selectable A-law or -law compression, which can reduce the data stream word width to 8 bits. Depending on the PCM_Mode register selection, every 8-bit compressed serial data word will occupy one time slot on the PCM highway, or every 16-bit uncompressed serial data word will occupy two time slots on the PCM highway. The detection process is performed twice within the 45 ms minimum tone time. A digit must be detected on two consecutive tests following a pause to be recognized as a new digit. If all tests pass, an interrupt is generated, and the DTMF digit value is loaded into the DTMF register. If tones occur at the maximum rate of 100 ms per digit, the interrupt must be serviced within 85 ms so that the current digit is not overwritten by a new one. There is no buffering of the digit information. 2.7. Audio Path Unlike traditional SLICs, the codec function is integrated into the ProSLIC. The 16-bit codec offers programmable gain/attenuation blocks and several loopback modes. The signal path block diagram is shown in Figure 25. 2.7.1. Transmit Path In the transmit path, the analog signal fed by the external ac coupling capacitors is amplified by the analog transmit amplifier, ATX, prior to the A/D converter. The gain of the ATX is user-selectable to one of mute/-3.5/0/3.5 dB options. The main role of ATX is to coarsely adjust the signal swing to be as close as possible to the full-scale input of the A/D converter in order to maximize the signal-to-noise ratio of the transmit path. After passing through an anti-aliasing filter, the analog signal is processed by the A/D converter, producing an 8 kHz, 16-bit wide, linear PCM data stream. The standard requirements for transmit path attenuation for signals above 3.4 kHz are implemented as part of the combined decimation filter characteristic of the A/D converter. One more digital Rev. 1.61 49 TIP RING 50 Ibuf Off Chip Gm On Chip RAC XAC From Billing Tone DAC - + ARX ATX D/A ALM1 Analog Loopback A/D Transmit Path Interpolation Filter DLM Digital Loopback Decimation Filter ADCG RHPF DACG Dual Tone Generator THPF Figure 25. AC Signal Path Block Diagram HYBA H +- From Billing Tone DAC H HYBP + RXM Mute TXM Mute DTMF Decoder + /A-law Expander /A-law Compressor ALM2 Serial Input Full Analog Loopback Serial Output Digital RX Digital TX Si3210/Si3211 Rev. 1.61 Si3210/Si3211 2.7.2. Receive Path In the receive path, the optionally-compressed 8-bit data is first expanded to 16-bit words. The PCMF register bit can bypass the expansion process, in which case two 8-bit words are assembled into one 16bit word. DACG is the receive path programmable gain amplifier, which can be programmed from - dB to 6 dB. An 8 kHz, 16-bit signal is then provided to a D/A converter. The resulting analog signal is amplified by the analog receive amplifier, ARX, which is userselectable to one of several options: mute, -3.5, 0, or 3.5 dB. It is then applied at the input of the transconductance amplifier (Gm), which drives the offchip current buffer (IBUF). 2.7.3. Audio Characteristics The dominant source of distortion and noise in both the transmit and receive paths is the quantization noise introduced by the -law or the A-law compression process. Figure 1 on page 6 specifies the minimum signal-to-noise-and-distortion ratio for either path for a sine wave input of 200 Hz to 3400 Hz. Both the -law and the A-law speech encoding allow the audio codec to transfer and process audio signals larger than 0 dBm0 without clipping. The maximum PCM code is generated for a -law encoded sine wave of 3.17 dBm0 or an A-law encoded sine wave of 3.14 dBm0. The ProSLIC overload clipping limits are driven by the PCM encoding process. Figure 2 on page 6 shows the acceptable limits for the analog-to-analog fundamental power transfer-function, which bounds the behavior of ProSLIC. The transmit path gain distortion versus frequency is shown in Figure 3 on page 7. The same figure also presents the minimum required attenuation for any outof-band analog signal that may be applied on the line. Note the presence of a high-pass filter transfer function that ensures at least 30 dB of attenuation for signals below 65 Hz. The low-pass filter transfer function that attenuates signals above 3.4 kHz has to exceed the requirements specified by the equations in Figure 3 on page 7 and is implemented as part of the A-to-D converter. The receive path transfer function requirement, shown in Figure 4 on page 8, is very similar to the transmit path transfer function. The most notable difference is the absence of the high-pass filter portion. The only other differences are the maximum 2 dB of attenuation at 200 Hz (as opposed to 3 dB for the transmit path) and the 28 dB of attenuation for any frequency above 4.6 kHz. The PCM data rate is 8 kHz and, thus, no frequencies greater than 4 kHz can be digitally encoded in the data stream. From this point of view, at frequencies greater than 4 kHz, the plot in Figure 4 should be interpreted as the maximum allowable magnitude of any spurious signals that are generated when a PCM data stream representing a sine wave signal in the range of 300 Hz to 3.4 kHz at a level of 0 dBm0 is applied at the digital input. The group delay distortion in either path is limited to no more than the levels indicated in Figure 5 on page 9. The reference in Figure 5 is the smallest group delay for a sine wave in the range of 500 Hz to 2500 Hz at 0 dBm0. The block diagram for the voice-band signal processing paths is shown in Figure 25. Both the receive and transmit paths employ the optimal combination of analog and digital signal processing to provide maximum performance while offering sufficient flexibility to allow users to optimize for their particular ProSLIC application. All programmable signal-processing blocks are indicated symbolically in Figure 25 by a dashed arrow across them. The two-wire (TIP/RING) voiceband interface to the ProSLIC is implemented using a small number of external components. The receive path interface consists of a unity-gain current buffer, IBUF, while the transmit path interface is simply an ac coupling capacitor. Signal paths, although implemented differentially, are shown as single-ended for simplicity. 2.7.4. Transhybrid Balance The ProSLIC provides programmable transhybrid balance with gain block H. (See Figure 25.) In the ideal case, where the synthesized SLIC impedance exactly matches the subscriber loop impedance, the transhybrid balance should be set to subtract a -6 dB level from the transmit path signal. The transhybrid balance gain can be adjusted from -2.77 dB to +4.08 dB around the ideal setting of -6 dB by programming the HYBA[2:0] bits of the Hybrid Control register (direct Register 11). Note that adjusting any of the analog or digital gain blocks will not require any modification of the transhybrid balance gain block, as the transhybrid gain is subtracted from the transmit path signal prior to any gain adjustment stages. If desired, the transhybrid balance can also be disabled using the appropriate register setting. 2.7.5. Loopback Testing Four loopback test options are available in the ProSLIC: Rev. 1.61 The full analog loopback (ALM2) tests almost all the circuitry of both the transmit and receive paths. The compressed 8-bit word transmit data stream is fed back serially to the input of the receive path expander. (See Figure 25.) The signal path starts with the analog signal at the input of the transmit 51 Si3210/Si3211 path and ends with an analog signal at the output of the receive path. An additional analog loopback (ALM1) takes the digital stream at the output of the A/D converter and feeds it back to the D/A converter. (See Figure 25.) The signal path starts with the analog signal at the input of the transmit path and ends with an analog signal at the output of the receive path. This loopback option allows testing of the analog signal processing circuitry of the Si3210 to be carried out completely independently of any activity in the DSP. The full digital loopback tests almost all the circuitry of both the transmit and receive paths. The analog signal at the output of the receive path are fed back to the input of the transmit path by way of the hybrid filter path. (See Figure 25.) The signal path starts with 8-bit PCM data input to the receive path and ends with 8-bit PCM data at the output of the transmit path. The user can bypass the companding process and interface directly to the 16-bit data. An additional digital loopback (DLM) takes the digital stream at the input of the D/A converter in the receive path and feeds it back to the transmit A/D digital filter. The signal path starts with 8-bit PCM data input to the receive path and ends with 8-bit PCM data at the output of the transmit path. This loopback option allows the testing of the digital signal processing circuitry of the Si3210 to be carried out completely independently of any analog signal processing activity. The user can bypass the companding process and interface directly to the 16bit data. 2.8. Two-Wire Impedance Matching The ProSLIC provides on-chip, programmable, two-wire impedance settings to meet a wide variety of worldwide two-wire return loss requirements. The two-wire impedance is programmed by loading one of the eight available impedance values into the TISS[2:0] bits of the Two-Wire Impedance Synthesis Control register (direct Register 10). If direct Register 10 is not user-defined, the default setting of 600 will be loaded into the TISS register. Real and complex two-wire impedances are realized by internal feedback of a programmable amplifier (RAC), a switched capacitor network (XAC), and a transconductance amplifier (Gm). (See Figure 25.) RAC creates the real portion, and XAC creates the imaginary portion of Gm's input. Gm then creates a current that models the desired impedance value to the subscriber loop. The differential ac current is fed to the subscriber loop via the ITIPP and IRINGP pins through an off-chip current buffer, IBUF, which is implemented using 52 transistors Q1 and Q2 (see Figure 13 on page 24). Gm is referenced to an off-chip resistor (R15). The ProSLIC also provides a means of compensating for degraded subscriber loop conditions involving excessive line capacitance (leakage). The CLC[1:0] bits of direct Register 10 increase the ac signal magnitude to compensate for the additional loss at the high end of the audio frequency range. The default setting of CLC[2:0] assumes no line capacitance. Silicon revisions C and higher support the option to remove the internal reference resistor used to synthesize ac impedances for 600 + 2.16 F and 900 + 2.16 F settings so that an external resistor reference may be used. This option is enabled by setting ZSEXT = 1 (direct Register 108, bit 4). 2.9. Clock Generation The ProSLIC will generate the necessary internal clock frequencies from the PCLK input. PCLK must be synchronous to the 8 kHz FSYNC clock and run at one of the following rates: 256 kHz, 512 kHz, 768 kHz, 1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz or 8.192 MHz. (Note that 768 kHz and 1.536 MHz are not valid rates for GCI mode.) The ratio of the PCLK rate to the FSYNC rate is determined via a counter clocked by PCLK. The three-bit ratio information is automatically transferred into an internal register, PLL_MULT, following a reset of the ProSLIC. The PLL_MULT is used to control the internal PLL, which multiplies PCLK as needed to generate the 16.384 MHz rate needed to run the internal filters and other circuitry. The PLL clock synthesizer settles very quickly following powerup. However, the settling time depends on the PCLK frequency, and it can be approximated by the following equation: 64 T SETTLE = ----------------F PCLK 2.10. Interrupt Logic The ProSLIC is capable of generating interrupts for the following events: Rev. 1.61 Loop current/ring ground detected Ring trip detected Power alarm DTMF digit detected Active timer 1 expired Inactive timer 1 expired Active timer 2 expired Inactive timer 2 expired Ringing active timer expired Ringing inactive timer expired Si3210/Si3211 Pulse metering active timer expired Pulse metering inactive timer expired Indirect register access complete The interface to the interrupt logic consists of six registers. Three interrupt status registers contain one bit for each of the above interrupt functions. These bits will be set when an interrupt is pending for the associated resource. Three interrupt enable registers also contain one bit for each interrupt function. In the case of the interrupt enable registers, the bits are active high. Refer to the appropriate functional description section for operational details of the interrupt functions. When a resource reaches an interrupt condition, it will signal an interrupt to the interrupt control block. The interrupt control block will then set the associated bit in the interrupt status register if the enable bit for that interrupt is set. The INT pin is a NOR of the bits of the interrupt status registers. Therefore, if a bit in the interrupt status registers is asserted, IRQ will assert low. Upon receiving the interrupt, the interrupt handler should read interrupt status registers to determine which resource is requesting service. To clear a pending interrupt, write the desired bit in the appropriate interrupt status register to 1. Writing a 0 has no effect. This provides a mechanism for clearing individual bits when multiple interrupts occur simultaneously. While the interrupt status registers are non-zero, the INT pin will remain asserted. 2.11. Serial Peripheral Interface The control interface to the ProSLIC is a 4-wire interface modeled after commonly-available micro-controller and serial peripheral devices. The interface consists of a clock (SCLK), chip select (CS), serial data input (SDI), and serial data output (SDO). Data is transferred a byte at a time with each register access consisting of a pair of byte transfers. Figures 26 and 27 illustrate read and write operation in the SPI bus. The first byte of the pair is the command/address byte. The MSB of this byte indicates a register read when 1 and a register write when 0. The remaining seven bits of the command/address byte indicate the address of the register to be accessed. The second byte of the pair is the data byte. Because the falling edge of CS provides resynchronization of the SPI state machine in the event of a framing error, it is recommended (but not required) that CS be taken high between byte transfers as shown in Figures 26 and 27. During a read operation, the SDO becomes active and the 8-bit contents of the register are driven out MSB first. The SDO will be high impedance on either the falling edge of SCLK following the LSB, or the rising of CS as specified by the SPIM bit (direct Register 0, bit 6). SDI is a "don't care" during the data portion of read operations. During write operations, data is driven into the ProSLIC via the SDI pin MSB first. The SDO pin will remain high impedance during write operations. Data always transitions with the falling edge of the clock and is latched on the rising edge. The clock should return to a logic high when no transfer is in progress. Indirect registers are accessed through direct registers 29 through 30. Instructions on how to access them is described in "3. Control Registers" beginning on page 60. There are a number of variations of usage on this four-wire interface: Continuous Clocking: During continuous clocking, the data transfers are controlled by the assertion of the CS pin. CS must assert before the falling edge of SCLK on which the first bit of data is expected during a read cycle, and must remain low for the duration of the 8-`bit transfer (command/address or data). SDI/SDO Wired Operation: Independent of the clocking options described, SDI and SDO can be treated as two separate lines or wired together if the master is capable of tristating its output during the data byte transfer of a read operation. Daisy Chain Mode: This mode allows communication with banks of up to eight ProSLIC devices using one chip select signal. When the SPIDC bit in the SPI Mode Select register is set, data transfer mode changes to a 3-byte operation: a chip select byte, an address/control byte, and a data byte. Using the circuit shown in Figure 28, a single device may select from the bank of devices by setting the appropriate chip select bit to 1. Each device uses the LSB of the chip select byte, shifts the data right by one bit, and passes the chip select byte using the SDITHRU pin to the next device in the chain. Address/control and data bytes are unaltered. Rev. 1.61 53 Si3210/Si3211 Don't Care SCLK CS SDI 0 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d2 d1 d0 SDO High Impedance Figure 26. Serial Write 8-Bit Mode Don't Care SCLK CS SDI 1 a6 a5 a4 a3 a2 a1 Don't Care a0 SDO d7 High Impedance d6 Figure 27. Serial Read 8-Bit Mode 54 Rev. 1.61 d5 d4 d3 Si3210/Si3211 SDO CPU CS SDI0 SDI CS SDO SDI SDITHRU SDI1 SDI CS SDO SDITHRU SDI2 SDI CS SDO SDITHRU SDI3 SDI CS SDO SDITHRU Chip Select Byte Address Byte Data Byte SCLK SDI0 C7 C6 C5 C4 C3 C2 C1 C0 R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDI1 - C7 C6 C5 C4 C3 C2 C1 R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDI2 - - C7 C6 C5 C4 C3 C2 R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDI3 - - - C7 C6 C5 C4 C3 R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the LSB of the chip select byte for its chip select. Figure 28. SPI Daisy Chain Mode Rev. 1.61 55 Si3210/Si3211 2.12. PCM Interface The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as PCM Mode Select (direct Register 1), PCM Transmit Start Count (direct registers 2 and 3), and PCM Receive Start Count (direct registers 4 and 5). The interface can be configured to support from 4 to 128 8-bit timeslots in each frame. This corresponds to PCLK frequencies of 256 kHz to 8.192 MHz in power of 2 increments. (768 kHz and 1.536 MHz are also available, but these frequencies are not valid for GCI mode.) Timeslots for data transmission and reception are independently configured using the TXS and RXS registers. By setting the correct starting point of the data, the ProSLIC can be configured to support long FSYNC and short FSYNC variants as well as IDL2 8-bit, 10-bit, B1 and B2 channel time slots. DTX data is high-impedance except for the duration of the 8-bit PCM transmit. DTX will return to high impedance either on the negative edge of PCLK during the LSB or on the positive edge of PCLK following the LSB. This is based on the setting of the TRI bit of the PCM Mode Select register. Tristating on the negative edge allows the transmission of data by multiple sources in adjacent timeslots without the risk of driver contention. In addition to 8-bit data modes, there is a 16-bit mode provided. This mode can be activated via the PCMT bit of the PCM Mode Select register. GCI timing is also supported in which the duration of a data bit is two PCLK cycles. This mode is also activated via the PCM Mode Select register. Setting the TXS or RXS register greater than the number of PCLK cycles in a sample period will stop data transmission because TXS or RXS will never equal the PCLK count. Figures 29-32 illustrate the usage of the PCM highway interface to adapt to common PCM standards. PCLK FSYNC 0 PCLK_CNT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX MSB LSB MSB LSB DTX HI-Z HI-Z Figure 29. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1) PCLK FSYNC 0 PCLK_CNT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DRX MSB LSB MSB LSB DTX HI-Z HI-Z Figure 30. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0) 56 Rev. 1.61 17 18 Si3210/Si3211 PCLK FSYNC 0 PCLK_CNT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX MSB LSB MSB LSB DTX HI-Z HI-Z Figure 31. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10) PCLK FSYNC 0 PCLK_CNT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DRX MSB LSB DTX HI-Z HI-Z Figure 32. GCI Example, Timeslot 1 (TXS/RXS = 0) 2.13. Companding The ProSLIC supports both -255 Law and A-Law companding formats in addition to linear data. These 8-bit companding schemes follow a segmented curve formatted as sign bit, three chord bits, and four step bits. -255 Law is more commonly used in North America and Japan, while A-Law is primarily used in Europe. Data format is selected via the PCMF register. Tables 34 and 35 define the -Law and A-Law encoding formats. Rev. 1.61 57 Si3210/Si3211 Table 34. -Law Encode-Decode Characteristics1,2 Segment Number #Intervals X Interval Size 8 16 X 256 7 16 X 128 6 16 X 64 5 16 X 32 4 16 X 16 3 16 X 8 2 16 X 4 15 X 2 1 __________________ 1 X 1 Value at Segment Endpoints 8159 . . . 4319 4063 Digital Code 10000000b 8031 10001111b 4191 . . . 2143 2015 10011111b 2079 . . . 1055 991 10101111b 1023 . . . 511 479 10111111b 495 . . . 239 223 11001111b 231 . . . 103 95 11011111b 99 . . . 35 31 11101111b 33 . . . 3 1 0 11111110b 11111111b 2 0 Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. Digital code includes inversion of all magnitude bits. 58 Decode Level Rev. 1.61 Si3210/Si3211 Table 35. A-Law Encode-Decode Characteristics1,2 Segment Number #intervals X interval size 7 16 X 128 6 16 X 64 5 16 X 32 4 16 X 16 3 16 X 8 2 16 X 4 32 X 2 1 Value at segment endpoints Digital Code Decode Level 10101010b 4032 10100101b 2112 . . . 1088 1024 10110101b 1056 . . . 544 512 10000101b 528 . . . 272 256 10010101b 264 . . . 136 128 11100101b 132 . . . 68 64 11110101b 66 . . . 2 0 11010101b 1 4096 3968 . . 2176 2048 Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values. 2. Digital code includes inversion of all even numbered bits. Rev. 1.61 59 Si3210/Si3211 3. Control Registers Note: Any register not listed here is reserved and must not be written. Table 36. Direct Register Summary Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Setup 0 SPI Mode Select 1 PCM Mode Select 2 PCM Transmit Start Count--Low Byte 3 PCM Transmit Start Count--High Byte 4 PCM Receive Start Count--Low Byte 5 PCM Receive Start Count--High Byte 6 Digital Input/Output Control SPIDC SPIM PNI[1:0] PNI2 PCME RNI[3:0] PCMF[1:0] PCMT GCI TRI TXS[7:0] TXS[9:8] RXS[7:0] RXS[9:8] DOUT1 DIO21 DIO11 PD21 PD11 ALM2 DLM ALM1 Audio 8 Audio Path Loopback Control 9 Audio Gain Control 10 Two-Wire Impedance Synthesis Control 11 Hybrid Control RXHP TXHP TXM RXM CLC[1:0] ATX[1:0] ARX[1:0] TISE TISS[2:0] HYBP[2:0] HYBA[2:0] Powerdown 14 Powerdown Control 1 PMON DCOF2 MOF 15 Powerdown Control 2 ADCM ADCON DACM DACON GMM GMON BIASOF SLICOF Interrupts 18 Interrupt Status 1 PMIP PMAP RGIP RGAP O2IP O2AP O1IP O1AP 19 Interrupt Status 2 Q6AP Q5AP Q4AP Q3AP Q2AP Q1AP LCIP RTIP 20 Interrupt Status 3 CMCP INDP DTMFP 21 Interrupt Enable 1 PMIE PMAE RGIE RGAE O2IE O2AE O1IE O1AE 22 Interrupt Enable 2 Q6AE Q5AE Q4AE Q3AE Q2AE Q1AE LCIE RTIE 23 Interrupt Enable 3 CMCE INDE DTMFE 24 Decode Status VAL Indirect Register Access Notes: 1. Si3211 only. 2. Si3210 only. 60 Rev. 1.61 DIG[3:0] Si3210/Si3211 Table 36. Direct Register Summary (Continued) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 28 Indirect Data Access-- Low Byte IDA[7:0] 29 Indirect Data Access-- High Byte IDA[15:8] 30 Indirect Address 31 Indirect Address Status Bit 2 Bit 1 Bit 0 IAA[7:0] IAS Oscillators 32 Oscillator 1 Control OSS1 33 Oscillator 2 Control 34 REL OZ1 O1TAE O1TIE O1E O1SO[1:0] OSS2 OZ2 O2TAE O2TIE O2E O2SO[1:0] Ringing Oscillator Control RSS RDAC RTAE RTIE ROE 35 Pulse Metering Oscillator Control PSTAT PMAE PMIE PMOE 36 Oscillator 1 Active Timer--Low Byte OAT1[7:0] 37 Oscillator 1 Active Timer--High Byte OAT1[15:8] 38 Oscillator 1 Inactive Timer--Low Byte OIT1[7:0] 39 Oscillator 1 Inactive Timer--High Byte OIT1[15:8] 40 Oscillator 2 Active Timer--Low Byte OAT2[7:0] 41 Oscillator 2 Active Timer--High Byte OAT2[15:8] 42 Oscillator 2 Inactive Timer--Low Byte OIT2[7:0] 43 Oscillator 2 Inactive Timer--High Byte OIT2[15:8] 44 Pulse Metering Oscillator Active Timer-- Low Byte PAT[7:0] 45 Pulse Metering Oscillator Active Timer-- High Byte PAT[15:8] 46 Pulse Metering Oscillator Inactive Timer--Low Byte RVO TSWS PIT[7:0] Notes: 1. Si3211 only. 2. Si3210 only. Rev. 1.61 61 Si3210/Si3211 Table 36. Direct Register Summary (Continued) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 47 Pulse Metering Oscillator Inactive Timer--High Byte PIT[15:8] 48 Ringing Oscillator Active Timer--Low Byte RAT[7:0] 49 Ringing Oscillator Active Timer--High Byte RAT[15:8] 50 Ringing Oscillator Inactive Timer--Low Byte RIT[7:0] 51 Ringing Oscillator Inactive Timer--High Byte RIT[15:8] 52 FSK Data Bit 2 Bit 1 Bit 0 FSKDAT SLIC 63 Loop Closure Debounce Interval for Automatic Ringing LCD[7:0] 64 Linefeed Control 65 External Bipolar Transistor Control 66 Battery Feed Control 67 Automatic/Manual Control 68 Loop Closure/Ring Trip Detect Status 69 Loop Closure Debounce Interval LCDI[6:0] 70 Ring Trip Detect Debounce Interval RTDI[6:0] 71 Loop Current Limit 72 On-Hook Line Voltage 73 Common Mode Voltage 74 High Battery Voltage VBATH[5:0] 75 Low Battery Voltage VBATL[5:0] 76 Power Monitor Pointer 77 Line Power Output Monitor 78 Loop Voltage Sense LFS[2:0] SQH CBY MNCM MNDIF ETBE ETBO[1:0] VOV2 FVBAT2 SPDS ABAT ETBA[1:0] BATSL1 TRACK2 AORD AOLD AOPN DBIRAW RTP LCR ILIM[2:0] VSGN VOC[5:0] VCM[5:0] PWRMP[2:0] PWROM[7:0] LVSP LVS[5:0] Notes: 1. Si3211 only. 2. Si3210 only. 62 LF[2:0] Rev. 1.61 Si3210/Si3211 Table 36. Direct Register Summary (Continued) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 LCSP Bit 2 79 Loop Current Sense 80 TIP Voltage Sense 81 RING Voltage Sense 82 Battery Voltage Sense 1 VBATS1[7:0] 83 Battery Voltage Sense 2 VBATS2[7:0] 84 Transistor 1 Current Sense IQ1[7:0] 85 Transistor 2 Current Sense IQ2[7:0] 86 Transistor 3 Current Sense IQ3[7:0] 87 Transistor 4 Current Sense IQ4[7:0] 88 Transistor 5 Current Sense IQ5[7:0] 89 Transistor 6 Current Sense IQ6[7:0] 92 DC-DC Converter PWM Period 93 DC-DC Converter Switching Delay 94 DC-DC Converter PWM Pulse Width 95 Reserved 96 Calibration Control/ Status Register 1 97 Calibration Control/ Status Register 2 98 RING Gain Mismatch Calibration Result CALGMR[4:0] 99 TIP Gain Mismatch Calibration Result CALGMT[4:0] 100 Differential Loop Current Gain Calibration Result CALGD[4:0] 101 Common Mode Loop Current Gain Calibration Result CALGC[4:0] Bit 1 Bit 0 LCS[5:0] VTIP[7:0] VRING[7:0] DCN[7:0]2 DCCAL2 DCPOL2 DCTOF[4:0]2 DCPW[7:0]2 CAL CALSP CALR CALT CALD CALC CALIL CALM1 CALM2 CALDAC CALADC CALCM Notes: 1. Si3211 only. 2. Si3210 only. Rev. 1.61 63 Si3210/Si3211 Table 36. Direct Register Summary (Continued) Register Name 102 Current Limit Calibration Result 103 Monitor ADC Offset Calibration Result 104 Analog DAC/ADC Offset 105 DAC Offset Calibration Result 106 Common Mode Balance Calibration Result 107 DC Peak Current Calibration Result 108 Enhancement Enable Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 CALGIL[3:0] CALMG1[3:0] CALMG2[3:0] DACP DACN ADCP ADCN DACOF[7:0] CMBAL[5:0] CMDCPK[3:0] ILIMEN FSKEN DCSU2 Notes: 1. Si3211 only. 2. Si3210 only. 64 Bit 4 Rev. 1.61 ZSEXT SWDB LCVE DCFIL2 HYSTEN Si3210/Si3211 Register 0. SPI Mode Select Bit D7 D6 D5 D4 D3 D2 D1 Name SPIDC SPIM PNI[1:0] RNI[3:0] Type R/W R/W R R D0 Reset settings = 00xx_xxxx Bit Name Function 7 SPIDC 6 SPIM 5:4 PNI[1:0] Part Number Identification. 00 = Si3210 01 = Si3211 10 = Unused 11 = Si3210M 3:0 RNI[3:0] Revision Number Identification. 0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc. SPI Daisy Chain Mode Enable. 0 = Disable SPI daisy chain mode. 1 = Enable SPI daisy chain mode. SPI Mode. 0 = Causes SDO to tri-state on rising edge of SCLK of LSB. 1 = Normal operation; SDO tri-states on rising edge of CS. Rev. 1.61 65 Si3210/Si3211 Register 1. PCM Mode Select Bit D7 Name PNI2 D6 Type D5 D4 D3 D1 D0 PCME PCMF[1:0] PCMT GCI TRI R/W R/W R/W R/W R/W Reset settings = 0000_1000 Bit Name 7 PNI2 6 Reserved 5 PCME 4:3 PCMF[1:0] 2 PCMT 1 GCI GCI Clock Format. 0 = 1 PCLK per data bit. 1 = 2 PCLKs per data bit. 0 TRI Tri-state Bit 0. 0 = Tri-state bit 0 on positive edge of PCLK. 1 = Tri-state bit 0 on negative edge of PCLK. 66 D2 Function Part Number Identification 2. 0 = Si3210/11 family. 1 = Si3215/16 family. Read returns zero. PCM Enable. 0 = Disable PCM transfers. 1 = Enable PCM transfers. PCM Format. 00 = A-Law 01 = -Law 10 = Reserved 11 = Linear PCM Transfer Size. 0 = 8-bit transfer. 1 = 16-bit transfer. Rev. 1.61 Si3210/Si3211 Register 2. PCM Transmit Start Count--Low Byte Bit D7 D6 D5 D4 D3 Name TXS[7:0] Type R/W D2 D1 D0 Reset settings = 0000_0000 Bit Name Function 7:0 TXS[7:0] PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data transmission begins. See Figure 29 on page 56. Register 3. PCM Transmit Start Count--High Byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Name TXS[9:8] Type R/W Reset settings = 0000_0000 Bit Name Function 7:2 Reserved Read returns zero. 1:0 TXS[9:8] PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data transmission begins. See Figure 29 on page 56. Register 4. PCM Receive Start Count--Low Byte Bit D7 D6 D5 D4 D3 Name RXS[7:0] Type R/W D2 D1 D0 Reset settings = 0000_0000 Bit Name 7:0 RXS[7:0] Function PCM Receive Start Count. PCM receive start count equals the number of PCLKs following FSYNC before data reception begins. See Figure 29 on page 56. Rev. 1.61 67 Si3210/Si3211 Register 5. PCM Receive Start Count--High Byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RXS[9:8] Type R/W Reset settings = 0000_0000 Bit Name Function 7:2 Reserved Read returns zero. 1:0 RXS[9:8] PCM Receive Start Count. PCM receive start count equals the number of PCLKs following FSYNC before data reception begins. See Figure 29 on page 56. Register 6. Digital Input/Output Control Si3210 Bit D7 D6 D5 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 Name DOUT DIO2 DIO1 PD2 PD1 Type R/W R/W R/W R/W R/W Name Type Reset settings = 0000_0000 Si3211 Bit D7 D6 D5 Reset settings = 0000_0000 68 Rev. 1.61 Si3210/Si3211 Bit Name Function 7:5 Reserved 4 DOUT DOUT Pin Output Data (Si3211 only). 0 = DOUT pin driven low. 1 = DOUT pin driven high. Si3210 = Reserved. 3 DIO2 DIO2 Pin Input/Output Direction (Si3211 only). 0 = DIO2 pin is an input. 1 = DIO2 pin is an output and driven to value of the PD2 bit. Si3210 = Reserved. 2 DIO1 DIO1 Pin Input/Output Direction (Si3211 only). 0 = DIO1 pin is an input. 1 = DIO1 pin is an output and driven to value of the PD1 bit. Si3210 = Reserved. 1 PD2 DIO2 Pin Data (Si3211 only). When DIO2 = 1: 0 = DIO2 pin driven low. 1 = DIO2 pin driven high. Si3210 = Reserved. When DIO2 = 0, PD2 value equals the logic input of DIO2 pin. 0 PD1 DIO1 Pin Data (Si3211 only). When DIO1 = 1: 0 = DIO1 pin driven low. 1 = DIO1 pin driven high. Si3210 = Reserved. When DIO1 = 0, PD1 value equals the logic input of DIO1 pin. Read returns zero. Rev. 1.61 69 Si3210/Si3211 Register 8. Audio Path Loopback Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ALM2 DLM ALM1 Type R/W R/W R/W Reset settings = 0000_0010 Bit Name 7:3 Reserved 2 ALM2 Analog Loopback Mode 2. (See Figure 25 on page 50.) 0 = Full analog loopback mode disabled. 1 = Full analog loopback mode enabled. 1 DLM Digital Loopback Mode. (See Figure 25 on page 50.) 0 = Digital loopback disabled. 1 = Digital loopback enabled. 0 ALM1 Analog Loopback Mode 1. (See Figure 25 on page 50.) 0 = Analog loopback disabled. 1 = Analog loopback enabled. 70 Function Read returns zero. Rev. 1.61 Si3210/Si3211 Register 9. Audio Gain Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RXHP TXHP TXM RXM ATX[1:0] ARX[1:0] Type R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Bit Name Function 7 RXHP Receive Path High Pass Filter Disable. 0 = HPF enabled in receive path, RHPF. 1 = HPF bypassed in receive path, RHPF. 6 TXHP Transmit Path High Pass Filter Disable. 0 = HPF enabled in transmit path, THPF. 1 = HPF bypassed in transmit path, THPF. 5 TXM Transmit Path Mute. Refer to position of digital mute in Figure 25 on page 50. 0 = Transmit signal passed. 1 = Transmit signal muted. 4 RXM Receive Path Mute. Refer to position of digital mute in Figure 25 on page 50. 0 = Receive signal passed. 1 = Receive signal muted. 3:2 ATX[1:0] Analog Transmit Path Gain. 00 = 0 dB 01 = -3.5 dB 10 = 3.5 dB 11 = ATX gain = 0 dB; analog transmit path muted. 1:0 ARX[1:0] Analog Receive Path Gain. 00 = 0 dB 01 = -3.5 dB 10 = 3.5 dB 11 = Analog receive path muted. Rev. 1.61 71 Si3210/Si3211 Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 D5 D4 D3 D2 D1 Name CLC[1:0] TISE TISS[2:0] Type R/W R/W R/W Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation. 00 = Off 01 = 4.7 nF 10 = 10 nF 11 = Reserved 3 TISE 2:0 TISS[2:0] 72 Function Two-Wire Impedance Synthesis Enable. 0 = Two-wire impedance synthesis disabled. 1 = Two-wire impedance synthesis enabled. Two-Wire Impedance Synthesis Selection. 000 = 600 001 = 900 010 = 600 + 2.16 F 011 = 900 + 2.16 F 100 = CTR21 (270 + 750 || 150 nF) 101 = Australia/New Zealand #1 (220 + 820 || 120 nF) 110 = Slovakia/Slovenia/South Africa (220 + 820 || 115 nF) 111 = New Zealand #2 (370 + 620 || 310 nF) Rev. 1.61 D0 Si3210/Si3211 Register 11. Hybrid Control Bit D7 D6 D5 D4 D3 D2 D1 Name HYBP[2:0] HYBA[2:0] Type R/W R/W D0 Reset settings = 0011_0011 Bit Name Function 7 Reserved Read returns zero. 6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = -1.02 dB 101 = -1.94 dB 110 = -2.77 dB 111 = Off 3 Reserved Read returns zero. 2:0 HYBA[2:0] Audio Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = -1.02 dB 101 = -1.94 dB 110 = -2.77 dB 111 = Off Rev. 1.61 73 Si3210/Si3211 Register 14. Powerdown Control 1 Si3210 Bit D7 D6 D5 D4 D3 Name PMON DCOF Type R/W R/W D2 D1 D0 MOF BIASOF SLICOF R/W R/W R/W D1 D0 Reset settings = 0001_0000 Si3211 Bit D7 D6 D5 D4 D3 D2 Name PMON MOF BIASOF SLICOF Type R/W R/W R/W R/W Reset settings = 0001_0000 Bit Name 7:6 Reserved 5 PMON Pulse Metering DAC Power-On Control. 0 = Automatic power control. 1 = Override automatic control and force pulse metering DAC circuitry on. 4 DCOF DC-DC Converter Power-Off Control (Si3210 only). 0 = Automatic power control. 1 = Override automatic control and force dc-dc circuitry off. Si3211 = Read returns 1; it cannot be written. 3 MOF 2 Reserved 1 BIASOF DC Bias Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force dc bias circuitry off. 0 SLICOF SLIC Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force SLIC circuitry off. 74 Function Read returns zero. Monitor ADC Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force monitor ADC circuitry off. Read returns zero. Rev. 1.61 Si3210/Si3211 Register 15. Powerdown Control 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ADCM ADCON DACM DACON GMM GMON Type R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Bit Name 7:6 Reserved 5 ADCM 4 ADCON 3 DACM 2 DACON 1 GMM 0 GMON Function Read returns zero. Analog to Digital Converter Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; ADCON controls on/off state. Analog to Digital Converter On/Off Power Control. When ADCM = 1: 0 = Analog to digital converter powered off. 1 = Analog to digital converter powered on. ADCON has no effect when ADCM = 0. Digital to Analog Converter Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; DACON controls on/off state. Digital to Analog Converter On/Off Power Control. When DACM = 1: 0 = Digital to analog converter powered off. 1 = Digital to analog converter powered on. DACON has no effect when DACM = 0. Transconductance Amplifier Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; GMON controls on/off state. Transconductance Amplifier On/Off Power Control. When GMM = 1: 0 = Analog to digital converter powered off. 1 = Analog to digital converter powered on. GMON has no effect when GMM = 0. Rev. 1.61 75 Si3210/Si3211 Register 18. Interrupt Status 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name PMIP PMAP RGIP RGAP O2IP O2AP O1IP O1AP Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIP Pulse Metering Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 6 PMAP Pulse Metering Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 5 RGIP Ringing Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 4 RGAP Ringing Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 3 O2IP Oscillator 2 Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 2 O2AP Oscillator 2 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 1 O1IP Oscillator 1 Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 0 O1AP Oscillator 1 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 76 Function Rev. 1.61 Si3210/Si3211 Register 19. Interrupt Status 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Q6AP Q5AP Q4AP Q3AP Q2AP Q1AP LCIP RTIP Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Bit Name Function 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 6 Q5AP Power Alarm Q5 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 5 Q4AP Power Alarm Q4 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 4 Q3AP Power Alarm Q3 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 3 Q2AP Power Alarm Q2 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 2 Q1AP Power Alarm Q1 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 1 LCIP Loop Closure Transition Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 0 RTIP Ring Trip Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Rev. 1.61 77 Si3210/Si3211 Register 20. Interrupt Status 3 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CMCP INDP DTMFP Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7:3 Reserved 2 CMCP Common Mode Calibration Error Interrupt. This bit is set when off-hook/on-hook status changes during the common mode balance calibration. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 1 INDP Indirect Register Access Serviced Interrupt. This bit is set once a pending indirect register service request has been completed. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 0 DTMFP 78 Function Read returns zero. DTMF Tone Detected Interrupt. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Rev. 1.61 Si3210/Si3211 Register 21. Interrupt Enable 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name PMIE PMAE RGIE RGAE O2IE O2AE O1IE O1AE Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Bit Name Function 7 PMIE Pulse Metering Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 6 PMAE Pulse Metering Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 5 RGIE Ringing Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 4 RGAE Ringing Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 3 O2IE Oscillator 2 Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 2 O2AE Oscillator 2 Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 1 O1IE Oscillator 1 Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 0 O1AE Oscillator 1 Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Rev. 1.61 79 Si3210/Si3211 Register 22. Interrupt Enable 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Q6AE Q5AE Q4AE Q3AE Q2AE Q1AE LCIE RTIE Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AE Power Alarm Q6 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 6 Q5AE Power Alarm Q5 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 5 Q4AE Power Alarm Q4 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 4 Q3AE Power Alarm Q3 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 3 Q2AE Power Alarm Q2 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 2 Q1AE Power Alarm Q1 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 1 LCIE Loop Closure Transition Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 0 RTIE Ring Trip Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 80 Function Rev. 1.61 Si3210/Si3211 Register 23. Interrupt Enable 3 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CMCE INDE DTMFE Type R/W R/W R/W Reset settings = 0000_0000 Bit Name Function 7:3 Reserved 2 CMCE Common Mode Calibration Error Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 1 INDE Indirect Register Access Serviced Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 0 DTMFE Read returns zero. DTMF Tone Detected Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Rev. 1.61 81 Si3210/Si3211 Register 24. DTMF Decode Status Bit D7 D6 D5 D4 D3 D2 D1 Name VAL DIG[3:0] Type R R Reset settings = 0000_0000 Bit Name 7:5 Reserved 4 VAL 3:0 DIG[3:0] 82 Function Read returns zero. DTMF Valid Digit Decoded. 0 = Not currently detecting digit. 1 = Currently detecting digit. DTMF Digit. 0001 = "1" 0010 = "2" 0011 = "3" 0100 = "4" 0101 = "5" 0110 = "6" 0111 = "7" 1000 = "8" 1001 = "9" 1010 = "0" 1011 = "*" 1100 = "#" 1101 = "A" 1110 = "B" 1111 = "C" 0000 = "D" Rev. 1.61 D0 Si3210/Si3211 Register 28. Indirect Data Access--Low Byte Bit D7 D6 D5 D4 D3 Name IDA[7:0] Type R/W D2 D1 D0 Reset settings = 0000_0000 Bit Name 7:0 IDA[7:0] Function Indirect Data Access--Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate--a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation). Register 29. Indirect Data Access--High Byte Bit D7 D6 D5 D4 D3 Name IDA[15:8] Type R/W D2 D1 D0 Reset settings = 0000_0000 Bit Name 7:0 IDA[15:8] Function Indirect Data Access--High Byte. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate--a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation). Rev. 1.61 83 Si3210/Si3211 Register 30. Indirect Address Bit D7 D6 D5 D4 D3 Name IAA[7:0] Type R/W D2 D1 D0 Reset settings = xxxx_xxxx Bit Name 7:0 IAA[7:0] Function Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate--a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation). Register 31. Indirect Address Status Bit D7 D6 D5 D4 D3 D2 D1 D0 Name IAS Type R Reset settings = 0000_0000 Bit Name 7:1 Reserved 0 IAS 84 Function Read returns zero. Indirect Access Status. 0 = No indirect memory access pending. 1 = Indirect memory access pending. Rev. 1.61 Si3210/Si3211 Register 32. Oscillator 1 Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name OSS1 REL OZ1 O1TAE O1TIE O1E O1SO[1:0] Type R R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Bit Name Function 7 OSS1 6 REL Oscillator 1 Automatic Register Reload. This bit should be set for FSK signaling. 0 = Oscillator 1 will stop signaling after inactive timer expires. 1 = Oscillator 1 will continue to read register parameters and output signals. 5 OZ1 Oscillator 1 Zero Cross Enable. 0 = Signal terminates after active timer expires. 1 = Signal terminates at zero crossing after active timer expires. 4 O1TAE Oscillator 1 Active Timer Enable. 0 = Disable timer. 1 = Enable timer. 3 O1TIE Oscillator 1 Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. 2 O1E 1:0 O1SO[1:0] Oscillator 1 Signal Status. 0 = Output signal inactive. 1 = Output signal active. Oscillator 1 Enable. 0 = Disable oscillator. 1 = Enable oscillator. Oscillator 1 Signal Output Routing. 00 = Unassigned path (output not connected). 01 = Assign to transmit path. 10 = Assign to receive path. 11 = Assign to both paths. Rev. 1.61 85 Si3210/Si3211 Register 33. Oscillator 2 Control Bit D7 Name Type D6 D5 D4 D3 D2 OSS2 OZ2 O2TAE O2TIE O2E O2SO[1:0] R R/W R/W R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 OSS2 6 Reserved 5 OZ2 4 O2TAE Oscillator 2 Active Timer Enable. 0 = Disable timer. 1 = Enable timer. 3 O2TIE Oscillator 2 Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. 2 O2E 1:0 O2SO[1:0] 86 Function Oscillator 2 Signal Status. 0 = Output signal inactive. 1 = Output signal active. Read returns zero. Oscillator 2 Zero Cross Enable. 0 = Signal terminates after active timer expires. 1 = Signal terminates at zero crossing. Oscillator 2 Enable. 0 = Disable oscillator. 1 = Enable oscillator. Oscillator 2 Signal Output Routing. 00 = Unassigned path (output not connected) 01 = Assign to transmit path. 10 = Assign to receive path. 11 = Assign to both paths. Rev. 1.61 D1 D0 Si3210/Si3211 Register 34. Ringing Oscillator Control Bit D7 Name Type D6 D5 D4 D3 D2 D1 D0 RSS RDAC RTAE RTIE ROE RVO TSWS R R R/W R/W R R/W R/W Reset settings = 0000_0000 Bit Name Function 7 RSS 6 Reserved 5 RDAC Ringing Signal DAC/Linefeed Cross Indicator. For ringing signal start and stop, output to TIP and RING is suspended to ensure continuity with dc linefeed voltages. RDAC indicates that ringing signal is actually present at TIP and RING. 0 = Ringing signal not present at TIP and RING. 1 = Ringing signal present at TIP and RING. 4 RTAE Ringing Active Timer Enable. 0 = Disable timer. 1 = Enable timer. 3 RTIE Ringing Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. 2 ROE Ringing Oscillator Enable. 0 = Ringing oscillator disabled. 1 = Ringing oscillator enabled. 1 RVO Ringing Voltage Offset. 0 = No dc offset added to ringing signal. 1 = DC offset added to ringing signal. 0 TSWS Ringing Signal Status. 0 = Ringing oscillator output signal inactive. 1 = Ringing oscillator output signal active. Read returns zero. Trapezoid/Sinusoid Waveshape Select. 0 = Sinusoid 1 = Trapezoid Rev. 1.61 87 Si3210/Si3211 Register 35. Pulse Metering Oscillator Control Bit D7 Name Type D6 D5 D4 D3 D2 PSTAT PMAE PMIE PMOE R R/W R/W R/W D1 D0 D1 D0 Reset settings = 0000_0000 Bit Name Function 7 PSTAT 6:5 Reserved 4 PMAE Pulse Metering Active Timer Enable. 0 = Disable timer. 1 = Enable timer. 3 PMIE Pulse Metering Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. 2 PMOE Pulse Metering Oscillator Enable. 0 = Disable oscillator. 1 = Enable oscillator. 1:0 Reserved Pulse Metering Signal Status. 0 = Output signal inactive. 1 = Output signal active. Read returns zero. Read returns zero. Register 36. Oscillator 1 Active Timer--Low Byte Bit D7 D6 D5 D4 D3 Name OAT1[7:0] Type R/W Reset settings = 0000_0000 Bit Name 7:0 OAT1[7:0] 88 Function Oscillator 1 Active Timer. LSB = 125 s Rev. 1.61 D2 Si3210/Si3211 Register 37. Oscillator 1 Active Timer--High Byte Bit D7 D6 D5 D4 D3 Name OAT1[15:8] Type R/W D2 D1 D0 D2 D1 D0 D2 D1 D0 Reset settings = 0000_0000 Bit Name 7:0 OAT1[15:8] Function Oscillator 1 Active Timer. Register 38. Oscillator 1 Inactive Timer--Low Byte Bit D7 D6 D5 D4 D3 Name OIT1[7:0] Type R/W Reset settings = 0000_0000 Bit Name 7:0 OIT1[7:0] Function Oscillator 1 Inactive Timer. LSB = 125 s Register 39. Oscillator 1 Inactive Timer--High Byte Bit D7 D6 D5 D4 D3 Name OIT1[15:8] Type R/W Reset settings = 0000_0000 Bit Name 7:0 OIT1[15:8] Function Oscillator 1 Inactive Timer. Rev. 1.61 89 Si3210/Si3211 Register 40. Oscillator 2 Active Timer--Low Byte Bit D7 D6 D5 D4 D3 Name OAT2[7:0] Type R/W D2 D1 D0 D2 D1 D0 D2 D1 D0 Reset settings = 0000_0000 Bit Name 7:0 OAT2[7:0] Function Oscillator 2 Active Timer. LSB = 125 s Register 41. Oscillator 2 Active Timer--High Byte Bit D7 D6 D5 D4 D3 Name OAT2[15:8] Type R/W Reset settings = 0000_0000 Bit Name 7:0 OAT2[15:8] Function Oscillator 2 Active Timer. Register 42. Oscillator 2 Inactive Timer--Low Byte Bit D7 D6 D5 D4 D3 Name OIT2[7:0] Type R/W Reset settings = 0000_0000 Bit Name 7:0 OIT2[7:0] 90 Function Oscillator 2 Inactive Timer. LSB = 125 s Rev. 1.61 Si3210/Si3211 Register 43. Oscillator 2 Inactive Timer--High Byte Bit D7 D6 D5 D4 D3 Name OIT2[15:8] Type R/W D2 D1 D0 D2 D1 D0 D2 D1 D0 Reset settings = 0000_0000 Bit Name 7:0 OIT2[15:8] Function Oscillator 2 Inactive Timer. Register 44. Pulse Metering Oscillator Active Timer--Low Byte Bit D7 D6 D5 D4 D3 Name PAT[7:0] Type R/W Reset settings = 0000_0000 Bit Name 7:0 PAT[7:0] Function Pulse Metering Active Timer. LSB = 125 s Register 45. Pulse Metering Oscillator Active Timer--High Byte Bit D7 D6 D5 D4 D3 Name PAT[15:8] Type R/W Reset settings = 0000_0000 Bit Name 7:0 PAT[15:8] Function Pulse Metering Active Timer. Rev. 1.61 91 Si3210/Si3211 Register 46. Pulse Metering Oscillator Inactive Timer--Low Byte Bit D7 D6 D5 D4 D3 Name PIT[7:0] Type R/W D2 D1 D0 D2 D1 D0 D2 D1 D0 Reset settings = 0000_0000 Bit Name 7:0 PIT[7:0] Function Pulse Metering Inactive Timer. LSB = 125 s Register 47. Pulse Metering Oscillator Inactive Timer--High Byte Bit D7 D6 D5 D4 D3 Name PIT[15:8] Type R/W Reset settings = 0000_0000 Bit Name 7:0 PIT[15:8] Function Pulse Metering Inactive Timer. Register 48. Ringing Oscillator Active Timer--Low Byte Bit D7 D6 D5 D4 D3 Name RAT[7:0] Type R/W Reset settings = 0000_0000 Bit Name 7:0 RAT[7:0] 92 Function Ringing Active Timer. LSB = 125 s Rev. 1.61 Si3210/Si3211 Register 49. Ringing Oscillator Active Timer--High Byte Bit D7 D6 D5 D4 D3 Name RAT[15:8] Type R/W D2 D1 D0 D2 D1 D0 D2 D1 D0 Reset settings = 0000_0000 Bit Name 7:0 RAT[15:8] Function Ringing Active Timer. Register 50. Ringing Oscillator Inactive Timer--Low Byte Bit D7 D6 D5 D4 D3 Name RIT[7:0] Type R/W Reset settings = 0000_0000 Bit Name 7:0 RIT[7:0] Function Ringing Inactive Timer. LSB = 125 s Register 51. Ringing Oscillator Inactive Timer--High Byte Bit D7 D6 D5 D4 D3 Name RIT[15:8] Type R/W Reset settings = 0000_0000 Bit Name 7:0 RIT[15:8] Function Ringing Inactive Timer. Rev. 1.61 93 Si3210/Si3211 Register 52. FSK Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Name FSKDAT Type R/W Reset settings = 0000_0000 Bit Name Function 7:1 Reserved Read returns zero. 0 FSKDAT FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this bit serves as the buffered input for FSK generation bit stream data. Register 63. Loop Closure Debounce Interval Bit D7 Name D6 D5 D4 D3 D2 D1 D0 LCD[7:0] Type Reset settings = 0011_0010 (revision C); 0101_0100 (subsequent revisions) Bit Name 7:0 LCD[7:0] 94 Function Loop Closure Debounce Interval for Automatic Ringing. This register sets the loop closure debounce interval for the ringing silent period when using automatic ringing cadences. The value may be set between 0 ms (0x00) and 159 ms (0x7F) in 1.25 ms steps. Rev. 1.61 Si3210/Si3211 Register 64. Linefeed Control Bit D7 D6 D5 D4 D3 D2 D1 Name LFS[2:0] LF[2:0] Type R R/W D0 Reset settings = 0000_0000 Bit Name Function 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual real-time linefeed state. Automatic operations may cause actual linefeed state to deviate from the state defined by linefeed register (e.g., when linefeed equals ringing state, LFS will equal on-hook transmission state during ringing silent period and ringing state during ring burst). 000 = Open 001 = Forward active 010 = Forward on-hook transmission 011 = TIP open 100 = Ringing 101 = Reverse active 110 = Reverse on-hook transmission 111 = RING open 3 Reserved Read returns zero. 2:0 LF[2:0] Linefeed. Writing to this register sets the linefeed state. 000 = Open 001 = Forward active 010 = Forward on-hook transmission 011 = TIP open 100 = Ringing 101 = Reverse active 110 = Reverse on-hook transmission 111 = RING open Rev. 1.61 95 Si3210/Si3211 Register 65. External Bipolar Transistor Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name SQH CBY ETBE ETBO[1:0] ETBA[1:0] Type R/W R/W R/W R/W R/W Reset settings = 0110_0001 Bit Name 7 Reserved 6 SQH Audio Squelch. 0 = No squelch. 1 = STIPAC and SRINGAC pins squelched. 5 CBY Capacitor Bypass. 0 = Capacitors CP (C1) and CM (C2) in circuit. 1 = Capacitors CP (C1) and CM (C2) bypassed. 4 ETBE External Transistor Bias Enable. 0 = Bias disabled. 1 = Bias enabled. 3:2 ETBO[1:0] External Transistor Bias Levels--On-Hook Transmission State. DC bias current which flows through external BJTs in the on-hook transmission state. Increasing this value increases the compliance of the ac longitudinal balance circuit. 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = Reserved 1:0 ETBA[1:0] External Transistor Bias Levels--Active Off-Hook State. DC bias current which flows through external BJTs in the active off-hook state. Increasing this value increases the compliance of the ac longitudinal balance circuit. 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = Reserved 96 Function Read returns zero. Rev. 1.61 Si3210/Si3211 Register 66. Battery Feed Control Si3210 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name VOV FVBAT TRACK Type R/W R/W R/W Reset settings = 0000_0011 Si3211 Bit D7 D6 D5 D4 D3 D2 D1 Name BATSL Type R/W D0 Reset settings = 0000_0110 Bit Name 7:5 Reserved 4 VOV 3 FVBAT Function Read returns zero. Overhead Voltage Range Increase. (Si3210 only; See Figure 19 on page 39.) This bit selects the programmable range for VOV, which is defined in indirect Register 41. 0 = VOV = 0 V to 9 V 1 = VOV = 0 V to 13.5 V Si3211 = Reserved. VBAT Manual Setting (Si3210 only). 0 = Normal operation 1 = VBAT tracks VBATHregister. Si3211 = Read returns 0; it cannot be written. 2 Reserved Si3210 = Read returns zero. Si3211 = Read returns one. 1 BATSL Battery Feed Select (Si3211 only). This bit selects between high and low battery supplies. 0 = Low battery selected (DCSW pin low). 1 = High battery selected (DCSW pin high). Si3210 = Read returns zero. 0 TRACK DC-DC Converter Tracking Mode (Si3210 only). 0 = |VBAT| will not decrease below VBATL. 1 = VBAT tracks VRING. Si3211 = Reserved. Rev. 1.61 97 Si3210/Si3211 Register 67. Automatic/Manual Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MNCM MNDIF SPDS ABAT AORD AOLD AOPN Type R/W R/W R/W R/W R/W R/W R/W Reset settings = 0001_1111 Bit Name 7 Reserved 6 MNCM Common Mode Manual/Automatic Select. 0 = Automatic control. 1 = Manual control, in which TIP (forward) or RING (reverse) forces voltage to follow VCM value. 5 MNDIF Differential Mode Manual/Automatic Select. 0 = Automatic control. 1 = Manual control (forces differential voltage to follow VOC value). 4 SPDS Speed-Up Mode Enable. 0 = Speed-up disabled. 1 = Automatic speed-up. 3 ABAT Battery Feed Automatic/Manual Select (Si3211 only). 0 = Automatic mode disabled. 1 = Automatic mode enabled (automatic switching to low battery in off-hook state). 2 AORD Automatic/Manual Ring Trip Detect. 0 = Manual mode. 1 = Enter off-hook active state automatically upon ring trip detect. 1 AOLD Automatic/Manual Loop Closure Detect. 0 = Manual mode. 1 = Enter off-hook active state automatically upon loop closure detect. 0 AOPN Power Alarm Automatic/Manual Detect. 0 = Manual mode. 1 = Enter open state automatically upon power alarm. 98 Function Read returns zero. Rev. 1.61 Si3210/Si3211 Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 D5 D4 D3 D2 D1 D0 Name DBIRAW RTP LCR Type R R R Reset settings = 0000_0100 Bit Name Function 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. State of this bit reflects the real-time output of ring trip and loop closure detect circuits before debouncing. 0 = Ring trip/loop closure threshold exceeded. 1 = Ring trip/loop closure threshold not exceeded. 1 RTP Ring Trip Detect Indicator (Filtered Output). 0 = Ring trip detect has not occurred. 1 = Ring trip detect occurred. 0 LCR Loop Closure Detect Indicator (Filtered Output). 0 = Loop closure detect has not occurred. 1 = Loop closure detect has occurred. Register 69. Loop Closure Debounce Interval Bit D7 D6 D5 D4 D3 Name LCDI[6:0] Type R/W D2 D1 D0 Reset settings = 0000_1010 Bit Name Function 7 Reserved Read returns zero. 6:0 LCDI[6:0] Loop Closure Debounce Interval. The value written to this register defines the minimum steady state debounce time. Value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms. Rev. 1.61 99 Si3210/Si3211 Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 D5 D4 D3 Name RTDI[6:0] Type R/W D2 D1 D0 Reset settings = 0000_1010 Bit Name Function 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady state debounce time. The value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms. Register 71. Loop Current Limit Bit D7 D6 D5 D4 D3 D2 D1 Name ILIM[2:0] Type R/W D0 Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 ILIM[2:0] Loop Current Limit. The value written to this register sets the constant loop current. The value may be set between 20 mA (0x00) and 41 mA (0x07) in 3 mA steps. 100 Function Rev. 1.61 Si3210/Si3211 Register 72. On-Hook Line Voltage Bit D7 D6 D5 D4 D3 D2 Name VSGN VOC[5:0] Type R/W R/W D1 D0 Reset settings = 0010_0000 Bit Name 7 Reserved 6 VSGN 5:0 VOC[5:0] Function Read returns zero. On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage polarity (VTIP-VRING). 0 = VTIP-VRINGis positive 1 = VTIP-VRING is negative On-Hook Line Voltage. The value written to this register sets the on-hook line voltage (VTIP-VRING). Value may be set between 0 V (0x00) and 94.5 V (0x3F) in 1.5 V steps. Default value = 48 V. Register 73. Common Mode Voltage Bit D7 D6 D5 D4 D3 D2 Name VCM[5:0] Type R/W D1 D0 Reset settings = 0000_0010 Bit Name Function 7:6 Reserved Read returns zero. 5:0 VCM[5:0] Common Mode Voltage. The value written to this register sets VTIP for forward active and forward on-hook transmission states and VRING for reverse active and reverse on-hook transmission states. The value may be set between 0 V (0x00) and -94.5 V (0x3F) in 1.5 V steps. Default value = -3 V. Rev. 1.61 101 Si3210/Si3211 Register 74. High Battery Voltage Bit D7 D6 D5 D4 D3 D2 Name VBATH[5:0] Type R/W D1 D0 Reset settings = 0011_0010 Bit Name 7:6 Reserved 5:0 VBATH[5:0] Function Read returns zero. High Battery Voltage. The value written to this register sets high battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and -94.5 V (0x3F) in 1.5 V steps. Default value = -75 V. For Si3211, VBATL must be set equal to the voltage supplied at the VBATL node shown in the Si3211 typical application circuit drawings, Figure 12 on page 22 and Figure 14 on page 26. Register 75. Low Battery Voltage Bit D7 D6 D5 D4 D3 D2 Name VBATL[5:0] Type R/W D1 D0 Reset settings = 0001_0000 Bit Name 7:6 Reserved 5:0 VBATL[5:0] 102 Function Read returns zero. Low Battery Voltage. The value written to this register sets low battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and -94.5 V (0x3F) in 1.5 V steps. Default value = -24 V. For Si3211, VBATL must be set equal to the voltage supplied at the VBATL node shown in the Si3211 typical application circuit drawings, Figure 12 on page 22 and Figure 14 on page 26. Rev. 1.61 Si3210/Si3211 Register 76. Power Monitor Pointer Bit D7 D6 D5 D4 D3 D2 D1 Name PWRMP[2:0] Type R/W D0 Reset settings = 0000_0000 Bit Name 7:3 Reserved 2:0 PWRMP[2:0] Function Read returns zero. Power Monitor Pointer. Selects the external transistor from which to read power output. The power of the selected transistor is read in the PWROM register. 000 = Q1 001 = Q2 010 = Q3 011 = Q4 100 = Q5 101 = Q6 110 = Undefined 111 = Undefined Register 77. Line Power Output Monitor Bit D7 D6 D5 D4 D3 Name PWROM[7:0] Type R D2 D1 D0 Reset settings = 0000_0000 Bit Name Function 7:0 PWROM[7:0] Line Power Output Monitor. This register reports the real-time power output of the transistor selected using PWRMP. The range is 0 W (0x00) to 7.8 W (0xFF) in 30.4 mW steps for Q1, Q2, Q5, and Q6. The range is 0 W (0x00) to 0.9 W (0xFF) in 3.62 mW steps for Q3 and Q4. Rev. 1.61 103 Si3210/Si3211 Register 78. Loop Voltage Sense Bit D7 D6 D5 D4 D3 D2 Name LVSP LVS[5:0] Type R R D1 D0 Reset settings = 0000_0000 Bit Name 7 Reserved 6 LVSP 5:0 LVS[5:0] Function Read returns zero. Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage (VTIP - VRING). 0 = Positive loop voltage (VTIP > VRING). 1 = Negative loop voltage (VTIP < VRING). Loop Voltage Sense Magnitude. This register reports the magnitude of the differential loop voltage (VTIP-VRING). The range is 0 V to 94.5 V in 1.5 V steps. Register 79. Loop Current Sense Bit D7 D6 D5 D4 D3 D2 Name LCSP LCS[5:0] Type R R D1 D0 Reset settings = 0000_0000 Bit Name 7 Reserved 6 LCSP 5:0 LCS[5:0] 104 Function Read returns zero. Loop Current Sense Polarity. This register reports the polarity of the loop current. 0 = Positive loop current (forward direction). 1 = Negative loop current (reverse direction). Loop Current Sense Magnitude. This register reports the magnitude of the loop current. The range is 0 mA to 78.75 mA in 1.25 mA steps. Rev. 1.61 Si3210/Si3211 Register 80. TIP Voltage Sense Bit D7 D6 D5 D4 D3 Name VTIP[7:0] Type R D2 D1 D0 Reset settings = 0000_0000 Bit Name Function 7:0 VTIP[7:0] TIP Voltage Sense. This register reports the real-time voltage at TIP with respect to ground. The range is 0 V (0x00) to -95.88 V (0xFF) in .376 V steps. Register 81. RING Voltage Sense Bit D7 D6 D5 D4 D3 Name VRING[7:0] Type R D2 D1 D0 Reset settings = 0000_0000 Bit Name 7:0 VRING[7:0] Function RING Voltage Sense. This register reports the real-time voltage at RING with respect to ground. The range is 0 V (0x00) to -95.88 V (0xFF) in .376 V steps. Register 82. Battery Voltage Sense 1 Bit D7 D6 D5 D4 D3 Name VBATS1[7:0] Type R D2 D1 D0 Reset settings = 0000_0000 Bit Name Function 7:0 VBATS1[7:0] Battery Voltage Sense 1. This register is one of two registers that reports the real-time voltage at VBAT with respect to ground. The range is 0 V (0x00) to -95.88 V (0xFF) in .376 V steps. Rev. 1.61 105 Si3210/Si3211 Register 83. Battery Voltage Sense 2 Bit D7 D6 D5 D4 D3 Name VBATS2[7:0] Type R D2 D1 D0 Reset settings = 0000_0000 Bit Name Function 7:0 VBATS2[7:0] Battery Voltage Sense 2. This register is one of two registers that reports the real-time voltage at VBAT with respect to ground. The range is 0 V (0x00) to -95.88 V (0xFF) in .376 V steps. Register 84. Transistor 1 Current Sense Bit D7 D6 D5 D4 D3 Name IQ1[7:0] Type R D2 D1 D0 Reset settings = xxxx_xxxx Bit Name Function 7:0 IQ1[7:0] Transistor 1 Current Sense. This register reports the real-time current through Q1. The range is 0 A (0x00) to 81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the additional ETBO/A current. Register 85. Transistor 2 Current Sense Bit D7 D6 D5 D4 D3 Name IQ2[7:0] Type R D2 D1 D0 Reset settings = xxxx_xxxx Bit Name Function 7:0 IQ2[7:0] Transistor 2 Current Sense. This register reports the real-time current through Q2. The range is 0 A (0x00) to 81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the additional ETBO/A current. 106 Rev. 1.61 Si3210/Si3211 Register 86. Transistor 3 Current Sense Bit D7 D6 D5 D4 D3 Name IQ3[7:0] Type R D2 D1 D0 Reset settings = xxxx_xxxx Bit Name 7:0 IQ3[7:0] Function Transistor 3 Current Sense. This register reports the real-time current through Q3. The range is 0 A (0x00) to 9.59 mA (0xFF) in 37.6 A steps. Register 87. Transistor 4 Current Sense Bit D7 D6 D5 D4 D3 Name IQ4[7:0] Type R D2 D1 D0 Reset settings = xxxx_xxxx Bit Name 7:0 IQ4[7:0] Function Transistor 4 Current Sense. This register reports the real-time current through Q4. The range is 0 A (0x00) to 9.59 mA (0xFF) in 37.6 A steps. Register 88. Transistor 5 Current Sense Bit D7 D6 D5 D4 D3 Name IQ5[7:0] Type R D2 D1 D0 Reset settings = xxxx_xxxx Bit Name 7:0 IQ5[7:0] Function Transistor 5 Current Sense. This register reports the real-time current through Q5. The range is 0 A (0x00) to 80.58 mA (0xFF) in .316 mA steps. Rev. 1.61 107 Si3210/Si3211 Register 89. Transistor 6 Current Sense Bit D7 D6 D5 D4 D3 Name IQ6[7:0] Type R D2 D1 D0 Reset settings = xxxx_xxxx Bit Name 7:0 IQ6[7:0] Function Transistor 6 Current Sense. This register reports the real-time current through Q6. The range is 0 A (0x00) to 80.58 mA (0xFF) in .316 mA steps. Register 92. DC-DC Converter PWM Period Si3210 Bit D7 D6 D5 D4 D3 Name DCN[7] 1 DCN[5:0] Type R/W R R/W D2 D1 D0 D2 D1 D0 Reset settings = 1111_1111 Si3211 Bit D7 D6 D5 D4 D3 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 DCN[7:0] 108 Function DC-DC Converter Period. This bit sets the PWM period for the dc-dc converter. The range is 3.906 s (0x40) to 15.564 s (0xFF) in 61.035 ns steps. Si3211 = Reserved. Bit 6 is fixed to one and read-only, so there are two ranges of operation: 3.906 s-7.751 s, used for MOSFET transistor switching. 11.719 s-15.564 s, used for BJT transistor switching. Rev. 1.61 Si3210/Si3211 Register 93. DC-DC Converter Switching Delay Si3210 Bit D7 D6 D5 D4 D3 D2 Name DCCAL DCPOL DCTOF[4:0] Type R/W R R/W D1 D0 D1 D0 Reset settings = 0001_0100 (Si3210) Reset settings = 0011_0100 (Si3210M) Si3211 Bit D7 D6 D5 D4 D3 D2 Name Type Reset settings = xxxx_xxxx Bit Name 7 DCCAL 6 Reserved 5 DCPOL 4:0 DCTOF[4:0] Function DC-DC Converter Peak Current Monitor Calibration Status (Si3210 only). Writing a one to this bit starts the dc-dc converter peak current monitor calibration routine. 0 = Normal operation. 1 = Calibration being performed. Si3211 = Reserved. Read returns zero. DC-DC Converter Feed Forward Pin (DCFF) Polarity (Si3210 only). This read-only register bit indicates the polarity relationship of the DCFF pin to the DCDRV pin. Two versions of the Si3210 are offered to support the two relationships. 0 = DCFF pin polarity is opposite of DCDRV pin (Si3210). 1 = DCFF pin polarity is same as DCDRV pin (Si3210M). Si3211 = Reserved. DC-DC Converter Minimum Off Time (Si3210 only). This register sets the minimum off time for the pulse width modulated dc-dc converter control. TOFF = (DCTOF + 4) 61.035 ns. Si3211 = Reserved. Rev. 1.61 109 Si3210/Si3211 Register 94. DC-DC Converter PWM Pulse Width Si3210 Bit D7 D6 D5 D4 D3 Name DCPW[7:0] Type R D2 D1 D0 D2 D1 D0 Reset settings = 0000_0000 Si3211 Bit D7 D6 D5 D4 D3 Name Type Reset settings = 0000_0000 Bit Name 7:0 DCPW[7:0] Function DC-DC Converter Pulse Width (Si3210 only). Pulse width of DCDRV is given by PW = (DCPW - DCTOF - 4) 61.035 ns. Si3211 = Reserved. 110 Rev. 1.61 Si3210/Si3211 Register 96. Calibration Control/Status Register 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CAL CALSP CALR CALT CALD CALC CALIL Type R/W R/W R/W R/W R/W R/W R/W Reset settings = 0001_1111 Bit Name Function 7 Reserved 6 CAL 5 CALSP 4 CALR RING Gain Mismatch Calibration. For use with discrete solution only. When using the Si3201, consult "AN35: Si321x User's Quick Reference Guide" and follow instructions for manual calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. 3 CALT TIP Gain Mismatch Calibration. For use with discrete solution only. When using the Si3201, consult "AN35: Si321x User's Quick Reference Guide" and follow instructions for manual calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. 2 CALD Differential DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. 1 CALC Common Mode DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. 0 CALIL ILIM Calibration. Read returns zero. Calibration Control/Status Bit. Setting this bit begins calibration of the entire system. 0 = Normal operation or calibration complete. 1 = Calibration in progress. Calibration Speedup. Setting this bit shortens the time allotted for VBAT settling at the beginning of the calibration cycle. 0 = 300 ms 1 = 30 ms 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Rev. 1.61 111 Si3210/Si3211 Register 97. Calibration Control/Status Register 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CALM1 CALM2 CALDAC CALADC CALCM Type R/W R/W R/W R/W R/W D1 D0 Reset settings = 0001_1111 Bit Name Function 7:5 Reserved 4 CALM1 Monitor ADC Calibration 1. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. 3 CALM2 Monitor ADC Calibration 2. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. 2 CALDAC DAC Calibration. Setting this bit begins calibration of the audio DAC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. 1 CALADC ADC Calibration. Setting this bit begins calibration of the audio ADC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. 0 CALCM Common Mode Balance Calibration. Setting this bit begins calibration of the ac longitudinal balance. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Read returns zero. Register 98. RING Gain Mismatch Calibration Result Bit D7 D6 D5 D4 D3 D2 Name CALGMR[4:0] Type R/W Reset settings = 0001_0000 Bit Name 7:5 Reserved 4:0 CALGMR[4:0] 112 Function Read returns zero. Gain Mismatch of IE Tracking Loop for RING Current. Rev. 1.61 Si3210/Si3211 Register 99. TIP Gain Mismatch Calibration Result Bit D7 D6 D5 D4 D3 D2 Name CALGMT[4:0] Type R/W D1 D0 D1 D0 D1 D0 Reset settings = 0001_0000 Bit Name 7:5 Reserved 4:0 CALGMT[4:0] Function Read returns zero. Gain Mismatch of IE Tracking Loop for TIP Current. Register 100. Differential Loop Current Gain Calibration Result Bit D7 D6 D5 D4 D3 D2 Name CALGD[4:0] Type R/W Reset settings = 0001_0001 Bit Name 7:5 Reserved 4:0 CALGD[4:0] Function Read returns zero. Differential DAC Gain Calibration Result. Register 101. Common Mode Loop Current Gain Calibration Result Bit D7 D6 D5 D4 D3 D2 Name CALGC[4:0] Type R/W Reset settings = 0001_0001 Bit Name 7:5 Reserved 4:0 CALGC[4:0] Function Read returns zero. Common Mode DAC Gain Calibration Result. Rev. 1.61 113 Si3210/Si3211 Register 102. Current Limit Calibration Result Bit D7 D6 D5 D4 D3 D2 D1 Name CALGIL[3:0] Type R/W D0 Reset settings = 0000_1000 Bit Name 7:5 Reserved 3:0 CALGIL[3:0] Function Read returns zero. Current Limit Calibration Result. Register 103. Monitor ADC Offset Calibration Result Bit D7 D6 D5 D4 D3 D2 D1 Name CALMG1[3:0] CALMG2[3:0] Type R/W R/W D0 Reset settings = 1000_1000 Bit Name Function 7:4 CALMG1[3:0] Monitor ADC Offset Calibration Result 1. 3:0 CALMG2[3:0] Monitor ADC Offset Calibration Result 2. Register 104. Analog DAC/ADC Offset Bit D7 D6 D5 D4 D3 D2 D1 D0 Name DACP DACN ADCP ADCN Type R/W R/W R/W R/W Reset settings = 0000_0000 Bit Name 7:4 Reserved 3 DACP Positive Analog DAC Offset. 2 DACN Negative Analog DAC Offset. 1 ADCP Positive Analog ADC Offset. 0 ADCN Negative Analog ADC Offset. 114 Function Read returns zero. Rev. 1.61 Si3210/Si3211 Register 105. DAC Offset Calibration Result Bit D7 D6 D5 D4 D3 Name DACOF[7:0] Type R/W D2 D1 D0 D2 D1 D0 D1 D0 Reset settings = 0000_0000 Bit Name 7:0 DACOF[7:0] Function DAC Offset Calibration Result. Register 106. Common Mode Balance Calibration Result Bit D7 D6 D5 D4 Name D3 CMBAL[5:0] Type Reset settings = 0010_0000 Bit Name 7:6 Reserved 5:0 CMBAL[5:0] Function Read returns zero. Common Mode Balance Calibration Result. Register 107. DC Peak Current Monitor Calibration Result Bit D7 D6 D5 D4 D3 D2 Name CMDCPK[3:0] Type R/W Reset settings = 0000_1000 Bit Name 7:4 Reserved 3:0 CMDCPK[3:0] Function Read returns zero. DC Peak Current Monitor Calibration Result. Rev. 1.61 115 Si3210/Si3211 Register 108. Enhancement Enable Note: The Enhancement Enable register and associated features are available in silicon revisions C and later. Si3210 Bit D7 D6 D5 D4 Name ILIMEN FSKEN DCSU Type R/W R/W R/W D3 D2 D1 D0 ZSEXT LCVE DCFIL HYSTEN R/W R/W R/W R/W D1 D0 Reset settings = 0000_0000 Si3211 Bit D7 D6 Name ILIMEN Type R/W D5 D4 D3 D2 FSKEN ZSEXT SWDB LCVE HYSTEN R/W R/W R/W R/W R/W Reset settings = 0000_0000 Bit Name Function 7 ILIMEN Current Limit Increase. When enabled, this bit temporarily increases the maximum differential current limit at the end of a ring burst to enable a faster settling time to a dc linefeed state. 0 = The value programmed in ILIM (direct Register 71) is used. 1 = The maximum differential loop current limit is temporarily increased to 41 mA. 6 FSKEN FSK Generation Enhancement. When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are used for FSK generation (indirect registers 99-104). Audio tones are generated using this new higher frequency, and oscillator 1 active and inactive timers have a finer bit resolution of 41.67 s. This provides greater resolution during FSK caller ID signal generation. 0 = Tone generator always clocked at 8 kHz; OSC1, OSC1X., and OSC1Y are always used. 1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only when REL = 1; otherwise clocked at 8 kHz. 5 DCSU DC-DC Converter Control Speedup (Si3210 only). When enabled, this bit invokes a multi-threshold error control algorithm which allows the dc-dc converter to adjust more quickly to voltage changes. 0 = Normal control algorithm used. 1 = Multi-threshold error control algorithm used. 116 Rev. 1.61 Si3210/Si3211 Bit Name Function 4 ZSEXT Impedance Internal Reference Resistor Disable. When enabled, this bit removes the internal reference resistor used to synthesize ac impedances for 600 + 2.1 F and 900 + 2.16 F so that an external resistor reference may be used. 0 = Internal resistor used to generate 600 + 2.1 F and 900 + 2.16 F impedances. 1 = Internal resistor removed from circuit. 3 SWDB Battery Switch Debounce (Si3211 only). When enabled, this bit allows debouncing of the battery switching circuit only when transitioning from VBATH to VBATL external battery supplies (EXTBAT = 1). 0 = No debounce used. 1 = 60 ms debounce period used. Si3210 = Reserved. 2 LCVE Voltage-Based Loop Closure. Enables loop closure to be determined by the TIP-to-RING voltage rather than loop current. 0 = Loop closure determined by loop current. 1 = Loop closure determined by TIP-to-RING voltage. 1 DCFIL DC-DC Converter Squelch (Si3210 only). When enabled, this bit squelches noise in the audio band from the dc-dc converter control loop. 0 = Voice band squelch disabled. 1 = Voice band squelch enabled. 0 HYSTEN Loop Closure Hysteresis Enable. When enabled, this bit allows hysteresis to the loop closure calculation. The upper and lower hysteresis thresholds are defined by indirect registers 28 and 43, respectively. 0 = Loop closure hysteresis disabled. 1 = Loop closure hysteresis enabled. Rev. 1.61 117 Si3210/Si3211 4. Indirect Registers Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update. A write to IAA without first writing to IDA is interpreted as a read request from an indirect register. In this case, the value located at IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of 16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition, an interrupt, IND (Register 20), can be generated upon completion of the indirect transfer. 4.1. DTMF Decoding All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined following the reset state. Table 37. DTMF Indirect Registers Summary Addr. D15 D14 D13 D12 D11 D10 D9 D8 D7 0 ROW0[15:0] 1 ROW1[15:0] 2 ROW2[15:0] 3 ROW3[15:0] 4 COL[15:0] 5 FWDTW[15:0] 6 REVTW[15:0] 7 ROWREL[15:0] 8 COLREL[15:0] 9 ROW2[15:0] 10 COL2[15:0] 11 PWRMIN[15:0] 12 HOTL[15:0] 118 Rev. 1.61 D6 D5 D4 D3 D2 D1 D0 Si3210/Si3211 Table 38. DTMF Indirect Registers Description Addr. Description Reference Page 0 DTMF Row 0 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 0 DTMF detection. If the ratio of power in row 0 to total power in the row band is greater than ROW0, a row 0 signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. 49 1 DTMF Row 1 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 1 DTMF detection. If the ratio of power in row 1 to total power in the row band is greater than ROW1, a row 1 signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. 49 2 DTMF Row 2 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 2 DTMF detection. If the ratio of power in row 2 to total power in the row band is greater than ROW2, a row 2 signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. 49 3 DTMF Row 3 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 3 DTMF detection. If the ratio of power in row 3 to total power in the row band is greater than ROW3, a row 3 signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. 49 4 DTMF Column Peak Magnitude Pass Threshold. This register sets the minimum power ratio threshold for column DTMF detection; all columns use the same threshold. If the ratio of power in a particular column to total power in the column band is greater than COL, a column detect for that particular column signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. 49 5 DTMF Forward Twist Threshold. This register sets the threshold for the power ratio of row power to column power. A value of 0x7F0 corresponds to a 1.0 ratio. 49 6 DTMF Reverse Twist Threshold. This register sets the threshold for the power ratio of column power to row power. A value of 0x7F0 corresponds to a 1.0 ratio. 49 7 DTMF Row Ratio Threshold. This register sets the threshold for the power ratio of highest power row to the other rows. A value of 0x7F0 corresponds to a 1.0 ratio. 49 8 DTMF Column Ratio Threshold. This register sets the threshold for the power ratio of highest power column to the other columns. A value of 0x7F0 corresponds to a 1.0 ratio. 49 9 DTMF Row Second Harmonic Threshold. This register sets the threshold for the power ratio of peak row tone to its second harmonic. A value of 0x7F0 corresponds to a 1.0 ratio. 49 10 DTMF Column Second Harmonic Threshold. This register sets the threshold for the power ratio of peak column tone to its second harmonic. A value of 0x7F0 corresponds to a 1.0 ratio. 49 11 DTMF Power Minimum Threshold. This register sets the threshold for the minimum total power in the DTMF calculation, under which the calculation is ignored. 49 12 DTMF Hot Limit Threshold. This register sets the two-step AGC in the DTMF path. 49 Rev. 1.61 119 Si3210/Si3211 4.2. Oscillators See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but must be written to zeroes. Table 39. Oscillator Indirect Registers Summary Addr. D15 D14 D13 D12 D11 D10 D9 D8 D7 13 OSC1[15:0] 14 OSC1X[15:0] 15 OSC1Y[15:0] 16 OSC2[15:0] 17 OSC2X[15:0] 18 OSC2Y[15:0] 19 ROFF[5:0] 20 RCO[15:0] 21 RNGX[15:0] 22 RNGY[15:0] 23 PLSD[15:0] 24 PLSX[15:0] 25 PLSCO[15:0] 120 Rev. 1.61 D6 D5 D4 D3 D2 D1 D0 Si3210/Si3211 Table 40. Oscillator Indirect Registers Description Addr. Description Reference Page 13 Oscillator 1 Frequency Coefficient. Sets tone generator 1 frequency. 41 14 Oscillator 1 Amplitude Register. Sets tone generator 1 signal amplitude. 41 15 Oscillator 1 Initial Phase Register. Sets initial phase of tone generator 1 signal. 41 16 Oscillator 2 Frequency Coefficient. Sets tone generator 2 frequency. 41 17 Oscillator 2 Amplitude Register. Sets tone generator 2 signal amplitude. 41 18 Oscillator 2 Initial Phase Register. Sets initial phase of tone generator 2 signal. 41 19 Ringing Oscillator DC Offset. Sets dc offset component (VTIP-VRING) to ringing waveform. The range is 0 to 94.5 V in 1.5 V increments. 43 20 Ringing Oscillator Frequency Coefficient. Sets ringing generator frequency. 43 21 Ringing Oscillator Amplitude Register. Sets ringing generator signal amplitude. 43 22 Ringing Oscillator Initial Phase Register. Sets initial phase of ringing generator signal. 43 23 Pulse Metering Oscillator Attack/Decay Ramp Rate. Sets pulse metering attack/decay ramp rate. 47 24 Pulse Metering Oscillator Amplitude Register. Sets pulse metering generator signal amplitude. 47 25 Pulse Metering Oscillator Frequency Coefficient. Sets pulse metering generator frequency. 47 Rev. 1.61 121 Si3210/Si3211 4.3. Digital Programmable Gain/Attenuation See functional description sections of digital programmable gain/attenuation for guidelines on computing register values. All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but must be written to zeroes. Table 41. Digital Programmable Gain/Attenuation Indirect Registers Summary Addr. D15 D14 D13 D12 D11 D10 D9 D8 26 DACG[11:0] 27 ADCG[11:0] D7 D6 D5 D4 D3 D2 D1 D0 Table 42. Digital Programmable Gain/Attenuation Indirect Registers Description Addr. Description Reference Page 26 Receive Path Digital to Analog Converter Gain/Attenuation. This register sets gain/attenuation for the receive path. The digitized signal is effectively multiplied by DACG to achieve gain/attenuation. A value of 0x00 corresponds to - dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. 49 27 Transmit Path Analog to Digital Converter Gain/Attenuation. This register sets gain/attenuation for the transmit path. The digitized signal is effectively multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to - dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. 49 122 Rev. 1.61 Si3210/Si3211 4.4. SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but must be written to zeroes. Table 43. SLIC Control Indirect Registers Summary Addr. D15 D14 D13 D12 D11 28 LCRT[5:0] 29 RPTP[5:0] D10 D9 30 CML[5:0] 31 CMH[5:0] 32 PPT12[7:0] 33 PPT34[7:0] 34 PPT56[7:0] D8 35 NCLR[12:0] 36 NRTP[12:0] 37 NQ12[12:0] 38 NQ34[12:0] 39 NQ56[12:0] 40 VCMR[3:0] 41 VMIND[3:0]* D7 D6 D5 D4 D3 D2 D1 D0 42 43 LCRTL[5:0] *Note: Si3210 only. Rev. 1.61 123 Si3210/Si3211 Table 44. SLIC Control Indirect Registers Description Addr. Description Reference Page 28 Loop Closure Threshold. Loop closure detection threshold. This register defines the upper bounds threshold if hysteresis is enabled (direct Register 108, bit 0). The range is 0-80 mA in 1.27 mA steps. 35 29 Ring Trip Threshold. Ring trip detection threshold during ringing. 46 30 Common Mode Minimum Threshold for Speed-Up. This register defines the negative common mode voltage threshold. Exceeding this threshold enables a wider bandwidth of dc linefeed control for faster settling times. The range is 0-23.625 V in 0.375 V steps. 31 Common Mode Maximum Threshold for Speed-Up. This register defines the positive common mode voltage threshold. Exceeding this threshold enables a wider bandwidth of dc linefeed control for faster settling times. The range is 0-23.625 V in 0.375 V steps. 32 Power Alarm Threshold for Transistors Q1 and Q2. 33 33 Power Alarm Threshold for Transistors Q3 and Q4. 33 34 Power Alarm Threshold for Transistors Q5 and Q6. 33 35 Loop Closure Filter Coefficient. 35 36 Ring Trip Filter Coefficient. 46 37 Thermal Low Pass Filter Pole for Transistors Q1 and Q2. 33 38 Thermal Low Pass Filter Pole for Transistors Q3 and Q4. 33 39 Thermal Low Pass Filter Pole for Transistors Q5 and Q6. 33 40 Common Mode Bias Adjust During Ringing. Recommended value of 0 decimal. 43 41 DC-DC Converter VOV Voltage (Si3210 only). 36 This register sets the overhead voltage, VOV, to be supplied by the dc-dc converter. When the VOV bit = 0 (direct Register 66, bit 4), VOV should be set between 0 and 9 V (VMIND = 0 to 6h). When the VOV bit = 1, VOV should be set between 0 and 13.5 V (VMIND = 0 to 9h). 42 Reserved. 43 Loop Closure Threshold--Lower Bound. This register defines the lower threshold for loop closure hysteresis, which is enabled in bit 0 of direct Register 108. The range is 0-80 mA in 1.27 mA steps. 124 Rev. 1.61 35 Si3210/Si3211 4.5. FSK Control For detailed instructions on FSK signal generation, refer to "Application Note 32: FSK Generation" (AN32). These registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6). Table 45. FSK Control Indirect Registers Summary Addr. D15 D14 D13 D12 D11 D10 D9 D8 D7 99 FSK0X[15:0] 100 FSK0[15:0] 101 FSK1X[15:0] 102 FSK1[15:0] 103 FSK01[15:0] 104 FSK10[15:0] D6 D5 D4 D3 D2 D1 D0 Table 46. FSK Control Indirect Registers Description Addr. Description Reference Page 99 FSK Amplitude Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when generating a space or "0". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1X. 43 and AN32 100 FSK Frequency Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the frequency to be used when generating a space or "0". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1. 43 and AN32 101 FSK Amplitude Coefficient for Mark. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when generating a mark or "1". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1X. 43 and AN32 102 FSK Frequency Coefficient for Mark. When FSKEN = 1 and REL = 1, this register sets the frequency to be used when generating a mark or "1". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1. 43 and AN32 103 FSK Transition Parameter from 0 to 1. When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is applied to signal amplitude when transitioning from a space (0) to a mark (1). 43 and AN32 104 FSK Transition Parameter from 1 to 0. When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is applied to signal amplitude when transitioning from a mark (1) to a space (0). 43 and AN32 Rev. 1.61 125 Si3210/Si3211 5. Pin Descriptions: Si3210/11 QFN DRX PCLK INT CS SCLK SDI SDO TSSOP 1 38 37 36 35 34 33 32 31 2 30 3 4 29 5 27 26 28 6 7 EPAD 25 8 9 24 23 10 22 21 11 12 13 14 15 16 17 18 19 20 SDITHRU DCDRV/DCSW DCFF/DOUT TEST GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP STIPE SVBAT SRINGE STIPAC SRINGAC IGMN GNDA DTX FSYNC RESET SDCH/DIO1 SDCL/DIO2 VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC CS INT PCLK DRX DTX FSYNC RESET SDCH/DIO1 SDCL/DIO2 VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC STIPE SVBAT SRINGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 SCLK SDI SDO SDITHRU DCDRV/DCSW DCFF/DOUT TEST GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP GNDA IGMN SRINGAC STIPAC QFN Pin # TSSOP Pin # Name 35 1 CS Chip Select. Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When active, the serial port is operational. 36 2 INT Interrupt. Description Maskable interrupt output. Open drain output for wire-ORed operation. 37 3 PCLK PCM Bus Clock. Clock input for PCM bus timing. 38 4 DRX Receive PCM Data. Input data from PCM bus. 1 5 DTX Transmit PCM Data. Output data to PCM bus. 2 6 FSYNC Frame Synch. 8 kHz frame synchronization signal for the PCM bus. May be short or long pulse format. 3 7 RESET Reset. Active low input. Hardware reset used to place all control registers in the default state. 4 8 SDCH/DIO1 DC Monitor/General Purpose I/O. DC-DC converter monitor input used to detect overcurrent situations in the converter (Si3210 only). General purpose I/O (Si3211 only). 126 Rev. 1.61 Si3210/Si3211 QFN Pin # TSSOP Pin # Name 5 9 SDCL/DIO2 Description DC Monitor/General Purpose I/O. DC-DC converter monitor input used to detect overcurrent situations in the converter (Si3210 only). General purpose I/O (Si3211 only). 6 10 VDDA1 Analog Supply Voltage. Analog power supply for internal analog circuitry. 7 11 IREF Current Reference. Connects to an external resistor used to provide a high accuracy reference current. 8 12 CAPP SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. 9 13 QGND Component Reference Ground. 10 14 CAPM SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. 11 15 STIPDC TIP Sense. Analog current input used to sense voltage on the TIP lead. 12 16 SRINGDC RING Sense. Analog current input used to sense voltage on the RING lead. 13 17 STIPE TIP Emitter Sense. Analog current input used to sense voltage on the Q6 emitter lead. 14 18 SVBAT VBAT Sense. Analog current input used to sense voltage on dc-dc converter output voltage lead. 15 19 SRINGE RING Emitter Sense. Analog current input used to sense voltage on the Q5 emitter lead. 16 20 STIPAC TIP Transmit Input. Analog ac input used to detect voltage on the TIP lead. 17 21 SRINGAC RING Transmit Input. Analog ac input used to detect voltage on the RING lead. 18 22 IGMN Transconductance Amplifier External Resistor. Negative connection for transconductance gain setting resistor. 19 23 GNDA Analog Ground. Ground connection for internal analog circuitry. 20 24 IGMP Transconductance Amplifier External Resistor. Positive connection for transconductance gain setting resistor. 21 25 IRINGN Negative Ring Current Control. Analog current output driving Q3. 22 26 IRINGP Positive Ring Current Control. Analog current output driving Q2. Rev. 1.61 127 Si3210/Si3211 QFN Pin # TSSOP Pin # Name 23 27 VDDA2 Description Analog Supply Voltage. Analog power supply for internal analog circuitry. 24 28 ITIPP Positive TIP Current Control. Analog current output driving Q1. 25 29 ITIPN Negative TIP Current Control. Analog current output driving Q4. 26 30 VDDD Digital Supply Voltage. Digital power supply for internal digital circuitry. 27 31 GNDD Digital Ground. Ground connection for internal digital circuitry. 28 32 TEST Test. Enables test modes for Silicon Labs internal testing. This pin should always be tied to ground for normal operation. 29 33 DCFF/DOUT DC Feed-Forward/High Current General Purpose Output. Feed-forward drive of external bipolar transistors to improve dc-dc converter efficiency (Si3210 only). High current output pin (Si3211 only). 30 34 DCDRV/DCSW DC Drive/Battery Switch. DC-DC converter control signal output which drives external bipolar transistor (Si3210 only). Battery switch control signal output which drives external bipolar transistor (Si3211 only). 31 35 SDITHRU SDI Passthrough. Cascaded SDI output signal for daisy-chain mode. 32 36 SDO Serial Port Data Out. Serial port control data output. 33 37 SDI Serial Port Data In. Serial port control data input. 34 38 SCLK Serial Port Bit Clock Input. Serial port clock input. Controls the serial data on SDO and latches the data on SDI. n/a n/a EPAD Exposed pad. Must have a low thermal resistance connection to ground. 128 Rev. 1.61 Si3210/Si3211 6. Pin Descriptions: Si3201 TIP 1 16 ITIPP NC 2 15 RING 3 14 ITIPN IRINGP VBAT VBATH 4 13 IRINGN 5 12 NC NC 6 11 STIPE GND 7 10 SRINGE VDD 8 9 NC Pin # Name Input/ Output 1 TIP I/O TIP Output--Connect to the TIP lead of the subscriber loop. 2, 6, 9, 12 NC -- No Internal Connection--Do not connect to any electrical signal. 3 RING I/O RING Output--Connect to the RING lead of the subscriber loop. 4 VBAT -- Operating Battery Voltage--Connect to the battery supply. 5 VBATH -- High Battery Voltage--This pin is internally connected to VBAT. 7 GND -- Ground--Connect to a low impedance ground plane. 8 VDD -- Supply Voltage--Main power supply for all internal circuitry. Connect to a 3.3 V or 5 V supply. Decouple locally with a 0.1 F/6 V capacitor. 10 SRINGE O RING Emitter Sense Output--Connect to the SRINGE pin of the Si321x pin. 11 STIPE O TIP Emitter Sense Output--Connect to the STIPE pin of the Si321x pin. 13 IRINGN I Negative RING Current Control--Connect to the IRINGN lead of the Si321x. 14 IRINGP I Positive RING Current Drive--Connect to the IRINGP lead of the Si321x. 15 ITIPN I Negative TIP Current Control--Connect to the ITIPN lead of the Si321x. 16 ITIPP I Positive TIP Current Control--Connect to the ITIPP lead of the Si321x. Bottom-Side Exposed Pad -- Description Exposed Thermal Pad--Connect to the bulk ground plane. Rev. 1.61 129 Si3210/Si3211 7. Ordering Guide Chip Description DC-DC Converter DTMF Decoder DCFF Pin Output Package Lead-Free and RoHSCompliant Temperature Si3210-E-FM ProSLIC DCDRV QFN-38 Yes 0 to 70 C Si3210-E-GM ProSLIC DCDRV QFN-38 Yes -40 to 85 C Si3210M-E-FM ProSLIC DCDRV QFN-38 Yes 0 to 70 C Si3210M-E-GM ProSLIC DCDRV QFN-38 Yes -40 to 85 C Si3210-FT ProSLIC DCDRV TSSOP-38 Yes 0 to 70 C Si3210-GT ProSLIC DCDRV TSSOP-38 Yes -40 to 85 C Si3210M-FT ProSLIC DCDRV TSSOP-38 Yes 0 to 70 C Si3210M-GT ProSLIC DCDRV TSSOP-38 Yes -40 to 85 C Si3211-E-FT ProSLIC n/a TSSOP-38 Yes 0 to 70 C Si3211-E-GT ProSLIC n/a TSSOP-38 Yes -40 to 85 C Si3211-E-FM ProSLIC n/a QFN-38 Yes 0 to 70 C Si3211-E-GM ProSLIC n/a QFN-38 Yes -40 to 85 C Si3201-FS Linefeed Interface n/a SOIC-16 Yes 0 to 70 C Si3201-GS Linefeed Interface n/a SOIC-16 Yes -40 to 85 C Note: Add an "R" at the end of the device to denote tape and reel; 2500 quantity per reel. 130 Rev. 1.61 Si3210/Si3211 Table 47. Evaluation Kit Ordering Guide Item Supported ProSLIC Description Linefeed Interface Si3210PPQX-EVB Si3210-QFN Eval Board, Daughter Card Discrete Si3210PPQ1-EVB Si3210-QFN Eval Board, Daughter Card Si3201 Si3210PPTX-EVB Si3210-TSSOP Eval Board, Daughter Card Discrete Si3210PPT1-EVB Si3210-TSSOP Eval Board, Daughter Card Si3201 Si3210MPPTX-EVB Si3210M-TSSOP Eval Board, Daughter Card Discrete Si3210MPPT1-EVB Si3210M-TSSOP Eval Board, Daughter Card Si3201 Si3211PPTX-EVB Si3211-TSSOP Eval Board, Daughter Card Discrete Rev. 1.61 131 Si3210/Si3211 8. Package Outlines and PCB Land Patterns 8.1. 38-Pin QFN 8.1.1. Package Outline: 38-Pin QFN Figure 33 illustrates the package details for the Si321x. Table 48 lists the values for the dimensions shown in the illustration. 2X bbb C B A ccc D C D2 A D/2 DETAIL "B" D2/2 A1 2X aaa C A 38 32 31 1 38 32 31 1 E/2 E2/2 E2 E e 20 12 13 20 19 12 19 13 38X L B 38X b C SEATING PLANE Detail A DETAIL "A" Detail B Pin-1 Identifier 38 (L) L1 38 1 1 (b) Option 1 Chamfered Corner Option 2 Corner Square Figure 33. 38-Pin Quad Flat No-Lead Package (QFN) 132 Rev. 1.61 ddd C A B Si3210/Si3211 Table 48. Package Diagram Dimensions1,2,3 Millimeters Symbol Min Nom Max A 0.75 0.85 0.95 A1 0.00 0.01 0.05 b 0.18 0.23 0.30 D D2 5.00 BSC. 3.10 e 3.20 3.30 0.50 BSC. E 7.00 BSC. E2 5.10 5.20 5.30 L 0.35 0.45 0.55 L1 0.03 0.05 0.08 aaa -- -- 0.10 bbb -- -- 0.10 ccc -- -- 0.08 ddd -- -- 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1982. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Rev. 1.61 133 Si3210/Si3211 8.1.2. PCB Land Pattern: 38-Pin QFN Figure 34 shows the recommended land pattern for the Si3210/11 QFN-38 package. Table 49 lists the values for the dimensions shown in the illustration. Figure 34. QFN-38 Land Pattern Drawing 134 Rev. 1.61 Si3210/Si3211 Table 49. QFN-38 PCB Land Pattern Dimensions Dimension Feature Min. Max. C1 Pad column spacing 4.70 4.80 C2 Pad row spacing 6.70 6.80 E Pad pitch X1 Pin pad width 0.20 0.30 X2 Thermal pad width 3.20 3.30 Y1 Pin pad width 0.80 0.90 Y2 Thermal pad length 5.20 5.30 0.50 BSC Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60m minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads 4. A 3x5 array of 0.90mm square openings on 1.10mm pitch should be used for the center ground pad. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPEC J-STD-020C specification for Small Body Components. Rev. 1.61 135 Si3210/Si3211 8.2. 38-Pin TSSOP 8.2.1. Package Outline: 38-Pin TSSOP Figure 35 illustrates the package details for the Si321x. Table 50 lists the values for the dimensions shown in the illustration. Figure 35. 38-Pin Thin Shrink Small Outline Package (TSSOP) Table 50. Package Diagram Dimensions Millimeters Symbol Min Nom Max A -- -- 1.20 A1 0.05 -- 0.15 A2 0.80 1.00 1.05 b 0.17 -- 0.27 c 0.09 -- 0.20 D 9.60 9.70 9.80 E E1 6.40 BSC 4.30 e L 0.45 L2 136 4.40 4.50 0.50 BSC 0.60 0.75 0.25 BSC 0 -- aaa 0.10 bbb 0.08 ccc 0.20 Rev. 1.61 8 Si3210/Si3211 8.2.2. PCB Land Pattern: 38-Pin TSSOP Figure 36 illustrates the recommended land pattern for the Si3210/11 TSSOP-38 package. Table 51 lists the values for the dimensions shown in the illustration. Figure 36. TSSOP-38 PCB Land Pattern Drawing Table 51. PCB Land Pattern Dimensions Dimension Feature (mm) Pad Column Spacing 5.80 E Pad Row Pitch 0.50 X1 Pad Width 0.30 Y1 Pad Length 1.45 C1 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ASME Y14.5M-1994. 3. This Land Pattern Design is based on IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabirication Allowance of 0.05mm. 5. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.61 137 Si3210/Si3211 8.3. 16-Pin ESOIC 8.3.1. Package Outline: 16-Pin ESOIC Figure 37 illustrates the package details for the Si3201. Table 52 lists the values for the dimensions shown in the illustration. Figure 37. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package Table 52. Package Diagram Dimensions Millimeters Symbol A A1 A2 b c D D1 E E1 E2 e L L2 h aaa bbb ccc ddd 138 Min -- 0.00 1.25 0.31 0.17 Max 1.75 0.15 -- 0.51 0.25 9.90 BSC 3.45 3.65 6.00 BSC 3.90 BSC 2.20 2.40 1.27 BSC 0.40 1.27 0.25 BSC 0.25 0 0.50 8 0.10 0.20 0.10 0.25 Rev. 1.61 Si3210/Si3211 8.3.2. PCB Land Pattern: 16-Pin ESOIC Figure 38 illustrates the recommended land pattern for the Si3201 SOIC-16 package. Table 53 lists the values for the dimensions shown in the illustration. Figure 38. SOIC-16 PCB Land Pattern Drawing Table 53. SOIC-16 PCB Land Pattern Dimensions Dimension Feature Min Max C1 Pin pad column spacing 5.30 5.40 E Pin pad row pitch X1 Pin pad width 0.50 0.60 Y1 Pin pad length 1.45 1.55 X2 Thermal pad width 2.20 2.30 Thermal pad length 3.50 3.60 Y2 1.27 BSC Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ASME Y14.5M-1994. 3. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X175-17N. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60m minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Rev. 1.61 139 Si3210/Si3211 9. Product Identification 9.1. Ordering Part Number The ordering part number indicates the device number, device variant (optional), device revision level, package type, temperature range, and packing format, e.g., tape-and-reel, and identifies Silicon Laboratories as the manufacturer. It will be of the following form: Si 32 10 M - E - FM R Pack ing format, e.g., tape-and-reel Pack age and temperature range Revision level (if applicable Part variant (if applicable) Part number Silicon Laboratories See the ordering guide above for a list of valid ordering part numbers. 9.2. Marking Part Number See the Package Marking section for an example and explanation of the markings on the device. Note that the part number marked on the device is different from the Ordering Part Number and that the product revision level is indicated by the first (1st) character of the Manufacturing Code. 140 Rev. 1.61 Si3210/Si3211 10. Package Marking (Top Mark) 10.1. QFN Package Figure 39. QFN Top Mark Diagram Table 54. Explanation of QFN Top Mark Line 1 Marking: Line 2 Marking: Line 3 Marking: Silicon Labs prefix "Si" Device number e.g., "3210" Device variant (optional) e.g., "M" Separator "-" Package/temperature range e.g., "FM', "GM", etc YY=Year WW=Work Week Date of manufacture TTTTTT=Mfg Code Internal manufacturing code; 1st character=product revision level Circle=0.5 mm Diameter Lower Left-Justified Pin 1 Identifier Circle=1.3 mm Diameter Center-Justified "e3" Pb-Free Symbol Country of Origin ISO Code Abbreviation e.g., KR, TW, etc Rev. 1.61 141 Si3210/Si3211 10.2. TSSOP Package Figure 40. TSSOP Top Mark Diagram Table 55. Explanation of TSSOP Top Mark Line 1 Marking: Line 2 Marking: Line 3 Marking: 142 Silicon Labs prefix "Si" Device number e.g., "3210" Device variant (optional) e.g., "M" Separator "-" Package/temperature range e.g., "FM', "GM", etc YY=Year WW=Work Week Date of manufacture RFAIXX=Mfg Code Internal manufacturing code; 1st character=product revision level Circle=0.5 mm Diameter Lower Left-Justified Pin 1 Identifier Circle=1.3 mm Diameter Center-Justified "e3" Pb-Free Symbol Country of Origin ISO Code Abbreviation e.g., KR, TW, etc Rev. 1.61 Si3210/Si3211 10.3. SOIC (Si3201) Package Figure 41. SOIC Top Mark Diagram Table 56. Explanation of SOIC Top Mark Line 1 Marking: Line 2 Marking: Silicon Labs prefix "Si" Device number e.g., "3201" Separator "-" Package/temperature range e.g., "GS" Circle=0.5 mm Diameter Center-Justified Pin 1 Identifier Circle=1.3 mm Diameter Lower Left-Justified "e3" Pb-Free Symbol YY=Year WW=Work Week Date of manufacture TTTTTT Internal manufacturing code; 1st character=product revision level Rev. 1.61 143 Si3210/Si3211 DOCUMENT CHANGE LIST Moved the schematic for the supply filtering network for VDDA1, VDDA2, and VDDD from the bottom of the diagram to the top. Moved the symbol for C9 closer to the VBATH pin on the Si3201 symbol. Changed R26 to 10 k. Added Note 4. Revision 1.41 to Revision 1.42 16-pin ESOIC dimension A1 corrected in Table 50 on page 136. Delay time between chip selects, tcs, changed from 220 ns to 440 ns in Table 10 on page 13. C10 changed from 22 nF to 0.1 F in Figure 10 on page 18. C18, C19 changed from 1.0 F to 4.7 F in Figure 12 on page 22. Recommended value for Indirect Register 40 changed from 6 to 0 in Table 44 on page 124. Added QFN package option. Revision 1.42 to Revision 1.43 the schematic for the supply filtering network for VDDA1, VDDA2, and VDDD from the bottom of the diagram to the top. Added Note 5 and moved the symbol for C26 to better illustrate its optimal position in a board layout. Changed R26 to 10 k. Added Note 6. the schematic for the supply filtering network for VDDA1, VDDA2, and VDDD from the bottom of the diagram to the top. Added Note 3 and moved the symbol for C26 to better illustrate its optimal position in a board layout. Added Note 4. Changed R26 to 10 k. Corrected connection between D1 and the linefeed components. Added Note 5 TO-92 transistor suppliers to BOM. "7. Ordering Guide" on page 130 to include product revision designator. changed to "Lead-Free and RoHSCompliant" "Lead-Free" Figure , "," on page 17. Added additional decoupling components to VDDA1, VDDA2, and VDDD. Figure 12, "Si3211 Typical Application Circuit Using Si3201," on page 22. additional decoupling components to VDDA1, VDDA2, and VDDD. longitudinal current per pin for EBTO/ EBTA = 10 to 12 mA. Figure 13, "Si3210/Si3210M Typical Application Circuit Using Discrete Components," on page 24. additional decoupling components to VDDA1, VDDA2, and VDDD. Added optional components to STIPE, SRINGE, and SVBAT pins to improve idle channel noise. Figure 14, "Si3211 Typical Application Circuit Using Discrete Solution," on page 26. typical values for IVDD and IBAT for VDDD, VDDA = 3.3 V. "PCLK Period Jitter Tolerance" to "PCLK-to-FSYNC Jitter Tolerance". Added Note 2. Changed title for AN45 to description of R28 and R29. column for component package type. Added Note 1. Added Updated Figure 12. 144 Updated Table 13. Rev. 1.61 column for component package type. Updated Table 14. Added the schematic for the supply filtering network for VDDA1, VDDA2, and VDDD from the bottom of the diagram to the top. Moved the symbol for C26 closer to the VBATH pin on the Si3201 symbol. Changed R26 to 10 k. Added Note 5. 10 k. Updated Figure 9. Moved current rating of L2 to 150 mA. new row for R26 and changed the value to Added Added Revision 1.43 to Revision 1.44 Added A1 max dimension from 0.10 to 0.15. Updated Table 12. Changed additional decoupling components to VDDA1, VDDA2, and VDDD. Added optional components to STIPE, SRINGE, and SVBAT pins to improve idle channel noise. Table 52, "Package Diagram Dimensions," on page 138 Updated Table 11. Renamed Added Updated Table 8. Filled-in Added Updated Table 3. Corrected Added Updated Figure 14. Moved Updated Updated Figure 13. Moved Table 16, "Si3210/Si3210M External Component Values--Discrete Solution," on page 25. Added column for component package type. Updated Table 15. Changed Added current rating of L2 to 150 mA. new row for R26 and changed the value to 10 k. Rearranged the rows for R8 through R32 to be in numerical order. Added column for component package type. Added Note 1. Si3210/Si3211 Updated Table 16. Changed current rating of L2 to 150 mA. missing reference to R5. Added new row for R26 and changed the value to 10 k. Added title for AN45 to description of R28 and R29. Added column for component package type. Added Note 1. Corrected Updated Table 17. Added new row for R26 and changed the value to 10 k. column for component package type. Added Note 1. Added Updated Table 18. Added Added column for component package type. Updated Table 19. column for component package type. Updated Table 36. Added mnemonic for bit 7 of direct register 1 (PNI2). name of Register 94 to match the name in the description of Register 94. Changed Updated Table 47. Removed Updated Register 1. Added mnemonic and description of bit 7 (PNI2). Updated Register 75. Clarified unsupported evaluation kit part numbers. the description of VBATL for Si3211. Updated "2.1.6. Loop Closure Transition Detection" on page 35. Modified first and second paragraphs to indicate that a loop closure event signals a transition from on-hook to off-hook or from off-hook to on-hook. Updated "2.4.2. Sinusoidal Ringing" on page 44. Modified second paragraph to indicate the minimum allowed peak TIP-to-RING ringing voltage depends on the linefeed state; i.e. forward-active or reverse-active. Updated "2.9. Clock Generation" on page 52. Modified Modified first paragraph to indicate that 768 kHz and 1.536 MHz are not valid rates for GCI mode. Updated "2.12. PCM Interface" on page 56. first paragraph to indicate that 768 kHz and 1.536 MHz are not valid rates for GCI mode. Updated "8.1.2. PCB Land Pattern: 38-Pin QFN" on page 134 with more detailed package drawing. Updated "8.3.1. Package Outline: 16-Pin ESOIC" on page 138 with more detailed package drawing. Revision 1.44 to Revision 1.45 Added Si3211-E-FT and Si3211-E-GT to Ordering Guide Clarified Ordering Guide Replaced Removed "X" with revision letter "E" in all ordering codes requiring a revision letter Note 1 from Ordering Guide Revision 1.45 to Revision 1.5 Front page: Changed Minor images to QFN-38 clean-up edits Removed erroneous reference to polarity reversal feature on front page Updated references to "K" and "B" temperature grades to "F" and "G", respectively, in Electrical Characteristics tables Clarified Gain Error specifications in "Table 5. Monitor ADC Characteristics" Corrected description of "Register 9. Audio Gain Control", Bit 7 ("RHDF"--> "RHPF") Corrected reset setting of "Register 68. Loop Closure/Ring Trip Detect Status"(0000_0000b-->0000_0100b) Removed obsolete non-RoHS-compliant device variants from the Ordering Guide Updated QFN package drawing and dimensions Added "8. Package Outlines and PCB Land Patterns" Rev. 1.61 145 Si3210/Si3211 Added "9. Product Identification" Added "10. Package Marking (Top Mark)" Removed erroneous entry in the previous Document Change List, Revision 1.44 to 1.45, "Added QFN-38 image to front page." Added a note to Table 9 cross-referencing it with section 1.2 ProSLIC Initialization in AN35. Updated contact information. Revision 1.5 to Revision 1.6 Updated "Power Supply Current, Analog and Digital" specification in Table 8. (Not released.) Revision 1.6 to Revision 1.61 Updated "Power Supply Current, Analog and Digital" specification in Table 8. 146 Rev. 1.61 Si3210/Si3211 NOTES: Rev. 1.61 147 Si3210/Si3211 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 148 Rev. 1.61