Rev. 1.61 1/12 Copyright © 2012 by Silicon Laboratories Si3210
Si3210/Si3211
PROSLIC® PROGRAMMABLE CMOS SLIC/CODEC
WITH RINGING/BATTERY VOLTAGE GENERATION
Features
Applications
Description
The Si3210/11 ProSLIC® chipset pro vid es a compl ete analog teleph one in te rf ace ideal
for customer premise equipment (CPE). It integrates a subscriber line interface circuit
(SLIC), voice codec, and battery generation (Si3210) or battery selection (Si3211) into
a single CMOS integrated circuit. The battery supply continuously adapts its output
voltage to minimize power dissipation and enables the entire circuit to be powered
from a single 3.3 or 5 V supply (Si3210). The CMOS ProSLIC interfaces to the line
through either the Si3201 Line-feed IC or a discrete line-feed circuit.
Si3210/11 features include software-configurable 5 REN internal ringing up to 90 VPK,
DTMF generation and decoding, Caller ID generation, and a comprehensive set of
telephony signaling capabilities for global operation with a single hardware solution.
The Si3210/11 is packaged in a 38-pin Q FN or TSSOP, and the Si3201 is packaged in
a thermally-enhanced 16-pin SOIC.
Functional Block Diagram
100% programmable global solution
Performs all BORSCHT functions
DC-DC controller provides tracking
battery from a 3.3–35V input (Si3210)
Minimizes power in all modes
Dynamic 0 to –94.5 V output
Choice of inductor (low cost ) or
transformer (high efficiency)
Programmable line-feed parameters
2-wire AC impedance and hybrid
Constant current feed (20 to 41 mA)
Loop closure and ring trip thresholds
and filtering
Internal balanced ringing up to 90VPK
5 REN up to 4 kft; 3 REN up to 8 kft
Programmable frequency, amplitude,
cadence, and wave shape
Programmable audio processing
DTMF encoding and decodin g
12 kHz/16 kHz pulse metering
Phase-continuous FSK (caller ID)
Dual tone generato rs
-Law/A-Law and linear PCM audio
Extensive test and diagnostic features
Multiple l oopback test modes
DC line V/I measurements
Supports GR-909 MLT
Comprehensive design tool s
Reference schematic and PCB
layout
ProSLIC API abstracts SLIC
functions, minimizing software
development
RoHS-compliant p ackages
SPI and PCM bus digital interfaces
Fixed Wireless (cellular) Terminals
Terminal Adapters
PBX/IP-PBX/Key telephone systems
Voice-over-IP Systems:
DSL/EMTAs/FTTx
WiMax/LTE
Linefeed
Interface
Control
Interface
PCM
Interface
PLL
DTMF
Decode
Gain/
Attenuation/
Filter
Tone
Generators
CompressionExpansion
Gain/
Attenuation/
Filter
Line
Feed
Control
Line
Status
DC-DC Converter Controller
(Si3210 only)
Prog.
Hybrid
D/A ZS
A/D TIP
RING
CS
SCLK
SDO
SDI
DTX
DRX
FSYNC
PCLK
RESETINT Si3210/11
Discrete
Components
U.S. Patent #6,567,521
U.S. Patent #6,812,744
Ordering Information
See page 130.
QFN Pin Assignments
Si3210/11
27
28
29
30
31
34 33 32
1
2
3
4
5
6
7
8
9
10
11
12 13
26
25
14
35363738
15 16 17 18 19
24
23
22
21
20
QFN
DTX
FSYNC
RESET
SDCH/DIO1
SDCL/DIO2
VDDA1
IREF
CAPP
QGND
CAPM
STIPDC
SRINGDC
STIPE
SVBAT
SRINGE
STIPAC
SRINGAC
IGMN
GNDA
IGMP
IRINGN
IRINGP
VDDA2
ITIPP
ITIPN
VDDD
GNDD
TEST
DCFF/DOUT
DCDRV/DCSW
SDITHRU
SDO
SDI
SCLK
CS
INT
PCLK
DRX
Si3210/Si3211
2 Rev. 1.61
TABLE OF CONTENTS
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.1. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.2. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.3. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.4. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
2.5. Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2.6. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2.7. Audio Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
2.8. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.9. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.10. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.11. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.12. PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.13. Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
4. Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
4.1. DTMF Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
4.2. Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
4.3. Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
4.4. SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
4.5. FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
5. Pin Descriptions: Si3210/11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
8. Package Outlines and PCB Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
8.1. 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
8.2. 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
8.3. 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
9. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.1. Ordering Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
9.2. Marking Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
10. Package Marking (Top Mark) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
10.1. QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
10.2. TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
10.3. SOIC (Si3201) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Si3210/Si3211
Rev. 1.61 3
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information1
Parameter Symbol Value Unit
Si3210/11
DC Supply Voltage VDDD, VDDA1, VDDA2 –0.5 to 6.0 V
Input Current, Digi tal Input Pins IIN ±10 mA
Digital Input Voltage VIND –0.3 to (VDDD +0.3) V
Operating Temperature Range2TA–40 to 100 C
Storage Temperature Range TSTG –40 to 150 C
TSSOP-38 Thermal Resistance, Typical JA 70 C/W
QFN-38 Thermal Resistance, Typical JA 35 C/W
Continuous Power Dissipation2PD0.7 W
Si3201
DC Supply Voltage VDD –0.5 to 6.0 V
Battery Supply Voltage VBAT –104 V
Input Voltage: TIP, RING, SRINGE, STIPE pins VINHV (VBAT – 0.3) to (VDD + 0.3) V
Input Voltage: ITIPP, ITIPN, IRINGP, IRINGN pins VIN –0.3 to (VDD + 0.3) V
Operating Temperature Range2TA–40 to 100 C
Storage Temperature Range TSTG –40 to 150 C
SOIC-16 Thermal Resistance, Typical3JA 55 C/W
Continuous Power Dissipation2PD0.8 at 70 °C W
0.6 at 85 °C
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation shoul d be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for ex tended periods may affect device reliabili ty.
2. Operation above 125 °C junction temperature may degrade device reliability.
3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.
Si3210/Si3211
4 Rev. 1.61
Table 2. Recommended Operating Conditions
Parameter Symbol Test Condition Min*Typ Max*Unit
Ambient Temperature TAF-grade 0 25 70 °C
Ambient Temperature TAG-grade –40 25 85 °C
Si3210/11 Supply Voltage VDDD,VDDA1,
VDDA2 3.13 3.3/5.0 5.25 V
Si3201 Supply Voltage VDD 3.13 3.3/5.0 5.25 V
Si3201 Battery Voltage VBAT VBATH =V
BAT –96 — –10 V
*Note: All minimum and maximum specifications are guaranteed and apply across the recomme nded operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
Product specifications are only guaranteed for the typical application circuit (including comp onent tolerances).
Table 3. AC Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter Test Condition Min Typ Max Unit
TX/RX Performance
Overload Level THD = 1.5% 2.5 — — VPK
Single Frequency Distortion12-wire – PCM or
PCM – 2-wire:
200 Hz–3.4 kHz ——–45dB
Signal-to-(Noise + Distortion) Ratio2
200 Hz to 3.4 kHz
D/A or A/D 8-bit
Active off-h ook, and OHT,
any ZAC
Figure 1 — —
Audio Tone Generator
Signal-to-Distortion Ratio20 dBm0, Active off-hook,
and OHT, any Zac 45 — — dB
Intermodulation Distortion — — –45 dB
Gain Accuracy22-wire to PCM, 1014 Hz –0.5 0 0.5 dB
PCM to 2-wire, 1014 Hz –0.5 0 0.5 dB
Gain Accuracy over Frequency Figure 3,4 — —
Group Delay over Frequency Figure 5,6 — —
Gain Tracking3
1014 Hz sine wave,
reference level –10 dBm
signal level:
3 to –37 dB –0.25 — 0.25 dB
–37 to –50 dB –0.5 — 0.5 dB
–50 to –60 dB –1.0 — 1.0 dB
Round-Trip Group Delay at 1000 Hz — 1100 — µs
Gain Step Accuracy –6 to +6 dB –0.017 — 0.017 dB
Gain Variation with Temperature All gain settings –0.25 — 0.25 dB
Gain Variation with Supply VDDA =V
DDA = 3.3/5 V ±5% –0.1 — 0.1 dB
Si3210/Si3211
Rev. 1.61 5
2-Wire Return Loss 200 Hz to 3.4 kHz 30 35 — dB
Transhybrid Balance 300 Hz to 3.4 kHz 30 — — dB
Noise Performance
Idle Channel Noise4C-Message Weighted — — 15 dBrnC
Psophometric Weighted — — –75 dBmP
3 k Hz flat — — 18 dBrn
PSRR from VDDA RX and TX, DC to 3.4 kHz 40 — — dB
PSRR from VDDD RX and TX, DC to 3.4 kHz 40 — — dB
PSRR from VBAT RX and TX, DC to 3.4 kHz 40 — — dB
Longitudinal Performance
Longitudinal to Metallic
or PCM Balance
200 Hz to 3.4 kHz, Q1,Q2
150, 1% mismatch 56 60 — dB
Q1,Q2 60 to 240543 60 — dB
Q1,Q2 300 to 800553 60 — dB
Using Si3201 53 60 — dB
Metallic to Longitudinal Balance 200 Hz to 3.4 kHz 40 — — dB
Longitudinal Impedance
200 Hz to 3.4 kHz at TIP or
RING
Register selectable
ETBO/ETBA
00
01
10
—
—
—
33
17
17
—
—
—
Longitudinal Current per Pin
Active off-hook
200 Hz to 3.4 kHz
Register selectable
ETBO/ETBA
00
01
10
—
—
—
4
8
12
—
—
—
mA
mA
mA
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be
–10 dBm0. The output signal magnitude at any other frequ ency will be smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inhe rent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer diviso rs of the 8 kHz PCM
sampling rate.
4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
5. Assumes normal distribution of betas.
Table 3. AC Characteristics (Continued)
(VDDA, VDDD = 3.13 to 5.25 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter Test Condition Min Typ Max Unit
Si3210/Si3211
6 Rev. 1.61
Figure 1. Transmit and Receive Path SNDR
Figure 2. Overload Compression Performance
123456789
1
2
3
4
5
6
7
8
9
0
2.6
Acceptable
Region
Fundamental Input Power (dBm0)
Fundamental
Output Power
(dBm0)
Si3210/Si3211
Rev. 1.61 7
Figure 3. Transmit Path Frequency Response
Typical Response
Typical Response
Si3210/Si3211
8 Rev. 1.61
Figure 4. Receive Path Frequency Response
Si3210/Si3211
Rev. 1.61 9
Figure 5. Transmit Group Delay Distortion
Figure 6. Receive Group Delay Distortion
Si3210/Si3211
10 Rev. 1.61
Table 4. Linefeed Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA= 0 to 70°C for F-Grade, –40 to 85°C for G-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
Loop Resistance Range* RLOOP See *Note. 0 — 160
DC Loop Current Accuracy ILIM = 29 mA, ETBA = 4 mA –10 — 10 %
DC Open Circuit Voltage
Accuracy Active Mode; VOC =48V,
VTIP – VRING –4 — 4 V
DC Differential Output
Resistance RDO ILOOP < ILIM —160—
DC Open Circuit Voltage—
Ground Start VOCTO IRING<ILIM; VRING wrt ground
VOC =48V –4 — 4 V
DC Output Resistance—
Ground Start RROTO IRING<ILIM; RING to ground —160—
DC Output Resistance—
Ground Start RTOTO TIP to ground 150 — — k
Loop Closure/Ring Ground
Detect Thr eshold Accuracy ITHR = 11.43 mA –20 — 20 %
Ring Trip Threshold
Accuracy ITHR = 40.64 mA –10 — 10 %
Ring Trip Response T ime User Programmable Register 70
and Indirect Register 36 ———
Ring Amplitude VTR 5 REN load; sine wave;
RLOOP =160VBAT = –75 V 44 — — Vrms
Ring DC Offset ROS Programmable in Indirect
Register 19 0——V
Tr ap ez oid a l Ring Cre st
Factor Accuracy Crest factor = 1.3 –.05 — .05
Sinusoidal Ring Crest
Factor RCF 1.35 — 1.45
Ringing Frequency Accuracy f = 20 Hz –1 — 1 %
Ringing Cadence Accuracy Accuracy of ON/OFF Times –50 — 50 ms
Calibration Time CAL to CAL Bit — — 600 ms
Power Alarm Threshold
Accuracy At Power Threshold = 300 mW –25 — 25 %
*Note: DC resistance round trip; 160 corresponds to 2 kft, 26 gauge AWG.
Si3210/Si3211
Rev. 1.61 11
Table 5. Monitor ADC Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
Differential Nonlinearity
(6-bit resolution) DNLE –1/2 — 1/2 LSB
Integral Nonlinearity
(6-bit resolution) INLE –1 — 1 LSB
Gain Error (Voltage) — — 10 %
Gain Error (Current) — — 20 %
Table 6. Si321x DC Characteristics, VDDA =V
DDD =5.0V
(VDDA,VDDD = 4.75 to 5.25 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 0.7 x VDDD ——V
Low Level Input Voltage VIL ——0.3xV
DDD V
High Level Output Voltage
VOH
DIO1,DIO2,SDITHRU:
IO= –4 mA SDO,
DTX:IO=–8mA VDDD – 0.6 — — V
DOUT: IO=–40mA VDDD – 0.8 — — V
Low Level Output Voltage VOL
DIO1,DIO2,DOUT,SDITHRU:
IO=4mA
SDO,INT,DTX:IO=8mA ——0.4V
Input Leakage Current IL–10 — 10 µA
Table 7. Si321x DC Characteristics, VDDA =V
DDD =3.3V
(VDDA,VDDD = 3.13 to 3.47 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 0.7 x VDDD —— V
Low Level Input Voltage VIL ——0.3xV
DDD V
High Level Output Voltage VOH
DIO1,DIO2,SDITHRU: IO =–2 mA
SDO, DTX:IO=–4mA VDDD – 0.6 — — V
DOUT: IO= –40 mA VDDD – 0.8 — — V
Low Level Output Voltage VOL
DIO1,DIO2,DOUT,SDITHRU:
IO=2mA
SDO,INT,DTX:IO=4mA ——0.4V
Input Leakage Current IL–10 — 10 µA
Si3210/Si3211
12 Rev. 1.61
Table 8. Power Supply Characteristics
(Unless otherwise noted, VDDA, VDDD=3.13 to 5.25 V; TA=0 to 70C for F-grade, –40 to 85C for G-grade)
Parameter Symbol Test Condition Typ1Typ2Max Unit
Power Supply Current,
Analog and Digital IA + ID
Sleep (RESET =0),
VDDA=VDDD=3.13 to 3.465 V 0.1 — 0.3 mA
Sleep (RESET =0),
VDDA=VDDD=4.75 to 5.25 V,
TA=0 to 70C/F-grade —0.10.3mA
Sleep (RESET =0),
VDDA=VDDD=4.75 to 5.25 V,
TA=–40 to 85C/G-grade — 0.1 0.35 mA
Open 33 42.8 49 mA
Active on-hook
ETBO = 4 mA, codec and Gm amplifier
powered down 37 53 68 mA
Active OHT
ETBO = 4 mA 57 72 83 mA
Active off-hook
ETBA = 4 mA, ILIM =20mA 738899mA
Ground Start 36 47 55 mA
Ringing sinewave, REN = 1, VPK =56V 45 55 65 mA
VDD Supply Current (Si3201) IVDD
Sleep mode, RESET = 0 100 100 — µA
Open (high impedance) 100 100 — µA
Active on-hook standby 110 110 — µA
Forward/reverse active off-hook, no ILOOP,
ETBO = 4 mA, VBAT =–24V 11—mA
Forward/reverse OHT, ETBO = 4 mA,
VBAT =–70V 11—mA
VBAT Sup ply Current3IBAT
Sleep (RESET =0) 0 0 — mA
Open (DCOF = 1) 0 0 — mA
Active on-hook
VOC = 48 V, ET BO = 4 mA 3 3 — mA
Active OHT
ETBO = 4 mA 11 11 — mA
Active off-hook
ETBA = 4 mA, ILIM =20mA 30 30 — mA
Ground Start 2 2 — mA
Ringing: VPK_RING = 56 VPK,
Sinewave ringing: REN = 1 5.5 5.5 — mA
VBAT Supply Slew Rate When using Si3201 — — 10 V/µs
Si3210/Si3211
Rev. 1.61 13
Notes:
1. VDDD, VDDA =3.3V.
2. VDDD, VDDA =5.25V.
3. IBAT = current from VBAT (the large negative supply). For a switched-mode power supp ly regulator efficiency of 71%,
the user can calculate the regulator current consumption as IBAT x VBAT/(0.71 x VDC).
Table 9. Switching Characteristics (General Inputs)1
VDDA =V
DDA = 3.13 to 5.25 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL=20pF)
Parameter Symbol Min Typ Max Unit
Rise Time, RESET tr——20ns
RESET Pulse Width2trl 100 — — ns
Notes:
1. All timing (except rise and fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH =V
D – 0.4 V, VIL = 0.4 V. Rise and fall times are referenced to the 20% and 80% leve ls of the wave form.
2. Additional initializa tion guidelines apply; see section 1.2 ProSLIC Initialization in AN35.
Table 10. Switching Characteristics (SPI)
VDDA =V
DDA = 3.13 to 5.25 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL=20pF
Parameter Symbol Test
Conditions Min Typ Max Unit
Cycle Time SCLK tc0.062 — — µs
Rise Time, SCLK tr— — 25 ns
Fall Time, SCLK tf— — 25 ns
Delay Time, SCLK Fall to SDO Active td1 — — 20 ns
Delay Time, SCLK Fall to SDO
Transition td2 — — 20 ns
Delay Time, CS Rise to SDO Tri-state td3 — — 20 ns
Setup Time, CS to SCLK Fall tsu1 25 — — ns
Hold Time, CS to SCLK Rise th1 20 — — ns
Setup Time, SDI to SCLK Rise tsu2 25 — — ns
Hold Time, SDI to SCLK Rise th2 20 — — ns
Delay Time between Chip Selects
(Continuous SCLK) tcs 440 — — ns
Delay Time between Chip Selects
(Non-continuous SCLK) tcs 220 — — ns
Table 8. Power Supply Characteristics (Continued)
(Unless otherwise noted, VDDA, VDDD=3.13 to 5.25 V; TA=0 to 70C for F-grade, –40 to 85C for G-grade)
Parameter Symbol Test Condition Typ1Typ2Max Unit
Si3210/Si3211
14 Rev. 1.61
Figure 7. SPI Timing Diagram
SDI to SDITHRU Propagation Delay td4 — 4 10 ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH =V
DDD –0.4 V, VIL =0.4V
Table 11. Switching Characteristics—PCM Highway Serial Interface
VD= 3.13 to 5.25 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL=20pF
Parameter Symbol Test
Conditions Min 1Typ 1Max 1Units
PCLK Frequency 1/tc
—
—
—
—
—
—
—
—
0.256
0.512
0.7682
1.024
1.5362
2.048
4.096
8.192
—
—
—
—
—
—
—
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PCLK Duty Cycle Tolerance tdty 40 50 60 %
PCLK-to-FSYNC Jitter Tolerance tjitter –120 — 120 ns
Rise Tim e, PC LK tr——25ns
Fall Time, PCLK tf——25ns
Delay Time, PCLK Rise to DTX Active td1 ——20ns
Delay Time, PCLK Rise to DTX
Transition td2 ——20ns
Delay Time, PCLK Rise to DTX Tri-state3td3 ——20ns
Setup Time, FSYNC to PCLK Fall tsu1 25 — — ns
Hold Time, FSYNC to PCLK Fall th1 20 — — ns
Table 10. Switching Characteristics (SPI)
VDDA =V
DDA = 3.13 to 5.25 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL=20pF
SCLK
CS
SDI
th1
td3
SDO
td1 td2
tsu1
trtr
tc
tsu2 th2
tcs
tthru
Si3210/Si3211
Rev. 1.61 15
Figure 8. PCM Highway Interface Timing Diagram
Setup Time, DRX to PCLK Fall tsu2 25 — — ns
Hold Time, DRX to PCLK Fall th2 20 — — ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O –0.4V, VIL =0.4V.
2. Not a valid PCLK frequency for GCI mode.
3. Specification applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0).
Table 11. Switching Characteristics—PCM Highway Serial Interface
VD= 3.13 to 5.25 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL=20pF
PCLK
DRX
FSYNC
DTX
td1 td2
tsu2 th2
td3
tr
tc
tsu1
th1
tf
Si3210/Si3211
16 Rev. 1.61
Figure 9. Si3210/Si3210M Application Circuit Using Si3201
Si32014
Si3210/Si3210M5
R15
243
C2
10 FC1
10 FR14
40.2k
C5
22nF
C6
22nF
ITIPN
IRINGN
ITIPP
IRINGP
STIPE
SRINGE
ITIPN
IRINGN
ITIPP
IRINGP
STIPE
SRINGE
TIP
RING
GND
VBAT
TIP
RING
IREF
CAPP
CAPM
IGMP
IGMN
QGND
SCLK
SDI
SDO
CS
FSYNC
PCLK
DRX
DTX
SPI Bus
PCM
Bus
INT
RESET
R5
200k
R281
R21
15
VDD
Protection
Circuit
C24
0.1 F
C19
4.7 F
R6
4.02k
R7
4.02k
VBATH
SVBAT
29
25
28
26
17
19
18
1
3
4
5
15
13
16
14
11
10
8
7
38
37
36
1
6
3
4
5
2
7
24
22
11
12
14
13
Q9
2N2222
C26
0.1 F
R291VCC
VCC
SDCL
SDCH
DC-DC Converter
Circuit
DCDRV
DCFF
VDC
VBAT VDC
SDCL
SDCH
DCDRV
DCFF
STIPDC
STIPAC
R262
10 k
GND
R322
10k
VCC
Note 2
Note 1
9
8
34
33
C18
4.7 F
R1
200k 15
20
C3
220 nF R8
470
R3
200k
21
16
C4
220 nF R9
470 SRINGAC
SRINGDC
Notes:
1. Values and configurations for these com p onents can
be derived from Tab le 19 or from “AN45: Design
Guide for the SI3210 DC-DC C onverter”.
2. Only one component per system needed.
3. All circuit ground should have a single-point
connection to the ground plane.
4. Si3201 bottom -side exposed pad should be
electrically and thermally conne cted to bulk ground
plane.
5. Pin numbers for TSS O P show n.
R2
196k
R4
196k
VDDD
VDDA1
GNDD
GNDA
VDDA2
31
23
TEST 32
10
27
30
47 µH
L2 VCC
C15
0.1 µF
C16
0.1 µF
C17
10 µF
C31 C30
10 µF
0.1 µF
Si3210/Si3211
Rev. 1.61 17
Table 12. Si3210/Si3210M + Si3201 External Component Values
Component(s) Value Package Supplier
C1,C2 10 µF, 6 V Ceramic or 16 V Low Leakage
Electrolytic, ±20% Radial Murata, Nichicon URL1C100MD
C3,C4 220 nF, 100 V, X7R, ±20% 1812 Murata, Johanson, Novacap, Venkel
C5,C6 22 nF, 100 V, X7R, ±20% 1206 Murata, Johanson, Novacap, Venkel
C15,C16,C17,C24 0.1 µF, 6 V, Y5V, ±20% 603 Murata, Johanson, Novacap, Venkel
C18,C19 4.7 µF, ceramic, 6 V, X7R, ±20% 1206 Murata, Johanson, Novacap, Venkel
C26 0.1 µF, 100 V, X7R, ±20% 1210 Murata, Johanson, Novacap, Venkel
C30,C31 10 µF, 10 V, Electrolytic, ±20% Radial Panasonic
L2 47 µH, 150 mA SMD Coilcraft
R11,R31,R51200 k, 1/10 W, ±1% 805
R21,R41196 k, 1/10 W, ±1% 805
R6,R7 4.02 k, 1/10 W, ±1% 805
R8,R9 470 , 1/10 W, ±1% 805
R14 40.2 k, 1/10 W, ±1% 805
R15 243 , 1/10 W, ±1% 805
R21 15 , 1/4 W, ±5% 805
R26210 k, 1/10 W, ±1% 805
R28,R29 1/10 W , 1% (See “AN4 5: Design Guide for
the Si3210 DC-DC Converter” or Table 19
for value selection) 805
R32210 k, 1/10 W, ±5% 805
Q9 60 V, General Purpose Switching NPN SOT-23 ON Semi MMBT222 2ALT1; Central
Semi CMPT2222A; Zetex
FMMT2222
Notes:
1. These resistors must be in an 0805 or larger package.
2. Only one component per system needed.
Si3210/Si3211
18 Rev. 1.61
Figure 10. Si3210 BJT/Inductor DC-DC Converter Circuit
Q8
2N2222
C9
10 µF
R191
R201
R181
R17
F1
GND
L1
VBAT
C142
0.1 µF
VDC
Note 1
Note 1
Si3210
Notes:
1. Values a nd configurations for these components can be derived from
“AN45: Design Guide for the Si3210 DC-DC Converter” or Table 21.
2. Voltage rating for C14 and C25 must be greater than VDC.
C252
10 µF
C10
0.1 µF R16
200
D1
ES1D
Q7
FZT953
DCDRV
DCFF
SDCL
SDCH
Si3210/Si3211
Rev. 1.61 19
Table 13. Si3210 BJT/Inductor DC-DC Converter Component Values
Component(s) Value Package Supplier
C9 10 µF, 100 V, Electrolytic, ±20% Radial Panasonic
C10 0.1 µF, 50 V, X7R, ±20% 1210 Murata, Johanson, Novacap, Venkel
C14* 0.1 µF, X7R, ±20% 1210 Murata, Johanson, Novacap, Venkel
C25* 10 µF, Electrolytic, ±20% Radial Panasonic
R16 200 , 1/10 W, ±5% 805
R17 1/10 W, ±5% (See AN45 or Table 21 for
value selection) 805
R18 1/4 W, ±5% (See AN45 or Table 21 for
value selection) 1206
R19,R20 1/10 W, ±1% (See AN45 or Table 21 for
value selection) 805
F1 Fuse SMD Belfuse SSQ Series
D1 Ultra Fast Recovery 200 V, 1A Rectifier DO214-
AA General Semi ES1D; Central Semi
CMR1U-02
L1 1 A, Shielded Inductor
(See AN45 or Table 21 for value selection) SMD
API Delevan SPD127 series, Sumida
CDRH127 series, Datatronics DR340-
1 series, Coilcraft DS5022, TDK
SLF12565
Q7 120 V, High Current Switching PNP SOT-223 Zetex FZT953, FZT955, ZTX953,
ZTX955; Sanyo 2SA1552
Q8 60 V, General Purpose Switching NPN SOT-23 ON Semi MMBT2222ALT1,
MPS2222A; Central Semi
CMPT2222A; Zetex FMMT2222
*Note: Voltage rating of this device must be greater than VDC.
Si3210/Si3211
20 Rev. 1.61
Figure 11. Si3210M MOSFET/Transformer DC-DC Converter Circuit
Si3210/Si3211
Rev. 1.61 21
Table 14. Si3210M MOSFET/Transformer DC-DC Converter Component Values
Component(s) Value Package Supplier
C9 10 µF, 100 V, Electrolytic, ±20% Radial Panasonic
C14* 0.1 µF, X7R, ±20% 1210 Murata, Joha nson, Novacap, Venkel
C25* 10 µF, Electr olyt ic, ±2 0% R ad ial Panasonic
C27 470 pF, 100 V, X7R, ±20% 1206 Murata, Johanson, Novacap, Venkel
R17 200 k, 1/10 W, ±5% 805
R18 1/4 W , ±5% (See “AN45: Design Guide for
the Si3210 DC-DC Converter” or Table 20
for value selection) 1206
R19,R20 1/10 W, ±1% (See AN45 or Table 20
for value selection) 805
R22 22 , 1/10 W, ±5% 805
F1 Fuse SMD Belfuse SSQ Series
D1 Ultra Fast Recovery 200 V, 1 A Rectifier D214-AA General Semi ES1D; Central Semi
CMR1U-02
T1 Power Transformer SMD Coiltronic CTX01-1527 5 ;
Datatronics SM76315 ;
Midcom 31353R-02
M1 100 V, Logic Level Input MOSFET SOT-223 Intl Rect. IRLL014N; Intersil
HUF76609D3S; ST Micro
STD5NE10L, STN2NE10L
*Note: Voltage rating of this device must be greater than VDC.
Si3210/Si3211
22 Rev. 1.61
Figure 12. Si3211 Typical Application Circuit Using Si3201
Si32013
Si32114
R15
243
C2
10 FC1
10 FR14
40.2k
C5
22 nF
C6
22 nF
ITIPN
IRINGN
ITIPN
IRINGN
TIP
RING
VBAT
TIP
RING
IREF
CAPP
CAPM
IGMP
IGMN
QGND
SCLK
SDI
SDO
CS
FSYNC
PCLK
DRX
DTX
SPI Bus
PCM
Bus
INT
RESET
R5
200k
Protection
Circuit
R6
4.02k
R7
4.02k
VBATH
SVBAT
SRINGAC
SRINGDC
29
25
28
26
17
19
18
1
3
4
5
16
14
11
10
38
37
36
1
6
3
4
5
2
7
24
22
11
12
14
13
DIO2
DIO1
DCSW
DOUT
STIPDC
STIPAC
R261
10k
R321
10k
VCC
Note 1
9
8
34
33
NC
ITIPP
IRINGP
STIPE
SRINGE
ITIPP
IRINGP
STIPE
SRINGE
NC NC
GND
VDD
C24
0.1 F
C19
4.7 F
15
13
8
7
VCC
C18
4.7 F
Notes:
1.Only one component per system needed.
2.All circuit grounds should have a single-
point connection to the ground plane.
3. Si3201 bottom -side exposed pad should
be electrically and thermally connected to
bulk ground plane.
4. Pin numbers for TSSO P shown.
R3
200k
21
16
C4
220 nF R9
470
R1
200k 15
20
C3
220 nF R8
470
R18
1.8k
Q8
5551
VBATH
GND
Q7
5401
VBATL
D1
4003
R16
200k
R2
196k
R4
196k
GND
0.1 µF
C9
VDDD
VDDA1
GNDD
GNDA
VDDA2
31
23
TEST 32
10
27
30
47 µH
L2 VCC
C15
0.1 µF
C16
0.1 µF
C17
10 µF
C31 C30
10 µF
0.1 µF
Si3210/Si3211
Rev. 1.61 23
Table 15. Si3211 + Si3201 External Component Values
Component(s) Value Package Supplier
C1,C2 10 µF, 6 V Ceramic or 16 V, Low-Leakage
Electrolytic, ±20% Radial Murata, Nichicon URL1C100MD
C3,C4 220 nF, 100 V, X7R, ±20% 1812 Murata, Johanson, Novacap, Venkel
C5,C6 22 nF, 100 V, X7R, ±20% 1206 Murata, Johanson, Novacap, Venkel
C9 0.1 µF, 100 V, X7R, ±20% 1210 Murata, Johanson, Novacap, Venkel
C15,C16,C17,C24 0.1 µF, 6 V, Y5V, ±20% 1206 Murat a, Johanson, Nova cap, V enkel
C18,C19 4.7 µF Ceramic, 6 V, X7R, ±20% 1206 Murat a, Johanson, Novaca p, V enkel
C30,C31 10 µF, 10 V, Electrolytic, ±20% Radial Panasonic
L2 47 µH, 150 mA SMD Coilcraft
D1 200 V, 1 A Rectifier MELF ON Semi: MRA4003, IN4003
Q7 120 V, PNP, BJT SOT-89 ON Semi: 2N5401
Q8 120 V, NPN, BJT SOT-223 ON Semi: 2N5551
R11,R31,R51,R161200 k, 1/10 W, ±1% 805
R21,R41196 k, 1/10 W, ±1% 805
R6,R7 4.02 k, 1/10 W, ±1% 805
R8,R9 470 , 1/10 W, ±1% 805
R14 40.2 k, 1/10 W, ±1% 805
R15 243 , 1/10 W, ±1% 805
R18 1.8 k, 1/10 W, ±5% 805
R26210 k, 1/10 W, ±1% 805
R32210 k, 1/10 W, ±5% 805
Notes:
1. These resistors must be in an 0805 or larger package.
2. Only one component per system needed.
Si3210/Si3211
24 Rev. 1.61
Figure 13. Si3210/Si3210M Typical Application Circuit Using Discrete Components
Notes:
1. Values and configurations for these compo -
nents can be derived from Table 19 or from
“AN45: D e sign Guide for the Si3210 D C-DC
Converter” .
2. Only one component per system needed.
3. All circuit grounds should have a single-point
connection to th e ground plane.
4. Optional components to im p rove idle channel
no ise.
5. The trace resistance between R6 and C 26
should equal the trace resistance between R7
and C 26.
6. Pin numbers for TSSOP shown.
Si3210/Si3210M6
R15
243
C2
10uF C1
10uF R14
40.2k
C5
22nF
C6
22nF
ITIPP
ITIPN
STIPE
IRINGP
IRINGN
SRINGE
R1
200k
R3
200k
TIP
RING
IREF
CAPP
CAPM
IGMP
IGMN
QGND
SCLK
SDI
SDO
CS
FSYNC
PCLK
DRX
DTX
SPI Bus
PCM Bus
INT
RESET
R281
R21
15
Protection
Circuit
R2
100k
15
20
28
29
17
26
25
19
18
21
16
38
37
36
1
6
3
4
5
2
7
24
22
11
12
14
13
Q9
2N2222
R291VCC
SDCL
SDCH
DC-DC Converter
Circuit
DCDRV
DCFF
VDC
VBAT VDC
SDCL
SDCH
DCDRV
DCFF
STIPDC
STIPAC
R262
10k
GND
R322
10k
VCC
Note 2
Note 1
9
8
34
33
R7
80.6
C7
220nF
Q5
5551
Q3
5401
Q2
5401 R11
10
R12
5.1k
R6
80.6
C8
220nF
Q6
5551
Q4
5401
Q1
5401 R10
10
R13
5.1k
GND
C4
220nF R9
470 SRINGAC
SRINGDC
C3
220nF R8
470
SVBAT
R102 (100k)
C324
C26
0.1 µF
R4
100k
0.1 µF
R104 (100k)
R5
100k
0.1 µF
R105 (100k)
0.1 µF
C344
C334
VDDD
VDDA1
GNDD
GNDA
VDDA2
31
23
TEST 32
10
27
30
47 µH
L2 VCC
C15
0.1 µF
C16
0.1 µF
C17
10 µF
C31 C30
10 µF
0.1 µF
Si3210/Si3211
Rev. 1.61 25
Table 16. Si3210/Si3210M External Component Values—Discrete Solution
Component(s) Value Package Supplier/Part Number
C1,C2 10 µF, 6 V Ceramic or 16 V Low-Leakage
Electrolytic, 20% Radial Murata, Panasonic, Nichicon
URL1C100MD
C3,C4 220 nF, 100 V, X7R, 20% 1812 Murata, Johanson, Novacap, Venkel
C5,C6 22nF, 100V, X7R, 20% 1206 Murata, Johanson, Novacap, Venkel
C7,C8 220 nF, 50 V, X7R, 20% 1812 Murata, Johanson , Novacap, Venkel
C15,C16,C17 0.1 µF, 6 V, Y5V, 20% 603 Murata, Johanson, Novacap, Venkel
C26 0.1 µF, 100 V, X7R, 20% 1210 M urata, Johanson, Novacap, Venkel
C30,C31 10 µF, 10 V, Electrolytic, ±20% Radial Panasonic
C32,C33,C34 0.1 µF, 50 V, ±20% 805 Venkel
L2 47 µH, 150 mA SMD Coilcraft
Q1,Q2,Q3,Q4 120 V, PNP, BJT SOT-23
Central Semi CMPT5401; ON Semi
MMBT5 40 1LT1, 2N54 01 ; Ze te x
FMMT5401;
Fairchild 2N5401; Samsu ng 2N5401
Q5,Q6 120 V, NPN, BJT SOT-223 Central Semi CZT5551, ON Semi
2N5551;
Fairchild 2N5551; Phillips 2N5551
Q9 NPN General Purpose BJT SOT-23 ON Semi MMBT2222ALT1, MPS2222A;
Central Semi CMPT2222A; Zetex
FMMT2222
R11, R31200 k, 1/10 W, 1% 805
R21, R41, R51,
R1021, R1041,
R1051100 k, 1/10 W, ±1% 805
R6,R7 80.6 , 1/4 W, 1% 1210
R8,R9 470 , 1/10 W, 1% 805
R10,R11 10 , 1/10 W, 5% 805
R12,R13 5.1 k, 1/10 W, 5% 805
R14 40.2 k, 1/10 W, 1% 805
R15 243 , 1/10 W, 1% 805
R21 15 , 1/4 W, 1% 805
R26210 k, 1/10 W, ±1% 805
R28,R29 1/10 W, 1% (See “AN45: Design Guide
for the Si3210/15/16 DC-DC Converter” or
Table 19 for value selection) 805
R32210 k, 1/10 W, 5% 805
Notes:
1. These resistors must be in 0805 or larger package.
2. Only one component per system needed.
Si3210/Si3211
26 Rev. 1.61
Figure 14. Si3211 Typical Application Circuit Using Discrete Solution
Si32115
R15
243
C2
10uF C1
10uF R14
40.2k
IREF
CAPP
CAPM
IGMP
IGMN
QGND
SCLK
SDI
SDO
CS
FSYNC
PCLK
DRX
DTX
SPI Bus
PCM Bus
INT
RESET
38
37
36
1
6
3
4
5
2
7
24
22
11
12
14
13
DIO2
DIO1
DCSW
DOUT
R261
10k
R321
10k
VCC
Note 1
9
8
34
33
NC NC NC
C5
22nF
C6
22nF
R1
200k
R3
200k
TIP
RING
R18
1.8k
Protection
Circuit
R2
100k
R4
100k
15
20
28
29
17
26
25
19
18
21
16
Q8
5551
VBATH
GND
Notes:
1. Only one component per system needed.
2. All circuit grounds should have a single-point
connection to the ground plane.
3. The trace resistance between R6 and C26
should equal the trace resistance between
R7 and C26.
4. Optional components to improve idle channel
noi s e.
5. Pin numbers for TS SO P shown.
R7
80.6
C7
220nF
Q5
5551
Q3
5401
Q2
5401 R11
10
R12
5.1k
R6
80.6
C8
220nF
Q6
5551
Q4
5401
Q1
5401 R10
10
R13
5.1k
GND
C4
220nF R9
470
C3
220nF R8
470
Q7
5401
VBATL
D1
4003
R16
200k
ITIPP
ITIPN
STIPE
IRINGP
IRINGN
SRINGE
STIPDC
STIPAC
SRINGAC
SRINGDC
SVBAT
R105 (100k)
C334
0.1µF
R5
100k
R104 (100k)
C344
0.1µF
R102 (100k)
C324
0.1µF
C26
0.1 µF
VDDD
VDDA1
GNDD
GNDA
VDDA2
31
23
TEST 32
10
27
30
47 µH
L2 VCC
C15
0.1 µF
C16
0.1 µF
C17
10 µF
C31 C30
10 µF
0.1 µF
Si3210/Si3211
Rev. 1.61 27
Table 17. Si3211 External Component Values—Discrete Solution
Component(s) Value Package Supplier/Part Number
C1,C2 10 µF, 6 V Ceramic or 16 V Low Leakage
Electrolytic, 20% Radial Murata, Panasonic, Nichicon
URL1C100MD
C3,C4 220 nF, 100 V, X7R, 20% 1812 Murata, Johanson, Novacap, Venkel
C5,C6 22nF, 100V, X7R, 20% 1206 Murata, Johanson, Novacap, Venkel
C7,C8 220 nF, 50 V, X7R, 20% 1812 Murata, Johanson, Novacap, Venkel
C9 0.1 µF, 100 V, X7R, 20% 1210 Panasonic
C15,C16,C17 0.1 µF, 6 V, Y5V, 20% 603 Murata, Johanson, Novacap, Venkel
C30,C31 10 µF, 10 V, X7R, ±20% Radial Panasonic
C32, C33, C34 0.1 µF, 50 V, X7R, ±20% 805 Venkel
L2 47 µH, 150 mA SMD Coilcraft
R11,R31,R161200 k, 1/10 W, 1% 805
R21, R41, R51,
R1021, R1041,
R1051100 k, 1/10 W, ±1% 805
R6,R7 80.6 , 1/4 W, 1% 1210
R8,R9 470 , 1/10 W, 1% 805
R10,R11 10 , 1/10 W, 5% 805
R12,R13 5.1 k, 1/10 W, 5% 805
R14 40.2 k, 1/ 10 W, 1% 805
R15 243 , 1/10 W, 1% 805
R18 1.8 k, 1/10 W, 5% 805
R26210 k, 1/10 W, ±1% 805
R32210 k, 1/10 W, 5% 805
D1 200 V 1A Rectifier MELF ON Semi MRA4003, 1N4003
Q1,Q2,Q3,Q 4,Q7 120 V, PNP, BJT SOT-23 Central Semi CMPT540 1; ON Semi
MMBT5401LT1, 2N5401; Zetex
FMMT5401
Q5,Q6 120 V, NPN, BJT SOT-223 Central Semi CZT5551, ON Semi
2N5551
Q8 120 V, NPN, BJT SOT-223 Central Semi CMPT5551, ON Semi
2N5551
Notes:
1. These resistors must be in an 0805 or larger package.
2. Only one component per system needed.
Si3210/Si3211
28 Rev. 1.61
Figure 15. Si321x Optional Equivalent Q5, Q6 Bias Circuit
The subcircuit above can be substitute d into any of the Pro SLIC so lutions as an optional bia s circuit for Q5 and Q6.
For this optional subcircuit, C7 and C8 di f f er in volt ag e and capacitance from the st anda rd circuit. R23 a nd R24 are
additional components.
Table 18. Si321x Optional Bias Component Values
Component Value Package Supplier/Part Number
C7,C8 100 nF, 100 V, X7R, 20% 1210 Murata, Johanson, Venkel
R23,R24 3.0 k, 1/10 W, 5% 805
Table 19. Component Value Selection for Si3210/Si3210M
Component Value Package Comments
R28 1/10 W, 1% resistor
For VDD = 3.3 V : 26.1 k
For VDD = 5.0 V : 37.4 k805 R28 = (VDD + VBE)/148 µA
where VBE is the nominal VBE for Q9
R29
1/10 W, 1% resistor
For VCLAMP = 80 V: 541 k
For VCLAMP = 85 V: 574 k
For VCLAMP =100V: 676k
805 R29 = VCLAMP/148 µA
where VCLAMP is the clamping voltage
for VBAT
R7
80.6
RRE
C7
100 nF
CRBN
Q4
5401
QTDN
C8
CTBN
100 nF
Q5
5551
QRP
R23
3.0k
RRBN0
R24
3.0k
RTBN0
Q3
5401
QRDN
R6
80.6
RTE
R12
5.1k
RRBN
R13
5.1k
RTBN
Q6
5551
QTN
Si3210/Si3211
Rev. 1.61 29
Table 20. Component Value Selection Examples for Si3210M MOSFET/Transformer DC-DC Converter1
VDC Maximum Ringing Load/
Loop Resistance Winding
Connections2Transformer Ratio R18 R19, R20
3.3 V 3 REN/117 1–2 1–2 0.06 7.15 k
5.0 V 5 REN/117 1–2 1–2 0.10 16.5 k
12 V 5 REN/117 1–3 1–3 0.6 56.2 k
24 V 5 REN/117 1–4 1–4 2.1 121 k
Notes:
1. There are other system and software conditions that influence component value selection.
Refer to “AN45: Design Guide for the Si3210 DC-DC Conv erter” for detailed guidance.
2. Applies to transformer specified in Table 14; other transformers may vary.
Table 21. Component Value Selection Examples for Si3210 BJT/Inductor DC-DC Converter
VDC Maximum Ringing Load/Loop Resistance L1 R17 R18 R19, R20
5 V 3 REN/117 67 µH 150 0.15 16.5 k
12 V 5 REN/117 150 µH 162 0.56 56.2 k
24 V 5 REN/117 220 µH 175 2.0 121 k
Note: There are other system and software conditions that influence component value selection.
Refer to “AN45: Design Guide for the Si3210 DC-DC Converter” for detailed guidance.
Si3210/Si3211
30 Rev. 1.61
2. Functional Description
The ProSLIC® is a single, low-voltage CMOS device
that provides all the SLIC, codec, DTMF detection, and
signal generation functions needed for a complete
analog telephone interface. The ProSLIC performs all
battery, overvoltage, ringing, supervision, codec, hybrid,
and test (BORSCHT) functions. Unlike most monolithic
SLICs, the Si3210 does not require externally-supplied
high-voltage battery supplies. Instead, it generates all
necessary battery voltages from a positive dc supply
using its own dc-dc converter controller. Two fully-
programmable tone generators can produce DTMF
tones, phase continuous FSK (caller ID) signaling, and
call progress tone s. DTMF decoding and pulse metering
signal generation are also integrated. The Si3201
linefeed interface IC performs all high-voltage functions.
As an option, the Si3201 can also be replaced with low-
cost discrete components as shown in the typical
application circuits in Figures 12, 13, and 14.
The ProSLIC is ideal for short loop applications, such as
terminal adapters, cable telephony, PBX/key systems,
wireless local loop (WLL), and voice over IP solutions.
The linefeed provides programmable on-hook voltage,
programmable off-hook loop current, reverse battery
operation, loop or ground start operation, and on-hook
transmission ringing voltage. Loop current and voltage
are continuously monitored using an integrated A/D
converter. Balanced 5 REN ringing with or without a
programmable dc offset is integrated. The available
offset, frequency, waveshape, and cadence options are
designed to ring the widest variety of terminal devices
and to reduce external controller requirements.
A complete audio transmit and receive path is
integrated, including DTMF decoding, ac impedance,
and hybrid gain. These features are software-
programmab le, allowin g for a sing le hard ware desig n to
meet international requirements. Digital voice data
transfer occurs over a standard PCM bus. Control data
is transferred using a standard SPI. The device is
available in a 38-pin QFN or TSSOP package.
2.1. Linefeed Interface
The ProSLIC’s linefeed interface offers a rich set of
features and programmable flexibility to meet the
broadest applications requirements. The dc linefeed
characteristics are software-programmable. Key
current, voltage, an d power measurement s are acquired
in real time and provided in software registers.
2.1.1. DC Feed Characteristics
The ProSLIC has programmable constant voltage and
constant current zones as shown in Figure 16. Open-
circuit TIP-to-RING voltage (VOC) defines the constant
voltage zone and is progra mmable fro m 0 V to 94.5 V in
1.5 V steps. The loop current limit (ILIM) defines the
constant current zone and is programmable from 20 mA
to 41 mA in 3 mA steps. The ProSLIC has an inherent
dc output resistance (RO) of 160 .
Figure 16. Simplified DC Current/Voltage
Linefeed Characteristic
The TIP-to-RING voltage (VOC) is offset from ground by
a programmable voltage (VCM) to provide voltage
headroom to the positive-most terminal (TIP in forward
polarity states and RING in reverse polarity states) for
carrying audio signals. Table 22 summarizes the
parameters to be initialized before entering an active
state.
Table 22. Programmable Ranges of DC
Linefeed Characteristics
Parameter Programmable
Range Default
Value Register
Bits Location*
ILIM 20 to 41 mA 20 mA ILIM[2:0] Direct
Register 71
VOC 0 to 94.5 V 48 V VOC[5:0] Direct
Register 72
VCM 0 to 94.5 V 3 V VCM[5:0] Direct
Register 73
*Note: The ProSLIC uses registers that are both directly and
indirectly mapped. A “direct” register is one that is mapped
directly.
V(TIP-RING) (V )
VOC
Constant
Voltage
Zone
RO=160 C onstant Current
Zone
ILIM ILOOP(mA)
Si3210/Si3211
Rev. 1.61 31
2.1.2. Linefeed Architecture
The ProSLIC is a low-voltage CMOS device that uses
either an Si3201 linefeed interface IC or low-cost
external components to control the high voltages
required for subscriber line interfaces. Figure 17 is a
simplified illustration of the linefeed control loop circuit
for TIP or RING and the external components used.
The ProSLIC uses both voltage and current sensing to
control TIP and RING. DC and ac line voltages on TIP
and RING are measured through sense resistors RDC
and RAC. The ProSLIC uses linefeed transistors QP an d
QN to drive TIP and RING. QDN isolates the high-volt age
base of QN from the ProSLIC.
The ProSLIC measures voltage at various nodes in
order to monitor the linefeed current. RDC, RSE, and
RBAT provide access to these measuring points. The
sense circuitry is calibrated on-chip to guarantee
measurement accuracy with standard external
component tolerances. See "2.1.9. Linefeed
Calibration" on page 36 for details.
2.1.3. Linefeed Operation States
The ProSLIC linefeed has eight states of operation as
shown in Table 23. The state of operation is controlled
using the Linefeed Control register (dire ct Register 64).
The open state turns off all currents into the external
bipolar transistors and can be used in the presence of
fault conditions on the line and to ge nerate Open Switch
Intervals (OSIs ). TIP and RING are effectively tri-stated
with a dc output impedance of about 150 k.
The ProSLIC can also automatically enter the open
state if it detects excessive power being consumed in
the external bipolar transistors.
See “2.1.5. Powe r Monitoring and Line F ault Detection”
for more details.
In the forward active and reverse active states, linefeed
circuitry is on, and the audio signal paths are powered
down.
In the forward and reverse on-hook transmission states,
audio signal paths are powered up to provide data
transmission during an on-hook loop condition.
The TIP Open state turns off all control currents to the
external bipolar devices connected to TIP and pr ovides
an active linefeed on RING for gr ou n d start operat ion .
The RING Open state provides similar operation with
the RING drivers off and TIP active.
The ringing state drives programmable ringing
waveforms onto the line.
2.1.4. Loop Voltage and Current Monitoring
The ProSLIC continuously monitors the TIP and RING
voltages and external BJT currents. These values are
available in registers 78–89. Table 24 on page 33 lists
the values that are measured and their associated
registers. An internal A/D converter samples the
measured voltages and currents from the analog sense
circuitry and translates them in to the digit al dom ain. The
A/D updates the samples at a rate of 800 Hz. Two
derived values are also reported: loop voltage and loop
current. The loop voltage, VTIP –V
RING, is re port ed a s a
1-bit sign, 6-bit magnitude format. For ground start
operation, the reported value is the RING voltage. The
loop current, (IQ1 – IQ2 + IQ5 –IQ6)/2, is reported in a 1-
bit sign, 6-bit magnitude format. In RING open and TIP
open states, the loop current is reported as (IQ1 – IQ2) +
(IQ5 –IQ6).
Si3210/Si3211
32 Rev. 1.61
Figure 17. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown)
Table 23. ProSLIC Linefeed Operations
LF[2:0]* Linefeed State Description
000 Open TIP and RING tri-stated
001 Forward Active VTIP > VRING
010 Forward On-Hook Transmission VTIP > VRING; audio signal paths powered on
011 TIP Open TIP tri-stated, RING active; used for ground st art
100 Ringing Ringing waveform applied to TIP and RING
101 Reverse Active VRING > VTIP
110 Reverse On-Hook Transmission VRING > VTIP; audio signal paths powered on
111 Ring Open RIN G tri-stated, TIP active
Note: The linefeed register (LF) is locate d in direct Register 64.
DSP A/D
D/AD/A
A/D
DC
Control
AC
Control
DC
Control
Loop
AC
Control
Loop
Battery Sense
Emitter Sense
DC Sense
RDC RSE RBAT
QDN
QP
QN
RE
VBAT
TIP or
RING
RBP
RAC
CAC
AC Sense
Audio
Codec Monitor A/D
SLIC DAC
On-ChipExternal Components
Si3201
Si3210/Si3211
Rev. 1.61 33
2.1.5. Power Monitoring and Line Fault Detection
In addition to reporting voltages and currents, the ProSLIC continuously monitors the power dissipated in each
external bipolar transistor. Real-time output power of any one of the six linefeed transistors can be read by setting
the Power Monitor Pointer (direct Register 76) to point to the desired transistor and then reading the Line Power
Output Monitor (direct Register 77).
The real-time power measurements are low-pass filtered and compared to a maximum power threshold. Maximum
power thresholds and filter time constants are software-programmable and should be set for each transistor pair
based on the characteristics of the trans istors us ed. Table 25 desc ribes the regis ters as sociat ed w ith th is fun ction .
If the power in any external transistor exceeds the programmed threshold, a power alarm event is triggered. The
ProSLIC sets the Power Alarm register bit, generates an interrupt (if enabled), and automatically enters the Open
state (if AOPN = 1). This feature protects the external transistors from fault conditions and, combined with the loop
voltage and current monitors, allows diagnosis of the type of fault condition present on the line.
The value of each thermal low-pass filter pole is set according to the equation:
where is the ther mal time co nstant of the transistor package, 4096 is the full range of the 12-bit register, and 800
is the sample rate in hertz. Generally = 3 seconds for SOT223 packages and = 0.16 seconds for SOT23, but
check with the ma nufacturer for the packag e thermal constant of a specific device. For example, the power alarm
threshold and low-pass filter values for Q5 and Q6 using a SOT223 package transistor are computed as follows:
Thus, indirect Register 34 should be set to 150Dh.
Table 24. Measured Real-Time Linefeed Interface Characteristics
Parameter Measurement
Range Resolution Register
Bits Location*
Loop Voltage Sense (VTIP – VRING) –94.5 to +94.5 V 1.5 V LVSP,
LVS[6:0] Direct Register 78
Loop Current Sense –78.75 to +78.5 mA 1.25 mA LCSP,
LCS[5:0] Direct Register 79
TIP Voltage Sense 0 to –95.88 V 0.376 V VTIP[7:0] Direct Register 80
RING Voltage Sense 0 to –95.88 V 0.376 V VRING[7:0] Direct Register 81
Battery Voltage Sense 1 (VBAT) 0 to –95.88 V 0.376 V VBATS1[7:0] Direct Register 82
Battery Voltage Sense 2 (VBAT) 0 to –95.88 V 0.376 V VBATS2[7:0] Direct Register 83
Transistor 1 Current Sense 0 to 81.35 mA 0.319 mA IQ1[7:0] Direct Register 84
Transistor 2 Current Sense 0 to 81.35 mA 0.319 mA IQ2[7:0] Direct Register 85
Transistor 3 Current Sense 0 to 9.59 mA 37.6 µA IQ3[7:0] Direct Register 86
Transistor 4 Current Sense 0 to 9.59 mA 37.6 µA IQ4[7:0] Direct Register 87
Transistor 5 Current Sense 0 to 80.58 mA 0.316 mA IQ5[7:0] Direct Register 88
Transistor 6 Current Sense 0 to 80.58 mA 0.316 mA IQ6[7:0] Direct Register 89
*Note: The ProSLIC uses registers that are both directly and indirectly mappe d.
A “direct” register is one that is mapped directly.
Thermal LPF register 4096
800
------------------ 23
=
Si3210/Si3211
34 Rev. 1.61
Note: The power monitor resolution for Q3 and Q4 is different from that of Q1, Q2, Q5, and Q6.
Table 25. Associated Power Monitoring and Power Fault Registers
Parameter Description/ Range Resolution Register
Bits Location*
Power Monitor Pointer 0 to 5 points t o Q1 to
Q6, respectively n/a PWRMP[2:0] Direct Register 76
Line Power Monitor Output 0 to 7.8 W for Q1,
Q2, Q5, Q6
0 to 0.9 W for Q3, Q4
30.4 mW
3.62 mW
PWROM[7:0] Direct Register 77
Power Alarm Threshold, Q1 & Q2 0 to 7.8 W 30.4 mW PPT12[7:0] Indirect Register 32
Power Alarm Threshold, Q3 & Q4 0 to 0.9 W 3.62 mW PPT34[7:0] Indirect Register 33
Power Alarm Threshold, Q5 & Q6 0 to 7.8 W 30.4 mW PPT56[7:0] Indirect Register 34
Thermal LPF Pole, Q1 & Q2 See equation above. NQ12[7:0] Indirect Register 3 7
Thermal LPF Pole, Q3 & Q4 See equation above. NQ34[7:0] Indirect Register 3 8
Thermal LPF Pole, Q5 & Q6 See equation above. NQ56[7:0] Indirect Register 3 9
Power Alarm Interrupt Pending Bits 2 to 7 correspond
to Q1 to Q6, respec-
tively
n/a Q nAP[n+1],
where n = 1
to 6
Direct Register 19
Power Alarm Interrupt Enable Bits 2 to 7 correspond
to Q1 to Q6, respec-
tively
n/a Q nAE[n+1],
where n = 1
to 6
Direct Register 22
Power Alarm
Automatic/Manual Detect 0 = manual mode
1 = enter open state
upon power alarm
n/a AOPN Direct Register 67
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
PPT56 PMAX
Resolution
------------------------------- 27
1.28
0.0304
------------------27
5389 150Dh====
Si3210/Si3211
Rev. 1.61 35
Figure 18. Loop Closure Detection
2.1.6. Loop Closure Transition Detection
A loop closure transition event signals that the terminal equipment has gone from on-hook to off-hook or from off-
hook to on-hook; detection occurs while the ProSLIC linefeed is in its on-hook transmission or active states. The
ProSLIC performs loop closure detection digitally using its on-chip monitor A/D converter. The functional blocks
required to imple ment loop closur e detection are show n in Figure 18. The primary input to the system is the Loop
Current Sense value provided in the LCS register (direct Register 79). The LCS value is processed in the Input
Signal Processor when the ProSLIC is in the on-hook transmission or active linefeed state, as indicated by the
Linefeed Shadow register, LFS[2:0] (direct Register 64). The data then feeds into a programmable digital low-pass
filter, which removes unwanted ac signal components before threshold detection.
The output of the low-pass filter is compared to a programmable threshold, LCRT (indirect Register 28). The
threshold comparator output feeds a programmable debouncing filter. The output of the debouncing filter remains
in its present state unless the input remains in the opposite state for the entire period of time programmed by the
loop closure debounce interval, LCDI (direct Register 69). If the debounce interval has been s atisfied, the LCR bi t
will change state to indicate that a valid loop closure transition has occurred. A loop closure transition interrupt is
generated if enabled by the LCIE bit (direct Register 22). Table 26 lists the registers that must be written or
monitored to correctly detect a loop closure condition.
2.1.7. Loop Closure Th reshold Hysteresis
Silicon revisions C and higher support the addition of programmable hysteresis to the loop closure threshold, which
can be enabled by setting HYSTEN = 1 (direct Register 108, bit 0). The hysteresis is defined by LCRT (indirect
Register 28) and LCRTL (indirect Register 43), which set the upper and lower bounds, respectively.
2.1.8. Voltage-Based Loop Closure Detection
Silicon revisions C and higher also support an optional voltage-based loop closure detection mode, which is
enabled by setting LCVE = 1 (direct Register 108, bit 2). In this mode, the loop voltage is compared to the loop
closure threshold register (LCRT), which represents a minimum voltage threshold instead of a maximum current
threshold. If hysteresis is als o enabled, LCRT represents the upper voltage boundary, and LCRTL represents the
lower voltage boundary for hysteresis. Although voltage-based loop closure detection is an option, the default
current-based loop closure detection is recommended.
ISP_OUT
NCLR LCDI
Input
Signal
Processor
Digital
LPF
Loop Closure
Threshold
Debounce
Filter
+
–
LCR LCIP
LCIE
Interrupt
Logic
LCS
LVS
LCVELFS
LCRTLLCRT
HYSTEN
Si3210/Si3211
36 Rev. 1.61
2.1.9. Linefeed Calibration
An internal calibratio n algorithm cor rect s for internal and
external component errors. The calib ration is initiated by
setting the CAL bit in direct Register 96. Upon
completion of the calibration cycle, this bit is
automatically reset.
It is recommended that a calibration be executed
following system powerup. Upon release of the chip
reset, the Si3210 will be in the open state. The
calibration can be initiated after powering up the dc-dc
converter and allowing it to settle for time (tsettle).
Additional calibrations may be performed, but only one
calibration should be necessary as long as the system
remains powere d up .
During calibration, VBAT, VTIP, and VRING voltages are
controlled by the calibration engine to provide the
correct external voltage conditions for the algorithm.
Calibration should be performed in the on-hook state.
RING or TIP must not be connected to ground during
the calibration.
When using the Si3201, automatic calibration routines
for RING gain mismatch and TI P gain mismatch sho uld
not be performed. Instead of running these two
calibrations automatically, follow the instructions for
manual calibration in “AN35: Si321x User’s Quick
Reference Gu id e” .
2.2. Battery Voltage Generation and
Switching
The ProSLIC supports two modes of battery supply
operation. First, the Si3210 integrates a dc-dc converter
controller that dynamically regulates a single output
voltage. This mode eliminates the need to supply large
external battery voltages. Instead, it converts a single
positive input voltage into the real-time battery voltage
needed for any given state according to programmed
linefeed parameters. Second, the Si3211 supports
switching between high and low battery voltage
supplies, as would a traditional monolithic SLIC.
For single to low channel count a pplications, the Si3210
proves to be an economical choice, as the dc-dc
converter eliminates the need to desig n and build high-
voltage power supplies. For higher channel count
applications where centralized battery voltage supply is
economical or for modular legacy systems where
battery voltage is already available, the Si3211 is
recommended.
2.2.1. DC-DC Converter General Description
(Si3210/Si3210M Only)
The dc-dc converter dynamically generates the large
negative voltages required to operate the linefeed
interface. The Si3210 acts as the controller for a buck-
Table 26. Register Set for Loop
Closure Detection
Parameter Register Location
Loop Closure
Interrupt Pending LCIP Direct Reg. 19
Loop Closure
Interrupt Enable LCIE Direct Reg. 22
Loop Closure Thresh-
old LCRT[5:0] Indirect Reg. 28
Loop Closure
Threshold—Lower LCRTL[5:0] Indirect Reg. 43
Loop Closure Filter
Coefficient NCLR[12:0] Indirect Reg. 35
Loop Closure Detect
Status (monitor only) LCR Direct Reg. 68
Loop Closure Detect
Debounce Interval LCDI[6:0] Direct Reg. 69
Hysteresis Enable HYSTEN Direct Reg. 108
Voltage-Based Loop
Closure LCVE Direct Reg. 108
Si3210/Si3211
Rev. 1.61 37
boost dc-dc converter that converts a positive dc
voltage into the desired negative battery voltage. In
addition to eliminating external power supplies, this
allows the Si3210 to dynamically control the battery
voltage to the minimum required for any given mode of
operation.
Two different dc-dc circuit options are offered: a BJT/
inductor version and a MOSFET/transformer version.
Due to the differences on the driving circuits, there are
two different versions of the Si3210. The Si3210
supports the BJT/inductor circuit option, and the
Si3210M version supports the MOSFET solution. The
only difference between the two versions is the polarity
of the DCFF pin with respect to the DCDRV pin. For the
Si3210, DCDRV and DCFF are of opposite polarity. For
the Si3210M, DCDRV and DCFF are the same polarity.
Table 27 summarizes these differences.
Extensive design guidance on each of these circui ts ca n
be obtained from “AN45: Design Guide for the Si3210
DC-DC Converter” and from an interactive dc-dc
converter design spreadsheet. Both of these documents
are available on the Silicon Laboratories website
(www.silabs.com).
2.2.2. BJT/Inductor Circuit Opt ion Using Si3210
The BJT/Inductor circuit option shown in Figure 10 on
page 18 offers a flexible, low-cost solution. Depending
on selected L1 inductance value and the switching
frequency, the input volt age (VDC) can range from 5 V to
30 V. Because of the nature of a dc-dc converter’s
operation, peak and aver age in put current s can becom e
large with small input voltages. Consider this when
selecting the appropriate input voltage and power rating
for the VDC power supply.
For this solution, a PNP power BJT (Q7) switches the
current flow through low ESR inductor L1. The Si3210
uses the DCDRV and DCFF pins to switch Q7 on and
off. DCDRV controls Q7 through NPN BJT Q8. DCFF is
ac-coupled to Q7 through cap acito r C10 to assist R16 in
turning off Q7. Therefore, DCFF must have opposite
polarity to DCDRV, and the Si3210 (not Si3210M) must
be used.
Table 27. Si3210 and Si3210M Differences
Device DCFF Signal
Polarity DCPOL
Si3210 = DCDRV 0
Si3210M = DCDRV 1
Notes:
1. DCFF signal polarity with respect to DCDRV signal.
2. Direct Register 93, bit 5; This is a read-only bit.
Si3210/Si3211
38 Rev. 1.61
2.2.3. MOSFET/Transformer Circuit Op ti on Usi n g
the Si3210M
The MOSFET/transformer circuit option (shown in
Figure 11 on page 20) offers higher power efficiencies
across a larger input voltage range. Depending on the
transformer’s primary inductor value and the switching
frequency, the input voltage (VDC) can range from 3.3 V
to 35 V. Therefore, it is possible to power the entire
ProSLIC solution from a single 3.3 V or 5 V power
supply. By nature of a dc-dc converter’s operation, peak
and average input cu rrents can become large with small
input voltages. Consider this when selecting the
appropriate input voltage and power rating for the VDC
power supply (number of REN supported).
For this solution, an N-channel power MOSFET (M1)
switches the current flow through a power transformer,
T1. T1 is specified in “AN45: Design Guide for the
Si3210 DC-DC Converter” and includes several taps on
the primary side to facilitate a wide range of input
voltages. The Si3210M version of the Si3210 must be
used for the application circuit depicted in Figure 11
because the DCFF pin is used to drive M1 directly and,
therefore, must be the same polarity as DCDRV.
DCDRV is not used in this circuit option; connecting
DCFF and DCDR V together is not recommended.
2.2.4. DC-DC Converter Architecture
(Si3210/Si3210M Only)
The control logic for a pulse-width-modulated (PWM)
dc-dc converter is incorporated in the Si3210. Output
pins DCDRV and DCFF are used to switch a bipolar
transistor or MO SFET. The p olarity of DCFF is o pposite
that of DCDRV.
The dc-dc converter circuit is powered on when the
DCOF bit in the Powerdown Register (direct
Register 14, bit 4) is cleared to 0. The switching
regulator circuit within the Si3210 is a high-
performance, pulse-width modulation controller. The
control pins are driven by the PWM controller logic in
the Si3210. The regulated output voltage (VBAT) is
sensed by the SVBAT pin and is used to detect whether
the output voltage is above or below an internal
reference for the desired battery voltage. The dc
monitor pins, SDCH and SDCL, monitor input current
and voltage to the dc-dc converter external circuitry. If
an overload condition is detected, the PWM controller
will turn off the switching transistor for the remainder of
a PWM period to prevent damage to external
components. It is important that the proper value of R18
be selected to ensure safe operation. Guidance is given
in AN45.
The PWM controller operates at a frequency set by the
dc-dc Converter PWM register (direct Register 92).
During a PWM period, the outputs of the control pins,
DCDRV and DCFF, are asserted for a time given by the
read-only PWM Pulse Width register (direct
Register 94).
The dc-dc converter must be off for some time in each
cycle to allow the inductor or transformer to transfer its
stored energy to th e output cap acitor, C9. This minimum
off time can be set through the dc-dc Converter
Switching Delay register, (direct Register 93). The
number of 16.384 MHz clock cycles that the controller is
off is equal to DCTOF (bits 0 through 4) plus 4. If the dc
Monitor pins detect an overload condition, the dc-dc
converter interrupts its conversion cycles regardless of
the register settings to prevent component damage.
These inputs should be calibrated by writing the DCCAL
bit (bit 7) of the dc-dc Converter Switching Delay
register, direct Register 93, after the dc-dc converter
has been turned on.
Because the Si3210 dynamically regulates its own
battery supply voltage using the dc-dc converter
controller, the battery voltage, VBAT, is offset from the
negative-most terminal by a programmable voltage,
VOV, to allow voltage headroom for carrying audio
signals.
As mentioned previously, the Si3210 dynamically
adjusts VBAT to suit the particular circuit requirement. To
illustrate this, the behavior of VBAT in the active state is
shown in Figur e 19. In the active state, the TI P-to- RIN G
open circuit voltage is kept at VOC in the constant
voltage region while the regulator output voltage
VBAT =V
CM + VOC + VOV.
When the loop current attempts to exceed ILIM, the dc
line driver circuit enters constant current mode allowing
the TIP to RING voltage to track RLOOP. As the TIP
terminal is kept at a constant voltage, it is the RING
terminal voltage that tracks RLOOP and, as a result, the
|VBAT| voltage will also track RLOOP. In this state,
|VBAT|=I
LIM x RLOOP + VCM +VOV. As RLOOP decreases
below the VOC/ILIM mark, the regulator output voltage
can continue to track RLOOP (TRACK = 1), or the RLOOP
tracking mechanism is stopped when |VBAT|=|V
BATL|
(TRACK = 0). The former case is the more common
application and provides the maximum power
dissipation savings. In principle, the regulator output
voltage can go as low as |VBAT|=V
CM+ VOV, offering
significant power savings.
When TRACK = 0, |VBAT| will not decrease below
VBATL. The RING terminal voltage, however, continues
to decrease with decreasing RLOOP.
Si3210/Si3211
Rev. 1.61 39
The power dissipation on the NPN bipolar transistor
driving the RING terminal can become large and may
require a higher power rating device. The non-tracking
mode of operation is required by specific terminal
equipment that, in order to initiate certain data
transmission modes, goes briefly on-hook to measure
the line voltage to determ ine whether there is any other
off-hook terminal equipment on the same line.
TRACK = 0 mode is desired since the regulator output
voltage has long settling time constants (on the order of
tens of milliseconds) and cannot change rapidly for
TRACK = 1 mode. Therefore, the brief on-hook voltage
measurement would yield approximately the same
voltage as the off-hook line voltage and cause the
terminal equipment to incorrectly sense another off-
hook terminal.
Figure 19. VTIP, VRING, and VBAT in the Forward Active State
Constant I Region Constant V Region
VOC
ILIM
VCM
VOC
VOV
VOV
VRING
VBAT
VBATL
RLOOP
V
VTIP
TRACK=1
TRACK=0
|VTIP - VRING|
Table 28. Associated Relevant DC-DC Converter Registers
Parameter Range Resolution Register Bit Location
DC-DC Converter Power-off
Control N/A N/A DCOF Direct Register 14
DC-DC Converter Calibration
Enable/Status N/A N/A DCCAL Direct Register 93
DC-DC Converter PWM Period 0 to 15.564 µs 61.035 ns DCN[7:0] Direct Register 92
DC-DC Converter Min. Off Time (0 to 1.892 µs) + 4 ns 61.035 ns DCTOF[4:0] Direct Register 93
High Battery Voltage—VBATH 0 to –94.5 V 1.5 V VBATH[5:0] Direct Register 74
Low Battery Voltage—VBATL 0 to –94.5 V 1.5 V VBATL[5:0] Direct Register 75
VOV 0 to –9 V or
0 to –13.5 V 1.5 V VMIND[3:0]
VOV Indirect Register 41
Direct Register 66
Note: The ProSLIC uses registers that are both directly and indi rectly mapped. A “direct” register is one that is mapped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
Si3210/Si3211
40 Rev. 1.61
2.2.5. DC-DC Converter Enhancements
Silicon revisions C and higher support two
enhancements to the dc-dc converter. The first is a
multi-threshold error control algorithm that enables the
dc-dc converter to adjust more quickly to voltage
changes. This option is enabled by setting DCSU = 1
(direct Register 108, bit 5). The second enhancement is
an audio band filter th at re moves au dio band noise fro m
the dc-dc converter control loop. This option is enabled
by setting DCFIL = 1 (direct Register 108, bit 1).
2.2.6. DC-DC Converter During Ringing
When the ProSLIC enters the ringing state, it requires
voltages well above those used in the active mode. The
voltage to be generated and regulated by the dc-dc
converter during a ringing burst is set using the VBATH
register (dir ect Register 74). V BATH can be set between
0 and –94.5 V in 1.5 V steps. To avoid clipping the
ringing signal, VBATH must be set larger than the ringing
amplitude. At the end of each ringing burst, the dc-dc
converter adjusts back to active state regulation as
described above.
2.2.7. External Battery Switching (Si3211 Only)
The Si3211 supports switching between two battery
voltages. The circuit for external battery switching is
defined in Figure 14. Typically, a high-voltage battery
(e.g., –70 V) is used for on-hook and ringing states, and
a low-voltage battery (e.g., –24 V) is used for the off-
hook condition. The Pr oSLIC uses an external tra nsistor
to switch between the two supplies.
When the ProSLIC changes operating states, it
automatically switches battery supplies if the automatic /
manual control bit, ABAT (direct Register 67, bit 3), is
set.
For example, the ProSLIC will switch from high battery
to low battery when it detects an off-hook event through
either a ring trip or loop closure event. If automatic
battery selection is disabled (ABAT = 0), the battery is
selected by the Battery Feed Select bit, BATSL (direct
Register 66, bit 1).
Silicon revisions C and higher support the option to add
a 60 ms debounce period to the battery switching circuit
when transitioning from high battery to low battery. This
option is enabled by setting SWDB = 1 (direct
Register 108, bit 3). This debounce minimizes battery
transitions in the case of pulse dialing or other quick on-
hook to off-hook transitions.
2.3. Tone Generation
Two digital tone generators ar e provided in the ProSL IC.
They allow the generation of a wide variety of single- or
dual-tone frequency and amplitude combinations and
spare the user the effort of generating the required
POTS signaling tones on the PCM highway. DTMF, FSK
(caller ID), call progress, and other tones can all be
generated on-chip. The tones can be sent to either the
receive or transmit paths (see Figure 25 on page 50).
2.3.1. Tone Generator Ar chitecture
A simplified diagram of the tone generator architecture
is shown in Figure 20. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected to give the user flexibility in creating audio
signals. Control a nd st atus re gister bit s are plac ed in the
figure to indicate their association with the tone
generator architecture. These registers are described in
more detail in Table 29.
Si3210/Si3211
Rev. 1.61 41
Figure 20. Simplified Tone Generator Diagram
2.3.2. Oscillator Frequency and Amplitude
Each of the two tone generators contains a two-pole
resonate oscillator circuit with a programmable
frequency and amplitude, which are programmed via
indirect registers OSC1, OSC1X, OSC1Y, OSC2,
OSC2X, and OSC2Y. The sample rate for the two
oscillators is 8000 Hz. The equations are as follows:
coeffn=cos(2fn/8000 Hz),
where fn is the frequency to be generated;
OSCn = coeffnx(2
15);
where desired Vrms is the amplitude to be generated;
OSCnY = 0,
n = 1 or 2 for oscillator 1 or oscillator 2, respectively.
For example, in order to generate a DTMF digit of 8, the
two required tones are 852 Hz and 1336 Hz. Assuming
the generation of half-scale values (ignoring twist) is
desired, the followin g value s ar e calculated:
OSC1Y = 0
OSC2 = 0.49819 (215) = 16324 = 3FC4h
OSC2Y = 0
The above computed values would be written to the
corresponding registers to initialize the oscillators. Once
the oscillators are initialized, the oscillator control
registers can be accessed to enable the os cillators and
direct their outputs.
2.3.3. Tone Generator Cadence Programming
Each of the two tone generators contains two timers,
one for setting the active period and one for setting the
inactive period. The oscillator signal is generated during
the active period and suspended during the inactive
period. Both the active and inactive periods can be
programmed from 0 to 8 seconds in 125 µs steps. The
active period time interval is set using OAT1 (direct
registers 36 and 37) for tone generator 1 and OAT2
(direct registers 40 and 41) for tone generator 2.
To enable automatic cadence for tone generator 1,
define the OAT1 and OIT1 registers and then set the
O1TAE bit (direct Register 32, bit 4) and O1TIE bit
(direct Register 32, bit 3). This enables each of the
timers to control the state of the Oscillator Enable bit,
O1E (direct Register 32, bit 2). The 16-bit counter will
begin counting until the active timer expires, at which
OZn
OSSn
*Tone Generator 1 Only
n = "1" or "2" for Tone Gener ator 1 and 2, respectively
Two-Pole
Resonance
Oscillator
16-Bit
Modulo
Counter
OATn
OITn
OITnE
OATnE
OSCn
OSCnY
OSCnX
Load
Logic
Zero
Cross
Logic Signal
Routing
OnSO
to TX Path
to RX Path
INT
Logic OnIP
OnIE
INT
Logic OnAP
OnAE
REL*
Register
Load
Enable
8 kHz
Clock
Zero Cross
OnE
OAT
Expire
OIT
Expire
8 kHz
Clock
OSCnX 1
4
---1 coeff–
1 coeff+
------------------------215 1–Desired Vrms
1.11 Vrms
-------------------------------------
=
coeff12852
8000
-----------------


cos 0.78434==
OSC1 0.78434 215
25701 6465h===
OSC1X 1
4
---0.21556
1.78434
---------------------215 1–0.51424 590h===
coeff221336
8000
--------------------


cos 0.49819==
OSC2X 1
4
---0.50181
1.49819
---------------------215 1–0.52370 942h===
Si3210/Si3211
42 Rev. 1.61
time the 16-bit counter will reset to zero and begin
counting until the inactive timer expires. The cadence
continues until the user clears the O1TAE and O1TIE
control bits. The zero crossing detect feature can be
implemented by setting the OZ1 bit (direct Register 32,
bit 5). This ensures that each oscillator pulse ends
without a dc component. The timing diagram in
Figure 21 is an example of an output cadence using the
zero crossing feature.
One-shot oscillation can be achieved by enabling O1E
and O1TAE. Direct control over the cadence can be
achieved by controlling the O1E bit (direct Register 32,
bit 2) directly if O1TAE and O1TIE are disabled.
The operation of tone generator 2 is identical to that of
tone generator 1 using its respective control registers.
Note: Tone Generator 2 should not be enabled simultane-
ously with the ringing oscillator due to resource sharing
within the hardware.
Continuous phase frequency-shift keying (FSK)
waveforms may be created using tone generator 1 (not
available on tone generator 2) by setting the REL bit
(direct Register 32, bit 6), which enables reloading of
the OSC1, OSC1X, and OSC1Y registers at the
expiration of the active timer, OAT1.
Table 29. Associated Tone Generator Registers
Tone Generator 1
Parameter Description / Range Register Bits Location
Oscillator 1 Frequency Coefficient Sets oscillator frequency OSC1[15:0] Indirect Register 13
Oscillator 1 Amplitude Coefficient Sets oscillator amplitude OSC1X[15:0] Indirect Register 14
Oscillator 1 initial phase coefficient Sets initial phase OSC1Y[15:0] Indirect Register 15
Oscillator 1 Active Timer 0 to 8 seconds OAT1[15:0] Direct Registers 36 & 37
Oscillator 1 Inactive Timer 0 to 8 seconds OIT1[15:0] Direct Register 38 & 39
Oscillator 1 Control Status and control
registers OSS1, REL, OZ1,
O1TAE, O1TIE,
O1E, O1SO[1:0]
Direct Register 32
Tone Generator 2
Parameter Description/Range Register Location
Oscillator 2 Frequency Coefficient Sets oscillator frequency OSC2[15:0] Indirect Register 16
Oscillator 2 Amplitude Coefficient Sets oscillator amplitude OSC2X[15:0] Indirect Register 17
Oscillator 2 initial phase coefficient Sets initial phase OSC2Y[15:0] Indirect Register 18
Oscillator 2 Active Timer 0 to 8 seconds OAT2[15:0] Direct Registers 40 & 41
Oscillator 2 Inactive Timer 0 to 8 seconds OIT2[15:0] Direct Register 42 & 43
Oscillator 2 Control Status and control
registers OSS 2, OZ2,
O2TAE, O2TIE,
O2E, O2SO[1:0]
Direct Register 33
Si3210/Si3211
Rev. 1.61 43
Figure 21. Tone Generator Timing Diagram
2.3.4. Enhanced FSK Waveform Generation
Silicon revisions C and higher support enhanced FSK
generation capabilities, which can be enabled by setting
FSKEN = 1 (direct Register 108, bit 6) and REN = 1
(direct Register 32, bit 6). In this mode, the user can
define mark (1) and space (0) attributes once during
initialization by defining indirect registers 99–104. The
user need only indicate 0-to-1 and 1-to-0 transitions in
the information stream. By writing to FSKDAT (direct
Register 52), this mode applies a 24 kHz sample rate to
tone generator 1 to give additional resolution to timers
and frequency generation. “AN32: Si321x Frequency
Shift Keying (FSK) Modulation” gives detailed
instructions on how to implement FSK in this mode.
Additionally, sample source code is available from
Silicon Laboratories upon request.
2.3.5. Tone Generator Interrupts
Both the active and inactive timers can generate their
own interrupt to signal “on/off” transitions to the
software. The timer interrupts for tone generator 1 can
be individually enabled by setting the O1AE and O1IE
bits (direct Register 21, bits 0 and 1, respectively).
Timer interrupts for tone generator two are O2AE and
O2IE (direct Register 21, bits 2 and 3, respectively). A
pending interrup t for each of the timers is determined by
reading the O1AP, O1IP, O2AP, and O2IP bits in the
Interrupt Status 1 register (direct Register 18, bits 0
through 3, respectively).
2.4. Ringing Generation
The ProSLIC provides fully-programmable internal
balanced ringing with or without a dc offset to ring a
wide variety of terminal devices. All parameters
associated with ringing (ringing frequency, waveform,
amplitude, dc offset, and ringing cadence) are software-
programmable. Both sinusoidal and trapezoidal ringing
waveforms are supported, and the trapezoidal crest
factor is programmable. Ringing signals of up to 88 V
peak or more can be generated, enabling the ProSLIC
to drive a 5 REN (1380 + 40 µF) ringer load across
loop lengths of 2000 feet (160 ) or more.
2.4.1. Ringing Architecture
The ringing generator architecture is nearly identical to
that of the tone generator. The sinusoidal ringing
waveform is generated using an internal two-pole
resonance oscillator circuit with programmable
frequency and amplitude. However, since ringing
frequencies are very low compared to the audio band
signaling frequencies, the ringing waveform is
generated at a rate of 1 kHz instead of 8 kHz.
The ringing generator has two timers that function the
same as the tone generator timers. They allow on/off
cadence settings of up to 8 seconds on and 8 seconds
off. In addition to controlling ringing cadence, these
timers control the transition into and out of the ringing
state. Table 30 summarizes the list of registers used for
ringing generation.
Note: Tone generator 2 should not be enabled concurrently
with the ringing generator due to resource sharing
within the hardware.
...
...
0,1 ... 0,1 ......, OA T 1 ..., OA T 1..., O IT10,1 ... 0,1 ...
O1E
OSS1
Tone
G en. 1
Signal
Output
Si3210/Si3211
44 Rev. 1.61
When the ringing state is invoked by writing
LF[2:0] = 100 (direct Register 64), the ProSLIC will go
into the ringing state and start the first ring. At the
expiration of RAT, the ProSLIC will turn off the ringing
waveform and will go to the on-hook transmission state.
At the expiration of RIT, ringing will again be initiated.
This process will continue as long as the two timers are
enabled and the Linefeed Control register is set to the
ringing state.
2.4.2. Sinusoidal Ringing
To configure the ProSLIC for sinusoidal ringing, the
frequency and amplitude are initialized by writing to the
following indirect registers: RCO, RNGX, and RNGY.
The equations for RCO, RNGX, RNGY are as follows:
where
and f = desired ringing frequency in Hertz.
The minimum allowed peak TIP-to -RING ringin g voltage
depends on the linefeed state. In the forward active
linefeed state, the selected ringing amplitude (RNGX,
Indirect Register 21) plus t he selected ring ing dc volt age
offset (ROFF, Indirect Register 19) must be greater than
the selected on-hook line voltage setting (VOC, direct
Register 72). In the reverse active linefeed state, the
selected ringing amplitude (RNGX, Indirect Register 21)
minus the selected ringing dc voltage offset (ROFF,
Indirect Register 19) must be greater than the selected
on-hook line voltage setting (VOC, direct Register 72).
Using a 70 VPK 20 Hz ringing signal as an example, the
equations ar e as follows:
Table 30. Registers for Ringing Generation
Parameter Range/ Description Register
Bits Location
Ringing Waveform Sine/Trapezoid TSWS Direct Register 34
Ringing Voltage Offset Enable Enabled/
Disabled RVO Direct Regi ster 34
Ringing Active Timer Enable Enabled/
Disabled RTAE Direct Register 34
Ringing Inactive Timer Enable Enabled/
Disabled RTIE Direct Register 34
Ringing Oscillator Enable Enabled/
Disabled ROE Direct Register 34
Ringing Oscillator Active Timer 0 to 8 seconds RAT[15:0] Direct Registers 48 and 49
Ringing Oscillator Inactive Timer 0 to 8 seconds RIT[15:0] Direct Registers 50 and 51
Linefeed Control (Initiates Ringing State) Ringing State = 100b LF[2:0] Direct Register 64
High Battery Voltage 0 to –94.5 V VBATH[5:0] Direct Register 74
Ringing dc voltage offset 0 to 94.5 V ROFF[15:0] Indirect Register 19
Ringing frequency 15 to 100 Hz RCO[15:0] Indirect Register 20
Ringing amplitude 0 to 94.5 V RNGX[15:0] Indirect Register 21
Ringing initial phase Sets initial phase for
sinewave and period
for
trapezoid
RNGY[15:0] Indirect Register 22
Common Mode Bias Adjust During Ringing 0 to 22.5 V VCMR[3:0] Indirect Register 40
Note: The ProSLIC uses registers that are both di rectly and indirectly mapped. A “direct” registe r is one that is ma pped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
RCO coeff 215
=
coeff 2f
1000 Hz
-----------------------


cos=
RNGX 1
4
---1coeff–
1 coeff+
------------------------215
Desired VPK 0to94.5V
96 V
------------------------------------------------------------------------
=
RNGY 0=
coeff 220
1000 Hz
-----------------------


0.99211=cos=
Si3210/Si3211
Rev. 1.61 45
In addition, the user must select the sinusoidal ringing
waveform by writing TSWS = 0 (direct Register 34,
bit 0).
2.4.3. Trapezoidal Ringing
In addition to the sinusoidal ringing waveform, the
ProSLIC supports trapezoidal ringing. Figure 22
illustrates a trapezoidal ringing waveform with offset
VROFF.
Figure 22. Trapezoidal Ringing Waveform
To configure the ProSLIC for trapezoidal ringing, the
user should follow the same basic procedure as in the
Sinusoidal Ringing section, but using the following
equations:
RCO is a value added or subtracted from the waveform
to ramp the signal up or down in a linear fashion. This
value is a function of rise time, period, and amplitude,
where rise time and period are related through the
following equation for the crest factor of a trapezoidal
waveform.
where T = ringing period, and CF = desired crest factor.
For example, to generate a 71 VPK, 20 Hz ringing
signal, the equations are as follows:
For a crest factor of 1.3 and a period of 0.05 seconds
(20 Hz), the rise time requirement is 0.0153 seconds.
In addition, the user must select the trapezoidal ringing
waveform by writing TSWS = 1 in direct Register 34.
2.4.4. Ringing DC voltage Offset
A dc offset can be added to the ac ringing waveform by
defining the offset voltage in ROFF (indirect
Register 19). The offset, VROFF, is added to the ringing
signal when RVO is set to 1 (direct Register 34, bit 1).
The value of ROFF is calculated as follows:
2.4.5. Linefeed Considerations During Ringing
Care must be taken to keep the gen erated ringing signal
within the ringing voltage rails (GNDA and VBAT) to
maintain proper biasing of the external bipolar
transistors. If the ringing signal nears the rails, a
distorted ringing signal and excessive power dissipation
in the external transistors results.
To prevent this invalid operation, set the VBATH value
(direct Register 74) to a value higher than the maximum
peak ringing voltage. The discussion be low outlines the
considerations and equations that govern the selection
of the VBATH setting for a particular desired peak ringing
voltage.
First, the required amount of ringing overhead voltage,
VOVR, is calculated based on the maximum value of
current through the load, ILOAD,PK, the minimum current
gain of Q5 and Q6, and a reasonable voltage required
to keep Q5 and Q6 out of saturation. For ringing signals
up to VPK =87V, V
OVR = 7.5 V is a safe value.
However, to determine VOVR for a specific case, use the
equations below.
RCO 0.99211 215
32509 7EFDh===
RNGX 1
4
---0.00789
1.99211
---------------------215
70
96
------
376 0177h===
RNGY 0=
time
VROFF T=1/freq
tRISE
VTIP-RING
RNGY 1
2
---Period8000=
RNGX Desired VPK
96 V
----------------------------------- 215
=
RCO 2 RNGX
tRISE 8000
---------------------------------
=
tRISE 3
4
---T1 1
CF2
-----------
–


=
RNGY 20 Hz
1
2
---1
20 Hz
----------------
8000200 C8h===
RNGX 71 VPK

71
96
------ 215
24235 5EABh===
RCO 20 Hz,1.3 crest factor
2 24235
0.0153 8000
--------------------------------------396 018Ch===
ROFF VROFF
96
------------------215
=
ILOAD,PK VAC,PK
RLOAD
------------------- IOS
+VAC,PK NREN
6.9 k
------------------
IOS
+==
Si3210/Si3211
46 Rev. 1.61
where:
NREN is the ringing REN load (max value = 5),
IOS is the offset current flowing in the line driver circuit
(max value=2mA), and
VAC,PK = amplitude of the ac ringing waveform.
It is good practice to provide a buffer of a few more
milliamperes for ILOAD,PK to account for possible line
leakages, etc. The total ILOAD,PK current should be
smaller than 80 mA.
where
is the minimum expected current gain of
transistors Q5 and Q6.
The minimum value for VBATH is therefore given by the
following:
The ProSLIC is designed to create a fully-balanced
ringing waveform, meaning that the TIP and RING
common mode voltage, (VTIP + VRING)/2, is fixed. This
voltage is referred to as VCM_RING and is
automatically set to the following:
VCMR is an indirect register, which provides the
headroom by the ringing waveform with respect to the
VBATH rail. The value is set as a 4-bit setting in indirect
Register 40 with an LSB voltage of 1.5 V/LSB.
Register 40 should be set with the calculated VOVR to
provide voltage headroom during ringing.
Silicon revisions C and higher support the option to
briefly increase the maximum differential current limit
between the voltage transition of TIP and RING from
ringing to a dc linefeed state. This mode is enabled by
setting ILIMEN = 1 (direct Register 108, bit 7).
2.4.6. Ring Trip Detection
A ring trip event signals that the terminal equipment has
gone off-hook during the ringing state. The ProSLIC
performs ring trip detection digitally using its on-chip A/
D converter. The functional blocks required to
implement ring trip detection are shown in Figure 23.
The primary input to the system is the loop current
sense (LCS) value provided by the current monitoring
circuitry and reported in direct Register 79. LCS data is
processed by the input signal processor when the
ProSLIC is in the ringing state as indicated by the
Linefeed Shadow register (direct Register 64). The data
then feeds into a programmable digital low-pass filter
that removes unwanted ac signal components before
threshold detection.
The output of the low-pass filter is compared to a
programmable threshold, RPTP (indirect Register 29).
The threshold comp ar ator output feed s a programm able
debouncing filter. The output of the debouncing filter
remains in its present state unless the input remains in
the opposite state for the entire period of time
programmed by the ring trip debounce interval,
RTDI[6:0] (direct Register 70). If the debounce interval
has been satisfied, the RTP bit of direct Register 68 will
be set to indicate that a valid ring trip has occurred. A
ring trip interrupt is generated if enabled by the RTIE bit
(direct Register 22). Table 31 lists the registers that
must be written or monitored to correctly detect a ring
trip condition.
The recommended values for RPTP, NRTP, and RTDI
vary according to the programmed ringing frequency.
Register values for various ringing frequencies are
given in Table 32.
Figure 23. Ring Trip Detector
VOVR ILOAD,PK 1+
-------------
80.6 1V+=
VBATH VAC,PK VROFF VOVR
++=
VCM_RING VBATH VCMR–
2
----------------------------------------------
=
LCS ISP_OUT
LFS NRTP
RPTP
RTDI
Input
Signal
Processor
Digital
LPF
R in g T rip
Threshold
Debounce
Filter
+
–
RTP RTIP
RTIE
Interrupt
Logic
DBIRAW
Si3210/Si3211
Rev. 1.61 47
2.5. Pulse Metering Generation
There is an additional tone generator suitable for
generating tones above the audio frequency. This
oscillator is provided for the generation of billing tones
that are typically 12 kHz or 16 kHz. The generator
follows the same algorithm as described in "2.3. Tone
Generation" on page 40 with the exception that the
sample rate for computation is 64 kHz instead of 8 kHz.
The equations ar e as follow s :
where full scale Vrms =0.85V
rms for a matched load.
The initial phase of the pulse metering signal is set to 0
internally; so, there is no register to serve this purpose.
The pulse metering generator timers and associated
pulse metering timer registers are similar to those of the
tone generators. These timers count 8 kHz sample
periods like th e other tones even though the sinusoid is
generated at 64 kHz.
Table 31. Associated Registers for Ring Trip Detection
Parameter Register Location
Ring Trip Interrupt Pending RTIP Direct Register 19
Ring Trip Interrupt Enable RTIE Direct Register 22
Ring Trip Detect Debounce Interval RTDI[6:0] Direct Register 70
Ring Trip Threshold RPTP[5:0] Indirect Register 29
Ring Trip Filter Coefficient NRTP[12:0] Indirect Register 36
Ring Trip Detect Status (monitor only) RTP Direct Register 68
Note: The ProSLIC uses registers that are both di rectly and indirectly mapped. A “direct” register is one that is mapped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
Table 32. Recommended Ring Trip Values for Ringing
Ringing
Frequency NRTP RPTP RTDI
Hz decimal hex decimal hex decimal hex
16.667 64 0200 34 mA 3600 15.4 ms 0F
20 100 0320 34 mA 3600 12.3 ms 0B
30 112 0380 34 mA 3600 8.96 ms 09
40 128 0400 34 mA 3600 7.5 ms 07
50 213 06A8 34 mA 3600 5 ms 05
60 256 0800 34 mA 3600 4.8 ms 05
coeff 2f
64000 Hz
--------------------------


cos=
PLSCO coeff 215 1–=
PLSX 1
4
---1 coeff–
1 coeff+
------------------------215 1–Desired Vrms
Full Scale Vrms
--------------------------------------------
=
Si3210/Si3211
48 Rev. 1.61
The pulse metering oscillator has a volume envelope (linear ramp) on the on/off transitions of the oscillator. The
volume value is incremented by the value in the PLSD register (indirect Register 23) at an 8 kHz rate. The
sinusoidal generator output is multiplied by this volume before being sent to the DAC. The volume will ramp from 0
to 7FFF in increments of PLSD; so, the value of PLSD will set the slope of the ramp. When the pulse metering
signal is turned off, the volume will ramp to 0 by decrementing according to the value of PLSD.
Figure 24. Pulse Metering Volume Envelope
Table 33. Associated Pulse Metering Generator Registers
Parameter Description / Range Register Bits Location
Pulse Metering Frequency
Coefficient Sets oscillator frequency PLSCO[15:0] Indirect Register 25
Pulse Metering Amplitude
Coefficient Sets oscillator amplitude PLSX[15:0] Indirect Register 24
Pulse Metering Attack/Decay
Ramp Rate 0 to PLSX (full amplitude) PLSD[15:0] Indirect Register 23
Pulse Metering Active Timer 0 to 8 seconds PAT[15:0] Direct Registers 44 & 45
Pulse Metering Inactive Timer 0 to 8 seconds PIT[15:0] Direct Register 46 & 47
Pulse Metering Control Status and control registers PSTAT, PMAE,
PMIE, PMOE Direct Register 35
Note: The ProSLIC uses registers that are both directly and indirectl y mapped. A direct register is one that is mapped
directly. An indirect register is one that is accessed using the indirect access registers (direct registers 28
through 31).
Pulse Metering O scillator
Volume
+/– PLSD
To D AC
Clip to 7FFF or 0
8 Khz
X
Si3210/Si3211
Rev. 1.61 49
2.6. DTMF Detection
The dual-tone multi-frequency (DTMF) tone signaling
standard is also known as touch tone. It is an in-band
signaling system used to replace the pulse-dial
signaling standard. In DTMF, two tones are used to
generate a DTMF digit. One tone is chosen from four
possible row tones, and one tone is chosen from four
possible column tones. The sum of these tones
constitutes one of 16 po ssib le DT MF digi ts.
2.6.1. DTMF Detection Architecture
DTMF detection is performed using a modified Goertzel
algorithm to compute the dual frequency tone (DFT) for
each of the eight DTMF frequencies as well as their
second harmonics. At the end of the DFT computation,
the squared magnitudes of the DFT results for the eight
DTMF fundamental tones are computed. The row
results are sorted to determine the strongest row
frequency; the column frequencies are sorted as well.
At the completion of this process, a number of checks
are made to determine whether the strongest row and
column tones constitute a DTMF digit.
The detection process is performed twice within the
45 ms minimum tone time. A digit must be detected on
two consecutive tests following a pause to be
recognized as a new digit. If all tests pass, an interrupt
is generated, and the DTMF digit value is loaded into
the DTMF register. If tones occur at the maximum rate
of 100 ms per digit, the interrupt must be serviced with in
85 ms so that the current digit is not overwritten by a
new one. There is no buffering of the digit information.
2.7. Audio Path
Unlike traditional SLICs, the codec function is integra ted
into the ProSLIC. Th e 16-bit codec o ffer s program mable
gain/attenuation blocks and several loopback modes.
The signal path block diagram is shown in Figure 25.
2.7.1. Transmit Path
In the transmit path, the analog signal fed by the
external ac coupling capacitors is amplified by the
analog transmit amplifier, ATX, prior to the A/D
converter. The gain of the ATX is user-selectable to one
of mute/–3.5/0/3.5 dB options. The main role of ATX is
to coarsely adjust the signal swing to be as close as
possible to the full-scale input of the A/D converter in
order to maximize the signal-to-noise ratio of the
transmit path. After passing through an anti-aliasing
filter, the analog signal is processed by the A/D
converter, producing an 8 kHz, 16-bit wide, linear PCM
data stream. The standard requirements for transmit
path attenuation for signals above 3.4 kHz are
implemented as part of the combined decimation filter
characteristic of the A/D converter. One more digital
filter is available in the transmit path: THPF. THPF
implements the high-pass attenuation requirements for
signals below 65 Hz. The linear PCM data stream
output from THPF is amplified by the transmit-path
programmable gain amplifier, ADCG, which can be
programmed from –dB to 6 dB. The DTMF decoder
can receive the linear PCM data stream at this point to
perform the digit extraction when enabled by the user.
The final step in transmit path signal processing is the
user-selectable A-law or µ- l aw c o m p re s s i on , w h i ch c a n
reduce the data stream word width to 8 bits. Depending
on the PCM_Mode register selection, every 8-bit
compressed serial data word will oc cu py one time slot
on the PCM highway, or every 16-bit uncompressed
serial data word will occupy two time slots on the PCM
highway.
Si3210/Si3211
50 Rev. 1.61
+
Mute
H
From Billing Tone
DAC
From Billing
Tone DAC
ATX
+
Interpolation
Filter Mute
DACG
/A-law
Compressor
/A-law
Expander Serial
Input
Decimation
Filter
RHPF
THPF
DTMF
Decoder
Serial
Output
Digital
RX
Digital
TX
Dual Tone
Generator
Full
Analog
Loopback
ADCG
D/A
+
A/D
HYBA
H
TXM
Digital
Loopback
DLM
ALM1
Analog
Loopback
ALM2
Off Chip On Chip HYBP Transmit Path
TIP
RING XAC
RACGm
Ibuf
–
+
ARX
RXM
–
Figure 25. AC Signal Path Block Diagram
Si3210/Si3211
Rev. 1.61 51
2.7.2. Receive Path
In the receive path, the optionally-compressed 8-bit
data is first expanded to 16-bit words. The PCMF
register bit can bypass the expansion process, in
which c ase t wo 8-bit words are assemb led into one 16-
bit word. DACG is the receive path programmable gain
amplifier, which can be programmed from –dB to
6 dB. An 8 kHz, 16-bit signal is then provided to a D/A
converter. The resulting analog signal is amplified by
the analog receive amplifier, ARX, which is user-
selectable to one of several options: mute, –3.5, 0, or
3.5 dB. It is then applied at the input of the
transconductance amplifier (Gm), which drives the off-
chip current buffer (IBUF).
2.7.3. Audio Characteristics
The dominant source of distortion and noise in both the
transmit and receive paths is the quantization noise
introduced by the µ-law or the A-law compression
process. Figure 1 on page 6 specifies the minimum
signal-to-noise-and-distortion ratio for either path for a
sine wave input of 200 Hz to 3400 Hz.
Both the µ-law and the A-law speech encoding allow the
audio codec to transfer and process audio signals lar ger
than 0 dBm0 without clipping. The maximum PCM code
is generated for a µ-law encoded sine wave of
3.17 dBm0 or an A-law encoded sine wave of
3.14 dBm0. The ProSLIC overload clipping limits are
driven by the PCM encodin g process. F igure 2 on page
6 shows the acceptable limits for the analog-to-analog
fundamental power transfer-function, which bounds the
behavior of ProSLIC.
The transmit path gain distortion versus frequency is
shown in Figure 3 on page 7. The same figure also
presents the minimum required attenuation for any out-
of-band analog signal that may be applied on the line.
Note the presence of a high-pass filter transfer function
that ensures at least 30 dB of attenuation for signals
below 65 Hz. The low-pass filter transfer function that
attenuates signals above 3.4 kHz has to exceed the
requirements specified by the equations in Figure 3 on
page 7 and is implemented as part of the A-to-D
converter.
The receive path transfer function requirement, shown
in Figure 4 on page 8, is very similar to the transmi t p ath
transfer function. The most notable difference is the
absence of the high-pass filter portion. The only other
differences are the maximum 2 dB of attenuation at
200 Hz (as opposed to 3 dB for the transmit path) and
the 28 dB of attenuation for any frequency above
4.6 kHz. The PCM data rate is 8 kHz and, thus, no
frequencies greater than 4 kHz can be digitally encoded
in the data stream.
From this point of view, at frequencies greater than
4 kHz, the plot in Figure 4 should be interpreted as the
maximum allowable magnitude of any spurious signals
that are generated when a PCM data stream
representing a sine wave signal in the range of 300 Hz
to 3.4 kHz at a level of 0 dBm0 is applied at the digital
input.
The group delay distortion in either path is limited to no
more than the levels indicated in Figure 5 on page 9.
The reference in Fig ure 5 is the smallest group dela y for
a sine wave in the range of 500 Hz to 2500 Hz at
0dBm0.
The block d iagram fo r the v oice-ban d signal pr ocessin g
paths is shown in Figure 25. Both the receive and
transmit paths employ the optimal combination of
analog and digital signal processing to provide
maximum performance while offering sufficient flexibility
to allow users to optimize for their particular ProSLIC
application. All programmable signal-processing blocks
are indicated symbolically in Figure 25 by a dashed
arrow across them. The two-wire (TIP/RING) voice-
band interface to the ProSLIC is implemented using a
small number of external components. The receive path
interface consists of a unity-gain current buffer, IBUF,
while the transmit path interface is simply an ac
coupling capacitor. Signal paths, although implemented
differentially, are shown as single-ended for simplicity.
2.7.4. Transhybrid Balance
The ProSLIC provides programmable transhybrid
balance with gain block H. (See Figure 25.) In the ideal
case, where the synthesized SLIC impedance exactly
matches the subscriber loop impedance, the
transhybrid balance should be set to subtract a –6 dB
level from the transmit path signal. The transhybrid
balance gain can be adjusted from –2.77 dB to
+4.08 dB around the ideal setting of –6 dB by
programming the HYBA[2:0] bits of the Hybrid Control
register (direct Register 11). Note that adjusting any of
the analog or digital gain blocks will not require any
modification of the transhybrid balance gain block, as
the transhybrid gain is subtracted from the transmit p a th
signal prior to any gain adjustment stages. If desired,
the transhybrid balance can also be disabled using the
appropriate register setting.
2.7.5. Loopback Testing
Four loopback test options ar e a vailabl e in the ProSL IC:
The full analog loopback (ALM2) tests almost all the
circuitry of both the transmit and receive paths. The
compressed 8-bit word transmit data stream is fed
back serially to the input of the receive path
expander. (See Figure 25.) The signal path starts
with the analog signal at the input of the transmit
Si3210/Si3211
52 Rev. 1.61
path and ends with an analog signal at the output of
the receive path.
An additional analog loopback (ALM1) takes the
digital stream at the output of the A/D converter and
feeds it back to the D/A converter. (See Figure 25.)
The signal pa th starts with the analog signal at the
input of the transmit path and ends with an analog
signal at the output of the receive path. This
loopback option allows testing of the analog signal
processing circ uitr y of th e Si32 1 0 to be car rie d out
completely independently of any activity in the DSP.
The full digital loopback tests almost all the circuitry
of both the transmit and receive paths. The analog
signal at the output of the receive path are fed back
to the input of the transmit path by way of the hybrid
filter path. (See Figure 25.) The signal path starts
with 8-bit PCM data input to the receive p ath and
ends with 8-bit PCM data at the output of the
transmit path. The user can bypass the companding
process and inte rf ac e dir ectly to the 16-bit data.
An additional digit al loop back (DLM) t akes the digit al
stream at the input of the D/A converter in the
receive path and fe eds it back to the transmit A/D
digital filter. The signal path starts with 8-bit PCM
data input to the receive path and ends with 8-bit
PCM data at the output of the transmit path. This
loopback option allows the testing of the digital
signal processing circuitry of the Si3210 to be carried
out completely independently of any analog signal
processing activity. The user can bypass the
companding pr ocess and interface directly to the 16-
bit data.
2.8. Two-Wire Impedance Matching
The ProSLIC provides on-chip, programmable, two-wire
impedance settings to meet a wide variety of worldwide
two-wire return loss requirements. The two-wire
impedance is programmed by loading one of the eight
available impedance va lues into the TISS[2:0] bit s of th e
Two-Wire Impedance Synthesis Control register (direct
Register 10). If direct Register 10 is not user-defined,
the default setting of 600 will be loaded into the TISS
register.
Real and complex tw o-wire impedances ar e realized by
internal feedback of a programmable amplifier (RAC), a
switched capacitor network (XAC), and a
transconduc ta nce amplifier (Gm). (See Figure 25.) RAC
creates the real portion, and XAC creates the imaginary
portion of Gm’s input. Gm then creates a current that
models the desired impedance value to the subscriber
loop. The differential ac current is fed to the subscriber
loop via the ITIPP and IRINGP pins through an off-chip
current buffer, IBUF, which is implemented using
transistors Q1 and Q2 (see Figure 13 on page 24). Gm
is referenced to an off-chip resistor (R15).
The ProSLIC also provides a means of compensating
for degraded subscriber loop conditions involving
excessive line capacitance (leakage). The CLC[1:0] bits
of direct Register 10 increase the ac signal magnitude
to compensate for the additional loss at the high end of
the audio frequency range. The default setting of
CLC[2:0] assumes no line capacitance.
Silicon revisions C and higher support the option to
remove the internal reference resistor used to
synthesize ac impedances for 600 + 2.16 µF and
900 + 2.16 µF settings so that an external resistor
reference may be used. This option is enabled by
setting ZSEXT = 1 (direct Register 108, bit 4).
2.9. Clock Generation
The ProSLIC will generate the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronou s to the 8 kH z FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 768 kHz,
1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz or
8.192 MHz. (Note that 768 kHz and 1.536 MHz are not
valid rates for GCI mode.) The ratio of the PCLK rate to
the FSYNC rate is determined via a counter clocked by
PCLK. The three-bit ratio information is automatically
transferred into an internal register, PLL_MULT,
following a reset of the ProSLIC. The PLL_MULT is
used to control the internal P LL, which multiplies PCLK
as needed to generate the 16.384 MHz rate needed to
run the internal filters and o ther circuitry.
The PLL clock synthesizer settles very quick ly following
powerup. However, the settling time depends on the
PCLK frequency, and it can be approximated by the
following equation:
2.10. Interrupt Logic
The ProSLIC is capable of generating interrupts for the
following events:
Loop current/ring ground detected
Ring trip detected
Power alarm
DTMF digit detected
Active timer 1 expired
Inactive timer 1 expired
Active timer 2 expired
Inactive timer 2 expired
Ringing active timer expired
Ringing inactive timer expired
TSETTLE 64
FPCLK
-----------------
=
Si3210/Si3211
Rev. 1.61 53
Pulse metering active timer expired
Pulse metering inactive timer expired
Indirect register access complete
The interface to the interrupt logic consists of six registers. Three interrupt status registers contain one bit for each
of the above interrupt functions. These bits will be set when an interrupt is pending for the associated resource.
Three interrupt enable registers also contain one bit for each interrupt f unction. In the case of the interrupt enable
registers, the bits are active high. Refer to the appropriate functional description section for operational details of
the interrupt functions.
When a resource reaches an interrupt condition, it will signal an interrupt to the interrupt control block. The interrupt
control block will then set the associated bit in the interrupt status register if the enable bit for that interrupt is set.
The INT pin is a NOR of the bit s of the inter rupt st atus re gisters. Therefore, if a bit in the interrupt status registers is
asserted, IRQ will assert low. Upon receiving the interrupt, the interrupt handler should read interrupt status
registers to dete rmine which resource is r equesting se rvice. To clear a pending interrupt, write the de sired bit in the
appropriate interrupt status register to 1. Writing a 0 has no effect. This provides a mechanism for clearing
individual bits when multiple interrupts occur simultaneously. While the interr upt status registers are non-zero, the
INT pin will remain asserted.
2.11. Serial Peripheral Interface
The control interface to the ProSLIC is a 4-wire interface modeled after commonly-available micro-controller and
serial peripheral devices. The interface consists of a clock (SCLK), chip select (CS), serial data input (SDI), and
serial data output (SDO). Data is transferred a byte at a time with each register access consisting of a pair of byte
transfers. Figures 26 and 27 illustrate read and write operation in the SPI bus.
The first byte of the pair is the command/address byte. The MSB of this byte indicates a register read when 1 and
a register write when 0. The remaining seven bit s of the command/address byte indicate the address of the register
to be accessed. The second byte of the pair is the data byte. Because the falling edge of CS provides
resynchronization of the SPI st ate machine in the event of a framing er ror, it is recommended (but not requ ired) that
CS be taken high between byte transfers as shown in Figures 26 and 27.
During a read operation, the SDO becomes active and the 8-bit contents of the register are driven out MSB first.
The SDO will be high impedance on either the falling edge of SCLK following the LSB, or the rising of CS as
specified by the SPIM bit (direct Register 0, bit 6). SDI is a “don’t care” during the data portion of read operations.
During write operations, data is driven into the ProSLIC via the SDI pin MSB first. The SDO pin will remain high
impedance during write operations. Data always transitions with the falling edge of the clock and is latched on the
rising edge. The clock should return to a logic high when no transfer is in progress.
Indirect registers are accessed through direct registers 29 through 30. Instructions on how to access them is
described in “3. Control Registers” beginning on page 60.
There are a number of variations of usage on this four-wire interface:
Continuous Clocking: Du ring continuo us clocking, the dat a tran sfers ar e controlled by the assertion of the CS
pin. CS must assert before the falling edge of SCLK on which the first bit of data is expected during a read
cycle, and must remain low for the duration of the 8-‘bit transfer (command/address or data).
SDI/SDO Wired Operation: Independent of the clockin g options described, SDI and SDO can be treated as
two separate lines or wired together if the master is capable of tristating its output during the data byte transfer
of a read operation.
Daisy Chain Mode: This mode allows communication with banks of up to eight ProSLIC devices using one
chip select signal. When the SPIDC bit in the SPI Mode Select register is se t, data transfer mode changes to a
3-byte operation: a chip select byte, an address/control byte, and a data byte. Using the circuit shown in
Figure 28, a single device may select from the bank of devices by setting the appropriate chip select bit to 1.
Each device uses the LSB of the ch ip select byte, shifts the data right by one bit, and passes the chip select
byte using the SDITHRU pin to the next device in the chain. Address/control and data bytes are unaltered.
Si3210/Si3211
54 Rev. 1.61
Figure 26. Serial Write 8-Bit Mode
Figure 27. Serial Read 8-Bit Mode
SCLK
CS
SDI
SDO High Impedance
0a0a1a2a3a4a5a6 d7 d0d1d2d3d4d5d6
Don't
Care
SCLK
CS
SDI
SDO
1a0a1a2a3a4a5a6
d7 d0d1d2d3d4d5d6
Don't Care
High Impedance
Don't
Care
Si3210/Si3211
Rev. 1.61 55
Figure 28. SPI Daisy Chain Mode
CPU
SDO
CS
SDI
CS SDI
SDITHRU
SDO
CS SDI
SDITHRU
SDO
C7 C6 C5 C4 C3 C 2 C1 C0 R/W A6 A5 A4 A3 A2 A1 A0
– C7 C6 C5 C4 C3 C2 C1
– – C7 C6 C5 C4 C3 C2
Chip Sele ct Byte Address Byte Data Byte
SCLK
SDI0
SDI1
SDI2
SDI3
R/W A6 A5 A4 A3 A2 A1 A0
R/W A6 A5 A4 A3 A2 A1 A0
R/W A6 A5 A4 A3 A2 A1 A0– – – C7 C6 C5 C4 C3
Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the
LSB of the ch ip select b yte for its chip select .
CS SDI
SDITHRU
SDO
CS SDI
SDITHRU
SDO
SDI0
SDI3
SDI2
SDI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Si3210/Si3211
56 Rev. 1.61
2.12. PCM Interface
The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM
samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as PCM Mode Select (direct
Register 1), PCM Transmit Start Count (direc t registers 2 and 3 ), and PCM Re ceive Start Count ( direct regi sters 4
and 5). The interface can be configured to support from 4 to 128 8-bit timeslots in each frame. This corresponds to
PCLK frequencies of 256 kHz to 8.192 MHz in power of 2 increments. (768 kHz and 1.536 MHz are also available,
but these frequencies are not valid for GCI mode.) Timeslots for data transmission and reception are independently
configured using the TXS and RXS registers. By setting the correct starting point of the data, the ProS LIC can be
configured to support long FSYNC and short FSYNC variants as well as IDL2 8-bit, 10-bit, B1 and B2 channel time
slots. DTX data is high-impedance except for the duration of the 8-bit PCM transmit.
DTX will return to high impedance either on the negative edge of PCLK during the LSB or on the positiv e edge of
PCLK following the LSB. This is based on the setting of the TRI bit of the PCM Mode Select register. Tristating on
the negative edge allows the transmission of dat a by multiple sources in adjacent timeslots without the risk of driver
contention. In addition to 8-bit data modes, there is a 16-bit mode provided. This mode can be activated via the
PCMT bit of the PCM Mode Select register. GCI timing is also supported in whic h the duration of a data bit is two
PCLK cycles. This mode is also activated via the PCM Mode Select register. Setting the TXS or RXS register
greater than the number of PCLK cycles in a sample period w ill stop data transmission because TXS or RXS will
never equal the PCLK count. Figures 29–32 illustrate the usage of the PCM highway interface to adapt to common
PCM standards.
Figure 29. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)
Figure 30. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0)
01 765432 16151413121110981817
MSB LSB
MSB LSB
HI-Z HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
01 765432 16151413121110981817
MSB LSB
MSB LSB
HI-Z HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
Si3210/Si3211
Rev. 1.61 57
Figure 31. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10)
Figure 32. GCI Example, Timeslot 1 (TXS/RXS = 0)
2.13. Companding
The ProSLIC supports both µ-255 Law and A-Law companding formats in addition to linear data. These 8-bit
companding schemes follow a segmented curve formatted as sign bit, three chord bits, and four step bits. µ-255
Law is more commonly used in North America and Japan, while A-Law is primarily used in Europe. Data format is
selected via the PCMF register. Tables 34 and 35 define the µ-Law and A-La w encod in g fo rm ats.
01 765432 16151413121110981817
MSB LSB
MSB LSB
HI-Z HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
01 765432 16151413121110981817
MSB LSB
HI-Z HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
Si3210/Si3211
58 Rev. 1.61
Table 34. µ-Law Encode-Decode Characteristics1,2
Segment
Number #Intervals X Interval Size Value at Segment Endpoints Digital Code Decode Level
8 16 X 256
8159
.
.
.
4319
4063
10000000b
10001111b
8031
4191
7 16 X 128
.
.
.
2143
2015 10011111b 2079
616 X 64
.
.
.
1055
991 10101111b 1023
516 X 32
.
.
.
511
479 10111111b 495
416 X 16
.
.
.
239
223 11001111b 231
316 X 8
.
.
.
103
95 11011111b 99
216 X 4
.
.
.
35
31 11101111b 33
1
15 X 2
__________________
1 X 1
.
.
.
3
1
011111110b
11111111b 2
0
Notes:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes inversion of all magnitude bits.
Si3210/Si3211
Rev. 1.61 59
Table 35. A-Law Encode-Decode Characteristics1,2
Segment
Number #intervals X interval size Value at segment endpoints Digital Code Decode Level
716 X 128
4096
3968
.
.
2176
2048
10101010b
10100101b
4032
2112
616 X 64
.
.
.
1088
1024 10110101b 1056
516 X 32
.
.
.
544
512 10000101b 528
416 X 16
.
.
.
272
256 10010101b 264
3 16 X 8
.
.
.
136
128 11100101b 132
2 16 X 4
.
.
.
68
64 11110101b 66
1
32 X 2 .
.
.
2
0 11010101b 1
Notes:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values.
2. Digital code includes inversion of all even numbered bits.
Si3210/Si3211
60 Rev. 1.61
3. Control Registers
Note: Any register not listed here is reserved and must not be written.
Table 36. Direct Register Summary
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Setup
0 SPI Mode Select SPIDC SPIM PNI[1:0] RNI[3:0]
1 PCM Mode Select PNI2 PCME PCMF[1:0] PCMT GCI TRI
2 PCM Transmit Start
Count—Low Byte TXS[7:0]
3 PCM Transmit Start
Count—High Byte TXS[9:8]
4 PCM Receive Start
Count—Low Byte RXS[7:0]
5 PCM Receive Start
Count—High Byte RXS[9:8]
6 Digital Input/Output
Control DOUT1DIO21DIO11PD21PD11
Audio
8 Audio Path Loopback
Control ALM2 DLM ALM1
9 Audio Gain Control RXHP TXHP TXM RXM ATX[1:0] ARX[1:0]
10 Two-Wire Impedance
Synthesis Control CLC[1:0] TISE TISS[2:0]
11 Hybrid Control HYBP[2:0] HYBA[2:0]
Powerdown
14 Powerdown Control 1 PMON DCOF2MOF BIASOF SLICOF
15 Powerdown Control 2 ADCM ADCON DACM DACON GMM GMON
Interrupts
18 Interrupt Status 1 PMIP PMAP RGIP RGAP O2IP O2 A P O1IP O1AP
19 Interrupt Status 2 Q6AP Q5AP Q4AP Q3AP Q2AP Q1AP LCIP RTIP
20 Interrupt Status 3 CMCP I NDP DTMFP
21 Interrupt Enable 1 PMIE PMAE RGIE RGAE O2IE O2AE O1IE O1AE
22 Interrupt Enable 2 Q6AE Q5AE Q4AE Q3AE Q2AE Q1AE LCIE RTIE
23 Interrupt Enable 3 CMCE INDE DTMFE
24 Decode Status VAL DIG[3:0]
Indirect Register Access
Notes:
1. Si3211 only.
2. Si3210 only.
Si3210/Si3211
Rev. 1.61 61
28 Indirect Data Access—
Low Byte IDA[7:0]
29 Indirect Data Access—
High Byte IDA[15:8]
30 Indirect Address IAA[7:0]
31 Indirect Address Status IAS
Oscillators
32 Oscillator 1 Control OSS1 REL OZ1 O1TAE O1TIE O1E O1SO[1:0]
33 Oscillator 2 Control OSS2 OZ2 O2TAE O2TIE O2E O2SO[1:0]
34 Ringing Oscillator
Control RSS RDAC RTAE RTIE ROE RVO TSWS
35 Pulse Metering
Oscillator Control PSTAT PMAE PMIE PMOE
36 Oscillator 1 Active
Timer—Low Byte OAT1[7:0]
37 Oscillator 1 Active
Timer—High Byte OAT1[15:8]
38 Oscillator 1 Inactive
Timer—Low Byte OIT1[7:0]
39 Oscillator 1 Inactive
Timer—High Byte OIT1[15:8]
40 Oscillator 2 Active
Timer—Low Byte OAT2[7:0]
41 Oscillator 2 Active
Timer—High Byte OAT2[15:8]
42 Oscillator 2 Inactive
Timer—Low Byte OIT2[7:0]
43 Oscillator 2 Inactive
Timer—High Byte OIT2[15:8]
44 Pulse Metering
Oscillator Active Timer—
Low Byte
PAT[7:0]
45 Pulse Metering
Oscillator Active Timer—
High Byte
PAT[15:8]
46 Pulse Metering
Oscillator Inactive
Timer—Low Byte
PIT[7:0]
Table 36. Direct Register Summary (Continued)
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes:
1. Si3211 only.
2. Si3210 only.
Si3210/Si3211
62 Rev. 1.61
47 Pulse Metering
Oscillator Inactive
Timer—High Byte
PIT[15:8]
48 Ringing Oscillator
Active Timer—Low Byte RAT[7:0]
49 Ringing Oscillator
Active Timer—High Byte RAT[15:8]
50 Ringing Oscillator Inac-
tive Timer—Low Byte RIT[7:0]
51 Ringing Oscillator Inac-
tive Timer—High Byte RIT[15:8]
52 FSK Data FSKDAT
SLIC
63 Loop Closure Debounce
Interval for Automatic
Ringing
LCD[7:0]
64 Linefeed Control LFS[2:0] LF[2:0]
65 External Bipolar
Transistor Control SQH CBY ETBE ETBO[1:0] ETBA[1:0]
66 Battery Feed Control VOV2FVBAT2BATSL1TRACK2
67 Automatic/Manual
Control MNCM MNDIF SPDS ABAT AORD AOLD AOPN
68 Loop Closure/Ring Trip
Detect Status DBIRAW RTP LCR
69 Loop Closure Debounce
Interval LCDI[6:0]
70 Ring Trip Detect
Debounce Interval RTDI[6:0]
71 Loop Curr ent Limit ILIM[2:0]
72 On-Hook Line Voltage VSGN VOC[5:0]
73 Common Mode Voltage VCM[5:0]
74 High Battery Voltage VBATH[5:0]
75 Low Battery Voltage VBATL[5:0]
76 Power Monitor Pointer PWRMP[2:0]
77 Line Power Output
Monitor PWROM[7:0]
78 Loop Voltage Sense LVSP LVS[5:0]
Table 36. Direct Register Summary (Continued)
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes:
1. Si3211 only.
2. Si3210 only.
Si3210/Si3211
Rev. 1.61 63
79 Loop Current Sense LCSP LCS[5:0]
80 TIP Voltage Sense VTIP[7:0]
81 RING Voltage Sense VRING[7:0]
82 Battery Voltage Sense 1 VBATS1[7:0]
83 Battery Voltage Sense 2 VBATS2[7:0]
84 Transistor 1 Current
Sense IQ1[7:0]
85 Transistor 2 Current
Sense IQ2[7:0]
86 Transistor 3 Current
Sense IQ3[7:0]
87 Transistor 4 Current
Sense IQ4[7:0]
88 Transistor 5 Current
Sense IQ5[7:0]
89 Transistor 6 Current
Sense IQ6[7:0]
92 DC-DC Converter PWM
Period DCN[7:0]2
93 DC-DC Converter
Switching Delay DCCAL2DCPOL2DCTOF[4:0]2
94 DC-DC Converter
PWM Pulse Width DCPW[7:0]2
95 Reserved
96 Calibration Control/
Status Register 1 CAL CALSP CALR CALT CALD CALC CALIL
97 Calibration Control/
Status Register 2 CALM1 CALM2 CALDAC CALADC CALCM
98 RING Gain Mismatch
Calibration Result CALGMR[4:0]
99 TIP Gain Mismatch
Calibration Result CALGMT[4:0]
100 Differential Loop
Current Gain
Calibration Result
CALGD[4:0]
101 Common Mode Loop
Current Gain
Calibration Result
CALGC[4:0]
Table 36. Direct Register Summary (Continued)
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes:
1. Si3211 only.
2. Si3210 only.
Si3210/Si3211
64 Rev. 1.61
102 Curr en t Lim it
Calibration Result CALGIL[3:0]
103 Monitor ADC Offset
Calibration Result CALMG1[3:0] CALMG2[3:0]
104 Analog DAC/ADC Offset DACP DACN ADCP ADCN
105 DAC Offset Calibration
Result DACOF[7:0]
106 Common Mode Balance
Calibration Result CMBAL[5:0]
107 DC Peak Current
Calibration Result CMDCPK[3:0]
108 Enhancement Enable ILIMEN FSKEN DCSU2ZSEXT SWDB LCVE DCFIL2HYSTEN
Table 36. Direct Register Summary (Continued)
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes:
1. Si3211 only.
2. Si3210 only.
Si3210/Si3211
Rev. 1.61 65
Reset settings = 00xx_xxxx
Register 0. SPI Mode Select
BitD7D6D5D4D3D2D1D0
Name SPIDC SPIM PNI[1:0] RNI[3:0]
Type R/W R/W R R
Bit Name Function
7 SPIDC SPI Daisy Chain Mode Enable.
0 = Disable SPI daisy chain mode.
1 = Enable SPI daisy chain mode.
6SPIMSPI Mode.
0 = Causes SDO to tri-state on rising edge of SCLK of LSB.
1 = Normal operation; SDO tri-states on rising edge of CS.
5:4 PNI[1:0] Part Number Identification.
00 = Si3210
01 = Si3211
10 = Unused
11 = Si3210M
3:0 RNI[3:0] Revision Number Identification.
0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc.
Si3210/Si3211
66 Rev. 1.61
Reset settings = 0000_1000
Register 1. PCM Mode Select
BitD7D6D5D4D3D2D1D0
Name PNI2 PCME PCMF[1:0] PCMT GCI TRI
Type R/W R/W R/W R/W R/W
Bit Name Function
7PNI2Part Number Identification 2.
0 = Si3210/11 family.
1 = Si3215/16 family.
6 Reserved Read returns zero.
5PCMEPCM Enable.
0 = Disable PCM transfers.
1 = Enable PCM transfers.
4:3 PCMF[1:0] PCM Format.
00 = A-Law
01 = µ-Law
10 = Reserved
11 = Linear
2PCMTPCM Transfer Size.
0 = 8-bit transfer.
1 = 16-bit transfer.
1GCIGCI Clock Format.
0 = 1 PCLK pe r da ta bit.
1 = 2 PCLKs per data bit.
0TRITri-st ate Bit 0.
0 = Tri-state bit 0 on positive edge of PCLK.
1 = Tri-state bit 0 on negative edge of PCLK.
Si3210/Si3211
Rev. 1.61 67
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 2. PCM Trans mit Start Count—Low Byte
BitD7D6D5D4D3D2D1D0
Name TXS[7:0]
Type R/W
Bit Name Function
7:0 TXS[7:0] PCM Transmit Start Count.
PCM transmit st art count equals th e number of PCLKs following FSYNC before dat a trans-
mission begins. See F igu re 29 on page 56.
Register 3. PCM Transmit Start Count—High Byte
BitD7D6D5D4D3D2D1D0
Name TXS[9:8]
Type R/W
Bit Name Function
7:2 Reserved Read returns zero.
1:0 TXS[9:8] PCM Transmit Start Count.
PCM transmit start count equals the number of PCLKs following FSYNC before data
transmission begins. See Figure 29 on page 56.
Register 4. PCM Receive Start Count—Low Byte
BitD7D6D5D4D3D2D1D0
Name RXS[7:0]
Type R/W
Bit Name Function
7:0 RXS[7:0] PCM Receive Start Count.
PCM receive start count equals the number of PCLKs following FSYNC before data
reception begins. See Figure 29 on page 56.
Si3210/Si3211
68 Rev. 1.61
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 5. PCM Receive Start Count—High Byte
BitD7D6D5D4D3D2D1D0
Name RXS[9:8]
Type R/W
Bit Name Function
7:2 Reserved Read returns zero.
1:0 RXS[9:8] PCM Receive Start Count.
PCM receive start count equals the number of PCLKs following FSYNC before data
reception begins. See Figure 29 on page 56.
Register 6. Digital Input/Outp ut Contro l
Si3210
BitD7D6D5D4D3D2D1D0
Name
Type
Si3211
BitD7D6D5D4D3D2D1D0
Name DOUT DIO2 DIO1 PD2 PD1
Type R/WR/WR/WR/WR/W
Si3210/Si3211
Rev. 1.61 69
Bit Name Function
7:5 Reserved Read returns zero.
4DOUTDOUT Pin Output Data (Si3211 only).
0 = DOUT pin driven low.
1 = DOUT pin driven high.
Si3210 = Reserved.
3DIO2DIO2 Pin Input/Output Direction (Si3211 only).
0 = DIO2 pin is an input.
1 = DIO2 pin is an output and driven to value of the PD2 bit.
Si3210 = Reserved.
2DIO1DIO1 Pin Input/Output Direction (Si3211 only).
0 = DIO1 pin is an input.
1 = DIO1 pin is an output and driven to value of the PD1 bit.
Si3210 = Reserved.
1PD2DIO2 Pin Data (Si3211 only).
When DIO2 = 1:
0 = DIO2 pin driven low.
1 = DIO2 pin driven high.
Si3210 = Reserved.
When DIO2 = 0, PD2 value equals the logic input of DIO2 pin.
0PD1DIO1 Pin Data (Si3211 only).
When DIO1 = 1:
0 = DIO1 pin driven low.
1 = DIO1 pin driven high.
Si3210 = Reserved.
When DIO1 = 0, PD1 value equals the logic input of DIO1 pin.
Si3210/Si3211
70 Rev. 1.61
Reset settings = 0000_0010
Register 8. Audio Path Loopback Control
BitD7D6D5D4D3D2D1D0
Name ALM2 DLM ALM1
Type R/W R/W R/W
Bit Name Function
7:3 Reserved Read returns zero.
2ALM2Analog Loopback Mode 2. (See Figure 25 on page 50.)
0 = Full analog loopback mode disabled.
1 = Full analog loopback mode enabled.
1DLMDigital Loopback Mode. (See Figure 25 on page 50.)
0 = Digital loopback disabled.
1 = Digital loopback enabled.
0ALM1Analog Loopback Mode 1. (See Figure 25 on page 50.)
0 = Analog loopback disabled.
1 = Analog loopback enabled.
Si3210/Si3211
Rev. 1.61 71
Reset settings = 0000_0000
Register 9. Audio Gain Control
BitD7D6D5D4D3D2D1D0
Name RXHP TXHP TXM RXM ATX[1:0] ARX[1:0]
Type R/WR/WR/WR/W R/W R/W
Bit Name Function
7RXHPReceive Path High Pass Filter Disable.
0 = HPF enabled in receive path, RHPF.
1 = HPF bypassed in receive path, RHPF.
6TXHPTransmit Path High Pass Filter Disable.
0 = HPF enabled in transmit path, THPF.
1 = HPF bypassed in transmit path, THPF.
5TXMTransmit Path Mute.
Refer to position of digital mute in Figure 25 on page 50.
0 = Transmit signal passed.
1 = Transmit signal muted.
4RXMReceive Path Mute.
Refer to position of digital mute in Figure 25 on page 50.
0 = Receive signal passed.
1 = Receive signal muted.
3:2 ATX[1:0] Analog Transmit Path Gain.
00 = 0 dB
01 = –3.5 dB
10 = 3.5 dB
11 = ATX gain = 0 dB; analog tran sm it path muted.
1:0 ARX[1:0] Analog Receive Path Gain.
00 = 0 dB
01 = –3.5 dB
10 = 3.5 dB
11 = Analog receive path muted.
Si3210/Si3211
72 Rev. 1.61
Reset settings = 0000_1000
Register 10. Two-Wire Impedance Synthesis Control
BitD7D6D5D4D3D2D1D0
Name CLC[1:0] TISE TISS[2:0]
Type R/W R/W R/W
Bit Name Function
7:6 Reserved Read returns zero.
5:4 CLC[1:0] Line Capacitance Compensation.
00 = Off
01 = 4.7 nF
10 = 10 nF
11 = Reserved
3TISETwo-Wire Impedance Synthesis Enable.
0 = Two-wire impedance synthesis disabled.
1 = Two-wire impedance synthesis enabled.
2:0 TISS[2:0] Two-Wire Impedance Synthesis Selection.
000 = 600
001 = 900
010 = 600 + 2.16 µF
011 = 900 + 2.16 µF
100 = CTR21 (270 + 750 || 150 nF)
101 = Australia/New Zealand #1 (220 + 820 || 120 nF)
110 = Slovakia/Slovenia/South Africa (220 + 820 || 115 nF)
111 = New Zealand #2 (370 + 620 || 310 nF)
Si3210/Si3211
Rev. 1.61 73
Reset settings = 0011_0011
Register 11. Hybrid Control
BitD7D6D5D4D3D2D1D0
Name HYBP[2:0] HYBA[2:0]
Type R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment.
000 = 4.08 dB
001 = 2.5 dB
010 = 1.16 dB
011=0dB
100 = –1.02 dB
101 = –1.94 dB
110 = –2.77 dB
111 = Off
3 Reserved Read returns zero.
2:0 HYBA[2:0] Audio Hybrid Adjustment.
000 = 4.08 dB
001 = 2.5 dB
010 = 1.16 dB
011=0dB
100 = –1.02 dB
101 = –1.94 dB
110 = –2.77 dB
111 = Off
Si3210/Si3211
74 Rev. 1.61
Reset settings = 0001_0000
Reset settings = 0001_0000
Register 14. Pow e rdo w n Co nt ro l 1
Si3210
BitD7D6D5D4D3D2D1D0
Name PMON DCOF MOF BIASOF SLICOF
Type R/W R/W R/W R/W R/W
Si3211
BitD7D6D5D4D3D2D1D0
Name PMON MOF BIASOF SLICOF
Type R/W R/W R/W R/W
Bit Name Function
7:6 Reserved Read returns zero.
5PMONPulse Me te rin g DAC Power-On Control.
0 = Automatic power control.
1 = Override automatic control and force pulse metering DAC circuitry on.
4 DCOF DC-DC Converter Power-Off Control (Si3210 only).
0 = Automatic power control.
1 = Override automatic control and force dc-dc circuitry off.
Si3211 = Read returns 1; it cannot be written.
3MOFMonitor ADC Power-Off Control.
0 = Automatic power control.
1 = Override automatic control and force monitor ADC circui try off.
2 Reserved Read returns zero.
1 BIASOF DC Bias Power-Off Control.
0 = Automatic power control.
1 = Override automatic control and force dc bias circuitry off.
0SLICOFSLIC Power-Off Control.
0 = Automatic power control.
1 = Override automatic control and force SLIC circuitry off.
Si3210/Si3211
Rev. 1.61 75
Reset settings = 0000_0000
Register 15. Pow e rd o w n Co nt ro l 2
BitD7D6D5D4D3D2D1D0
Name ADCM ADCON DACM DACON GMM GMON
Type R/W R/W R/W R/W R/W R/W
Bit Name Function
7:6 Reserved Read return s zero.
5 ADCM Analog to Digital Converter Manual/Automatic Power Control.
0 = Automatic power control.
1 = Manual power control; ADCON controls on/off state.
4ADCONAnalog to Digital Converter On/Off Power Control.
When ADCM = 1:
0 = Analog to digital converter powered off.
1 = Analog to digital converter powered on.
ADCON has no effect when ADCM = 0.
3DACMDigital to Analog Converter Manual/Automatic Power Control.
0 = Automatic power control.
1 = Manual power control; DACON controls on/off state.
2DACONDigital to Analog Converter On/Off Power Control.
When DACM = 1:
0 = Digital to analog conve rter powered off.
1 = Digital to analog converter powered on.
DACON has no effect when DACM = 0.
1GMMTransconductance Amplifier Manual/Automatic Power Control.
0 = Automatic power control.
1 = Manual power control; GMON controls on/off state.
0GMONTransconductance Amplifier On/Off Power Control.
When GMM = 1:
0 = Analog to digital converter powered off.
1 = Analog to digital converter powered on.
GMON has no effect when GMM = 0.
Si3210/Si3211
76 Rev. 1.61
Reset settings = 0000_0000
Register 18. Inte rru p t Status 1
BitD7D6D5D4D3D2D1D0
Name PMIP PMAP RGIP RGAP O2IP O2AP O1IP O1AP
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7PMIPPulse Metering Inactive Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
6PMAPPulse Metering Active Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
5RGIPRinging Inactive Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
4RGAPRinging Active Timer In terrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
3O2IPOscillator 2 Inacti ve Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
2O2APOscillator 2 Active Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
1O1IPOscillator 1 Inacti ve Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
0O1APOscillator 1 Active Timer Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Si3210/Si3211
Rev. 1.61 77
Reset settings = 0000_0000
Register 19. In te rru p t Status 2
BitD7D6D5D4D3D2D1D0
Name Q6AP Q5AP Q4AP Q3AP Q2AP Q1AP LCIP RTIP
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7Q6APPower Alarm Q6 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
6Q5APPower Alarm Q5 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
5Q4APPower Alarm Q4 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
4Q3APPower Alarm Q3 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
3Q2APPower Alarm Q2 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
2Q1APPower Alarm Q1 Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
1LCIPLoop Closure Transition Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
0RTIPRing Trip Interrupt Pending.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Si3210/Si3211
78 Rev. 1.61
Reset settings = 0000_0000
Register 20. In te rru p t Status 3
BitD7D6D5D4D3D2D1D0
Name CMCP INDP DTMFP
Type R/W R/W R/W
Bit Name Function
7:3 Reserved Read returns zero.
2CMCPCommon Mode Calibration Er ror Interrupt.
This bit is set when off-hook/on-hook status changes dur ing the common mode balance
calibration. Writing 1 to this bit clears a pending inter rupt .
0 = No interrupt pending.
1 = Interrupt pending.
1INDPIndirect Register Access Serviced Interrupt.
This bit is set once a pending indirect register service request has been completed. Writ-
ing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
0 DTMFP DTMF Tone Detected Interrupt.
Writing 1 to this bit clears a pending interrupt.
0 = No interrupt pending.
1 = Interrupt pending.
Si3210/Si3211
Rev. 1.61 79
Reset settings = 0000_0000
Register 21. In te rrup t Ena b le 1
BitD7D6D5D4D3D2D1D0
Name PMIE PMAE RGIE RGAE O2IE O2AE O1IE O1AE
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7PMIEPulse Metering Inact ive Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
6PMAEPulse Metering Active Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
5RGIERinging Inactive Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
4RGAERinging Active Timer In terrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
3O2IEOscillator 2 Inacti ve Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
2O2AEOscillator 2 Active Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
1O1IEOscillator 1 Inacti ve Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
0O1AEOscillator 1 Active Timer Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Si3210/Si3211
80 Rev. 1.61
Reset settings = 0000_0000
Register 22. In te rrup t Ena b le 2
BitD7D6D5D4D3D2D1D0
Name Q6AE Q5AE Q4AE Q3AE Q2AE Q1AE LCIE RTIE
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7Q6AEPower Alarm Q6 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
6Q5AEPower Alarm Q5 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
5Q4AEPower Alarm Q4 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
4Q3AEPower Alarm Q3 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
3Q2AEPower Alarm Q2 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
2Q1AEPower Alarm Q1 Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
1LCIELoop Closure Transition Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
0RTIERing Trip Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Si3210/Si3211
Rev. 1.61 81
Reset settings = 0000_0000
Register 23. In te rrup t Ena b le 3
BitD7D6D5D4D3D2D1D0
Name CMCE INDE DTMFE
Type R/W R/W R/W
Bit Name Function
7:3 Reserved Read returns zero.
2CMCECommon Mode Calibration Error Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
1INDEIndirect Register Access Serviced Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
0 DTMFE DTMF Tone Detected Interrupt Enable.
0 = Interrupt masked.
1 = Interrupt enabled.
Si3210/Si3211
82 Rev. 1.61
Reset settings = 0000_0000
Register 24. DTMF Decode Status
BitD7D6D5D4D3D2D1D0
Name VAL DIG[3:0]
Type RR
Bit Name Function
7:5 Reserved Read returns zero.
4VALDTMF Valid Digit Decoded.
0 = Not currently detecting digit.
1 = Currently detecting digit.
3:0 DIG[3:0] DTMF Digit.
0001 = “1”
0010 = “2”
0011 = “3”
0100 = “4”
0101 = “5”
0110 = “6”
0111 = “7”
1000 = “8”
1001 = “9”
1010 = “0”
1011 = “*”
1100 = “#”
1101 = “A”
1110 = “B”
1111 = “C”
0000 = “D”
Si3210/Si3211
Rev. 1.61 83
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 28. Indirect Data Access—Low Byte
BitD7D6D5D4D3D2D1D0
Name IDA[7:0]
Type R/W
Bit Name Function
7:0 IDA[7:0] Indirect Data Access—Low Byte.
A write to IDA followed by a write to IAA will place the contents of IDA into an indirect
register at the location referenced by IAA at the next indirect register update (16 kHz
update rate—a write operation). Writing IAA only will load IDA with the value stored at
IAA at the next indirect memory update (a read operation).
Register 29. Indirect Data Access—High Byte
BitD7D6D5D4D3D2D1D0
Name IDA[15:8]
Type R/W
Bit Name Function
7:0 IDA[15:8] Indirect Data Access—High Byte.
A write to IDA followed by a write to IAA will place the contents of IDA into an indirect
register at the location referenced by IAA at the next indirect register update (16 kHz
update rate—a write operation). Writing IAA only will load IDA with the value stored at
IAA at the next indirect memory update (a read operation).
Si3210/Si3211
84 Rev. 1.61
Reset settings = xxxx_xxxx
Reset settings = 0000_0000
Register 30. Indirect Address
BitD7D6D5D4D3D2D1D0
Name IAA[7:0]
Type R/W
Bit Name Function
7:0 IAA[7:0] Indirect Address Access.
A write to IDA followed by a write to IAA will place the contents of IDA into an indirect
register at the location referenced by IAA at the next indirect register update (16 kHz
update rate—a write operation). Writing IAA only will load IDA with the value stored at
IAA at the next indirect memory update (a read operation).
Register 31. Indirect Address Status
BitD7D6D5D4D3D2D1D0
Name IAS
Type R
Bit Name Function
7:1 Reserved Read returns zero.
0IASIndirect Access Status.
0 = No indirect memory access pending.
1 = Indirect memory access pending.
Si3210/Si3211
Rev. 1.61 85
Reset settings = 0000_0000
Register 32. Oscillator 1 Control
BitD7D6D5D4D3D2D1D0
Name OSS1 REL OZ1 O1TAE O1TIE O1E O1SO[1:0]
Type R R/W R/W R/W R/W R/W R/W
Bit Name Function
7 OSS1 Oscillator 1 Signal Status.
0 = Output signal inactive.
1 = Output signal active.
6RELOscillator 1 Automatic Register Reload.
This bit should be set for FSK signaling.
0 = Oscillator 1 will stop signaling after inactive timer expires.
1 = Oscillator 1 will continue to read register parameters and output signals.
5OZ1Oscillator 1 Zero Cross Enable.
0 = Signal te rm ina te s after active time r ex pir es .
1 = Signal terminates at zero crossing after active timer expires.
4O1TAEOscillator 1 Activ e Timer Enable.
0=Disable timer.
1 = Enable timer.
3O1TIEOscill at or 1 In ac ti ve Timer Enable.
0=Disable timer.
1 = Enable timer.
2O1EOscillator 1 Enable.
0 = Disable oscillator.
1 = Enable oscillator.
1:0 O1SO[1:0] Oscillator 1 Signal Output Routing.
00 = Unassigned path (output no t connected).
01 = Assign to transmit path.
10 = Assign to receive path.
11 = Assign to both paths.
Si3210/Si3211
86 Rev. 1.61
Reset settings = 0000_0000
Register 33. Oscillator 2 Control
BitD7D6D5D4D3D2D1D0
Name OSS2 OZ2 O2TAE O2TIE O2E O2SO[1:0]
Type R R/W R/W R/W R/W R/W
Bit Name Function
7 OSS2 Oscillator 2 Signal Status.
0 = Output signal inactive.
1 = Output signal active.
6 Reserved Read returns zero.
5OZ2Oscillator 2 Zero Cross Enable.
0 = Signal te rm ina te s after active time r ex pir es .
1 = Signal terminates at zero crossing.
4O2TAEOscillator 2 Activ e Timer Enable.
0=Disable timer.
1 = Enable timer.
3O2TIEOscill at or 2 In ac ti ve Timer Enable.
0=Disable timer.
1 = Enable timer.
2O2EOscillator 2 Enable.
0 = Disable oscillator.
1 = Enable oscillator.
1:0 O2SO[1:0] Oscillator 2 Signal Output Routing.
00 = Unassigned path (output no t connected)
01 = Assign to transmit path.
10 = Assign to receive path.
11 = Assign to both paths.
Si3210/Si3211
Rev. 1.61 87
Reset settings = 0000_0000
Register 34. Rin g in g Osc ill at or Co nt rol
BitD7D6D5D4D3D2D1D0
Name RSS RDAC RTAE RTIE ROE RVO TSWS
Type RRR/WR/WRR/WR/W
Bit Name Function
7RSSRinging Signal Status.
0 = Ringing oscillator output signal inactive.
1 = Ringing oscillator output signal active.
6 Reserved Read returns zero.
5 RDAC Ringing Signal DAC/Linefeed Cross Indicat or.
For ringing signal start and stop, output to TIP and RING is suspended to ensure conti-
nuity with dc linefeed voltages. RDAC indicates that ringing signal is actually present at
TIP and RING.
0 = Ringing signal not present at TIP and RING.
1 = Ringing signal present at TIP and RING.
4RTAERinging Active Timer Enable.
0=Disable timer.
1 = Enable timer.
3RTIERinging Inactive Timer Enable.
0=Disable timer.
1 = Enable timer.
2ROERinging Oscillator Enable.
0 = Ringing oscillator disabled.
1 = Ringing oscillator enabled.
1RVORinging Voltage Offset.
0 = No dc offset adde d to ring in g si gn a l.
1 = DC offset added to ringing signal.
0TSWSTrapezoid/Sinusoid Waveshape Select.
0 = Sinusoid
1 = Trapezoid
Si3210/Si3211
88 Rev. 1.61
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 35. Pulse Metering Oscillator Control
BitD7D6D5D4D3D2D1D0
Name PSTAT PMAE PMIE PMOE
Type R R/W R/W R/W
Bit Name Function
7 PSTAT Pulse Metering Signal Status.
0 = Output signal inactive.
1 = Output signal active.
6:5 Reserved Read returns zero.
4PMAEPulse Metering Active Timer Enable.
0=Disable timer.
1 = Enable timer.
3PMIEPulse Metering Inact ive Timer Enable.
0=Disable timer.
1 = Enable timer.
2PMOEPulse Metering Oscillator Enable.
0 = Disable oscillator.
1 = Enable oscillator.
1:0 Reserved Read returns zero.
Register 36. Oscillator 1 Active Timer—Low Byte
BitD7D6D5D4D3D2D1D0
Name OAT1[7:0]
Type R/W
Bit Name Function
7:0 OAT1[7:0] Oscillator 1 Active Timer.
LSB = 125 µs
Si3210/Si3211
Rev. 1.61 89
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 37. Oscillator 1 Active Timer—High Byte
BitD7D6D5D4D3D2D1D0
Name OAT1[15:8]
Type R/W
Bit Name Function
7:0 OAT1[15:8] Oscillator 1 Active Timer.
Register 38. Oscillator 1 Inactive Timer—Low Byte
BitD7D6D5D4D3D2D1D0
Name OIT1[7:0]
Type R/W
Bit Name Function
7:0 OIT1[7:0] Oscillator 1 Inacti ve Timer.
LSB = 125 µs
Register 39. Oscillator 1 Inactive Timer—High Byte
BitD7D6D5D4D3D2D1D0
Name OIT1[15:8]
Type R/W
Bit Name Function
7:0 OIT1[15:8] Oscillator 1 Inactive Timer.
Si3210/Si3211
90 Rev. 1.61
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 40. Oscillator 2 Active Timer—Low Byte
BitD7D6D5D4D3D2D1D0
Name OAT2[7:0]
Type R/W
Bit Name Function
7:0 OAT2[7:0] Oscillator 2 Active Timer.
LSB = 125 µs
Register 41. Oscillator 2 Active Timer—High Byte
BitD7D6D5D4D3D2D1D0
Name OAT2[15:8]
Type R/W
Bit Name Function
7:0 OAT2[15:8] Oscillator 2 Active Timer.
Register 42. Oscillator 2 Inactive Timer—Low Byte
BitD7D6D5D4D3D2D1D0
Name OIT2[7:0]
Type R/W
Bit Name Function
7:0 OIT2[7:0] Oscillator 2 Inacti ve Timer.
LSB = 125 µs
Si3210/Si3211
Rev. 1.61 91
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 43. Oscillator 2 Inactive Timer—High Byte
BitD7D6D5D4D3D2D1D0
Name OIT2[15:8]
Type R/W
Bit Name Function
7:0 OIT2[15:8] Oscillator 2 Inactive Timer.
Register 44. Pulse Metering Oscillator Active Timer—Low Byte
BitD7D6D5D4D3D2D1D0
Name PAT[7:0]
Type R/W
Bit Name Function
7:0 PAT[7:0] Pulse Metering Active Timer.
LSB = 125 µs
Register 45. Pulse Metering Oscillator Active Timer—High Byte
BitD7D6D5D4D3D2D1D0
Name PAT[15:8]
Type R/W
Bit Name Function
7:0 PAT[15:8] Pulse Metering Active Timer.
Si3210/Si3211
92 Rev. 1.61
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 46. Pulse Metering Oscillator Inactive Timer—Low Byte
BitD7D6D5D4D3D2D1D0
Name PIT[7:0]
Type R/W
Bit Name Function
7:0 PIT[7:0] Pulse Metering Inactive Timer.
LSB = 125 µs
Register 47. Pulse Metering Oscillator Inactive Timer—High Byte
BitD7D6D5D4D3D2D1D0
Name PIT[15:8]
Type R/W
Bit Name Function
7:0 PIT[15:8] Pulse Me terin g Inact ive Timer.
Register 48. Rin g in g Osc ill at or Act iv e Timer—L ow Byt e
BitD7D6D5D4D3D2D1D0
Name RAT[7:0]
Type R/W
Bit Name Function
7:0 RAT[7:0] Ringing Active Timer.
LSB = 125 µs
Si3210/Si3211
Rev. 1.61 93
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 49. Rin g in g Osc ill at or Act iv e Timer—Hi gh Byt e
BitD7D6D5D4D3D2D1D0
Name RAT[15:8]
Type R/W
Bit Name Function
7:0 RAT[15:8] Ringing Active Timer.
Register 50. Rin g ing Os c ill at or In ac ti ve Timer—Low Byte
BitD7D6D5D4D3D2D1D0
Name RIT[7:0]
Type R/W
Bit Name Function
7:0 RIT[7:0] Ringing Inactive Timer.
LSB = 125 µs
Register 51. Rin g ing Os c ill at or In ac ti ve Timer—High Byte
BitD7D6D5D4D3D2D1D0
Name RIT[15:8]
Type R/W
Bit Name Function
7:0 RIT[15:8] Ringing Inactive Timer.
Si3210/Si3211
94 Rev. 1.61
Reset settings = 0000_0000
Reset settings = 0011_0010 (revision C); 0101_0100 (subsequent revisions)
Register 52. FSK Data
BitD7D6D5D4D3D2D1D0
Name FSKDAT
Type R/W
Bit Name Function
7:1 Reserved Read returns zero.
0 FSKDAT FSK Data.
When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this
bit serves as the buffered input for FSK generation bit stream dat a.
Register 63. Loop Closure Debounce Interval
BitD7D6D5D4D3D2D1D0
Name LCD[7:0]
Type
Bit Name Function
7:0 LCD[7:0] Loop Closure Debounce Interval for Automatic Ringing.
This register sets the loop closure debounce interval for the ringing silent period when
using automatic ringing cadences. The value may be set between 0 ms (0x00) and
159 ms (0x7F) in 1.25 ms steps.
Si3210/Si3211
Rev. 1.61 95
Reset settings = 0000_0000
Register 64. Linefe e d Con tro l
BitD7D6D5D4D3D2D1D0
Name LFS[2:0] LF[2:0]
Type RR/W
Bit Name Function
7 Reserved Read returns zero.
6:4 LFS[2:0] Linefeed Shadow.
This register reflects the actual real-time linefeed state. Automatic o perations may cause
actual linefeed state to deviate from the state defined by linefeed register (e.g., when
linefeed equals ringing state, LFS will equal on-hook transmission state during ringing
silent period and ringing state during ring burst).
000 = Open
001 = Forward ac tive
010 = Forward on-h o ok transmission
011 = T IP op e n
100 = Ringing
101 = Reverse active
110 = Reverse on-ho ok tran sm iss i on
111 = RING open
3 Reserved Read returns zero.
2:0 LF[2:0] Linefeed.
Writing to this register sets the linefeed state.
000 = Open
001 = Forward ac tive
010 = Forward on-h o ok transmission
011 = T IP op e n
100 = Ringing
101 = Reverse active
110 = Reverse on-ho ok tran sm iss i on
111 = RING open
Si3210/Si3211
96 Rev. 1.61
Reset settings = 0110_0001
Register 65. External Bipolar Transistor Control
BitD7D6D5D4D3D2D1D0
Name SQH CBY ETBE ETBO[1:0] ETBA[1:0]
Type R/W R/W R/W R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6SQHAudio Squelch.
0 = No squelch.
1 = STIPAC and SRINGAC pins squelched.
5CBYCapacitor Bypass.
0 = Capacitors CP (C1) and CM (C2) in circuit.
1 = Capacitors CP (C1) and CM (C2) bypassed.
4ETBEExternal Transistor Bias Enable.
0 = Bias disabled.
1 = Bias enabled.
3:2 ETBO[1:0] External Transistor Bias Levels—On-Hook Transmission State.
DC bias current which flows through external BJTs in the on-hook transmission state.
Increasing this value increases the compliance of the ac longitudinal balance circuit.
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = Reserved
1:0 ETBA[1:0] External Transistor Bias Levels—Active Off-Hook State.
DC bias current which flows through external BJTs in the active of f-hook state. Increasing
this value increas es the comp lia nce of the ac longitudin al bala nce ci rcu it.
00 = 4 mA
01 = 8 mA
10 = 12 mA
11 = Reserved
Si3210/Si3211
Rev. 1.61 97
Reset settings = 0000_0011
Reset settings = 0000_0110
Register 66. Bat ter y Fe e d Con tro l
Si3210
BitD7D6D5D4D3D2D1D0
Name VOV FVBAT TRACK
Type R/W R/W R/W
Si3211
BitD7D6D5D4D3D2D1D0
Name BATSL
Type R/W
Bit Name Function
7:5 Reserved Read returns zero.
4VOVOverhead Voltage Range Increase. (Si3210 only; See Figure 19 on page 39.)
This bit selects the programmable range for VOV, which is defined in indirect Register 41.
0=V
OV = 0 V to 9 V
1=V
OV = 0 V to 13.5 V
Si3211 = Reserved.
3FVBATVBAT Manual Setting (Si3210 only).
0 = Normal operation
1=V
BAT tracks VBATHregister.
Si3211 = Read returns 0; it cannot be written.
2 Reserved Si321 0 = Read retu rn s zer o.
Si3211 = Read returns one.
1BATSLBattery Feed Select (Si3211 only).
This bit selects between high and low battery supplies.
0 = Low battery selected (DCSW pin low).
1 = High battery selected (DCSW pin high).
Si3210 = Read returns zero.
0TRACKDC-DC Converter Tracking Mode (Si3210 only).
0=|V
BAT| will not decrease below VBATL.
1=V
BAT tracks VRING.
Si3211 = Reserved.
Si3210/Si3211
98 Rev. 1.61
Reset settings = 0001_1111
Register 67. Automatic/Manual Control
BitD7D6D5D4D3D2D1D0
Name MNCM MNDIF SPDS ABAT AORD AOLD AOPN
Type R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6 MNCM Common Mode Manual/Automatic Select.
0 = Automatic control.
1 = Manual control, in which TIP (forward) or RING (reverse) forces voltage to follow
VCM value.
5 MNDIF Differential Mode Manual/Automatic Select.
0 = Automatic control.
1 = Manual control (forces differential voltage to follow VOC value).
4 SPDS Speed-Up Mode Enable.
0 = Speed-up disabled.
1 = Automatic speed-up.
3ABATBattery Feed Automatic/Manual Selec t (Si3211 only).
0 = Automatic mode disabled.
1 = Automatic mode enabled (automatic switching to low battery in off-hook state).
2AORDAutomatic/Manual Ring Trip Detect.
0 = Manual mode.
1 = Enter off-hook active state automatically upon ring trip detect.
1AOLDAutomatic/Manual Loop Closure Detect.
0 = Manual mode.
1 = Enter off-hook active state automatically upon loop closure detect.
0AOPNPower Alarm Automatic/Manual Detect.
0 = Manual mode.
1 = Enter open state automatically upon power alarm.
Si3210/Si3211
Rev. 1.61 99
Reset settings = 0000_0100
Reset settings = 0000_1010
Register 68. Loop Closure/Ring Trip Detect Status
BitD7D6D5D4D3D2D1D0
Name DBIRAW RTP LCR
Type RRR
Bit Name Function
7:3 Reserved Read returns zero.
2DBIRAWRing Trip/Loop Closure Unfiltered Output.
State of this bit reflects the real-tim e ou tput of ring trip and loop closur e de te ct circuits
before debouncing.
0 = Ring trip/loop closure threshold excee ded.
1 = Ring trip/loop closure threshold not exceeded.
1RTPRing Trip Detect Indicator (Filtered Output).
0 = Ring trip detect has not occurred.
1 = Ring trip detect occurred.
0LCRLoop Closure Detect Indicator (Filtered Output).
0 = Loop closure detect has not occurred.
1 = Loop closure detect has occurred.
Register 69. Loop Closure Debounce Interval
BitD7D6D5D4D3D2D1D0
Name LCDI[6:0]
Type R/W
Bit Name Function
7 Reserved Read returns zero.
6:0 LCDI[6:0] Loop Closure Debounce Interval.
The value written to this register defines the minimum steady st ate debounce time. Value
may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default
value = 12.5 ms.
Si3210/Si3211
100 Rev. 1.61
Reset settings = 0000_1010
Reset settings = 0000_0000
Register 70. Ring Trip Detect Debounce Interval
BitD7D6D5D4D3D2D1D0
Name RTDI[6:0]
Type R/W
Bit Name Function
7 Reserved Read returns zero.
6:0 RTDI[6:0] Ring Trip Detect Debounce Interval.
The value written to this register defines the minimum steady state debounce time. The
value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default
value = 12.5 ms.
Register 71. Loop Current Limit
BitD7D6D5D4D3D2D1D0
Name ILIM[2:0]
Type R/W
Bit Name Function
7:3 Reserved Read returns zero.
2:0 ILIM[2:0] Loop Current Limit.
The value written to this register sets the constant loop current. The value may be set
between 20 mA (0x00) and 41 mA (0x07) in 3 mA steps.
Si3210/Si3211
Rev. 1.61 101
Reset settings = 0010_0000
Reset settings = 0000_0010
Register 72. On-Hook Line Voltage
BitD7D6D5D4D3D2D1D0
Name VSGN VOC[5:0]
Type R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6 VSGN On-Hook Line Voltage.
The value written to this bit sets the on-hook line voltage polarity (VTIP–VRING).
0=V
TIP–VRINGis positive
1=V
TIP–VRING is negative
5:0 VOC[5:0] On-Hook Line Voltage.
The value written to this register sets the on-hook line voltage (VTIP–VRING). Value may
be set between 0 V (0x00) and 94.5 V (0x3F) in 1.5 V steps. Default value = 48 V.
Register 73. Co mmon Mod e Vol tage
BitD7D6D5D4D3D2D1D0
Name VCM[5:0]
Type R/W
Bit Name Function
7:6 Reserved Read returns zero.
5:0 VCM[5:0] Common Mode Voltage.
The value written to this register sets VTIP for forward active and forward on-hook trans-
mission states and VRING for reverse active and reverse on-hook transmission states.
The value may be set be tw ee n 0 V (0x0 0 ) and –9 4. 5 V (0x3 F) in 1. 5 V steps. Defau lt
value = –3 V.
Si3210/Si3211
102 Rev. 1.61
Reset settings = 0011_0010
Reset settings = 0001_0000
Register 74. High Battery Voltage
BitD7D6D5D4D3D2D1D0
Name VBATH[5:0]
Type R/W
Bit Name Function
7:6 Reserved Read returns zero.
5:0 VBATH[5:0] High Battery Voltage.
The value written to this reg ister sets h igh battery volt age. VBATH must b e greater th an or
equal to VBATL. The valu e ma y be set between 0 V (0x00) and –94.5 V (0x 3F) in 1. 5 V
steps. Default value = –75 V. For Si321 1, VBATL must be set equal to the voltage supplied
at the VBATL node shown in the Si3211 typical application circuit drawings, Figure 12 on
page 22 and Figure 14 on page 26.
Register 75. Low Battery Voltage
BitD7D6D5D4D3D2D1D0
Name VBATL[5:0]
Type R/W
Bit Name Function
7:6 Reserved Read returns zero.
5:0 VBATL[5:0] Low Battery Voltage.
The value written to this register sets low battery voltage. VBATH must be greater than or
equal to VBATL. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V
steps. Default value = –24 V. For Si321 1, VBATL must be set equal to the voltage supplied
at the VBATL node shown in the Si3211 typical application circuit drawings, Figure 12 on
page 22 and Figure 14 on page 26.
Si3210/Si3211
Rev. 1.61 103
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 76. P ow e r Mo n it o r Po in te r
BitD7D6D5D4D3D2D1D0
Name PWRMP[2:0]
Type R/W
Bit Name Function
7:3 Reserved Read returns zero.
2:0 PWRMP[2:0] Power Monitor Pointer.
Selects the external transistor from which to read power output. The power of the
selected transistor is read in the PWROM register.
000 = Q1
001 = Q2
010 = Q3
011 = Q4
100 = Q5
101 = Q6
110 = Undefined
111 = Undefined
Register 77. Line Power Output Monitor
BitD7D6D5D4D3D2D1D0
Name PWROM[7:0]
Type R
Bit Name Function
7:0 PWROM[7:0] Line Power Output Monitor.
This register report s the real-time power outp ut of the transistor selected using PWRMP.
The range is 0 W (0x00) to 7.8 W (0xFF) in 30.4 mW steps for Q1, Q2, Q5, and Q6.
The range is 0 W (0x00) to 0.9 W (0xFF) in 3.62 mW steps for Q3 and Q4.
Si3210/Si3211
104 Rev. 1.61
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 78. Loop Voltage Sense
BitD7D6D5D4D3D2D1D0
Name LVSP LVS[5:0]
Type RR
Bit Name Function
7 Reserved Read returns zero.
6LVSPLoop Voltage Sense Polarity.
This register reports the polarity of the differential loop voltage (VTIP – VRING).
0 = Positive loop voltage (VTIP > VRING).
1 = Negative loop voltage (VTIP < VRING).
5:0 LVS[5:0] Loop Voltage Sense Magnitude.
This register reports the magnitude of the differential loop voltage (VTIP–VRING). The
range is 0 V to 94.5 V in 1.5 V steps.
Register 79. Loop Current Sense
BitD7D6D5D4D3D2D1D0
Name LCSP LCS[5:0]
Type RR
Bit Name Function
7 Reserved Read returns zero.
6LCSPLoop Current Sense Polarity.
This register reports the polarity of the loop current.
0 = Positive loop current (forward direction).
1 = Negative loop current (reverse direction).
5:0 LCS[5:0] Loop Current Sense Magnitude.
This register reports the magnitude of th e loop current. T he range is 0 mA to 78.75 mA in
1.25 mA steps.
Si3210/Si3211
Rev. 1.61 105
Reset settings = 0000_0000
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 80. TIP Voltage Sense
BitD7D6D5D4D3D2D1D0
Name VTIP[7:0]
Type R
Bit Name Function
7:0 VTIP[7:0] TIP Voltage Sense.
This register repo rts the rea l-time volt age at TIP with respect to grou nd. The range is 0 V
(0x00) to –95.88 V (0xFF) in .376 V steps.
Register 81. RING Voltage Sense
BitD7D6D5D4D3D2D1D0
Name VRING[7:0]
Type R
Bit Name Function
7:0 VRING[7:0] RING Voltage Sense.
This register reports the real-time voltage at RING with respect to ground. The range is
0 V (0x00) to –95.88 V (0xFF) in .376 V steps.
Register 82. Bat te r y Vo l tage Sense 1
BitD7D6D5D4D3D2D1D0
Name VBATS1[7:0]
Type R
Bit Name Function
7:0 VBATS1[7:0] Battery Voltage Sense 1.
This register is one of two registers that repor ts the real-time volta ge at VBAT with respect
to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in .376 V steps.
Si3210/Si3211
106 Rev. 1.61
Reset settings = 0000_0000
Reset settings = xxxx_xxxx
Reset settings = xxxx_xxxx
Register 83. Bat te r y Vo l tage Sense 2
BitD7D6D5D4D3D2D1D0
Name VBATS2[7:0]
Type R
Bit Name Function
7:0 VBATS2[7:0] Battery Voltage Sense 2.
This register is one of two registers that repor ts the real-time volta ge at VBAT with respect
to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in .376 V steps.
Register 84. Transistor 1 Current Sense
BitD7D6D5D4D3D2D1D0
Name IQ1[7:0]
Type R
Bit Name Function
7:0 IQ1[7:0] Tra n si st or 1 Cu rren t Sen se .
This register reports the real-time current through Q1. The range is 0 A (0x00) to
81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the
additional ETBO/A current.
Register 85. Transistor 2 Current Sense
BitD7D6D5D4D3D2D1D0
Name IQ2[7:0]
Type R
Bit Name Function
7:0 IQ2[7:0] Tra n si st or 2 Cu rren t Sen se .
This register reports the real-time current through Q2. The range is 0 A (0x00) to
81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the
additional ETBO/A current.
Si3210/Si3211
Rev. 1.61 107
Reset settings = xxxx_xxxx
Reset settings = xxxx_xxxx
Reset settings = xxxx_xxxx
Register 86. Transistor 3 Current Sense
BitD7D6D5D4D3D2D1D0
Name IQ3[7:0]
Type R
Bit Name Function
7:0 IQ3[7:0] Tra n si st or 3 Cu rren t Sen se .
This register reports the real-time current through Q3. The range is 0 A (0x00) to
9.59 mA (0xFF) in 37.6 µA steps.
Register 87. Transistor 4 Current Sense
BitD7D6D5D4D3D2D1D0
Name IQ4[7:0]
Type R
Bit Name Function
7:0 IQ4[7:0] Tra n si st or 4 Cu rren t Sen se .
This register reports the real-time current through Q4. The range is 0 A (0x00) to
9.59 mA (0xFF) in 37.6 µA steps.
Register 88. Transistor 5 Current Sense
BitD7D6D5D4D3D2D1D0
Name IQ5[7:0]
Type R
Bit Name Function
7:0 IQ5[7:0] Tra n si st or 5 Cu rren t Sen se .
This register reports the real-time current through Q5. The range is 0 A (0x00) to
80.58 mA (0xFF) in .316 mA steps.
Si3210/Si3211
108 Rev. 1.61
Reset settings = xxxx_xxxx
Reset settings = 1111_1111
Reset settings = xxxx_xxxx
Register 89. Transistor 6 Current Sense
BitD7D6D5D4D3D2D1D0
Name IQ6[7:0]
Type R
Bit Name Function
7:0 IQ6[7:0] Tra n si st or 6 Cu rren t Sen se .
This register reports the real-time current through Q6. The range is 0 A (0x00) to
80.58 mA (0xFF) in .316 mA steps.
Register 92. DC-DC Converter PWM Period
Si3210
BitD7D6D5D4D3D2D1D0
Name DCN[7] 1 DCN[5:0]
Type R/W R R/W
Si3211
BitD7D6D5D4D3D2D1D0
Name
Type
Bit Name Function
7:0 DCN[7:0] DC-DC Converter Period.
This bit sets the PWM period for the dc-dc converter. The range is 3.906 µs (0x40) to
15.564 µs (0xFF) in 61.035 ns steps.
Si3211 = Reserved.
Bit 6 is fixed to one and read-only, so there are two ranges of operation:
3.906 µs–7.751 µs, used for MOSFET transistor switching.
11.719 µs–15.564 µs, us ed for BJT transistor switching.
Si3210/Si3211
Rev. 1.61 109
Reset settings = 0001_0100 (Si3210)
Reset settings = 0011_0100 (Si3210M)
Reset settings = xxxx_xxxx
Register 93. DC-DC Converter Switching Delay
Si3210
BitD7D6D5D4D3D2D1D0
Name DCCAL DCPOL DCTOF[4:0]
Type R/W R R/W
Si3211
BitD7D6D5D4D3D2D1D0
Name
Type
Bit Name Function
7 DCCAL DC-DC Converter Peak Current Monitor Calibration S tatus (Si3210 only).
Writing a one to this bit starts the dc-dc converter peak current monitor calibration rou-
tine.
0 = Normal operation.
1 = Calib ra tio n be in g pe rf or me d .
Si3211 = Reserved.
6 Reserved Read returns zero.
5 DCPOL DC-DC Converter Feed Forward Pin (DCFF) Polarity (Si3210 only).
This read-only register bit indicates the polarity relationship of the DCFF pin to the
DCDRV pin. Two versions of the Si3210 are offered to support the two relationships.
0 = DCFF pin polarity is opposite of DCDRV pin (Si3210).
1 = DCFF pin polarity is same as DCDRV pin (Si3210M) .
Si3211 = Reserved.
4:0 DCTOF[4:0] DC-DC Converter Minimum Off Time (Si3210 only).
This register sets the min imum off time for the pulse width modulated dc-dc
converter control. TOFF =(DCTOF + 4)61.035 ns.
Si3211 = Reserved.
Si3210/Si3211
110 Rev. 1.61
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 94. DC-DC Converter PWM Pulse Width
Si3210
BitD7D6D5D4D3D2D1D0
Name DCPW[7:0]
Type R
Si3211
BitD7D6D5D4D3D2D1D0
Name
Type
Bit Name Function
7:0 DCPW[7:0] DC-DC Converter Pulse Width (Si3210 only).
Pulse width of DCDRV is given by PW = (DCPW – DCTOF – 4) 61.035 ns.
Si3211 = Reserved.
Si3210/Si3211
Rev. 1.61 111
Reset settings = 0001_1111
Register 96. Calibration Control/Status Register 1
BitD7D6D5D4D3D2D1D0
Name CAL CALSP CALR CALT CALD CALC CALIL
Type R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6CALCalibration Control/Status Bit.
Setting this bit begins calibration of the entire system.
0 = Normal operation or calibration complete.
1 = Calibration in progress.
5 CALSP Calibration Speedup.
Setting this bit shortens the time allotted for VBAT settling at the beginning of the
calibration cycle.
0 = 300 ms
1=30ms
4CALRRING Gain Mismatch Calibration.
For use with discrete solution only. When using the Si3201, consult “AN35: Si321x
User’s Quick Re ference Guide” and follow instructions for manual calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
3CALTTIP Gain Mismatch Calibration.
For use with discrete solution only. When using the Si3201, consult “AN35: Si321x
User’s Quick Re ference Guide” and follow instructions for manual calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
2CALDDifferential DAC Gain Calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
1CALCCommon Mode DAC Gain Calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
0CALILILIM Calibration.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
Si3210/Si3211
112 Rev. 1.61
Reset settings = 0001_1111
Reset settings = 0001_0000
Register 97. Calibration Control/Status Register 2
BitD7D6D5D4D3D2D1D0
Name CALM1 CALM2 CALDAC CALADC CALCM
Type R/WR/WR/WR/WR/W
Bit Name Function
7:5 Reserved Read returns zero.
4CALM1Monitor ADC Calibration 1.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
3CALM2Monitor ADC Calibration 2.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
2CALDACDAC Calibration.
Setting this bit begins calibration of the audio DAC offset.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
1 CALADC ADC Calibration.
Setting this bit begins calibration of the audio ADC offset.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
0CALCMCommon Mode Balance Calibration.
Setting this bit begins calibration of the ac longitudinal balance.
0 = Normal operation or calibration complete.
1 = Calibration enabled or in progress.
Register 98. RING Gain Mismatch Calibration Result
BitD7D6D5D4D3D2D1D0
Name CALGMR[4:0]
Type R/W
Bit Name Function
7:5 Reserved Read return s zero.
4:0 CALGMR[4:0] Gain Mismatch of IE Tracking Loop for RING Current.
Si3210/Si3211
Rev. 1.61 113
Reset settings = 0001_0000
Reset settings = 0001_0001
Reset settings = 0001_0001
Register 99. TIP Gain Mismatch Calibration Result
BitD7D6D5D4D3D2D1D0
Name CALGMT[4:0]
Type R/W
Bit Name Function
7:5 Reserved Read return s zero.
4:0 CALGMT[4:0] Gain Mismatch of IE Tracking Loop for TIP Current.
Register 100. Differential Loop Curre nt Gain Calibration Result
BitD7D6D5D4D3D2D1D0
Name CALGD[4:0]
Type R/W
Bit Name Function
7:5 Reserved Read return s zero.
4:0 CALGD[4:0] Differential DAC Gain Calibration Result.
Register 101. Common Mode Loop Current Gain Calibration Result
BitD7D6D5D4D3D2D1D0
Name CALGC[4:0]
Type R/W
Bit Name Function
7:5 Reserved Read return s zero.
4:0 CALGC[4:0] Common Mode DAC Gain Calibration Result.
Si3210/Si3211
114 Rev. 1.61
Reset settings = 0000_1000
Reset settings = 1000_1000
Reset settings = 0000_0000
Register 102. Current Limit Calibration Result
BitD7D6D5D4D3D2D1D0
Name CALGIL[3:0]
Type R/W
Bit Name Function
7:5 Reserved Read return s zero.
3:0 CALGIL[3:0] Current Limit Calibration Result.
Register 103. Monitor ADC Offset Calibration Result
BitD7D6D5D4D3D2D1D0
Name CALMG1[3:0] CALMG2[3:0]
Type R/W R/W
Bit Name Function
7:4 CALMG1[3:0] Monitor ADC Offset Calibration Result 1.
3:0 CALMG2[3:0] Monitor ADC Offset Calibration Result 2.
Register 104. Analog DAC/ADC Offset
BitD7D6D5D4D3D2D1D0
Name DACP DACN ADCP ADCN
Type R/WR/WR/WR/W
Bit Name Function
7:4 Reserved Read return s zero.
3DACPPositive Analog DAC Offset.
2DACNNegative Analog DAC Offset.
1 ADCP Positive Analog ADC Offset.
0ADCNNegative Analog ADC Offset.
Si3210/Si3211
Rev. 1.61 115
Reset settings = 0000_0000
Reset settings = 0010_0000
Reset settings = 0000_1000
Register 105. DAC Offset Calibration Result
BitD7D6D5D4D3D2D1D0
Name DACOF[7:0]
Type R/W
Bit Name Function
7:0 DACOF[7:0] DAC Offset Calibration Result.
Register 106. Common Mode Balance Calibration Result
BitD7D6D5D4D3D2D1D0
Name CMBAL[5:0]
Type
Bit Name Function
7:6 Reserved Read return s zero.
5:0 CMBAL[5:0] Common Mode Balance Calibration Result.
Register 107. DC Peak Current Monitor Calibration Result
BitD7D6D5D4D3D2D1D0
Name CMDCPK[3:0]
Type R/W
Bit Name Function
7:4 Reserved Read return s zero.
3:0 CMDCPK[3:0] DC Peak Current Monitor Calibration Result.
Si3210/Si3211
116 Rev. 1.61
Reset settings = 0000_0000
Reset settings = 0000_0000
Register 108. Enhan c eme n t En able
Note: The Enhancement Enable register and associated features are available in silicon rev isions C and later.
Si3210
BitD7D6D5D4D3D2D1D0
Name ILIMEN FSKEN DCSU ZSEXT LCVE DCFIL HYSTEN
Type R/W R/W R/W R/W R/W R/W R/W
Si3211
BitD7D6D5D4D3D2D1D0
Name ILIMEN FSKEN ZSEXT SWDB LCVE HYSTEN
Type R/W R/W R/W R/W R/W R/W
Bit Name Function
7ILIMENCurrent Limit Increase.
When enabled, this bit tempo rarily increase s the maximum dif f erential cur rent limit at the
end of a ring burst to enable a faster settling time to a dc linefeed state.
0 = The value programmed in ILIM (direct Register 71) is used.
1 = The ma xim u m differential loo p cu rr en t limit is temporarily increased to 41 mA.
6 FSKEN FSK Generation Enhancement.
When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only
when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscill ator r egisters are
used for FSK generation (indirect registers 99–104). Audio tones are generated using
this new higher frequency, and oscillator 1 active and inactive timers have a finer bit res-
olution of 41.67 µs. This provides greater resolution during FSK caller ID signal genera-
tion.
0 = Tone generator always clocked at 8 kHz; OSC1, OSC1X., and OSC1Y are always
used.
1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only
when REL = 1; otherwise clocked at 8 kHz.
5 DCSU DC-DC Converter Control Speedup (Si3210 only).
When enabled, this bit invokes a multi- thre sh old e rror control alg ori thm which a llows th e
dc-dc converter to adjust more quickly to voltage changes.
0 = Normal control algorithm used.
1 = Multi-threshold error control algorithm used.
Si3210/Si3211
Rev. 1.61 117
4 ZSEXT Impedance Internal Reference Resistor Disable.
When enabled, this bit removes the internal reference resistor used to synthesize ac
impedances for 600 + 2.1 µF and 900 + 2.16 µF so that an external resistor reference
may be used.
0 = Internal resistor used to generate 600 + 2.1 µF and 900 + 2.16 µF impedances.
1 = Internal resistor removed from circuit.
3SWDBBattery Switch Debounce (Si3 211 only).
When enabled, this bit allows debouncing of the battery switching circuit only when tran-
sitioning from VBATH to VBATL exte rn al ba tte ry supplie s (EXTBAT = 1).
0 = No debounce used.
1 = 60 ms debounce period used.
Si3210 = Reserved.
2LCVEVoltage-Based Loop Closure.
Enables loop closu re to be det er m ine d by the T IP-t o- RING voltage rather than loop cu r-
rent.
0 = Loop closure determined by loop current.
1 = Loop closure determined by TIP-to-RING voltage.
1DCFILDC-DC Converter Squelch (Si3210 only).
When enabled, this bit squelches noise in the audio band from the dc-dc converter con-
trol loop.
0 = Voice band squelch disabled.
1 = Voice band squelch enabled.
0 HYSTEN Loop Closure Hysteresis Enable.
When enabled, this bit allows hysteresis to the loop closure calculation. The upper and
lower hysteresis thresholds are defined by indirect registers 28 and 43, respectively.
0 = Loop closure hysteresis disabled.
1 = Loop closure hysteresis enabled.
Bit Name Function
Si3210/Si3211
118 Rev. 1.61
4. Indirect Registers
Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A
write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the
contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update.
A write to IAA without firs t writing to IDA is interpreted as a read request from an indirect register. In this case, the
value located at IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of
16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition, an
interrupt, IND (Register 20), can be generated upon completion of the indirect transfer.
4.1. DTMF Decoding
All values are represented in 2s-complement format.
Note: The values of all indirect registers are undefined following the reset state.
Table 37. DTMF Indirect Registers Summary
Addr.D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
0 ROW0[15:0]
1 ROW1[15:0]
2 ROW2[15:0]
3 ROW3[15:0]
4 COL[15:0]
5 FWDTW[15:0]
6 REVTW[15:0]
7 ROWREL[15:0]
8 COLREL[15:0]
9 ROW2[15:0]
10 COL2[15:0]
11 PWRMIN[15:0]
12 HOTL[15:0]
Si3210/Si3211
Rev. 1.61 119
Table 38. DTMF Indirect Registers Description
Addr. Description Reference
Page
0DTMF Row 0 Peak Magnitude Pass Ratio Threshold.
This register sets the minimum power ratio threshold for row 0 DTMF detection. If the ratio of
power in row 0 to tot al power in the row band i s greater than ROW0, a row 0 signal is detected.
A value of 0x7FF0 corresponds to a 1.0 ratio.
49
1DTMF Row 1 Peak Magnitude Pass Ratio Threshold.
This register sets the minimum power ratio threshold for row 1 DTMF detection. If the ratio of
power in row 1 to tot al power in the row band i s greater than ROW1, a row 1 signal is detected.
A value of 0x7FF0 corresponds to a 1.0 ratio.
49
2DTMF Row 2 Peak Magnitude Pass Ratio Threshold.
This register sets the minimum power ratio threshold for row 2 DTMF detection. If the ratio of
power in row 2 to tot al power in the row band i s greater than ROW2, a row 2 signal is detected.
A value of 0x7FF0 corresponds to a 1.0 ratio.
49
3DTMF Row 3 Peak Magnitude Pass Ratio Threshold.
This register sets the minimum power ratio threshold for row 3 DTMF detection. If the ratio of
power in row 3 to tot al power in the row band i s greater than ROW3, a row 3 signal is detected.
A value of 0x7FF0 corresponds to a 1.0 ratio.
49
4DTMF Column Peak Magnitude Pass Threshold.
This register sets the minimum power ratio threshold for column DTMF detection; all columns
use the same threshold. If the ratio of power in a particular column to total power in the column
band is greater than COL, a column detect for that p articular column signal is detected. A value
of 0x7FF0 corresponds to a 1.0 ratio.
49
5DTMF Forward Tw ist Threshold.
This register sets the threshold for the power ratio of row power to column power. A value of
0x7F0 corresponds to a 1.0 ratio.
49
6DTMF Reverse Twist Threshold.
This register sets the threshold for the power ratio of column power to row power. A value of
0x7F0 corresponds to a 1.0 ratio.
49
7DTMF Row Ratio Threshold.
This register sets the threshold for the power ratio of highest power row to the other rows. A
value of 0x7F0 corresponds to a 1.0 ratio.
49
8DTMF Column Ratio Threshold.
This register sets the threshold for the power ratio of highest power column to the other col-
umns. A value of 0x7F0 corresponds to a 1.0 ratio.
49
9DTMF Row Second Harmonic Threshold.
This register sets the threshold for the power ratio of peak row tone to its second harmonic. A
value of 0x7F0 corresponds to a 1.0 ratio.
49
10 DTMF Column Second Harmonic Threshold.
This register set s the threshold for the powe r ratio of peak column tone to it s second ha rmonic.
A value of 0x7F0 corresponds to a 1.0 ratio.
49
11 DTMF Power Minimum Threshold.
This register sets the threshold for the minimum total power in the DTMF calculation, under
which the calculation is ignored.
49
12 DTMF Hot Limit Threshold.
This register sets the two-step AGC in the DTMF path. 49
Si3210/Si3211
120 Rev. 1.61
4.2. Oscillators
See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing
register value s. All value s ar e re pr es en te d in 2s-co m ple m en t fo rm at .
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
and written but must be written to zeroes.
Table 39. Oscillator Indirect Registers Summary
Addr.D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
13 OSC1[15:0]
14 OSC1X[15:0]
15 OSC1Y[15:0]
16 OSC2[15:0]
17 OSC2X[15:0]
18 OSC2Y[15:0]
19 ROFF[5:0]
20 RCO[15:0]
21 RNGX[15:0]
22 RNGY[15:0]
23 PLSD[15:0]
24 PLSX[15:0]
25 PLSCO[15:0]
Si3210/Si3211
Rev. 1.61 121
Table 40. Oscillator Indirect Registers Description
Addr. Description Reference
Page
13 Oscillator 1 Frequency Coefficient.
Sets tone generator 1 frequency. 41
14 Oscillator 1 Amplitude Register.
Sets tone generator 1 signal amplitude. 41
15 Oscillator 1 Initial Phase Register.
Sets initial phase of tone generator 1 signal. 41
16 Oscillator 2 Frequency Coefficient.
Sets tone generator 2 frequency. 41
17 Oscillator 2 Amplitude Register.
Sets tone generator 2 signal amplitude. 41
18 Oscillator 2 Initial Phase Register.
Sets initial phase of tone generator 2 signal. 41
19 Ringing Oscillator DC Offset.
Sets dc offset component (VTIP–VRING) to ringing waveform. The range is 0 to 94.5 V in
1.5 V increments. 43
20 Ringing Oscillator Frequency Coeff icient.
Sets ringing generator frequency. 43
21 Ringing Oscillator Amplitude Register.
Sets ringing generator signal amplitude. 43
22 Ringing Oscillator Initial Phase Register.
Sets initial phase of ringing generator signal. 43
23 Pulse Metering Oscillator Attack/Decay Ramp Rate.
Sets pulse metering attack/decay ramp rate. 47
24 Pulse Metering Oscillator Amplitude Register.
Sets pulse metering generator signal amplitude. 47
25 Pulse Metering Oscillator Frequency Coefficient.
Sets pulse metering generator frequency. 47
Si3210/Si3211
122 Rev. 1.61
4.3. Digital Programmable Gain/Attenuation
See functional description sections of digital programmable gain/attenuation for guidelines on computing register
values. All values are represented in 2s-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
and written but must be written to zeroes.
Table 41. Digital Programmable Gain/Attenuation Indirect Registers Summary
Addr.D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
26 DACG[11:0]
27 ADCG[11:0]
Table 42. Digital Programmable Gain/Attenuation Indirect Registers Description
Addr. Description Reference
Page
26 Receive Path Digital to Analog Converter Gain/Attenuation.
This register sets gain/attenuation for the receive path. The digitized signal is effectively mul-
tiplied by DACG to achieve gain/attenuation. A value of 0x00 corresponds to –dB gain
(mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corr esponds to a gain
of 6 dB.
49
27 Transmit Path Analog to Digital Converter Gain/Attenuation.
This register sets gain/attenuation for the transmit p ath. The digitized signal is effectively
multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to –dB gain
(mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corr esponds to a gain
of 6 dB.
49
Si3210/Si3211
Rev. 1.61 123
4.4. SLIC Control
See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values
are represented in 2s-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
and written but must be written to zeroes.
Table 43. SLIC Control Indirect Registers Summary
Addr.D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
28 LCRT[5:0]
29 RPTP[5:0]
30 CML[5:0]
31 CMH[5:0]
32 PPT12[7:0]
33 PPT34[7:0]
34 PPT56[7:0]
35 NCLR[12:0]
36 NRTP[12:0]
37 NQ12[12:0]
38 NQ34[12:0]
39 NQ56[12:0]
40 VCMR[3:0]
41 VMIND[3:0]*
42
43 LCRTL[5:0]
*Note: Si3210 only.
Si3210/Si3211
124 Rev. 1.61
Table 44. SLIC Control Indirect Registers Description
Addr. Description Reference
Page
28 Loop Closure Threshold.
Loop closure detection thr eshold. This regist er defines th e upper bound s threshold if hys-
teresis is enabled (direct Register 108, bit 0). The range is 0–80 mA in 1.27 mA steps.
35
29 Ring Trip Threshold.
Ring trip detection threshold during ringing. 46
30 Common Mode Minimum Threshold for Speed-Up.
This register defines the negative common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
31 Common Mode Maximum Threshold for Speed-Up.
This register defin es the po sit ive commo n m od e voltage thre sh old. Exce ed in g th is
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
32 Power Alarm Threshold for Transistors Q1 and Q2. 33
33 Power Alarm Threshold for Transistors Q3 and Q4. 33
34 Power Alarm Threshold for Transistors Q5 and Q6. 33
35 Loop Closure Filter Coefficient. 35
36 Ring Trip Filter Coefficient. 46
37 Thermal Low Pass Filter Pole for Transistors Q1 and Q2. 33
38 Thermal Low Pass Filter Pole for Transistors Q3 and Q4. 33
39 Thermal Low Pass Filter Pole for Transistors Q5 and Q6. 33
40 Common Mode Bias Adjust During Ringing.
Recommended value of 0 decimal. 43
41 DC-DC Converter VOV Voltage (Si3210 only).
This register sets the overhead voltage, VOV, to be supplied by the dc-dc converter.
When the VOV bit = 0 (direct Register 66, bit 4), VOV should be set between 0 and 9 V
(VMIND = 0 to 6h). When the VOV bit = 1, VOV should be set between 0 and 13.5 V
(VMIND = 0 to 9h).
36
42 Reserved.
43 Loop Closure Threshold—Lower Bound.
This register defines the lower threshold for loop closure hysteresis, which is enabled in
bit 0 of direct Register 108. The range is 0–80 mA in 1.27 mA steps.
35
Si3210/Si3211
Rev. 1.61 125
4.5. FSK Control
For detailed instructions on FSK signal generation , refer to “Application Note 32: FSK Generation ” (AN32). These
registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108,
bit 6) and REL = 1 (direct Register 32, bit 6).
Table 45. FSK Control Indirect Registers Summary
Addr.D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
99 FSK0X[15:0]
100 FSK0[15:0]
101 FSK1X[15:0]
102 FSK1[15:0]
103 FSK01[15:0]
104 FSK10[15:0]
Table 46. FSK Control Indirect Registers Description
Addr. Description Reference Page
99 FSK Amplitude Coefficient for Space.
When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener-
ating a space or “0”. When the active ti mer (OAT1) expires , the value of th is reg ist er is
loaded into oscillator 1 instead of OSC1X.
43 and AN32
100 FSK Frequency Coefficient for Space.
When FSKEN = 1 and REL = 1, this register sets the frequency to be used when gener-
ating a space or “0”. When the active ti mer (OAT1) expires , the value of th is reg ist er is
loaded into oscillator 1 instead of OSC1.
43 and AN32
101 FSK Amplitude Coefficient for Mark.
When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener-
ating a mark or “1”. When the active timer (OAT1) expires, the value of this register is
loaded into oscillator 1 instead of OSC1X.
43 and AN32
102 FSK Frequency Coefficient for Mark.
When FSKEN = 1 and REL = 1, this register sets the frequency to be used when gener-
ating a mark or “1”. When the active timer (OAT1) expires, the value of this register is
loaded into oscillator 1 instead of OSC1.
43 and AN32
103 FSK Transition Parameter from 0 to 1.
When FSKEN = 1 and REL = 1, this registe r define s a ga in co rr ec tion fac tor tha t is
applied to signal amplitude when transitioning from a space (0) to a mark (1).
43 and AN32
104 FSK Transition Parameter from 1 to 0.
When FSKEN = 1 and REL = 1, this registe r define s a ga in co rr ec tion fac tor tha t is
applied to signal amplitude when transitioning from a mark (1) to a space (0).
43 and AN32
Si3210/Si3211
126 Rev. 1.61
5. Pin Descriptions: Si3210/11
QFN
Pin # TSSOP
Pin # Name Description
35 1 CS Chip Select.
Active low. When inactive, SCLK and SDI are ignored and SDO is high
impedance. When active, the serial port is operational.
36 2 INT Interrupt.
Maskable interrupt output. Open drain output for wire-ORed operation.
37 3 PCLK PCM Bus Clock.
Clock input for PC M bu s tim ing .
38 4 DRX Receive PCM Data.
Input data from PCM bus.
15 DTXTransmit PCM Data.
Output data to PCM bus.
2 6 FSYNC Frame Synch.
8 kHz frame synchronization signal for the PCM bus. May be short or long
pulse format.
3 7 RESET Reset.
Active low input. Hardware reset used to place all control registers in the
default state.
4 8 SDCH/DIO1 DC Monitor/General Purpose I/O.
DC-DC converter monitor input used to detect overcurrent situations in the
converter (Si321 0 only). General purpose I/O (Si3211 only).
TSSOP
27
28
29
30
31
34
33
32
CS
INT
PCLK
DTX
FSYNC
RESET
SDCH/DIO1
SCLK
SDI
SDITHRU
SDO
DCFF/DOUT
DCDRV/DCSW
GNDD
TEST
DRX
1
2
3
4
5
6
7
8
9
10
11
12
13 26
25
14
SDCL/DIO2
VDDA1
IREF
CAPP
ITIPN
VDDD
VDDA2
ITIPP
35
36
37
38
QGND
CAPM IRINGP
IRINGN
STIPDC
SRINGDC
STIPE
SVBAT
SRINGE
IGMP
GNDA
IGMN
SRINGAC
STIPAC
15
16
17
18
19
24
23
22
21
20
27
28
29
30
31
34 33 32
1
2
3
4
5
6
7
8
9
10
11
12 13
26
25
14
35363738
15 16 17 18 19
24
23
22
21
20
QFN
DTX
FSYNC
RESET
SDCH/DIO1
SDCL/DIO2
VDDA1
IREF
CAPP
QGND
CAPM
STIPDC
SRINGDC
STIPE
SVBAT
SRINGE
STIPAC
SRINGAC
IGMN
GNDA
IGMP
IRINGN
IRINGP
VDDA2
ITIPP
ITIPN
VDDD
GNDD
TEST
DCFF/DOUT
DCDRV/DCSW
SDITHRU
SDO
SDI
SCLK
CS
INT
PCLK
DRX
EPAD
Si3210/Si3211
Rev. 1.61 127
5 9 SDCL/DIO2 DC Monitor/General Purpose I/O.
DC-DC converter monitor input used to detect overcurrent situations in the
converter (Si321 0 only). General purpose I/O (Si3211 only).
6 10 VDDA1 Analog Supply Voltage.
Analog power supply for internal analog circuitry.
711 IREFCurrent Reference.
Connects to an external resistor used to provide a high accuracy reference
current.
8 12 CAPP SLIC Stabilization Capacitor.
Capacitor used in low pass filter to stabilize SLIC feedback loops.
9 13 QGND Component Reference Ground.
10 14 CAPM SLIC Stabilization Capacitor.
Capacitor used in low pass filter to stabilize SLIC feedback loops.
11 15 STIPDC TIP Sense.
Analog current input used to sense voltage on the TIP lead.
12 16 SRINGDC RING Sense.
Analog current input used to sense voltage on the RING lead.
13 17 STIPE TIP Emitter Sense.
Analog current input used to sense voltage on the Q6 emitter lead.
14 18 SVBAT VBAT Sense.
Analog current input used to sense voltage on dc-dc converter output voltage
lead.
15 19 SRINGE RING Emitter Sense.
Analog current input used to sense voltage on the Q5 emitter lead.
16 20 STIPAC TIP Transmit Input.
Analog ac input used to detect voltage on the TIP lead.
17 21 SRINGAC RING Transmit Input.
Analog ac input used to detect voltage on the RING lead.
18 22 IGMN Transconductance Amplifier External Resistor.
Negative connection for transconductance gain setting resistor.
19 23 GNDA Analog Ground.
Ground connectio n for internal analog circuitry.
20 24 IGMP Transconductance Amplifier External Resistor.
Positive connection for transconductance gain setting resistor.
21 25 IRINGN Negative Ring Current Control.
Analog current output driving Q3.
22 26 IRINGP Positive Ring Current Control.
Analog current output driving Q2.
QFN
Pin # TSSOP
Pin # Name Description
Si3210/Si3211
128 Rev. 1.61
23 27 VDDA2 Analog Supply Voltage.
Analog power supply for internal analog circuitry.
24 28 ITIPP Positive TIP Current Control.
Analog current output driving Q1.
25 29 ITIPN Negative TIP Current Control.
Analog current output driving Q4.
26 30 VDDD Digital Supply Voltage.
Digital power supply for internal digital circuitry.
27 31 GNDD Digital Ground.
Ground connection for internal digital circuitry.
28 32 TEST Test.
Enables test modes for Silicon Labs internal testing. This pin should always
be tied to ground for normal operation.
29 33 DCFF/DOUT DC Feed-Forward/High Current General Purpose Output.
Feed-forward drive of external bipolar transistors to improve dc-dc converter
efficiency (Si3210 only). High current output pin (Si3211 only).
30 34 DCDRV/DCSW DC Drive/Batter y Switch.
DC-DC converter control signal output which d rives external bipolar transistor
(Si3210 only). Battery switch control signal output which drives external
bipolar transistor (Si3211 only).
31 35 SDITHRU SDI Passthrough.
Cascaded SDI output signal for daisy-chain mode.
32 36 SDO Serial Port Data O ut.
Serial port control data output.
33 37 SDI Serial Port Data In.
Serial port control data input.
34 38 SCLK Serial Port Bit Clock Input.
Serial port clock input. Controls the serial data on SDO and latches the data
on SDI.
n/a n/a EPAD Exposed pad.
Must have a low thermal resistance connection to ground.
QFN
Pin # TSSOP
Pin # Name Description
Si3210/Si3211
Rev. 1.61 129
6. Pin Descriptions: Si3201
Pin # Name Input/
Output Description
1 TIP I/O TIP Output—Connect to the TIP lead of the subscriber loop.
2, 6, 9, 12 NC — No Internal Connection—Do not connect to any electrical signal.
3 RING I/O RING Output—Connect to the RING lead of the subscriber loop.
4VBAT—Operating Battery Voltage—Connect to the battery supply.
5VBATH—High Battery Voltage—This pin is inter nally co nn ec te d to VBAT.
7GND—Ground—Connect to a low impeda nce ground plane.
8VDD—Supply Voltage—Main power supply for all internal circuitry. Connect to a
3.3 V or 5 V supply. Decouple locally with a 0.1 F/6 V capacitor.
10 SRINGE O RING Emitter Sense Output—Connect to the SRINGE pin of the Si321x
pin.
11 STIPE O TIP Emitter Sense Output—Connect to the STIPE pin of the Si321x pin.
13 IRINGN I Negative RING Current Control—Connect to the IRINGN lead of the
Si321x.
14 IRINGP I Positive RING Current Drive—Connect to the IRINGP lead of the Si321x.
15 ITIPN I Negative TIP Current Control—Connect to the ITIPN lead of the Si321x.
16 ITIPP I Positive TIP Current Control—Connect to the ITIPP lead of the Si321x.
Bottom-Side
Exposed Pad —Exposed Thermal Pad—Connect to the bulk ground plane.
116
215
314
413
512
611
710
89
ITIPP
IRINGP
IRINGN
NC
STIPE
SRINGE
NC
ITIPN
TIP
NC
RING
VBATH
GND
NC
VDD
VBAT
Si3210/Si3211
130 Rev. 1.61
7. Ordering Guide
Chip Description DC-DC
Converter DTMF
Decoder DCFF Pin
Output Package Lead-Free
and
RoHS-
Compliant
Temperature
Si3210-E-FM ProSLIC DCDRV QFN-38 Yes 0 to 70 °C
Si3210-E-GM ProSLIC DCDRV QFN-38 Yes –40 to 85 °C
Si3210M-E-FM ProSLIC D CDRV QFN-38 Yes 0 to 70 °C
Si3210M-E-GM ProSLIC DCDRV QFN-38 Yes –40 to 85 °C
Si3210-FT ProSLIC DCDRV TSSOP-38 Yes 0 to 70 °C
Si3210-GT ProSLIC DCDRV TSSOP-38 Yes –40 to 85 °C
Si3210M-FT ProSLIC DCDRV TSSOP-38 Yes 0 to 70 °C
Si3210M-GT ProSLIC DCDRV TSSOP-38 Yes –40 to 85 °C
Si3211-E-FT ProSLIC n/a TSSOP-38 Yes 0 to 70 °C
Si3211-E-GT ProSLIC n/a TSSOP-38 Yes –40 to 85 °C
Si3211-E-FM ProSLIC n/a Q F N- 38 Yes 0 to 70 °C
Si3211-E-GM ProSLIC n/a QFN-38 Yes –40 to 85 °C
Si3201-FS Linefeed
Interface n/a SOIC-16 Yes 0 to 70 °C
Si3201-GS Linefeed
Interface n/a SOIC-16 Yes –40 to 85 °C
Note: Add an “R” at the end of the device to denote tape and reel; 2500 quantity per reel.
Si3210/Si3211
Rev. 1.61 131
Table 47. Evaluation Kit Ordering Guide
Item Supported
ProSLIC Description Linefeed
Interface
Si3210PPQX-EVB Si3210-QFN Eval Board, Daughter Card Discrete
Si3210PPQ1-EVB Si3210-QFN Eval Board, Daughter Card Si3201
Si3210PPTX-EVB Si3210-TSSOP Eval Board, Daughter Card Discrete
Si3210PPT1-EVB Si3210-TSSOP Eval Board, Daughter Card Si3201
Si3210MPPTX-EVB Si3210M-TSSOP Eval Board, Daughter Card Discrete
Si3210MPPT1-EVB Si3210M-TSSOP Eval Board, Daughter Card Si3201
Si3211PPTX-EVB Si3211-TSSOP Eval Board, Daughter Card Discrete
Si3210/Si3211
132 Rev. 1.61
8. Package Outlines and PCB Land Patterns
8.1. 38-Pin QFN
8.1.1. Package Outline: 38-Pin QFN
Figure 33 illustrates the package details for the Si321x. Table 48 lists the values for the dimensions shown in the
illustration.
Figure 33. 38-Pin Quad Flat No-Lead Package (QFN)
1
38
1
38
19
31
38
20
13
12
32
1
19
31
38
20
13
12
32
1
D
D/2
E
E/2
A
A1
D2
D2/2
E2
E2/2
38X b
e
aaa C A
bbb C B
2X
2X
ccc C
A
B
C
SEATING PLANE
ddd C A B
38X L
(L) L1
(b)
DETAIL "A"
DETAIL "B"
Detail B
Pin-1 Identifier
Option 2
Corner Square
Chamfered Corner
Option 1
Detail A
Si3210/Si3211
Rev. 1.61 133
Table 48. Package Diagram Dimensions1,2,3
Symbol
Millimeters
Min Nom Max
A 0.75 0.85 0.95
A1 0.00 0.01 0.05
b 0.18 0.23 0.30
D5.00 BSC.
D2 3.10 3.20 3.30
e0.50 BSC.
E7.00 BSC.
E2 5.10 5.20 5.30
L 0.35 0.45 0.55
L1 0.03 0.05 0.08
aaa — — 0.10
bbb — — 0.10
ccc — — 0.08
ddd — — 0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless
otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1982.
3. Recommended card reflow profile is per the JEDEC/IPC
J-STD-020C specification for Small Body Componen ts.
Si3210/Si3211
134 Rev. 1.61
8.1.2. PCB Land Pattern: 38-Pin QFN
Figure 34 shows the recommended land pattern for the Si3210/11 QFN-38 package. Table 49 lists the values for
the dimensions shown in the illustration.
Figure 34. QFN-38 Land Pattern Drawing
Si3210/Si3211
Rev. 1.61 135
Table 49. QFN-38 PCB Land Pattern Dimensions
Dimension Feature Min. Max.
C1 Pad column spacing 4.70 4.80
C2 Pad row spacing 6.70 6.80
E Pad pitch 0.50 BSC
X1 Pin pad width 0.20 0.30
X2 Thermal pad width 3.20 3.30
Y1 Pin pad width 0.80 0.90
Y2 Thermal pad length 5.20 5.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60m minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads
4. A 3x5 array of 0.90mm square openings on 1.10mm pitch should be used for the center
ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPEC J-STD-020C specification for
Small Body Components.
Si3210/Si3211
136 Rev. 1.61
8.2. 38-Pin TSSOP
8.2.1. Package Outline: 38-Pin TSSOP
Figure 35 illustrates the package details for the Si321x. Table 50 lists the values for the dimensions shown in the
illustration.
Figure 35. 38-Pin Thin Shrink Small Outline Package (TSSOP)
Table 50. Package Diagram Dimensions
Symbol Millimeters
Min Nom Max
A— —1.20
A1 0.05 — 0.15
A2 0.80 1.00 1.05
b 0.17 — 0.27
c 0.09 — 0.20
D 9.60 9.70 9.80
E6.40 BSC
E1 4.30 4.40 4.50
e0.50 BSC
L 0.45 0.60 0.75
L2 0.25 BSC
0° — 8°
aaa 0.10
bbb 0.08
ccc 0.20
Si3210/Si3211
Rev. 1.61 137
8.2.2. PCB Land Pattern: 38-Pin TSSOP
Figure 36 illustrates the recommended land pattern for the Si3210/11 TSSOP-38 package. Table 51 lists the values
for the dimensions shown in the illustration.
Figure 36. TSSOP-38 PCB Land Pattern Drawing
Table 51. PCB Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 5.80
E Pad Row Pitch 0.50
X1 Pad Width 0.30
Y1 Pad Leng th 1.45
Notes:
1. All dimensions shown are in millimeters (mm) unless
otherwise noted.
2. Dimensioning and Toleran ci ng per ASME Y14.5 M-1994.
3. This Land Pattern Design is based on IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Conditi on
(MMC). Least Material Condition (LMC) is calculated based
on a Fabirication Allo wance of 0.05mm.
5. The recommended card reflow profile is per the JEDEC/IPC
J-STD-020 specification for Small Body Components.
Si3210/Si3211
138 Rev. 1.61
8.3. 16-Pin ESOIC
8.3.1. Package Outline: 16-Pin ESOIC
Figure 37 illustrates the package details for the Si3201. Table 52 lists the values for the dimensions shown in the
illustration.
Figure 37. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package
Table 52. Package Diagram Dimensions
Symbol Millimeters
Min Max
A—1.75
A1 0.00 0.15
A2 1.25 —
b0.310.51
c0.170.25
D 9.90 BSC
D1 3.45 3.65
E 6.00 BSC
E1 3.90 BSC
E2 2.20 2.40
e 1.27 BSC
L0.401.27
L2 0.25 BSC
h0.250.50
0° 8°
aaa 0.10
bbb 0.20
ccc 0.10
ddd 0.25
Si3210/Si3211
Rev. 1.61 139
8.3.2. PCB Land Pattern: 16-Pin ESOIC
Figure 38 illustrates the recommended land pattern for the Si3201 SOIC-16 package. Table 53 lists the values for
the dimensions shown in the illustration.
Figure 38. SOIC-16 PCB Land Pattern Drawing
Table 53. SOIC-16 PCB Land Pattern Dimensions
Dimension Feature Min Max
C1 Pin pad column spacing 5.30 5.40
E Pin pad row pitch 1.27 BSC
X1 Pin pad width 0.50 0.60
Y1 Pin pad length 1.45 1.55
X2 Thermal pad width 2.20 2.30
Y2 Thermal pad length 3.50 3.60
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X175-17N.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60m minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card refl ow profile is per the JEDEC/IPC J-STD-020C specification for
Small Body Components.
Si3210/Si3211
140 Rev. 1.61
9. Product Identification
9.1. Ordering Part Number
The ordering part number indicates the device number, device variant (optional), device revision level, package
type, temperature range, and packing format, e.g., tape-and-reel, and identifies Silicon Laboratories as the
manufacturer. It will be of the following form:
See the ordering guide above for a list of valid ordering pa rt numbers.
9.2. Marking Part Number
See the Package Marking section for an example and explan ation of the markin gs on the device. Note that th e p art
number marked on the device is different from the Ordering Part Number and that the product revision level is
indicated by the first (1st) character of the Manufacturing Code.
S i 3 2 1 0 M - E - F M R
Si l icon Lab or ator ies
Par t num ber
Par t variant (if applicable)
R evi sion level (if appli cabl e
Pac kage and temperature range
Packing fo rmat, e.g., tap e- an d-reel
Si3210/Si3211
Rev. 1.61 141
10. Package Marking (Top Mark)
10.1. QFN Package
Figure 39. QFN Top Mark Diagram
Table 54. Explanation of QFN Top Mark
Line 1 Marking: Silicon Labs prefix “Si”
Device number e.g., “3210”
Device variant (optional) e.g., “M”
Separator “–”
Package/temperature range e.g., “FM’, “GM”, etc
Line 2 Marking: YY=Year
WW=Work Week Date of manufacture
TTTTTT=Mfg Code Internal manufacturing code; 1st
character=product revision level
Line 3 Marking: Circle=0.5 mm Diameter
Lower Left-Justified Pin 1 Identifier
Circle=1.3 mm Diameter
Center-Justified “e3” Pb-Free Symb ol
Country of Origin
ISO Code Abbreviation e.g., KR, TW, etc
Si3210/Si3211
142 Rev. 1.61
10.2. TSSOP Package
Figure 40. TSSOP Top Mark Diagram
Table 55. Explanation of TSSOP Top Mark
Line 1 Marking: Silicon Labs prefix “Si”
Device number e.g., “3210”
Device variant (optional) e.g., “M”
Separator “–”
Package/temperature range e.g., “FM’, “GM”, etc
Line 2 Marking: YY=Year
WW=Work Week Date of manufacture
RFAIXX=Mfg Code Internal manufacturing code; 1st
character=product revision level
Line 3 Marking: Circle=0.5 mm Diameter
Lower Left-Justified Pin 1 Identifier
Circle=1.3 mm Diameter
Center-Justified “e3” Pb-Free Symb ol
Country of Origin
ISO Code Abbreviation e.g., KR, TW, etc
Si3210/Si3211
Rev. 1.61 143
10.3. SOIC (Si3201) Package
Figure 41. SOIC Top Mark Diagram
Table 56. Explanation of SOIC Top Mark
Line 1 Marking:
Silicon Labs prefix “Si”
Device number e.g., “3201”
Separator “–”
Package/temperature
range e.g., “GS”
Line 2 Marking:
Circle=0.5 mm Diameter
Center-Justified Pi n 1 Identifier
Circle=1.3 mm Diameter
Lower Left-Justified “e3” Pb-Free Symbol
YY=Year
WW=Wor k Week Date of manufacture
TTTTTT Internal manufacturing code; 1st
character=product revision level
Si3210/Si3211
144 Rev. 1.61
DOCUMENT CHANGE LIST
Revision 1.41 to Revision 1.42
16-pin ESOIC dimension A1 corrected in Table 50
on page 136.
Delay time between chip selects, tcs, changed from
220 ns to 440 ns in Table 10 on page 13.
C10 changed from 22 nF to 0.1 µF in Figure 10 on
page 18.
C18, C19 chang ed from 1.0 µF to 4. 7 µF in
Figure 12 on page 22.
Recommended value for Indirect Register 40
changed fro m 6 to 0 in Ta ble 44 on page 124.
Added QFN package option.
Revision 1.42 to Revision 1.43
Table 16, “Si3210/Si3210M External Component
Values—Discrete Solution,” on page 25.
Added TO-92 transistor suppliers to BOM.
"7. Ordering Guide" on page 130
Updated to include product revisi on designator.
“Lead-Free” changed to “Lead-Free and RoHS-
Compliant”
Figure , “,” on page 17.
Added additional decoupling components to VDDA1,
VDDA2, and VDDD.
Figure 12, “Si3211 Typical Application Circuit Using
Si3201,” on page 22.
Added additional decoupling components to VDDA1,
VDDA2, and VDDD.
Figure 13, “Si3210/Si3210M Typical Application
Circuit Using Discrete Components,” on page 24.
Added additional decoupling components to VDDA1,
VDDA2, and VDDD.
Added optional components to STIPE, SRINGE, and
SVBAT pins to improve idle channel noise.
Figure 14, “Si3211 Typical Application Circuit Using
Discrete Solution,” on page 26.
Added additional decoupling components to VDDA1,
VDDA2, and VDDD.
Added optional components to STIPE, SRINGE, and
SVBAT pins to improve idle channel noise.
Table 52, “Package Diagram Dimensions,” on
page 138
Changed A1 max dimension from 0.10 to 0.15.
Revision 1.43 to Revision 1.44
Updated Figu re 9.
Moved the schematic for the supply filtering network for
VDDA1, VDDA2, and VDDD from the bottom of the
diagram to the top.
Moved the symbol for C26 closer to the VBATH pin on
the Si3201 symbol.
Changed R26 to 10 k.
Added Note 5.
Updated Figu re 12.
Moved the schematic for the supply filtering network for
VDDA1, VDDA2, and VDDD from the bottom of the
diagram to the top.
Moved the symbol for C9 closer to the VBATH pin on the
Si3201 symbol.
Changed R26 to 10 k.
Added Note 4.
Updated Figure 13.
Moved the schematic for the supply filtering network for
VDDA1, VDDA2, and VDDD from the bottom of the
diagram to the top.
Added Note 5 and moved the symbol fo r C26 to better
illustrate its optimal position in a board layout.
Changed R26 to 10 k.
Added Note 6.
Updated Figure 14.
Moved the schematic for the supply filtering network for
VDDA1, VDDA2, and VDDD from the bottom of the
diagram to the top.
Added Note 3 and moved the symbol fo r C26 to better
illustrate its optimal position in a board layout.
Added Note 4.
Changed R26 to 10 k.
Corrected connection between D1 and the linefeed
components.
Added Note 5
Updated Table 3.
Corrected longitudinal current per pin for EBTO/
EBTA = 10 to 12 mA.
Updated Table 8.
Filled-in typical value s for IVDD and IBAT for VDDD,
VDDA =3.3V.
Updated Table 11.
Renamed "PCLK Period Jitter Toleran c e" to
"PCLK-to-FSYNC Jitter Tolerance".
Added Note 2.
Updated Table 12.
Changed current rating of L2 to 150 mA.
Added new row for R26 and changed the value to
10 k.
Added title for AN45 to description of R28 and R29.
Added column for component package type.
Added Note 1.
Updated Table 13.
Added column for component package type.
Updated Table 14.
Added column for component package type.
Updated Table 15.
Changed current rating of L2 to 150 mA.
Added new row for R26 and changed the value to
10 k.
Rearranged the rows for R8 through R32 to be in
numerical order.
Added column for component package type.
Added Note 1.
Si3210/Si3211
Rev. 1.61 145
Updated Table 16.
Changed current rating of L2 to 150 mA.
Corrected missing reference to R5.
Added new row for R26 and changed the value to 10 k.
Added title for AN45 to description of R28 an d R29.
Added column for component package type.
Added Note 1.
Updated Table 17.
Added new row for R26 and changed the value to 10 k.
Added column for component package type.
Added Note 1.
Updated Table 18.
Added column for component package type.
Updated Table 19.
Added column for component package type.
Updated Table 36.
Added mnemonic for bi t 7 of direct register 1 (PNI2).
Changed name of Register 94 to match the name in the description of Register 94.
Updated Table 47.
Removed unsupported evaluation kit part numbers.
Updated Regis ter 1.
Added mnemonic and description of bit 7 (PNI2).
Updated Regis ter 75 .
Clarified the description of VBATL for Si3211.
Updated "2.1.6. Loop Closure Transition Detection" on page 35.
Modified first and second paragraphs to indicate that a loop closure event signals a transition from on-hook to off-hook or
from off-hook to on-hook.
Updated "2.4.2. Sinuso idal Ringing" on page 44.
Modified second paragraph to indicate the minimum allowed peak TIP-to-RING ringing voltage depends on the linefeed
state; i.e. forward-active or reverse-active.
Updated "2.9. Clock Generation" on page 52.
Modified first paragraph to indicate that 768 kHz and 1.536 MHz are not valid rates for GCI mo de.
Updated "2.12. PCM Inte rf ace" on page 56.
Modified first paragraph to indicate that 768 kHz and 1.536 MHz are not valid rates for GCI mo de.
Updated "8.1.2. PCB Land Pattern: 38-Pin QFN" on page 134 with more detailed package drawing.
Updated "8.3.1. Package Outline: 16-Pin ESOIC" on page 138 with more detailed package drawing.
Revision 1.44 to Revision 1.45
Added Si3211-E-FT and Si3211-E-GT to Ordering Guide
Clarified Ordering Guide
Replaced "X" with revision letter "E" in all ordering codes requiring a revision letter
Removed Note 1 from Ordering Guide
Revision 1.45 to Revision 1.5
Front page:
Changed images to QFN-38
Minor clean-up edits
Removed erroneous reference to polarity reversal feature on front page
Updated references to “K” and “B” temperature grades to “F” and “G”, respectively, in Electrical Characteristics
tables
Clarified Gain Error specifications in “Table 5. Monitor ADC Characteristics”
Corrected description of “Register 9. Audio Gain Control”, Bit 7 (“RHDF”--> “RHPF”)
Corrected reset setting of “Register 68. Loop Closure/Ring Trip Detect Status”(0000_0000b-->0000_0100b)
Removed obsolete non-RoHS-compliant device variants from the Ordering Guide
Updated QFN package drawing and dimensions
Added “8. Package Outlines and PCB Land Patterns”
Si3210/Si3211
146 Rev. 1.61
Added “9. Product Identification”
Added “10. Package Marking (Top Mark)”
Removed erroneous e ntry in the previous Document Change L ist, Revision 1.44 to 1.45, “Add ed QFN-38 image
to front page.”
Added a note to Table 9 cross-referencing it with section 1. 2 ProSLIC Initialization in AN35.
Updated contact information.
Revision 1.5 to Revision 1.6
Updated “Power Supply Current, Analog and Digital” specification in Table 8. (Not released.)
Revision 1.6 to Revision 1.61
Updated “Power Supply Current, Analog an d Digital” specification in Table 8.
Si3210/Si3211
Rev. 1.61 147
NOTES:
Si3210/Si3211
148 Rev. 1.61
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.