FAN7393A Half-Bridge Gate Drive IC Features Description Floating Channel for Bootstrap Operation to +600V The FAN7393A is a half-bridge gate-drive IC with shutdown and programmable dead-time control functions that can drive high-speed MOSFETs and Isolated Gate Bridge Transistors (IGBTs) operating up to +600V. It has a buffered output stage with all NMOS transistors designed for high-pulse-current driving capability and minimum cross-conduction. Typically 2.5A/2.5A Sourcing/Sinking Current Driving Capability Extended Allowable Negative VS Swing to -9.8V for Signal Propagation at VBS=15V High-Side Output in Phase of IN Input Signal 3.3V and 5V Input Logic Compatible Matched Propagation Delay for Both Channels Built-in Shutdown Function Built-in UVLO Functions for Both Channels Built-in Common-Mode dv/dt Noise Cancelling Circuit Internal 400ns Minimum Dead Time at RDT=0 Programmable Turn-On Delay Control Fairchild's high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level-shift circuit offers high-side gate driver operation up to VS=-9.8V (typical) for VBS=15V. (Dead-Time) The UVLO circuit prevents malfunction when VDD and VBS are lower than the specified threshold voltage. Applications The high-current and low-output voltage drop feature makes this device suitable for diverse half- and fullbridge inverters; motor drive inverters, switching mode power supplies, induction heating, and high-power DCDC converter applications. High-Speed Power MOSFET and IGBT Gate Driver Induction Heating High-Power DC-DC Converter 14-SOP Synchronous Step-Down Converter Motor Drive Inverter Ordering Information Part Number Package Operating Temperature Packing Method FAN7393AMX 14-SOIC -40C to +125C Tape & Reel (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 www.fairchildsemi.com FAN7393A -- Half-Bridge Gate Drive IC July 2012 FAN7393A -- Half-Bridge Gate Drive IC Typical Application Diagrams Up to 600V +15V RBOOT DBOOT FAN7393A PWM IC Control PWM 1 IN NC 14 Shutdown 2 SD VB 13 3 VSS HO 12 4 DT VS 11 RDT R1 CBOOT 5 COM NC 10 6 LO NC 9 7 VDD NC 8 Load R2 Figure 1. Typical Application Circuit Internal Block Diagram 13 VB UVLO 250K NOISE CANCELLER R DRIVER HS(ON/OFF) 1 PULSE GENERATOR IN R S Q 11 VS SCHMITT TRIGGER INPUT 5V 12 HO 250K SD 2 7 VDD SHOOT-THROUGH PREVENTION UVLO 4 VSS 3 DEAD-TIME { DTMIN=400ns } LS(ON/OFF) VSS/COM LEVEL SHIFT DELAY DRIVER RDTINT DT 6 LO 5 COM Pin 8, 9, 10 and 14 are no connection Figure 2. Functional Block Diagram (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 www.fairchildsemi.com 2 FAN7393A -- Half-Bridge Gate Drive IC Pin Configuration 1 14 NC SD 2 13 VB VSS 3 12 HO DT 4 11 VS COM 5 10 NC LO 6 9 NC VDD 7 8 NC FAN7393A IN Figure 3. Pin Configurations (Top View) Pin Definitions Pin # Name Description 1 IN Logic Input for High-Side and Low-Side Gate Driver Output, In-Phase with HO 2 SD Logic Input for Shutdown 3 VSS Logic Ground 4 DT Dead-Time Control with External Resistor (Referenced to VSS) 5 COM 6 LO Low-Side Driver Return 7 VDD Supply Voltage 8 NC No Connection 9 NC No Connection 10 NC No Connection Ground 11 VS High-Voltage Floating Supply Return 12 HO High-Side Driver Output 13 VB High-Side Floating Supply 14 NC No Connection (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25C unless otherwise specified. Symbol Characteristics Min. Max. Unit VB High-Side Floating Supply Voltage -0.3 625.0 V VS High-Side Floating Offset Voltage(1) VB-VSHUNT VB+0.3 V VS-0.3 VB+0.3 V VDD+0.3 V VHO High-Side Floating Output Voltage VLO Low-Side Output Voltage -0.3 VDD Low-Side and Logic Fixed Supply Voltage -0.3 25.0 V VIN Logic Input Voltage (IN) -0.3 VDD+0.3 V VSD Logic Input Voltage (SD) VSS 5.5 V DT Programmable Dead-Time Pin Voltage -0.3 VDD+0.3 V VSS Logic Ground VDD-25 VDD+0.3 V 50 V/ns 1 W 110 C/W +150 C +150 C dVS/dt Allowable Offset Voltage Slew Rate PD Power Dissipation(2, 3, 4) JA Thermal Resistance TJ Junction Temperature TSTG Storage Temperature -55 Notes: 1. This IC contains a shunt regulator on VBS. This supply pin should not be driven by a low-impedance voltage source greater than VSHUNT specified in the Electrical Characteristics section. 2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). 3. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection, and JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages. 4. Do not exceed maximum PD under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Unit VB High-Side Floating Supply Voltage VS+10 VS+20 V VS High-Side Floating Supply Offset Voltage 6-VDD 600 V VS VB V VHO High-Side Output Voltage VDD Low-Side and Logic Fixed Supply Voltage 10 20 V VLO Low-Side Output Voltage COM VDD V VIN Logic Input Voltage (IN) VSS VDD V VSD Logic Input Voltage (SD) VSS 5 V DT Programmable Dead-Time Pin Voltage VSS VDD V VSS Logic Ground -5 +5 V Operating Ambient Temperature -40 +125 C TA (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 www.fairchildsemi.com 4 FAN7393A -- Half-Bridge Gate Drive IC Absolute Maximum Ratings VBIAS(VDD, VBS)=15.0V, VSS=COM=0V, DT=VSS, and TA=25C unless otherwise specified. The VIN and IIN parameters are referenced to VSS/COM and are applicable to the respective input leads: IN and SD. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol Characteristics Test Condition Min. Typ. Max. Unit POWER SUPPLY SECTION IQDD Quiescent VDD Supply Current VIN=0V or 5V 600 1000 A IQBS Quiescent VBS Supply Current VIN=0V or 5V 55 100 A IPDD Operating VDD Supply Current fIN=20KHz, No Load 1.0 1.6 mA IPBS Operating VBS Supply Current CL=1nF, fIN=20KHz, RMS 450 800 A ISD Shutdown Mode Supply Current SD=VSS 650 1000 A ILK Offset Supply Leakage Current VB=VS=600V 10 A BOOTSTRAPPED SUPPLY SECTION VDDUV+ VBSUV+ VDD and VBS Supply Under-Voltage Positive-Going Threshold Voltage VIN=0V, VDD=VBS=Sweep 7.8 8.8 9.8 V VDDUVVBSUV- VDD and VBS Supply Under-Voltage Negative-Going Threshold Voltage VIN=0V, VDD=VBS=Sweep 7.3 8.3 9.3 V VDD and VBS Supply Under-Voltage Lockout Hysteresis Voltage VIN=0V, VDD=VBS=Sweep VDDUVHVBSUVH 0.5 V SHUNT REGULATOR SECTION VSHUNT VBS=Sweep, ISHUNT=5mA Shunt Regulator Clamping Voltage for VBS 21 23 25 V INPUT LOGIC SECTION VIH Logic "1" Input Voltage for HO & Logic "0" for LO VIL Logic "0" Input Voltage for HO & Logic "1" for LO IIN+ Logic Input High Bias Current VIN=5V, SD=0V IIN- Logic Input Low Bias Current VIN=0V, SD=5V RIN Logic Input Pull-Down Resistance VSDCLAMP Shutdown (SD) Input Clamping V 20 100 Voltage(5) Shutdown (SD) Input Positive-Going Threshold SD- Shutdown (SD) Input Negative-Going Threshold 0.8 V 50 A 3 A 250 5.0 SD+ RPSD 2.5 K 5.5 2.5 V 0.8 Shutdown (SD) Input Pull-Up Resistance 100 V 250 V K GATE DRIVER OUTPUT SECTION VOH High-Level Output Voltage (VBIAS - VO) No Load (IO=0A) 1.5 V VOL Low-Level Output Voltage No Load (IO=0A) 100 mV IO+ Output High, Short-Circuit Pulsed Current(5) VHO=0V, VIN=5V, PW 10s 2.0 2.5 A IO- Output Low, Short-Circuit Pulsed Current(5) VHO=15V, VIN=0V, PW 10s 2.0 2.5 A VSS/COM VSS-COM/COM-VSS Voltage Endurability(5) VS -5.0 Allowable Negative VS Pin Voltage for IN Signal Propagation to HO -9.8 5.0 V -7.0 V Note: 5 These parameters are guaranteed by design. (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 www.fairchildsemi.com 5 FAN7393A -- Half-Bridge Gate Drive IC Electrical Characteristics VBIAS(VDD, VBS)=15.0V, VSS=COM=0V, CL=1000pF, DT=VSS, and TA=25C, unless otherwise specified. Symbol Parameter Conditions (6) Min. Typ. Max. Unit tON Turn-On Propagation Delay VS=0V, RDT=0 530 730 ns tOFF Turn-Off Propagation Delay VS=0V 130 250 ns tSD Shutdown Propagation Delay 140 210 ns MtON Delay Matching, HO and LO Turn-On 0 90 ns MtOFF Delay Matching, HO and LO Turn-Off 0 40 ns tR Turn-On Rise Time VS=0V 25 50 ns tF Turn-Off Fall Time VS=0V 15 35 ns DT Dead Time: LO Turn-Off to HO Turn-On, HO Turn-Off to LO Turn-On RDT=0 300 400 500 ns 4 5 6 s MDT Dead-Time Matching=|DTLO-HO - DTHO-LO| RDT=200K RDT=0 0 40 ns RDT=200K 0 500 ns Note: 6 The turn-on propagation delay includes dead time. (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 www.fairchildsemi.com 6 FAN7393A -- Half-Bridge Gate Drive IC Dynamic Electrical Characteristics 750 250 High-Side Low-Side 700 200 600 tOFF [ns] tON [ns] 650 550 500 150 450 100 High-Side Low-Side 400 350 -40 -20 0 20 40 60 80 100 50 -40 120 -20 0 Temperature [C] 20 40 60 80 100 120 Temperature [C] Figure 4. Turn-On Propagation Delay vs. Temperature Figure 5. Turn-Off Propagation Delay vs. Temperature 35 50 High-Side Low-Side High-Side Low-Side 30 40 tF [ns] tR [ns] 25 30 20 15 20 10 10 0 -40 5 -20 0 20 40 60 80 100 0 -40 120 -20 0 Figure 6. Turn-On Rise Time vs. Temperature 40 60 80 100 120 Figure 7. Turn-Off Fall Time vs. Temperature 500 40 450 20 MDT [ns] DT [ns] 20 Temperature [C] Temperature [C] 400 350 0 -20 DT1 DT2 300 -40 -20 0 20 40 60 80 100 -40 -40 120 Temperature [C] 0 20 40 60 80 100 120 Temperature [C] Figure 8. Dead Time (RDT=0) vs. Temperature (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 -20 Figure 9. Dead Time Matching (RDT=0) vs. Temperature www.fairchildsemi.com 7 FAN7393A -- Half-Bridge Gate Drive IC Typical Characteristics 500 6.0 DT1 DT2 RDT=200K 250 MDT [ns] DT [s] 5.5 RDT=200K 5.0 0 -250 4.5 4.0 -40 -20 0 20 40 60 80 100 -500 -40 120 -20 0 Figure 10. Dead Time (RDT=200K) vs. Temperature 40 60 80 100 120 Figure 11. Dead-Time Matching (RDT=200K) vs. Temperature 6 100 MTON MTOFF 75 5 50 4 25 DT [s] Delay Matching [ns] 20 Temperature [C] Temperature [C] 0 -25 3 2 -50 1 -75 -100 -40 -20 0 20 40 60 80 100 0 0 120 50 100 150 200 RDT [K] Temperature [C] Figure 12. Delay Matching vs. Temperature Figure 13. Dead Time vs. RDT 1000 900 180 800 160 700 ISD [A] tSD [ns] 200 140 600 500 120 100 -40 High-Side Low-Side -20 0 20 40 60 80 100 400 300 -40 120 Temperature [C] 0 20 40 60 80 100 120 Temperature [C] Figure 14. Shutdown Propagation Delay vs. Temperature (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 -20 Figure 15. Shutdown Mode Supply Current vs. Temperature www.fairchildsemi.com 8 FAN7393A -- Half-Bridge Gate Drive IC Typical Characteristics (Continued) 100 1000 900 80 IQBS [A] IQDD [A] 800 700 600 60 40 500 20 400 300 -40 -20 0 20 40 60 80 100 0 -40 120 -20 0 1300 800 1200 700 1100 600 1000 400 800 300 0 20 40 60 80 100 200 -40 120 -20 0 Temperature [C] 9.5 9.5 VDDUV- [V] VDDUV+ [V] 10.0 9.0 8.5 8.0 8.0 20 40 60 80 100 7.5 -40 120 20 40 60 80 100 120 -20 0 20 40 60 80 100 120 Temperature [C] Temperature [C] Figure 20. VDD UVLO+ vs. Temperature (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 120 9.0 8.5 0 100 Figure 19. Operating VBS Supply Current vs. Temperature 10.0 -20 80 Temperature [C] Figure 18. Operating VDD Supply Current vs. Temperature 7.5 -40 60 500 900 -20 40 Figure 17. Quiescent VBS Supply Current vs. Temperature IPBS [V] IPDD [A] Figure 16. Quiescent VDD Supply Current vs. Temperature 700 -40 20 Temperature [C] Temperature [C] Figure 21. VDD UVLO- vs. Temperature www.fairchildsemi.com 9 FAN7393A -- Half-Bridge Gate Drive IC Typical Characteristics (Continued) 10.0 9.5 9.5 VBSUV- [V] VBSUV+ [V] 10.0 9.0 8.5 8.0 9.0 8.5 8.0 7.5 -40 -20 0 20 40 60 80 100 7.5 -40 120 -20 0 Temperature [C] Figure 22. VBS UVLO+ vs. Temperature 40 60 80 100 120 Figure 23. VBS UVLO- vs. Temperature 2.0 1.0 High-Side Low-Side High-Side Low-Side 0.8 1.5 0.6 VOL [V] VOH [V] 20 Temperature [C] 1.0 0.4 0.2 0.0 0.5 -0.2 -0.4 0.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 Temperature [C] Figure 24. High-Level Output Voltage vs. Temperature 40 60 80 100 120 Figure 25. Low-Level Output Voltage vs. Temperature 3.0 3.0 2.5 VIL [V] 2.5 VIH [V] 20 Temperature [C] 2.0 2.0 1.5 1.5 1.0 1.0 -40 -20 0 20 40 60 80 100 0.5 -40 120 Temperature [C] 0 20 40 60 80 100 120 Temperature [C] Figure 26. Logic HIGH Input Voltage vs. Temperature (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 -20 Figure 27. Logic LOW Input Voltage vs. Temperature www.fairchildsemi.com 10 FAN7393A -- Half-Bridge Gate Drive IC Typical Characteristics (Continued) -7 50 -8 -9 VS [V] IIN+ [A] 40 30 -10 20 -11 10 0 -40 -12 -20 0 20 40 60 80 100 -13 -40 120 -20 0 Temperature [C] Figure 28. Logic Input High Bias Current vs. Temperature 40 60 80 100 120 Figure 29. Allowable Negative VS Voltage vs. Temperature 250 750 High-Side Low-Side High-Side Low-Side 700 tOFF [ns] 650 tON [ns] 20 Temperature [C] 600 550 200 150 500 100 450 400 350 10 12 14 16 18 50 10 20 12 Supply Voltage [V] 14 16 18 20 Supply Voltage [V] Figure 30. Turn-On Propagation Delay vs. Supply Voltage Figure 31. Turn-Off Propagation Delay vs. Supply Voltage 35 50 High-Side Low-Side High-Side Low-Side 30 40 tF [ns] tR [ns] 25 30 20 15 20 10 10 0 10 5 12 14 16 18 0 10 20 Figure 32. Turn-On Rise Time vs. Supply Voltage (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 12 14 16 18 20 Supply Voltage [V] Supply Voltage [V] Figure 33. Turn-Off Fall Time vs. Supply Voltage www.fairchildsemi.com 11 FAN7393A -- Half-Bridge Gate Drive IC Typical Characteristics (Continued) 1000 100 900 80 IQBS [A] IQDD [A] 800 700 600 60 40 500 20 400 300 10 12 14 16 18 0 10 20 12 Supply Voltage [V] 16 18 Figure 34. Quiescent VDD Supply Current vs. Supply Voltage Figure 35. Quiescent VBS Supply Current vs. Supply Voltage 2.0 1.0 High-Side Low-Side 20 High-Side Low-Side 0.8 1.5 0.6 VOL [V] VOH [V] 14 Supply Voltage [V] 1.0 0.4 0.2 0.0 0.5 -0.2 -0.4 0.0 10 12 14 16 18 20 10 Supply Voltage [V] 14 16 18 20 Supply Voltage [V] Figure 36. High-Level Output Voltage vs. Supply Voltage (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 12 Figure 37. Low-Level Output Voltage vs. Supply Voltage www.fairchildsemi.com 12 FAN7393A -- Half-Bridge Gate Drive IC Typical Characteristics (Continued) FAN7393A -- Half-Bridge Gate Drive IC Switching Time Definitions SD 1 IN NC 14 2 SD VB 13 3 VSS HO 12 4 DT VS 11 5 COM NC 10 6 LO NC 9 7 VDD NC 8 +15V 1nF LO 10F 100nF 1nF +15V 10F 100nF Figure 38. Switching Time Test Circuit IN HO LO SD DT1 DT2 DT1 DT2 Shutdown DT2 DT1 DT1 Shutdown Figure 39. Input / Output Timing Diagram IN 50% 50% tOFF tF tON tR 90% 90% LO 10% tON 10% tR 90% 90% HO tOFF 10% tF 10% Figure 40. Switching Time Waveform Definition (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 www.fairchildsemi.com 13 FAN7393A -- Half-Bridge Gate Drive IC 50% SD tSD 90% HO or LO Figure 41. Shutdown Waveform Definition IN 50% 50% tOFF DTHO-LO 90% LO 10% DTLO-HO 90% HO tOFF 10% MDT= DTLO-HO - DTHO-LO Figure 42. Dead-Time Waveform Definition IN(LO) 50% 50% 50% 50% IN(HO) MTOFF LO MTON 10% 90% HO 90% 10% Figure 43. Delay Matching Waveform Definition (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 www.fairchildsemi.com 14 8.76 8.36 0.65 A 7.62 14 8 B 5.60 6.00 4.15 3.75 B 1.70 B #1 1.27 PIN ONE INDICATOR 7 #1 (0.27) 1.27 TOP VIEW 0.51 0.36 0.20 C B A LAND PATTERN RECOMMENDATION SEE DETAIL A 1.80 MAX 1.65 1.45 (R0.20) C 0.30 0.15 B 0.05MIN 1.27 SIDE VIEW END VIEW 0.10 MAX C NOTES: A) THIS DRAWING COMPLIES WITH JEDEC MS-012 EXCEPT AS NOTED. B) THIS DIMENSION IS OUTSIDE THE JEDEC MS-012 VALUE. C) ALL DIMENSIONS ARE IN MILLIMETERS. D) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. E) LANDPATTERN STANDARD: SOIC127P600X145-14M F) DRAWING FILE NAME AND REVISION : M14CREV1 8AE GAGE PLANE (R0.10) 0.90 0.50 0.36 SEATING PLANE DETAIL A Figure 49. 14-Lead, Small Outline Integrated Circuit (SOIC), Non-JEDEC, .150-Inch Narrow Body, 225SOP Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 www.fairchildsemi.com 15 FAN7393A -- Half-Bridge Gate Drive IC Package Dimensions FAN7393A -- Half-Bridge Gate Drive IC (c) 2012 Fairchild Semiconductor Corporation FAN7393A * Rev. 1.0.1 www.fairchildsemi.com 16