© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A — Half-Bridge Gate Drive IC
FAN7393A • Rev. 1.0.1
July 2012
FAN7393A
Half-Bridge Gate Drive IC
Features
Floating Channe l for Bootstrap Operation to +600V
Typically 2.5A/2.5A Sourcing/Sinking Current Driving
Capability
Extended Allowable Negative VS Swing to -9.8V for
Signal Propagation at VBS=15V
High-Side Output in Phase of IN Input Signal
3.3V and 5V Input Logic Compatible
Matched Propagation Delay for Both Channels
Built-in Shutdown Function
Built-in UVLO Functions for Both Channels
Built-in Common-Mode dv/dt Noise Cancelling Circuit
Internal 400ns Minimum Dead Time at RDT=0
Programmable Turn-On Delay Control
(Dead-Time)
Applications
High-Speed Power MOSFET and IGBT Gate Driver
Induction Heating
High-Power DC-DC Converter
Synchronous Step-Down Converter
Motor Drive Inverter
Description
The FAN7393A is a half-bridge gate-drive IC with shut-
down and programmable dead-time control functions
that can drive high-speed MOSFETs and Isolated Gate
Bridge Transistors (IGBTs) operating up to +600V. It has
a buffered output stage with all NMOS transistors
designed for high-pulse-current driving capability and
minimum cross-conduction.
Fairchild’s high-voltage process and common-mode
noise canceling techniques provide stable operation of
the high-side driver under high dv/dt noise circum-
stances. An advanced level-shift circuit offers high-side
gate driver operation up to VS=-9.8V (typical) for
VBS=15V.
The UVLO circuit prevents malfunction when VDD and
VBS are lower than the specified threshold voltage.
The high-current and low-output voltage drop feature
makes this device suitable for diverse half- and full-
bridge inverters; motor drive inverters, switching mode
power supplies, induction heating, and high-power DC-
DC converter applications.
Ordering Information
14-SOP
Part Number Package Operating Temperature Packing Method
FAN7393AMX 14-SOIC -40°C to +125°C Tape & Reel
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 2
FAN7393A — Half-Bridge Gate Drive IC
Typical Application Diagrams
Figure 1. Typical Application Circuit
Internal Block Diagram
Figure 2. Functional Block Diagram
+15V Up to 600V
PWM
Shutdown
PWM IC
Control
RDT
DBOOT
CBOOT
R1
RBOOT
LO
COM
VB
VS
VDD
SD
IN
DT
NC
13
NC
NC
HO
VSS
NC
12
14
11
10
9
8
2
3
1
4
7
5
6
Load
R2
FAN7393A
UVLO
DRIVER
PULSE
GENERATOR
7
5
13
11
IN
VDD
COM
VB
VS
R
R
SQ
DRIVER
HS(ON/OFF)
LS(ON/OFF)
DT
HO
LO
NOISE
CANCELLER
6
12
VSS
SD
5V
2
1
4
3
Pin 8, 9, 10 and 14 are no connection
RDTINT
250K
DELAY
UVLO
SCHMITT
TRIGGER INPUT
SHOOT-THROUGH
PREVENTION
DEAD-TIME
{ DTMIN=400ns }
VSS/COM
LEVEL
SHIFT
250K
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 3
FAN7393A — Half-Bridge Gate Drive IC
Pin Configuration
Figure 3. Pin Configurations (Top View)
Pin Definitions
Pin # Name Description
1IN Logic Input for High-Side and Low-Side Gate Driver Output, In-Phase with HO
2SD Logic Input for Shutdown
3 VSS Logic Ground
4DT Dead-Time Control with External Resistor (Referenced to VSS)
5 COM Ground
6LO Low-Side Driver Return
7 VDD Supply Voltage
8NC No Connection
9NC No Connection
10 NC No Connection
11 VSHigh-Voltage Floating Supply Return
12 HO High-Side Driver Output
13 VBHigh-Side Floating Supply
14 NC No Connection
LO NC
FAN7393A
IN
HO
DT
NC
NC
VDD
COM
VB
VS
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SD
NC
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 4
FAN7393A — Half-Bridge Gate Drive IC
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not fun ction o r be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C unless otherwise specified.
Notes:
1. This IC contains a shunt regulator on VBS. This supply pin should not be driven by a low-impedance voltage
source greater than VSHUNT specified in the Electrical Characteristics section.
2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
3. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection, and
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages.
4. Do not exceed maximum PD under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Characteristics Min. Max. Unit
VBHigh-Side Floating Supply Voltage -0.3 625.0 V
VSHigh-Side Floating Offset Voltage(1) VB-VSHUNT VB+0.3 V
VHO High-Side Floating Output Voltage VS-0.3 VB+0.3 V
VLO Low-Side Output Voltage -0.3 VDD+0.3 V
VDD Low-Side and Logic Fixed Supply Voltage -0.3 25.0 V
VIN Logic Input Voltage (IN) -0.3 VDD+0.3 V
VSD Logic Input Voltage (SD) VSS 5.5 V
DT Programmable Dead-Time Pin Voltag e -0.3 VDD+0.3 V
VSS Logic Ground VDD-25 VDD+0.3 V
dVS/dt Allowable Offset Voltage Slew Rate ± 50 V/ns
PDPower Dissipation(2, 3, 4) 1 W
JA Thermal Resistance 110 C/W
TJJunction Temperature +150 C
TSTG Storage Temperature -55 +150 C
Symbol Parameter Min. Max. Unit
VBHigh-Side Floating Supply Voltage VS+10 VS+20 V
VSHigh-Side Floating Supply Offset Voltage 6-VDD 600 V
VHO High-Side Output Voltage VSVBV
VDD Low-Side and Logic Fixed Supply Voltage 10 20 V
VLO Low-Side Output Voltage COM VDD V
VIN Logic Input Voltage (IN) VSS VDD V
VSD Logic Input Voltage (SD) VSS 5 V
DT Programmable Dead-Time Pin Voltage VSS VDD V
VSS Logic Ground -5 +5 V
TAOperating Ambien t Temperature -40 +125 C
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 5
FAN7393A — Half-Bridge Gate Drive IC
Electrical Characteristics
VBIAS(VDD, VBS)=15.0V, VSS=COM=0V, DT=VSS, and TA=25°C unless otherwise specified. The VIN and IIN
parameters are referenced to VSS/COM and are applicable to the respective input leads: IN and SD. The VO and IO
parameters are referenced to COM and are applicable to the respective output leads: HO and LO.
Note:
5 These parameters are guara nteed by design.
Symbol Characteristics Test Condition Min. Typ. Max. Unit
POWER SUPPLY SECTION
IQDD Quiescent VDD Supply Cu rrent VIN=0V or 5V 600 1000 A
IQBS Quiescent VBS Supply Current VIN=0V or 5V 55 100 A
IPDD Operating VDD Supply Current fIN=20KHz, No Load 1.0 1.6 mA
IPBS Operating VBS Supply Current CL=1nF, fIN=20KHz, RMS 450 800 A
ISD Shutdown Mode Supply Current SD=VSS 650 1000 A
ILK Offset Supply Leakage Current VB=VS=600V 10 A
BOOTSTRAPPED SUPPLY SECTION
VDDUV+
VBSUV+
VDD and VBS Supply Under-Voltage
Positive-Going Threshold Voltage VIN=0V, VDD=VBS=Sweep 7.8 8.8 9.8 V
VDDUV-
VBSUV-
VDD and VBS Supply Under-Voltage
Negative-Going Threshold Voltage VIN=0V, VDD=VBS=Sweep 7.3 8.3 9.3 V
VDDUVH-
VBSUVH
VDD and VBS Supply Under-Voltage Lockout
Hysteresis Voltage VIN=0V, VDD=VBS=Sweep 0.5 V
SHUNT REGULATOR SECTION
VSHUNT Shunt Regulator Clamping Voltage for VBS VBS=Sweep, ISHUNT=5mA 21 23 25 V
INPUT LOGIC SECTION
VIH Logic “1” Input Voltage for HO & Logic “0” for LO 2.5 V
VIL Logic “0” Input Voltage for HO & Logic “1” for LO 0.8 V
IIN+ Logic Input High Bias Current VIN=5V, SD=0V 20 50 A
IIN- Logic Input Low Bias Current VIN=0V, SD=5V 3A
RIN Logic Input Pull-Down Resistance 100 250 K
VSDCLAMP Shutdown (SD) Input Clamping Voltage(5) 5.0 5.5 V
SD+Shutdown (SD) Input Positive-Going Threshold 2.5 V
SD-Shutdown (SD) Input Negative-Going Threshold 0.8 V
RPSD Shutdown (SD) Input Pull-Up Resistance 100 250 K
GATE DRIVER OUTPUT SECTION
VOH High-Level Output Voltage (VBIAS - VO)No Load (IO=0A) 1.5 V
VOL Low-Level Output Voltage No Load (IO=0A) 100 mV
IO+ Output High, Short-Circuit Pulsed Current(5) VHO=0 V, VIN=5V,
PW 10µs 2.0 2.5 A
IO- Output Low, Short-Circuit Pulsed Current(5) VHO=15V, VIN=0V,
PW 10µs 2.0 2.5 A
VSS/COM VSS-COM/COM-VSS Voltage Endurability(5) -5.0 5.0 V
VSAllowable Negative VS Pin Voltage for IN Signal
Propagation to HO -9.8 -7.0 V
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 6
FAN7393A — Half-Bridge Gate Drive IC
Dynamic Electrical Characteristics
VBIAS(VDD, VBS)=15.0V, VSS=COM=0V, CL=1000pF, DT=VSS, and TA=25°C, unless otherwise specified.
Note:
6 The turn-on propagation delay inclu des dead time.
Symbol Parameter Conditions Min. Typ. Max. Unit
tON Turn-On Propagation Delay(6) VS=0V, RDT=0530 730 ns
tOFF Turn-Off Propagation Delay VS=0V 130 250 ns
tSD Shutdown Propagation Delay 140 210 ns
MtON Delay Matching, HO and LO Tu rn-On 090 ns
MtOFF Delay Matching, HO and LO Turn-Off 040 ns
tRTurn-On Rise Time VS=0V 25 50 ns
tFTurn-Off Fall Time VS=0V 15 35 ns
DT Dead Time: LO Turn-Off to HO Turn-On,
HO Turn-Off to LO Turn-On RDT=0300 400 500 ns
RDT=200K456µs
MDT Dead-Tim e Matching=|DTLO-HO - DTHO-LO|RDT=0040 ns
RDT=200K0500 ns
FAN7393A — Half-Bridge Gate Drive IC
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 7
Typical Characteristics
Figure 4. Turn-On Propagation Delay
vs. Temperature Figure 5. Turn-Off Propagation Delay
vs. Temperature
Figure 6. Turn-On Rise Time vs. Temperature Figure 7. Turn-Off Fall Time vs. Temperatur e
Figure 8. Dead Time (RDT=0) vs. Temperature Figure 9. Dead Time Matching (RDT=0)
vs. Temperature
-40 -20 0 20 40 60 80 100 120
350
400
450
500
550
600
650
700
750
High-Side
Low-Side
tON [ns]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
50
100
150
200
250 High-Side
Low-Side
tOFF [ns]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
0
10
20
30
40
50 High-Side
Low-Side
tR [ns]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
0
5
10
15
20
25
30
35 High-Side
Low-Side
tF [ns]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
300
350
400
450
500
DT1
DT2
DT [ns]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
-40
-20
0
20
40
MDT [ns]
Temperature [°C]
FAN7393A — Half-Bridge Gate Drive IC
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 8
Typical Characteristics (Continued)
Figure 10. Dead Time (RDT=200K) vs. Temperature Figure 11. Dead-Time Matching (RDT=200K)
vs. Temperature
Figure 12. Delay Matching vs. Temperature Figure 13. Dead Ti me vs . RDT
Figure 14. Shutdown Propagation Delay
vs. Temperature Figure 15. Shutdown Mode Supply Current
vs. Temperature
-40 -20 0 20 40 60 80 100 120
4.0
4.5
5.0
5.5
6.0
RDT=200K
DT1
DT2
DT [s]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
-500
-250
0
250
500
MDT [ns]
Temperature [°C]
RDT=200K
-40 -20 0 20 40 60 80 100 120
-100
-75
-50
-25
0
25
50
75
100 MTON
MTOFF
Delay Matching [ns]
Temperature [°C]
0 50 100 150 200
0
1
2
3
4
5
6
DT [s]
RDT [K]
-40 -20 0 20 40 60 80 100 120
100
120
140
160
180
200
High-Side
Low-Side
tSD [ns]
Temperature [°C]
-40-200 20406080100120
300
400
500
600
700
800
900
1000
ISD [A]
Temperature [°C]
FAN7393A — Half-Bridge Gate Drive IC
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 9
Typical Characteristics (Continued)
Figure 16. Quiescent VDD Supply Current
vs. Temperature Figure 17. Quiesce nt VBS Supply Current
vs. Temperature
Figure 18. Operating VDD Supply Current
vs. Temperature Figure 19. Operating V BS Supply Current
vs. Temperature
Figure 20. VDD UVLO+ vs. Temperatur e Figure 21 . VDD UVLO- vs. Temperature
-40 -20 0 20 40 60 80 100 120
0
20
40
60
80
100
IQBS [A]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
300
400
500
600
700
800
900
1000
IQDD [A]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
700
800
900
1000
1100
1200
1300
IPDD [A]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
200
300
400
500
600
700
800
IPBS [V]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
7.5
8.0
8.5
9.0
9.5
10.0
VDDUV+ [V]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
7.5
8.0
8.5
9.0
9.5
10.0
VDDUV- [V]
Temperature [°C]
FAN7393A — Half-Bridge Gate Drive IC
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 10
Typical Characteristics (Continued)
Figure 22. V BS UVLO+ vs. Temperature Figure 23. V BS UVLO- vs. Temperature
Figure 24. High-Level Output Voltage
vs. Temperature Figure 25. Low-Level Output Vol ta ge
vs. Temperature
Figure 26. Logic HIGH Input Voltage
vs. Temperature Figure 27. Logi c LOW Input Voltage
vs. Temperature
-40 -20 0 20 40 60 80 100 120
7.5
8.0
8.5
9.0
9.5
10.0
VBSUV+ [V]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
7.5
8.0
8.5
9.0
9.5
10.0
VBSUV- [V]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
0.0
0.5
1.0
1.5
2.0 High-Side
Low-Side
VOH [V]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0 High-Side
Low-Side
VOL [V]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
1.0
1.5
2.0
2.5
3.0
VIH [V]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
0.5
1.0
1.5
2.0
2.5
3.0
VIL [V]
Temperature [°C]
FAN7393A — Half-Bridge Gate Drive IC
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 11
Typical Characteristics (Continued)
Figure 28. Logic Inp ut High Bias Current
vs. Temperature Figure 29. Allowable Negative VS Voltage
vs. Temperature
Figure 30. Turn-On Propagation Delay
vs. Supply Voltage Figure 31. Turn-Off Propagation Delay
vs. Supply Voltage
Figure 32. Turn-On Rise Time vs. Supply Voltage Figure 33. Turn-Off Fall Time vs. Supply Voltage
-40 -20 0 20 40 60 80 100 120
0
10
20
30
40
50
IIN+ [A]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
-13
-12
-11
-10
-9
-8
-7
VS [V]
Temperature [°C]
10 12 14 16 18 20
350
400
450
500
550
600
650
700
750 High-Side
Low-Side
tON [ns]
Supply Voltage [V]
10 12 14 16 18 20
50
100
150
200
250 High-Side
Low-Side
Supply Voltage [V]
tOFF [ns]
10 12 14 16 18 20
0
10
20
30
40
50 High-Side
Low-Side
tR [ns]
Supply Voltage [V]
10 12 14 16 18 20
0
5
10
15
20
25
30
35 High-Side
Low-Side
tF [ns]
Supply Voltage [V]
FAN7393A — Half-Bridge Gate Drive IC
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 12
Typical Characteristics (Continued)
Figure 34. Quiescent VDD Supply Current
vs. Supply Voltage Figure 35. Quiesce nt VBS Supply Current
vs. Supply Voltage
Figure 36. High-Level Output Voltage
vs. Supply Voltage Figure 37. Low-L evel Output Voltage
vs. Supply Voltage
10 12 14 16 18 20
0
20
40
60
80
100
IQBS [A]
Supply Voltage [V]
10 12 14 16 18 20
300
400
500
600
700
800
900
1000
IQDD [A]
Supply Voltage [V]
10 12 14 16 18 20
0.0
0.5
1.0
1.5
2.0 High-Side
Low-Side
VOH [V]
Supply Voltage [V]
10 12 14 16 18 20
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0 High-Side
Low-Side
VOL [V]
Supply Voltage [V]
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 13
FAN7393A — Half-Bridge Gate Drive IC
Switching Time Definitions
Figure 38. Switching Time Test Circuit
Figure 39. Input / Output Timing Diagram
Figure 40. Switc hin g Time Waveform Definition
+15VSD
10μF100nF
1nF
1nF
+15V
100nF
LO
10μF
LO
COM
VB
VS
VDD
SD
IN
DT
NC
13
NC
NC
HO
VSS
NC
12
14
11
10
9
2
3
1
4
7
5
6
8
IN
HO
LO
10%
90%
50% 50%
90%
10%
tOFF
10%
90%
tF
tR
10%
90%
tR
tF
tOFF
tON
tON
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 14
FAN7393A — Half-Bridge Gate Drive IC
Figure 41. Shutdown Waveform Definition
Figure 42. Dead-Time Waveform Definition
Figure 43. Delay Matching Waveform Definition
90%
50%
tSD
HO or LO
SD
MDT= DTLO-HO - DTHO-LO
HO
LO
10%
90%
90%
10%
tOFF
DTLO-HO
DTHO-LO
IN 50% 50%
tOFF
50%
IN(HO)
50%
90%
90%
10% 10%
IN(LO)
MTON
MTOFF
HO
LO
50% 50%
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 15
FAN7393A — Half-Bridge Gate Drive IC
Package Dimensions
Figure 49. 14-Lead, Small Outline Integrated Circuit (SOIC), Non-JEDEC, .150-Inch Narrow Body, 225SOP
Package drawings are provided as a service to customers consider ing Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the draw ing and contact a Fairchild Semicond uctor r epresentative to ver ify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
NOTES:
A) THIS DRAWING COMPLIES WITH JEDEC MS-012
EXCEPT AS NOTED.
B) THIS DIMENSIO N IS OUTSIDE THE JEDEC MS-012 VALUE .
C) ALL DIMENSIONS ARE IN MILLIMETERS.
D) DIMENSIONS ARE EXCLUSIV E OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS.
E) LANDPATTERN STANDARD: SOIC127P600X145-14M
F) DRAWING FILE NAME AND REVIS I ON : M14CREV1
7.62
#1
1.27
1.80 MAX
1.65
1.45
0.05MIN
0.10 MAX C
0.30
0.15
0.51
0.36
PIN ONE
INDICATOR
6.00
8.76
8.36
7
814
4.15
3.75
1.27
LAND PATTERN RECOMMENDATION
(R0.20)
DETAIL A
SEE DETAIL A
0.90
0.50
(R0.10)
8¡Æ
TOP VIEW
SIDE VIEW END VIEW
(0.27) 0.20 CBA
C
B
A
0.36
SEATING
PLANE
GAGE
PLANE
1.70
1.27
5.60
0.65
B
B
B
#1
FAN7393A — Half-Bridge Gate Drive IC
© 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN7393A • Rev. 1.0.1 16