General Description
The MAX690 family of supervisory circuits reduces the
complexity and number of components required for
power supply monitoring and battery control functions in
microprocessor systems. These include µP reset and
backup-battery switchover, watchdog timer, CMOS RAM
write protection, and power-failure warning. The MAX690
family significantly improves system reliability and accu-
racy compared to that obtainable with separate ICs or
discrete components.
The MAX690, MAX692, and MAX694 are supplied in
8-pin packages and provide four functions:
A reset output during power-up, power-down, and
brownout conditions.
Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power logic.
A Reset pulse if the optional watchdog timer has not
been toggled within a specified time.
A 1.3V threshold detector for power fail warning, low
battery detection, or to monitor a power supply other
than +5V.
The MAX691, MAX693, and MAX695 are supplied in 16-pin
packages and perform all MAX690, MAX692, MAX694
functions, plus:
Write protection of CMOS RAM or EEPROM.
Adjustable reset and watchdog timeout periods.
Separate outputs for indicating a watchdog timeout,
backup-battery switchover, and low VCC.
Benets and Features
Supervisory Function Integration Saves Board Space
while Fully Protecting Microprocessor-Based Systems
Precision Voltage Monitor
- 4.65V (MAX690, MAX691, MAX694, MAX695)
- 4.40V (MAX692, MAX693)
Power OK/Reset Time Delay
- 50ms, 200ms, or Adjustable
Watchdog Timer
- 100ms, 1.6s, or Adjustable
Battery Backup Power Switching
Voltage Monitor for Power Fail or Low Battery
Warning
Minimum External Component Count
Low Power Consumption in Battery Backup Mode
Extends Battery Life
1µA Standby Current
Onboard Gating of Chip Enable Signals Protects
Against Erroneous Data Written to RAM During Low
VCC Events
Applications
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical µP Power Monitoring
Ordering information appears at end of data sheet.
19-0218; Rev 5; 4/15
MAX690
MAX692
MAX694
81
72
63
5
VBATT
RESET
WDI
PFO
4
VOUT
TOP VIEW
VCC
GND
PFI
MAX691
MAX693
MAX695
161
152
143
13
RESET
RESET
WDO
CE IN
4
VBATT
VOUT
VCC
GND
125
116
10
CE OUT
WDI
PFO
7
BATT ON
LOW LINE
OSC IN
98 PFIOSC SEL
MAX690
VCC
VBATT
PFI
VOUT
+5V
PFO
WDI
GND
MAX690 TYPICAL APPLICATION
RESET
POWER TO
CMOS RAM
µP
POWER
µP
SYSTEM
µP NMI
I/O
LINE
µP RESET
MAX690–MAX695 Microprocessor Supervisory Circuits
Pin Congurations
Typical Operating Circuit
Terminal Voltage (with respect to GND)
VCC ................................................................... -0.3V to +6.0V
VBATT ...............................................................-0.3V to +6.0V
All Other Inputs (Note 1) ................... -0.3V to (VOUT + 0.5V)
Input Current
VCC ............................................................................... 200mA
VBATT .............................................................................50mA
GND ...............................................................................20mA
Output Current
VOUT .....................................................Short circuit protected
All Other Outputs ............................................................ 20mA
Rate-of-Rise, VBATT, VCC ..............................................100V/µs
Operating Temperature Range
C suffix ................................................................0°C to +70°C
E suffix ............................................................ -40°C to +85°C
M suffix ......................................................... -55°C to +125°C
Power Dissipation
8-Pin Plastic DIP
(derate 5mW/°C above +70°C) ....................................400mV
8-Pin CERDIP
(derate 8mW/°C above +85°C) ....................................500mV
16-Pin Plastic DIP
(derate 7mW/°C above +70°C) ....................................600mV
16-Pin Small Outline
(derate 7mW/°C above +70°C) ....................................600mV
16-Pin CERDIP
(derate 10mW/°C above +85°C) ..................................600mV
Storage Temperature Range ............................ -65°C to +160°C
Lead Temperature (Soldering, 10s) ................................... 300°C
VCC = full operating range, VBATT = 2.8V, TA = +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
BATTERY BACKUP SWITCHING
Operating Voltage Range
(MAX690, MAX691, MAX694, MAX695 VCC)4.75 5.5
V
Operating Voltage Range (MAX690, MAX691,
MAX694, MAX695 VBATT)2.0 4.25
Operating Voltage Range
(MAX692, MAX693 VCC)4.5 5.5
Operating Voltage Range
(MAX692, MAX693 VBATT)2.0 4.0
VOUT Output Voltage
IOUT = 1mA VCC -
0.3
VCC -
0.1 V
IOUT = 50mA VCC -
0.5
VCC -
0.25
VOUT in Battery Backup Mode IOUT = 250µA, VCC < VBATT - 0.2V
VBATT
- 0.1
VBATT
- 0.02
V
Supply Current (Excluded IOUT)IOUT = 1mA 2 5 mA
IOUT = 50mA 3.5 10
Supply Current in Battery Backup Mode VCC = 0V, VBATT = 2.8V 0.6 1 µA
Battery Standby Current
(+ = Discharge, - = Charge)
5.5V > VCC >
VBATT + 1V
TA = +25°C -0.1 +0.02
µA
TA = full operating
range -1.0 +0.02
Battery Switchover Threshold
(VCC - VBATT)
Power-up 70 mV
Power-down 50
MAX690–MAX695 Microprocessor Supervisory Circuits
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Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
VCC = full operating range, VBATT = 2.8V, TA = +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Battery Switchover Hysteresis 20 mV
BATT ON Output Voltage ISINK = 3.2mA 0.4 V
BATT ON Output Short-Circuit Current BATT ON = VOUT = 4.5V sink current 25 mA
BATT ON = 0V source current 0.5 1 25 µA
RESET AND WATCHDOG TIMER
Reset Voltage Threshold TA = full
operating range
MAX690, MAX691,
MAX694, MAX695 4.5 4.65 4.75 V
MAX692, MAX693 4.25 4.4 4.5
Reset Threshold Hysteresis 40 mV
Reset Timeout Delay (MAX690/MAX691/
MAX692/MAX693) Figure 6, OSC SEL HIGH, VCC = 5V 35 50 70 ms
Reset Timeout Delay (MAX694/MAX695) Figure 6, OSC SEL HIGH, VCC = 5V 140 200 280 ms
Watchdog Timeout Period, Internal Oscillator Long period, VCC = 5V 1.0 1.6 2.25 s
Short period, VCC = 5V 70 100 140 ms
Watchdog Timeout Period, External Clock Long period 3840 4097 Clock
Cycles
Short period 768 1025
Minimum WDI Input Pulse Width VIL = 0.4, VIH = 0.8VCC 200 ns
RESET and LOW LINE Output Voltage ISINK = 1.6mA, VCC = 4.25V 0.4 V
ISOURCE = 1µA, VCC = 5V 3.5
RESET and WDO Output Voltage ISINK = 1.6mA 0.4 V
ISOURCE = 1µA, VCC = 5V 3.5
Output Short-Circuit Current RESET, RESET, WDO, LOW LINE 1 3 25 µA
WDI Input Threshold Logic-Low VCC = 5V (Note 2) 0.8 V
WDI Input Threshold Logic-High VCC = 5V (Note 2) 3.5
WDI Input Current WDI = VOUT 20 50 µA
WDI = 0V -50 -15
POWER-FAIL DETECTOR
PFI Threshold VCC = 5V, TA = full 1.2 1.3 1.4 V
PFI Current ±0.01 ±25 nA
PFO Output Voltage ISINK = 3.2mA 0.4 V
ISOURCE = 1µA 3.5 V
PFO Short Circuit Source Current PFI = VIH, PFO = 0V 1 3 25 µA
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Electrical Characteristics (continued)
VCC = full operating range, VBATT = 2.8V, TA = +25°C, unless otherwise noted.)
Note 1: The input voltage limits on PFI and WDI may be exceeded provided the input current is limited to less than 10mA.
Note 2: WDI is guaranteed to be in the mid-level (inactive) state if WDI is floating and VCC is in the operating voltage range. WDI is
internally biased to 38% of VCC with an impedance of approximately 125kΩ.
PARAMETER CONDITIONS MIN TYP MAX UNITS
CHIP ENABLE GATING
CE IN Thresholds VIL 0.8 V
VIH 3.0
CE IN Pullup Current 3 µA
CE OUT Output Voltage
ISINK = 3.2mA 0.4
VISOURCE = 3.0mA VOUT - 1.5
ISOURCE = 1µA, VCC = 0V VOUT - 0.05
CE Propagation Delay VCC = 5V 50 200 ns
OSCILLATOR
OSC IN Input Current ±2 µA
OSC SEL Input Pullup Current 5 µA
OSC IN Frequency Range OSC SEL = 0V 0 250 kHz
OSC IN Frequency
with External Capacitor
OSC SEL = 0V
COSC = 47pF 4 kHz
PIN
NAME FUNCTION
MAX690/
MAX692/
MAX694
MAX691/
MAX693/
MAX695
2 3 VCC The +5V Input
8 1 VBATT Backup Battery Input. Connect to Ground if a backup battery is not used.
1 2 VOUT
The higher of VCC or VBATT is internally switched to VOUT. Connect VOUT to VCC if
VOUT and VBATT are not used. Connect a 0.1µF or larger bypass capacitor to VOUT.
3 4 GND 0V Ground Reference for All Signals
7 15 RESET
RESET goes low whenever VCC falls below either the reset voltage threshold or the
VBATT input voltage. The reset threshold is typically 4.65V for the MAX690/691/694/695,
and 4.4V for the MAX692 and MAX693. RESET remains low for 50ms after VCC returns
to 5V, (except 200ms in MAX694/695). RESET also goes low for 50ms if the Watchdog
Timer is enabled but not serviced within its timeout period. The RESET pulse width can
be adjusted as shown in Table 1.
611 WDI
Watchdog Input (WDI). WDI is a three level input. If WDI remains either high or low for
longer than the watchdog timeout period, RESET pulses low and WDO goes low. The
Watchdog Timer is disabled when WDI is left oating or is driven to mid-supply. The
timer resets with each transition at the Watchdog Timer input.
4 9 PFI Noninverting Input to the Power-Fail Comparator. When PFI is less than 1.3V, PFO
goes low. Connect PFI to GND or VOUT when not used. See Figure 1.
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Electrical Characteristics (continued)
Pin Description
PIN
NAME FUNCTION
MAX690/
MAX692/
MAX694
MAX691/
MAX693/
MAX695
5 10 PFO Output of the Power-Fail Comparator. It goes low when PFI is less than 1.3V. The
comparator is turned off and PFO goes low when VCC is below VBATT.
13 CE IN CE Gating Circuit Input. Connect to GND or VOUT if not used.
12 CE OUT CE OUT goes low only when CE IN is low and VCC is above the reset threshold (4.65V
for MAX691 and MAX695, 4.4V for MAX693). See Figure 6.
5 BATT ON
BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low
when VOUT is internally switched to VCC. The output typically sinks 25mA and can
directly drive the base of an external PNP transistor to increase the output current
above the 50mA rating of VOUT.
6 LOW LINE LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon
as VCC rises above the reset threshold. See Figure 6, Reset Timing.
16 RESET Active-High Output. It is the inverse of RESET.
8 OSC SEL
When OSC SEL is unconnected or driven high, the internal oscillator sets the reset time
delay and watchdog timeout period. When OSC SEL is low, the external oscillator input,
OSC IN, is enabled. OSC SEL has a 3µA internal pullup. See Table 1.
7 OSC IN
When OSC SEL is low, OSC IN can be driven by an external clock to adjust both the
reset delay and the watchdog timeout period. The timing can also be adjusted by
connecting and external oscillator to this pin. See Figure 8. When OSC SEL is high or
oating, OSC IN selects between fast and slow Watchdog timeout periods.
14 WDO
The Watchdog Output (WDO). WDO goes low if WDI remains either high or low for
longer than the watchdog timeout period. WDO is set high by the next transition at WDI.
If WDI is unconnected or at mid-supply, WDO remains high. WDO also goes high when
LOW LINE goes low.
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Pin Description (continued)
Typical Applications
MAX691, MAX693, and MAX695
A typical connection for the MAX691/693/695 is shown
in Figure 1. CMOS RAM is powered from VOUT. VOUT is
internally connected to VCC when 5V power is present,
or to VBATT when VCC is less than the battery voltage.
VOUT can supply 50mA from VCC, but if more current
is required, an external PNP transistor can be added.
When VCC is higher than VBATT, the BATT ON output
goes low, providing 25mA of base drive for the external
transistor. When VCC is lower than VBATT, an internal
200Ω MOSFET connects the backup battery to VOUT.
The quiescent current in the battery backup mode is 1µA
maximum when VCC is between 0V and VBATT–700mV.
Reset Output
A voltage detector monitors VCC and generates a RESET
output to hold the microprocessors Reset line low when
VCC is below 4.65V (4.4V for MAX693). An internal
monostable holds RESET low for 50ms* after VCC rises
above 4.65V (4.4V for MAX693). This prevents repeated
toggling of RESET even if the 5V power drops out and
recovers with each power line cycle.
The crystal oscillator normally used to generate the clock
for microprocessors takes several milliseconds to start.
Since most microprocessors need several clock cycles
to reset, RESET must be held low until the micropro-
cessor clock oscillator has started. The MAX690 family
power-up RESET pulse lasts 50ms* to allow for this
oscillator start-up time. The manual reset switch and
the 0.1µF capacitor connected to the reset bus can be
omitted if manual reset is not needed. An inverted, active
high, RESET output is also supplied.
Power-Fail Detector
The MAX691/93/95 issues a nonmaskable interrupt (NMI)
to the microprocessor when a power failure occurs. The
+5V power line is monitored via two external resistors
connected to the power-fail input (PFI). When the volt-
age at PFI falls below 1.3V, the power-fail output (PFO)
drives the processors NMI input low. If a power-fail
threshold of 4.8V is chosen, the microprocessor will
have the time when VCC fails from 4.8V to 4.65V to save
data into RAM. An earlier power-fail warning can be
generated if the unregulated DC input of the 5V regulator
is available for monitoring.
RAM Write Protection
The MAX691/MAX693/MAX695 CE OUT line drives the
Chip Select inputs of the CMOS RAM. CE OUT follows
CE IN as long as VCC is above the 4.65V (4.4V for
MAX693) reset threshold. If VCC falls below the reset
threshold, CE OUT goes high, independent of the logic
level at CE IN. This prevents the microprocessor from
writing erroneous data into RAM during power-up, power-
down, brownouts, and momentary power interruptions.
The LOW LINE output goes low when VCC falls below
4.65V (4.4V for MAX693).
*200ms for MAX695
Figure 1. MAX691/693/695 Typical Application
+5V
V
CC
INPUT
NO CONNECTION
0.1µF
0.1µF
0.1µF
3
1
9
4
V
CC
V
BATT
I/O
NMI
RESET
PFI
GND
BATT ON
LOW LINE WDO
SYSTEM STATUS INDICATORS
3V
BATTERY
5
2
12
13
6 14
MAX691
MAX693
MAX695
11
10
15
7OSC IN
V
OUT
CE IN
CE OUT
PFO
WDI
RESET
RESET
8OSC SEL
AUDIBLE
ALARM
ADDRESS
DECODE
CMOS
RAM
MICROPROCESSOR
OTHER SYSTEM RESET SOURCES
A0-A15
MAX690–MAX695 Microprocessor Supervisory Circuits
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Watchdog Timer
The microprocessor drives the WATCHDOG INPUT
(WDI) with an I/O line. When OSC IN and OSC SEL are
unconnected, the microprocessor must toggle the WDI
pin once every 1.6s to verify proper software execution. If
a hardware or software failure occurs such that WDI not
toggled the MAX691/MAX693 will issue a 50ms* RESET
pulse after 1.6s. This typically restarts the microproces-
sors power-up routine. A new RESET pulse is issued
every 1.6s until the WDI is again strobed.
The WATCHDOG OUTPUT (WDO) goes low if the
watchdog timer is not serviced within its timeout period.
Once WDO goes low it remains low until a transition
occurs at WDI. The watchdog timer feature can be dis-
abled by leaving WDI unconnected. OSC IN and OSC
SEL also allow other watchdog timing options, as shown
in Table 1 and Figure 8.
MAX690, MAX692, and MAX694
The 8 pin MAX690, MAX692, and MAX694 have most
of the features of the MAX691, MAX693, and MAX695.
Figure 2 shows the MAX690/MAX692/MAX694 in a typical
application. Operation is much the same as with the
MAX691/MAX693/MAX695 (Figure 1), but in this case, the
power- fail input (PFI) monitors the unregulated input to the
7805 regulator. The MAX690/MAX694 RESET output goes
low when VCC falls below 4.65V. The RESET output of the
MAX692 goes low when VCC drops below 4.4V.
The current consumption of the battery-backed-up power
bus must be less than 50mA. The MAX690/MAX692/
MAX694 does not have a BATT ON output to drive an
external transistor. The MAX690/MAX692/MAX694 also
does not include chip enable gating circuitry that is avail-
able on the MAX690/MAX692/MAX694. In many systems
though, CE gating is not needed since a low input to
the microprocessor RESET line prevents the processor
from writing to RAM during power-up and power-down
transients.
The MAX690/MAX692/MAX694 watchdog timer has a
fixed 1.6s timeout period. If WDI remains either low or
high for more than 1.6s, a RESET pulse is sent to the
microprocessor. The watchdog timer is disabled if WDI is
left unconnected.
*200ms for MAX695
Figure 2. MAX690/692/694 Typical Application
7805
3-TERMINAL
REGULATOR
+8V +5V
0.1µF
0.1µF
2
4
3
MAX690
MAX692
MAX694
GND
MICROPROCESSOR
MICRO-
PROCESSOR
POWER
POWER
TO
CMOS
RAM
1
VCC VOUT
8
7
5
6
VBATT
RESET
PFI
RESET
PFO NMI
WDI I/O LINE
MAX690–MAX695 Microprocessor Supervisory Circuits
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Detailed Description
Battery-Switchover and VOUT
The battery switchover circuit compares VCC to the VBATT
input, and connects VOUT to whichever is higher. Switchover
occurs when VCC is 50mV greater than VBATT as VCC falls,
and VCC is 70mV more than VBATT as VCC rises (see
Figure 4). The switchover comparator has 20mV of hyster-
esis to prevent repeated, rapid switching if VCC falls very
slowly or remains nearly equal to the battery voltage.
When VCC is higher than VBATT, VCC is internally
switched to VOUT via a low saturation PNP transis-
tor. VOUT has 50mA output current capability. Use an
external PNP pass transistor in parallel with internal tran-
sistor if the output current requirement at VOUT exceeds
50mA or if a lower VCC-VOUT voltage differential is
desired. The BATT ON output (MAX691/MAX693/MAX695
only) can directly drive the base of the external transistor.
It should be noted that the MAX690–MAX695 need only
supply the average current drawn by the CMOS RAM if
there is adequate filtering. Many RAM data sheets specify
a 75mA maximum supply current, but this peak current
spike lasts only 100ns. A 0.1µF bypass capacitor at VOUT
supplies the high instantaneous current, while VOUT need
only supply the average load current, which is much less.
A capacitance of 0.1µF or greater must be connected to
the VOUT terminal to ensure stability.
A 200Ω MOSFET connects VBATT input to VOUT during
battery backup. This MOSFET has very low input-to-
output differential (dropout voltage) at the low current
levels required for battery backup of CMOS RAM or other
low power CMOS circuitry. When VCC equals VBATT the
supply current is typically 12µA. When VCC is between
0V and (VBATT - 700mV) the typical supply current is only
600nA typical, 1µA maximum.
The MAX690/MAX691/MAX694/MAX695 operate with
battery voltages from 2.0V to 4.25V while MAX692/
MAX693 operate with battery voltages from 2.0V to
4.0V. High value capacitors can also be used for short-
term memory backup. External circuitry is required to
ensure that the capacitor voltage does not rise above
the reset threshold, and that the charging resistor does
not discharge the capacitor when in backup mode. The
MAX691A and the MAX791 provide solutions requiring
fewer external components.
A small charging current of typically 10nA (0.1µA max)
flows out of the VBATT terminal. This current varies with the
amount of current that is drawn from VOUT but its polarity
is such that the backup battery is always slightly charged,
and is never discharged while VCC is in its operating volt-
age range. This extends the shelf life of the backup battery
by compensating for its self-discharge current. Also note
that this current poses no problem when lithium batteries
are used for backup since the maximum charging current
(0.1µA) is safe for even the smallest lithium cells.
If the battery-switchover section is not used, connect
VBATT to GND and connect VOUT to VCC. Table 2 shows
the state of the inputs and output in the low power battery
backup mode.
Figure 3. MAX691/MAX693/MAX695 Block Diagram
RESET GENERATOR
TIMEBASE FOR RESET
AND
WATCHDOG
WATCHDOG TRANSITION
DETECTOR
WATCHDOG
TIMER
+
-
1.3V
+
-
+
-
*
4.65V
V
BATT
BATT ON1 5
V
CC
CHIP-ENABLE INPUT
OSC IN
*4.4V (MAX693)
OSC SEL
WATCHDOG INPUT
POWER FAIL
INPUT
3
13
7
8
11
9
4
V
OUT
CHIP ENABLE OUTPUT
LOW LINE
RESET
GROUND
RESET
WATCHDOG OUTPUT
POWER FAIL OUTPUT
2
12
6
15
16
14
10
MAX690–MAX695 Microprocessor Supervisory Circuits
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Reset Output
RESET is an active-low output which goes low when-
ever VCC falls below 4.5V (MAX690/MAX691/MAX694/
MAX695) or 4.25V (MAX692/MAX693). It will remain low
until VCC rises above 4.75V (MAX690/691/694/695) or 4.5V
(MAX692/MAX693) for milliseconds*. See Figures 5 and 6.
The guaranteed minimum and maximum thresholds of
MAX690/MAX691/MAX694/MAX695 are 4.5V and 4.75V,
while the guaranteed thresholds of the MAX692/MAX693
are 4.25V and 4.5V. The MAX690/MAX691/MAX694/
MAX695 is compatible with 5V supplies with a +10%, -5%
tolerance while the MAX692/MAX693 is compatible with
5V ±10% supplies. The reset threshold comparator has
approximately 50mV of hysteresis, with a nominal thresh-
old of 4.65V in the MAX690/MAX691/MAX694/MAX695,
and 4.4V in the MAX692/MAX693.
The response time of the reset voltage comparator is
about 100µs. VCC should be bypassed to ensure that
glitches do not activate the RESET output.
RESET also goes low if the watchdog timer is enabled
and WDI remains either high or low longer than the watch-
dog timeout period. RESET has an internal 3µA pullup,
and can either connect to and open collector Reset bus
or directly drive a CMOS gate without and external pullup
resistor.
CE Gating and RAM Write Protection
The MAX691/MAX693/MAX695 use two pins to control
the Chip Enable or Write inputs of CMOS RAMs. When
VCC is +5V, CE OUT is a buffered replica of CE IN, with
a 50ns propagation delay. If VCC input falls below 4.65V
(4.5V min, 4.75V max) an internal gate forces CE OUT
high, independent of CE IN. The MAX693 CE OUT goes
high whenever VCC is below 4.4V (4.25V min, 4.5V max).
The CE output of both devices is also forced high when
VCC is less than VBATT. (See Figure 5.)
CE OUT typically drives the CE, CS, or Write input of
battery backed up CMOS RAM. This ensures the integ-
rity of the data in memory by preventing write operations
when VCC is at and invalid level. Similar protection of
EEPROMs can be achieved by using the CE OUT to
drive the Store or Write inputs of an EEPROM, EAROM,
or NOVRAM.
If the 50ns typical propagation delay of CE OUT is too
long, connect CE IN to GND and use the resulting CE
OUT to control a high speed external logic gate. A second
alternative is to AND the LOW LINE output with the CE or
WR signal. An external logic gate and the RESET output
of the MAX690/MAX692/MAX694 can also be used for
CMOS RAM write protection.
*200ms for MAX694 and MAX695
Figure 4. Battery-Switchover Block Diagram
+
-
+
+
-
-
BASE DRIVE
LOW IQ MODE
SELECT
V
OUT
0.1F
TO CMOS
RAM AND
REALTIME
CLOCK
V
CC
IN
100
mV
700
mV
3V
BATTERY
INPUT
P CHANNEL
MOSFET
BATT ON
(MAX691, MAX693, MAX695 ONLY)
INTERNAL
SHUTDOWN
SIGNAL WHEN
V
BATT
> V
CC
+ 0.7V
V
CC
V
CC
+5V
MAX690–MAX695 Microprocessor Supervisory Circuits
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9
Figure 5. Reset Block Diagram
Figure 6. Reset Timing
+
-
1.3V
RESET RESET
TIME Q
R
RESET
RESET
WATCHDOG
FROM
WATCHDOG
TIMER
V
CC
CE IN CE OUT
LOW LINE
10 kHz CLOCK
FROM TIMEBASE
SECTION
POWER-ON
RESET
METAL
LINK
TRIMMED
RESISTORS
4.7V
50ms*
VCC
RESET
OUTPUT
4.7V4.6V 4.6V
*200ms FOR MAX694 AND MAX695
VOUT - VBATT
LOW LINE
OUTPUT
CE
IN
CE
IN
50ms*
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1.3V Comparator and Power-Fail Warning
The power-fail input (PFI) is compared to an internal
1.3V reference. The power-fail output (PFO) goes low
when the voltage at PFI is less than 1.3V. Typically, PFI is
driven by an external voltage divider which senses either
the unregulated DC input to the system’s 5V regulator or
the regulated 5V output. The voltage divider ratio can be
chosen such that the voltage at PFI falls below 1.3V sev-
eral milliseconds before the +5V supply falls below 4.75V.
PFO is normally used to interrupt the microprocessor so
that data can be stored in RAM before VCC falls below
4.75V and the RESET output goes low (4.5V for MAX692/
MAX693).
The power-fail detector can also monitor the backup bat-
tery to warn of a low battery condition. To conserve bat-
tery power, the power-fail detector comparator is turned
off and PFO is forced when VCC is lower than VBATT
input voltage.
Watchdog Timer and Oscillator
The watchdog circuit monitors the activity of the micro-
processor. If the microprocessor does not toggle the
Watchdog Input (WDI) within the selected timeout period,
a 50ms* RESET pulse is generated. Since many systems
cannot service the watchdog timer immediately after a
reset, the MAX691/MAX693/MAX695 has a longer time-
out period after reset is issued. The normal timeout period
becomes effective following the first transition of WDI after
RESET has gone high. The watchdog timer is restarted
at the end of reset, whether the reset was caused by
lack of activity on WDI or by VCC falling below the reset
threshold. If WDI remains either high or low, reset pulses
will be issued every 1.6s. The watchdog monitor can be
deactivated by floating the watchdog input (WDI).
The watchdog output (WDO, MAX691/MAX693/MAX695
only) goes low if the watchdog timer times out and
remains low until set high by the next transition on the
watchdog input. WDO is also set high when VCC goes
below the reset threshold.
The watchdog timeout period is fixed at 1.6s and the
reset pulse width is fixed at 50ms* on the 8-pin MAX690/
MAX692/MAX694. The MAX691/MAX693/MAX695 allow
these times to be adjusted per Table 1.
Figures 8 shows
various oscillator configurations.
The internal oscillator is enabled when OSC SEL is
floating. In this mode, OSC IN selects between the
1.6s and 100ms watchdog timeout periods. In either
case, immediately after a reset the timeout period 1.6s.
This gives the microprocessors time to reintialize the
system. If OSC IN is low, then the 100ms watchdog
period becomes effective after the first transition of WDI.
The software should be written such that the I/O port
driving WDI is left in its power-up reset state until the ini-
tialization routines are completed and the microprocessor
is able to toggle WDI at the minimum watchdog timeout
period of 70ms.
*200ms for MAX694
Figure 7. Watchdog Timer Block Diagram
+
-
-
+
1.0V
2.7V
VCC
TRANSACTION
DETECTOR
WATCHDOG INPUT
HI IF WATCHDOG
INPUT IS FLOATING
FOR EACH TRANSITION
RESET
COUNTER
R Q10/12
Q6
PRESCALER
WATCHDOG
COUNTER
R
Q11
Q13
Q15
WATCHDOG
TIMEOUT
SELECTOR
LOGIC
GOES HIGH AT THE
END OF WATCHDOG
TIMEOUT PERIOD
WATCHDOG
FAULT FF
WATCHDOG TIMEOUT SELECT
WATCHDOG OUTPUT
10.24 kHz FROM INTERNAL OSCILLATOR
OR EXTERNALLY SET FREQUENCY FROM
OSC IN PIN
LOW
LINE
RESET
FLIP FLOP
Q
S R
QQ
Q
LONG/SHORT
FF
S R
R
S
RESET RESET
LOW LINE
(HI IF VCC < 4.65V)
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Note 1: The MAX690/MAX692/MAX694 watchdog timeout period is fixed at 1.6s nominal, the MAX690/692 reset pulse width is fixed
at 50ms nominal and the MAX694 is 200ms nominal.
Note 2: When the MAX691 OSC SEL pin is low, OSC IN can be driven by an external clock signal or an external capacitor can be
connected between OSC IN and GND. The nominal internal oscillator frequency is 6.55kHz. The nominal oscillator frequency
with capacitor is:
OSC
120,000
f (Hz)
C(pF)
=
Note 3: See Electrical Characteristics table for minimum and maximum timing values.
Figure 8. Oscillator Circuits
Table 1. MAX691/MAX693/MAX695 Reset Pulse Width and Watchdog Timeout Selections
OSC SEL OSC IN
WATCHDOG TIMEOUT PERIOD RESET TIMEOUT PERIOD
NORMAL IMMEDIATELY
AFTER REST MAX691/MAX693 MAX695
Low External Clock Input 1024 clks 4096 clks 512 clks 2048 clks
Low External Capacitor 400ms/47pF x C 1.6s/47pF x C 200ms/47pF x C 800ms/47pF x C
Floating Low 100ms 1.6s 50ms 200ms
Floating Floating 1.6s 1.6s 50ms 200ms
MAX691
MAX693
MAX695
EXTERNAL CLOCK
0 TO 250kHz
OSC SEL
OSC IN
8
7
MAX691
MAX693
MAX695
EXTERNAL OSCILLATOR
COSC
OSC SEL
OSC IN
8
7
MAX691
MAX693
MAX695
INTERNAL OSCILLATOR
1.6s WATCHDOG
N.C. OSC SEL
OSC IN
8N.C. 8
7
MAX691
MAX693
MAX695
INTERNAL OSCILLATOR
100ms WATCHDOG
OSC SEL
OSC IN
7
N.C.
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Application Hints
Other Uses of the Power-Fail Detector
In Figure 9, the power-fail detector is used to initiate a
system reset when VCC falls to 4.85V. Since the thresh-
old of the power-fail detector is not as accurate as the
onboard reset-voltage detector, a trimpot must be used
to adjust the voltage detection threshold. Both the PFO
and RESET outputs have high sink current capability and
only 10µA of source current drive. This allows the two
outputs to be connected directly to each other in a wired
OR fashion.
The overvoltage detector circuit in Figure 10 resets the
microprocessor whenever the nominal 5V VCC is above
5.5V. The battery monitor circuit (Figure 11) shows the
status of the memory backup battery. If desired, the CE
OUT can be used to apply a test load to the battery. Since
CE OUT is forced high during the battery backup mode,
the test load will not be applied to the battery while it is in
use even if the microprocessor is not powered.
Adding Hysteresis
to the Power Fail Comparator
Since the power fail comparator circuit is noninvert-
ing, hysteresis can be added by connecting a resistor
between the PFO output and the PFI input as shown in
Figure 12. When PFO is low, resistor R3 sinks current
from the summing junction at the PFI pin. When PFO is
high, the series combination of R3 and R4 source current
into the PFI summing junction.
Alternate Watchdog Input Drive Circuits
The Watchdog feature can be enabled and disabled
under program control by driving WDI with a three-state
buffer (Figure 13). The drawback to this circuit is that a
software fault may be erroneously three-state the buffer,
thereby preventing the MAX690 from detecting that the
microprocessor is no longer working. In most cases a bet-
ter method is to extend the watchdog period rather than
disabling the watchdog. See Figure 14. When the control
input is high, the OSC SEL pin is low and the watchdog
timeout is set by the external capacitor. A 0.01µF capaci-
tor sets a watchdog timeout delay of 100s. When the
control input is low the OSC SEL pin is high, selecting
the internal oscillator. The 100ms or the 1.6s period is
chosen, depending on which diode in Figure 14 is used.
Figure 9. Externally Adjustable VCC Reset Threshold Figure 10. Reset on Overvoltage or Undervoltage
MAX690
MAX691
MAX692
MAX693
MAX694
MAX695
PFI
TO µP
RESET
INPUT
GND
+5V
VCC
PFO
10k
2k
29.4k
RESET
MAX690
MAX691
MAX692
MAX693
MAX694
MAX695
PFI
TO µP
RESET
INPUT
N-CHANNEL
GND
+5V
VCC
PFO
10k
2k
35.7k
RESET
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Figure 11. Backup VBattery Monitor with Optional Test Load
Figure 13. Disabling the Watchdog Under Program Control
Figure 12. Adding Hysteresis to the Power-Fail Voltage
Comparator
Figure 14. Selecting Internal or External Watchdog Timeout
MAX690
MAX691
MAX692
MAX693
MAX694
MAX695
PFI
RL
VBATT
CE OUT
LOW BATTERY
SIGNAL TO
µP I/O PIN
FROM µP
I/O PIN
GND
LOW
APPLIES
LOAD
TO BATTERY
+5V
VCC
CE IN
10M
10M
PFO
MAX690
MAX691
MAX692
MAX693
MAX694
MAX695
WDI
WATCHDOG
STROBE
GND
+5V
VCC
WATCHDOG
DISABLE
EN
MAX690
MAX691
MAX692
MAX693
MAX694
MAX695
PFO
VCC
PFI
GND
TO P
7805
+5V7V TO 15V
R4
10k
R1
75k
R2
13k
VH = 9.125V
VL = 7.9V
HYSTERESIS = 1.23V
VH = 1.3V (1 + + )
R3
300k
R1
R2
R1
R3
R1
R3
VL = 1.3V (1 + - )
HYSTERESIS 5V x
ASSUMING R4 < < R3
R1
R2
(5V -1.3V) R1
1.3V (R3 + R4)
MAX691
MAX693
OSC SEL
LOW = INTERNAL
WATCHDOG TIMEOUT
HI = EXTERNAL
WATCHDOG
TIMEOUE
GND
+5V
VCC
OSC IN
CONNECT FOR
100ms TIMEOUT
WHEN INTERNAL
TIMEOUT IS
SELECTED CONNECT FOR
1.6s INTERNAL
TIMEOUT
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Table 2. Input and Output Status In Battery Backup Mode
VBATT, VOUT VBATT is connected to VOUT via internal MOSFET.
RESET Logic-low
RESET Logic-high. The open circuit output voltage is equal to VOUT.
LOW LINE Logic-low
BATT ON Logic-high
WDI WDI is internally disconnected from its internal pullup and does not source or sink current as long as its input
voltage is between GND and VOUT. The input voltage does not affect the source current.
WDO Logic-high
PFI The power-fail comparator is turned off and the power-fail input voltage has no effect on the power-fail output.
PFO Logic-low
CE IN CE IN is internally disconnected from its internal pullup and does not source or sink current as long as its input
voltage is between GND and VOUT. The input voltage does not affect the source current.
CE OUT Logic-high
OSC IN OSC IN is ignored.
OSC SEL OSC SEL is ignored.
VCC
Approximately 12µA is drawn from the VBATT input when VCC is between VBATT +100mV and VBATT - 700mV.
The supply current is 1µA maximum when VCC is less than VBATT - 700mV.
MAX690–MAX695 Microprocessor Supervisory Circuits
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*Contact factory for dice specifications.
Devices in PDIP and SO packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at
the end of the part number when ordering. Lead free not available for CERDIP package.
PART TEMP RANGE PIN-PACKAGE
MAX693CPE 0°C to +70°C 16 Lead Plastic DIP
MAX693CWE 0°C to +70°C 16 Lead Wide SO
MAX693EPE -40°C to +85°C 16 Lead Plastic DIP
MAX693EJE -40°C to +85°C 16 Lead CERDIP
MAX693EWE -40°C to +85°C 16 Lead Wide SO
MAX693MJE -55°C to +125°C 16 Lead CERDIP
MAX694C/D 0°C to +70°C Dice
MAX694CPA 0°C to +70°C 8 Lead Plastic DIP
MAX694EPA -40°C to +85°C 8 Lead Plastic DIP
MAX694EJA -40°C to +85°C 8 Lead CERDIP
MAX694MJA -55°C to +125°C 8 Lead CERDIP
MAX695C/D 0°C to +70°C Dice
MAX695CPE 0°C to +70°C 16 Lead Plastic DIP
MAX695CWE 0°C to +70°C 16 Lead Wide SO
MAX695EPE -40°C to +85°C 16 Lead Plastic DIP
MAX695EJE -40°C to +85°C 16 Lead CERDIP
MAX695EWE -40°C to +85°C 16 Lead Wide SO
MAX695MJE -55°C to +125°C 16 Lead CERDIP
PART TEMP RANGE PIN-PACKAGE
MAX690CPA 0°C to +70°C 8 Lead Plastic DIP
MAX690C/D 0°C to +70°C Dice*
MAX690EPA -40°C to +85°C 8 Lead Plastic DIP
MAX690EJA -40°C to +85°C 8 Lead CERDIP
MAX690MJA -55°C to +125°C 8 Lead CERDIP
MAX691CPE 0°C to +70°C 16 Lead Plastic DIP
MAX691CWE 0°C to +70°C 16 Lead Wide SO
MAX691C/D 0°C to +70°C Dice*
MAX691EPE -40°C to +85°C 16 Lead Plastic DIP
MAX691EWE -40°C to +85°C 16 Lead Wide SO
MAX691EJE -40°C to +85°C 16 Lead CERDIP
MAX691MJE -55°C to +125°C 16 Lead CERDIP
MAX692C/D 0°C to +70°C Dice
MAX692CPA 0°C to +70°C 8 Lead Plastic DIP
MAX692EPA -40°C to +85°C 8 Lead Plastic DIP
MAX692EJA -40°C to +85°C 8 Lead CERDIP
MAX692MJA -55°C to +125°C 8 Lead CERDIP
MAX693C/D 0°C to +70°C Dice
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16
Ordering Information
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 PDIP P8-2 21-0043
8 CEDIP J8-2 21-0045
16 PDIP P16-1 21-0043
16 Wide SO W16-1 21-0042
16 CERDIP P16-1 21-0043
3
VCC
WDO
CE IN
CE OUT
2
VOUT
GND
BATT
ON
1
VBATT
16
RESET
15
4
14
13
12
5
RESET
6
LOW LINE
7 8
OSC
IN
OSC
SEL
0.086”
(2.184 mm)
WDI
9
PFI
10 11
PFO
0.122”
(3.098 mm)
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Chip Topography
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
5 4/15 Revised Benets and Features section 1
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX690–MAX695 Microprocessor Supervisory Circuits
© 2015 Maxim Integrated Products, Inc.
18
Revision History
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