November 2006 Rev 1 1/7
EMIF02-MIC03C2
2 line EMI filter and ESD protection
Main product characteristics
Where EMI filtering in ESD sensitive equipment is
required:
■Mobile phones and communication systems
■Computers and printers and MCU Boards
Description
The EMIF02-MIC03C2 is a highly integrated
device designed to suppress EMI/RFI noise in all
systems subjected to electromagnetic
interference. The Flip-Chip packaging means the
package size is equal to the die size.
This filter includes ESD protection circuitry, which
prevents damage to the application when it is
subjected to ESD surges up to 15 kV.
Benefits
■EMI symmetrical (I/O) low-pass filter
■High efficiency EMI filter (-35 dB @ 900 MHz)
■Very low PCB space consumption:
1.07 mm x 1.47 mm
■Very thin package: 0.695 mm
■Coating resin on back side and lead free
package
■High efficiency in ESD suppression
■High reliability offered by monolithic integration
■High reduction of parasitic elements through
integration and wafer level packaging.
Pin configuration (Bump side)
Complies with following standards:
IEC 61000-4-2
MIL STD 883G - Method 3015-7 Class 3
level 4 input pins 15 kV (air discharge)
8 kV (contact discharge
level 1 output pins 2 kV (air discharge)
2 kV (contact discharge
Coated Flip-Chip package
(about 20 times real size)
B
132
C
A
I1
O1
GND
I2
O2
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Characteristics EMIF02-MIC03C2
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1 Characteristics
Figure 1. Basic cell configuration
Table 1. Absolute ratings (limiting values)
Symbol Parameter Value Unit
TjMaximum junction temperature 125 °C
Top Operating temperature range -40 to +85 °C
Tstg Storage temperature range -55 to +150 °C
Table 2. Electrical characteristics (Tamb = 25° C)
Symbol Parameters
VBR Breakdown voltage
IRM Leakage current @ VRM
VRM Stand-off voltage
VCL Clamping voltage
RdDynamic impedance
IPP Peak pulse current
RI/O Series resistance between input and output
Cline Input capacitance per line
Symbol Test conditions Min Typ Max Unit
VBR IR = 1 mA 6 8 V
IRM VRM = 3 V per line 500 nA
RI/O Tolerance 68 Ω
Cline VR = 0 V 100 pF
Input Output
GND GND GND
Low-pass Filter
Ri/o = 68
Cline = 100 pF
Ω
I
V
IPP
VCL
VBRVRM
IR
IRM
IRM
IR
IPP
VRMVBR
VCL
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Figure 2. S21 (dB) attenuation measurement Figure 3. Analog crosstalk measurement
100.0k 1.0M 10.0M 100.0M 1.0G
-50.00
-45.00
-40.00
-35.00
-30.00
-25.00
-20.00
-15.00
-10.00
-5.00
0.00
100.0k 1.0M 10.0M 100.0M 1.0G
-50.00
-45.00
-40.00
-35.00
-30.00
-25.00
-20.00
-15.00
-10.00
-5.00
0.00 dB
F (Hz)
dB
100.0k 1.0M 10.0M 100.0M 1.0G
-80.00
-70.00
-60.00
-50.00
-40.00
-30.00
-20.00
-10.00
0.00
100.0k 1.0M 10.0M 100.0M 1.0G
-80.00
-70.00
-60.00
-50.00
-40.00
-30.00
-20.00
-10.00
0.00
F (Hz)
Figure 4. ESD response to IEC 61000-4-2
(+15 kV air discharge) on one
input Vin and one output Vout
Figure 5. ESD response to IEC 61000-4-2
(- 15 kV air discharge) on one
input Vin and one output Vout
Figure 6. Line capacitance versus applied
voltage
0
20
40
60
80
100
120
140
012345
V (V)R
F=1MHz
Vosc=30mVRMS
Tj=25°C
C(pF)
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Characteristics EMIF02-MIC03C2
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Figure 7. Aplac model
Figure 8. Aplac parameters
model = D1 model = D2
model = D2
IN1
model = D1
OUT1
Rbump Lbump Lbump Rbump
Rmic Lmic
Rbump Lbump Lbump RbumpRmic Lmic
model = D3
IN2 OUT2
GND
Lsub
Rsub
Rbump
Lbump
Lgnd
Rgnd
Cgnd
GND
EMIF02-MIC03C2 model Ground return
aplacvar Rmic 68
aplacvar Lmic 10p
aplacvar Cdiode1 100pF
aplacvar Cdiode2 3.6pF
aplacvar Cdiode3 1.17nF
aplacvar Lbump 50pH
aplacvar Rbump 20m
aplacvar Rsub 0.5m
aplacvar Rgnd 10m
aplacvar Lgnd 50pH
aplacvar Cgnd 0.15pF
aplacvar Lsub 10pH
Model D1
CJO=Cdiode1
BV=7
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.7
VJ=0.6
TT=50n
Model D2
CJO=Cdiode2
BV=7
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.3
VJ=0.6
TT=50n
Model D3
CJO=Cdiode3
BV=7
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.12
VJ=0.6
TT=50n
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EMIF02-MIC03C2 Ordering information scheme
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2 Ordering information scheme
3 Package information
Figure 9. Flip-Chip Dimensions
EMIF yy - xxx zz Cx
EMI Filter
Number of lines
Information
Package
3 letters = application
2 digits = version
C = Coated Flip-Chip
x = 2: Leadfree Pitch = 500 µm, Bump = 315 µm
Figure 10. Marking Figure 11. Footprint recommendation
1.07 mm ± 50 µm
1.47 mm ± 50 µm
5
00 µm ± 15
315 µm ± 50
500 µm ± 10
250 µm ± 10
695 µm ± 50
x
y
x
w
z
w
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year ww = week) E
Copper pad Diameter:
250µm recommended, 300 µm max
Solder stencil opening: 330 µm
Solder mask opening recommendation:
340 µm min for 315 µm copper pad diameter
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Ordering information EMIF02-MIC03C2
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Figure 12. Flip-Chip tape and reel specification
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available
at: www.st.com.
4 Ordering information
5 Revision history
Dot identifying Pin A1 location
User direction of unreeling
All dimensions in mm
4 ± 0.1
8 ± 0.3
4 ± 0.1
1.75 ± 0.1
3.5 ± 0.1
Ø 1.5 ± 0.1
0.73 ± 0.05
xxz
yww
ST
xxz
yww
ST
xxz
yww
ST
E E E
Ordering code Marking Package Weight Base qty Delivery mode
EMIF02-MIC03C2 FW Flip-Chip 2.3 mg 5000 7” Tape and reel
Date Revision Changes
28-Nov-2006 1Initial release.
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EMIF02-MIC03C2
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