ACPL-M484/P484/W484
Positive Logic High CMR Intelligent Power Module
and Gate Drive Interface Optocoupler
Data Sheet
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Description
The ACPL-M484/P484/W484 fast speed optocoupler con-
tains a AlGaAs LED and photo detector with built-in Schmitt
trigger to provide logic-compatible waveforms, elimi-
nating the need for additional wave shaping. The totem
pole output eliminates the need for a pull up resistor and
allows for direct drive Intelligent Power Module or gate
drive. Minimized propagation delay dierence between
devices makes these optocouplers excellent solutions for
improving inverter eciency through reduced switching
dead time.
Applications
• IPM Interface Isolation
• Isolated IGBT/MOSFET Gate Drive
• AC and Brushless DC Motor Drives
• Industrial Inverters
• General Digital Isolation
Functional Diagram
Note: A 0.1 µF bypass
capacitor must be con-
nected between pins
Vcc and Ground.
Truth Table
(Positive Logic)
LED VO
ON HIGH
OFF LOW
Truth Table Guaranteed:
Vcc from 4.5 V to 30 V
Features
• Positive output type (totem pole output)
• Truth Table Guaranteed: Vcc from 4.5 V to 30 V
• Performance Specied for Common IPM Applications
Over Industrial Temperature Range.
• Short Maximum Propagation Delays
• Minimized Pulse Width Distortion (PWD)
• Very High Common Mode Rejection (CMR)
• Hysteresis
• Available in SO-5 (ACPL-M484) and Stretched SO-6
package (ACPCL-P484/W484).
• Package Clearance/Creepage at 8 mm (ACPL-W484)
• Safety Approval:
– UL Recognized with 5000 Vrms (ACPL-W484) for
1 minute per UL1577.
– CSA Approved.
– IEC/EN/DIN EN 60747-5-5 Approved with VIORM =
567 Vpeak for ACPL-M484 and VIORM = 891 Vpeak for
ACPL-P484 and VIORM = 1140 Vpeak for ACPL-W484,
under option 060.
Specications
• Wide operating temperature range: -40° C to 105° C
• Maximum propagation delay tPHL / tPLH = 150/120 ns
• Maximum Pulse Width Distortion (PWD) = 90 ns
• Propagation Delay Dierence Min/Max = -130/130 ns
• Wide Operating VCC Range: 4.5 to 30 Volts
• 30 kV/µs minimum common mode rejection (CMR) at
VCM = 1000 V
Ground
VCC
Anode
Cathode
VO
61
5
43 SHIELD
Ground
VCC
Anode
N.C.
Cathode
VO
61
52
43 SHIELD
ACPL-M484
ACPL-P484 & ACPL-W484
2
Ordering Information
ACPL-M484/P484/W484 is UL recognized with 3750/3750/5000 Vrms/1 minute rating per UL 1577.
Part number
Option
Package Surface Mount Tape & Reel
IEC/EN/DIN
EN 60747-5-5 QuantityRoHS Compliant
ACPL-M484 -000E SO-5 X 100 per tube
-500E X X 1500 per reel
-060E X X 100 per tube
-560E X X X 1500 per reel
ACPL-P484
ACPL-W484
-000E Stretched
SO-6
X 100 per tube
-500E X X 1000 per reel
-060E X X 100 per tube
-560E X X X 1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-P484-560E to order product of Stretched SO-6 Surface Mount package in Tape and Reel packaging with IEC/EN/
DIN EN 60747-5-5 Safety Approval in RoHS compliant.
Example 2:
ACPL-P484-000E to order product of Stretched SO-6 Surface Mount package in Tube packaging and RoHS compliant.
Example 3:
ACPL-M484-000E to order product of SO-5 Surface Mount package in Tube packaging and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
3
Package Outline Drawings
ACPL-M484 SO-5 Package, 5 mm Creepage & Clearance
MXXX
XXX
6
5
43
1
7.0 ± 0.2
(0.276 ± 0.008)
2.5 ± 0.1
(0.098 ± 0.004)
0.102 ± 0.102
(0.004 ± 0.004)
VCC
VOUT
GND
CATHODE
ANODE
4.4 ± 0.1
(0.173 ± 0.004)
1.27
(0.050)BSC
0.15 ± 0.025
(0.006 ± 0.001)
0.71
(0.028) MIN
0.4 ± 0.05
(0.016 ± 0.002)
3.6 ± 0.1*
(0.142 ± 0.004)
Dimensions in millimeters (inches).
* Maximum Mold ash on each side is 0.15 mm (0.006).
Note: Foating Lead Protrusion is 0.15 mm (6 mils) max.
TYPE NUMBER (LAST 3 DIGITS)
DATE CODE
7° MAX.
MAX. LEAD COPLANARITY
= 0.102 (0.004)
Land Pattern Recommendation
8.27
(0.325)
2.0
(0.080)
2.5
(0.10)
1.3
(0.05)
0.64
(0.025)
4.4
(0.17)
Dimension in millimeters (inches)
4
ACPL-P484 Stretched SO-6 Package, 7 mm clearance
7°
7°
45°
5°
NOM.
0.381 ±0.127
(0.015 ±0.005)
1.27 (0.050) BSG
4.580
+ 0.254
0
7°
7°
3.180 ±0.127
(0.125 ±0.005)
1.590 ±0.127
(0.063 ±0.005)
0.254 ±0.050
(0.010 ±0.002)
9.7 ±0.250
(0.382 ±0.010)
10.7 (0.421)
2.16 (0.085)
0.76 (0.030)
1.27 (0.050)
Floating Lead Protusions max. 0.25 (0.01)
Dimensions in Millimeters (Inches)
Lead Coplanarity = 0.1 mm (0.004 Inches)
0.180
+ 0.010
0.000
( )
1 ±0.250
(0.040 ±0.010)
0.20 ±0.10
(0.008 ±0.004)
7.62 (0.300)
6.81 (0.268)
0.45 (0.018)
Land Pattern Recommendation
ACPL-W484 Stretched SO-6 Package, 8 mm clearance Land Pattern Recommendation (W-type)
45°
7°
7°
2
1
3 4
5
6
7°
7°
0.381 ±0.127
(0.015 ±0.005)
0.20 ±0.10
(0.008 ±0.004)
Floating Lead Protusions max. 0.25 (0.01)
Dimensions in Millimeters (Inches)
Lead Coplanarity = 0.1 mm (0.004 Inches)
4.580
+ 0.254
0
0.180
+ 0.010
0.000
( )
6.807
+ 0.127
0
0.268
+ 0.005
0.000
( )
1.27 (0.050) BSG
35°
NOM.
0.750 ±0.250
(0.0295 ±0.010)
11.500 ±0.25
(0.453 ±0.010)
0.254 ±0.050
(0.010 ±0.002)
1.590 ±0.127
(0.063 ±0.005) 3.180 ±0.127
(0.125 ±0.005)
0.45 (0.018)
7.62 (0.300) 1.270 (0.050) 1.905 (0.075)
12.650 (0.498) 0.760 (0.030)
5
Recommended Pb-Free IR Prole
Recommended reow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-M484/P484/W484 is approved by the following organizations:
IEC/EN/DIN EN 60747-5-5 (Option 060 only)
Approved with Maximum Working Insulation Voltage VIORM = 567 Vpeak for ACPL-M484, VIORM = 891 Vpeak for ACPL-P484
and VIORM = 1140 Vpeak for ACPL-W484
UL
Approval under UL 1577, component recognition program up to VISO = 3750 VRMS File E55361 for ACPL-M484 & ACPL-
P484;
Approval under UL 1577, component recognition program up to VISO = 5000 VRMS File E55361 for ACPL-W484;
CSA
Approval under CSA Component Acceptance Notice #5, File CA 88324.
Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (ACPL-M484/P484/W484 Option 060)
Description Symbol ACPL-M484 ACPL-P484 ACPL-W484 Unit
Installation classication per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
I – IV
I – III
I – II
I – IV
I – III
I – II
I – IV
I – III
I – II
Climatic Classication 55/105/21 55/105/21 55/105/21
Pollution Degree (DIN VDE 0110/1.89) 2 2 2
Maximum Working Insulation Voltage VIORM 567 891 1140 Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial discharge < 5 pC
VPR 1063 1670 2137 Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec,
Partial discharge < 5 pC
VPR 907 1426 1824 Vpeak
Highest Allowable Overvoltage
(Transient Overvoltage tini = 60 sec)
VIOTM 6000 6000 8000 Vpeak
Safety-limiting values – maximum values allowed in
the event of a failure.
Case Temperature
Input Current
Output Power
TS
IS, INPUT
PS, OUTPUT
175
230
600
175
230
600
175
230
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V RS>109>109>109Ω
* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/
DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test proles.
6
Table 2. Insulation and Safety Related Specications
Parameter Symbol ACPL-M484 ACPL-P484 ACPL-W484 Units Conditions
Minimum External Air Gap
(External Clearance)
L(101) 5.0 7.0 8.0 mm Measured from input terminals to
output terminals, shortest distance
through air.
Minimum External Tracking
(External Creepage)
L(102) 5.0 8.0 8.0 mm Measured from input terminals to
output terminals, shortest distance
path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08 0.08 0.08 mm Through insulation distance conductor
to conductor, usually the straight line
distance thickness between the
emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
CTI >175 >175 >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa IIIa IIIa Material Group (DIN VDE 0110, 1/89,
Table 1)
Table 3. Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Note
Storage Temperature TS-55 125 °C
Operating Temperature TA-40 105 °C
Average Input Current IF(avg) 10 mA
Peak Transient Input Current
(<1 µs pulse width, 300 pps)
(<200 µs pulse width, < 1% duty cycle)
IF(tran)
1.0
40
A
mA
Reverse Input Voltage VR5 V
Average Output Current IO50 mA
Supply Voltage VCC 0 35
Output Voltage VO-0.5 35
Total Package Power Dissipation (ACPL-M484) PT145 mW 1
Total Package Power Dissipation PT210 mW 1
Solder Reow Temperature Prole See Reow Thermal Prole.
Table 4. Recommended Operating Conditions
Parameter Symbol Min. Max. Units Note
Power Supply Voltage (1) VCC 4.5 30 V 2
Forward Input Current (ON) IF(ON) 4 7 mA
Forward Input Voltage (OFF) VF(OFF) – 0.8 V
Operating Temperature TA-40 105 °C
Note:
1. Truth Table guaranteed: 4.5 V to 30 V
7
Table 5. Electrical Specications
Over recommended operating conditions TA = -40° C to 105° C, VCC = +4.5 V to 30 V, IF(ON)= 4 mA to 7 mA, VF(OFF) = 0 V to
0.8 V, unless otherwise specied. All typical values at TA = 25° C.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Logic Low Output Voltage VOL 0.3 V IOL = 3.5 mA 1, 3
0.5 IOL = 6.5 mA
Logic High Output Voltage VOH VCC -0.3 VCC -0.04 V IOH = -3.5 mA 2, 3, 7
Vcc -0.5 VCC -0.07 IOH = -6.5 mA
Logic Low Supply Current ICCL 1.5 3.0 mA VCC = 5.5 V, VF = 0 V, Io = 0 mA
1.7 3.0 mA VCC = 20 V, VF = 0 V, Io = 0 mA
Logic High Supply Current ICCH 1.5 3.0 mA VCC = 5.5 V, IF = 7 mA, Io = 0 mA
1.7 3.0 mA VCC = 30 V, IF = 7 mA, Io = 0 mA
Threshold Input Current
Low to High
IFLH 0.8 2.2 mA
Threshold Input Voltage
High to Low
VFHL 0.8 V IF = 4 mA
Logic Low Short Circuit
Output Current
IOSL 125 200 mA VO = VCC = 5.5 V, VF = 0 V 3
125 200 mA VO = VCC = 30 V, VF = 0 V
Logic High Short Circuit
Output Current
IOSH -200 -125 mA VCC = 5.5 V, IF = 7 mA, VO = GND 3
-200 -125 mA VCC = 20 V, IF = 7 mA, VO = GND
Input Forward Voltage VF1.3 1.5 1.7 V TA = 25° C, IF = 4 mA 4
1.85 V IF = 4 mA
Input Reverse Breakdown
Voltage
BVR5 V IR = 10 µA
Input Diode Temperature
Coecient
∆VF/∆TA1.7 mV/°C IF = 4 mA
Input Capacitance CIN 60 pF f = 1 MHz, VF = 0 V 4
8
Table 6. Switching Specications
Over recommended operating conditions TA = -40° C to 105° C, VCC = +4.5 V to 30 V, IF(ON) = 4 mA to 7 mA, VF(OFF) = 0 V
to 0.8 V, unless otherwise specied. All typicals at TA = 25° C.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Propagation Delay Time
to Logic Low Output Level
tPHL 95 150 ns CL = 100 pF, IF(ON) = 4 mA →VF = 0 V 5, 6, 8 6
150 Loaded as per Fig. 5
Propagation Delay Time
to Logic High Output Level
tPLH 85 120 ns CL = 100 pF, VF = 0 V → IF(ON) = 4 mA 5, 6, 8 6
120 Loaded as per Fig. 5
Pulse Width Distortion |tPHL - tPLH|
= PWD
90 ns CL = 100 pF 9
90 Loaded as per Fig. 5
Propagation Delay
Dierence Between
Any 2 Parts
PDD -130 130 ns CL = 100 pF 10
-130 130 Loaded as per Fig. 5
Output Rise Time (10-90%) tr6 ns 5
Output Fall Time (90-10%) tf6 ns 5
Logic High Common Mode
Transient Immunity
|CMH| 30 kV/µs|VCM| = 1000 V, IF = 4.0 mA,
VCC = 5 V, TA = 25° C
9 7
Logic Low Common Mode
Transient Immunity
|CML| 30 kV/µs|VCM| = 1000 V, VF = 0 V,
VCC = 5 V, TA = 25° C
9 7
Table 7. Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary
Withstand Voltage*
VISO 3750 (ACPL-M484/P484)
5000 (ACPL-W484)
Vrms RH < 50%, t = 1 min.
TA = 25° C
5, 8
Input-Output Resistance RI-O 1012 Ohm VI-O = 500 Vdc 5
Input-Output Capacitance CI-O 0.6 pF f = 1 MHz, VI-O = 0 Vdc 5
* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating, refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable).
UVLO
Figure 10a & b show typical output waveforms during Power-up and Power-down processes.
Notes:
1. Derate total package power dissipation, PT, linearly above 70° C free-air temperature at a rate of 4.5mW/°C(ACPL-P484/W484) and linearly above
85° C free-air temperature at a rate of 0.75mW/°C(ACPL-M484).
2. Detector requires a Vcc of 4.5 V or higher for stable operation as output might be unstable if Vcc is lower than 4.5 V. Be sure to check the power
ON/OFF operation other than the supply current.
3. Duration of output short circuit time should not exceed 500 µs.
4. Input capacitance is measured between pin 1 and pin 3.
5. Device considered a two-terminal device: pins 1, 2 and 3 shorted together and pins 4, 5 and 6 shorted together.
6. The tPLH propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of the
output pulse. The tPHL propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the trailing
edge of the output pulse.
7. CMH is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, VO > 2.0 V.
CML is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, VO < 0.8 V. Note:
Equal value split resistors (Rin/2) must be used at both ends of the LED.
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS for one second (leakage detection
current limit, II-O < = 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN
60747-5-5 Insulation Characteristics Table, if applicable.
9. Pulse Width Distortion (PWD) is dened as |tPHL - tPLH | for any given device.
10. The dierence of tPLH and tPHL between any two devices under the same test condition.
11. Use of a 0.1 µF bypass capacitor connected between pins Vcc and Ground is recommended.
9
Figure 1. Typical Logic Low Output Voltage vs. Temperature Figure 2. Typical Logic High Output Current vs. Temperature
Figure 3. Typical Output Voltage vs. Forward Input Current Figure 4. Typical Input Diode Forward Characteristic
Figure 5. Circuit for tPLH, tPHL, tr, tf
TA - TEMPERATURE - °C
VOL - LOW LEVEL OUTPUT VOLTAGE - V
IO = 6.5 mA
IO = 3.5 mA
PULSE GEN.
tr = tf = 5 ns
f = 100 kHz
1% DUTY
CYCLE
Vo = 5 V
Zo = 50
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0.045
-40 -10 20 50 80 110
VCC = 4.5 V
VF = 0 V
0
1
2
3
4
5
0 0.5 1 1.5 2 2.5 3
IF - INPUT CURRENT - mA
Vo - OUTPUT VOLTAGE - V
VCC = 4.5 V
TA = 25° C
*0.1 µF BYPASS – SEE NOTE 11
0.02
0.04
0.06
0.08
0.1
-40 -10 20 50 80 110
TA - TEMPERATURE - °C
(VCC-VOH) - High Level Output Voltage - V
IF = 4 mA
IO = -6.5 mA
IO = -3.5 mA
0.00001
0.00010
0.00100
0.01000
0.10000
1.00000
10.00000
100.00000
1.1 1.2 1.3 1.4 1.5 1.6
IF - FORWARD CURRENT - mA
VF - FORWARD VOLTAGE - V
TA = 25° C
R1
INPUT
MONITORING
NODE
*
C1 =
15 pF 5 kΩ
D1
D2
D3
D4
619 Ω
5 V
OUTPUT Vo
MONITORING
NODE
VCC
tPLH tPHL
VOH
1.3 V
VOL (0 V)
INPUT IF
OUTPUT V
50% IF(ON)
0 mA
IF(ON)
61
52
43 SHIELD
THE PROBE AND JIG CAPACITANCES ARE
INCLUDED IN C1.
7 mA4 mAIF(ON)
560 Ω1000 Ω
R1
ALL DIODES ARE EITHER 1N916 OR 1N3064
10
Figure 6. Typical Propagation Delays vs. Temperature Figure 7. Typical Logic High Output Voltage vs. Supply Voltage
Figure 8. Typical Propagation Delay vs. Supply Voltage
Figure 9. Test Circuit for Common Mode Transient Immunity and Typical Waveforms
60
80
100
120
0 5 10 15 20 25 30 35
VCC - Supply Voltage - V
Tp - Propagation Delay - ns
60
80
100
120
-40 -10 20 50 80 110
TA - Temperature - °C
Tp - Propagation Delay - ns
VO - Output Voltage - V
|VCM|
0 V
VCM
(PEAK)
CMHCML
IF = 4 mA
TA = 25° C
A
RIN/2
B
+
–
VFF 0.1 µF
VCC
OUTPUT Vo
MONITORING
NODE
+ –
VCM
VCC = 4.5 V TPHL (IF = 4 mA)
TPHL (IF = 7 mA)
TPLH (IF = 4 mA)
TPLH (IF = 7 mA)
0
5
10
15
20
25
30
35
50 10 15 20 25 30 35
VCC - Supply Voltage - V
TA = 25° C
TPHL (IF = 4 mA)
TPHL (IF = 7 mA)
TPLH (IF = 4 mA)
TPLH (IF = 7 mA)
RIN/2
VOH
OUTPUT Vo
SWITCH AT A: IF = 4 mA
Vo (MIN.)*
SWITCH AT B: VF = 0 V
VOL
Vo (MAX.)*
* SEE NOTE 7
61
52
43 SHIELD
11
Vcc = 2~4 V Vcc
Output
i. LED is ON
High
Impedance
state
High
Impedance
state
Discharge delay,
depending on the
power supply slew rate
Vcc = 2~4 V
0 V
10 V
1 ms
Vcc = 1.8 V (typ) Vcc = 1.8 V (typ)
Vcc
Output
ii. LED is OFF Discharge delay,
depending on the
power supply slew rate
0 V
10V
1 ms
High
Impedance
state
High
Impedance
state
Vcc = 2~4 V Vcc = 2~4 V
Vcc = 1.8 V (typ) Vcc = 1.8 V (typ)
Figure 10a. Vcc Ramp when LED is ON
Figure 10b. Vcc Ramp when LED is OFF
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Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-2947EN - September 23, 2013
Thermal Model for ACPL-P484/W484
SO6 Package Optocoupler
Denitions
R11: Junction to Ambient Thermal Resistance of LED due
to heating of LED
R12: Junction to Ambient Thermal Resistance of LED due
to heating of Detector (Output IC)
R21: Junction to Ambient Thermal Resistance of Detector
(Output IC) due to heating of LED.
R22: Junction to Ambient Thermal Resistance of Detector
(Output IC) due to heating of Detector (Output IC).
P1: Power dissipation of LED (W).
P2: Power dissipation of Detector / Output IC (W).
T1: Junction temperature of LED (˚C).
T2: Junction temperature of Detector (˚C).
Ta: Ambient temperature.
∆T1: Temperature dierence between LED junction and
ambient (˚C).
∆T2: Temperature deference between Detector junction
and ambient.
Ambient Temperature: Junction to Ambient Thermal Re-
sistances were measured approximately 1.25cm above
optocoupler at ~23˚C in still air
Description
This thermal model assumes that an 6-pin single-channel
plastic package optocoupler is soldered into a 7.62 cm x
7.62 cm printed circuit board (PCB). The temperature at
the LED and Detector junctions of the optocoupler can be
calculated using the equations below.
T1 = (R11 * P1 + R12 * P2) + Ta -- (1)
T2 = (R21 * P1 + R22 * P2) + Ta -- (2)
Jedec Specications R11 R12, R21 R22
low K board 167 64, 81 89
high K board 117 31, 39 54
Notes:
1. Maximum junction temperature for above parts: 125 °C.
Thermal Model for ACPL-M484
SO5 Package Optocoupler
Denitions
R11: Junction to Ambient Thermal Resistance of LED due
to heating of LED
R12: Junction to Ambient Thermal Resistance of LED due
to heating of Detector (Output IC)
R21: Junction to Ambient Thermal Resistance of Detector
(Output IC) due to heating of LED.
R22: Junction to Ambient Thermal Resistance of Detector
(Output IC) due to heating of Detector (Output IC).
P1: Power dissipation of LED (W).
P2: Power dissipation of Detector / Output IC (W).
T1: Junction temperature of LED (˚C).
T2: Junction temperature of Detector (˚C).
Ta: Ambient temperature.
∆T1: Temperature dierence between LED junction and
ambient (˚C).
∆T2: Temperature deference between Detector junction
and ambient.
Ambient Temperature: Junction to Ambient Thermal Re-
sistances were measured approximately 1.25cm above
optocoupler at ~23˚C in still air
Description
This thermal model assumes that an 5-pin single-channel
plastic package optocoupler is soldered into a 7.62 cm x
7.62 cm printed circuit board (PCB). The temperature at
the LED and Detector junctions of the optocoupler can be
calculated using the equations below.
T1 = (R11 * P1 + R12 * P2) + Ta -- (1)
T2 = (R21 * P1 + R22 * P2) + Ta -- (2)
Jedec Specications R11 R12, R21 R22
low K board 191 77, 91 99
high K board 126 26, 35 51
Notes:
1. Maximum junction temperature for above parts: 125 °C.
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Authorized Distributor
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ACPL-W484-060E ACPL-P484-500E ACPL-M484-060E ACPL-W484-500E ACPL-M484-500E ACPL-W484-560E
ACPL-P484-560E ACPL-M484-560E ACPL-M484-000E ACPL-P484-000E ACPL-P484-060E ACPL-W484-000E