© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 1 1Publication Order Number:
74LVC574A/D
74LVC574A
Low-Voltage CMOS Octal
D-Type Flip-Flop
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The 74LVC574A is a high performance, non−inverting octal D−type
flip−flop operating from a 1.2 to 3.6 V supply. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A V I specification of 5.5 V allows 74LVC574A inputs to
be safely driven from 5 V devices.
The 74LVC574A consists of 8 edge−triggered flip−flops with
individual D−type inputs and 3−state true outputs. The buffered clock
and buffered Output Enable (OE) are common to all flip−flops. The
eight flip−flops will store the state of individual D inputs that meet the
setup and hold time requirements on the LOW−to−HIGH Clock (CP)
transition. With the OE LOW, the contents of the eight flip−flops are
available at the outputs. When the OE is HIGH, the outputs go to the
high impedance state. The OE input level does not affect the operation
of the flip−flops.
Features
•Designed for 1.2 to 3.6 V VCC Operation
•5 V Tolerant − Interface Capability With 5 V TTL Logic
•Supports Live Insertion and Withdrawal
•IOFF Specification Guarantees High Impedance When VCC = 0 V
•24 mA Output Sink and Source Capability
•Near Zero Static Supply Current in All Three Logic States (10 mA)
Substantially Reduces System Power Requirements
•ESD Performance:
♦Human Body Model >2000 V
♦Machine Model >200 V
•These are Pb−Free Devices
MARKING
DIAGRAM
See detailed ordering and shipping information on page 8 o
f
this data sheet.
ORDERING INFORMATION
1
20
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G= Pb−Free Package
LCV
574A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
1
20
(Note: Microdot may be in either location)
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2
Figure 1. Pinout: 20−Lead (Top View)
1920 18 17 16 15 14
21 34567
VCC
13
8
12
9
11
10
O0 O1 O2 O3 O4 O5 O6 O7 CP
OE D0 D1 D2 D3 D4 D5 D6 D7 GND
Figure 2. Logic Diagram
PIN NAMES
Function
Output Enable Input
Clock Pulse Input
Data Inputs
3−State Outputs
Pins
OE
CP
D0−D7
O0−O7
O0
D0
O1
D1
O2
D2
O3
D3
O4
D4
O5
D5
O6
D6
O7
D7
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
OE
11
1
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
TRUTH TABLE
INPUTS OUTPUTS
OPERATING MODE
OE CP Dn On
L
L↑
↑l
hL
HLoad and Read Register
L↑X NC Hold and Read Register
H↑X Z Hold and Disable Outputs
H
H↑
↑l
hZ
ZLoad Internal Register and Disable Outputs
H = High Voltage Level
h = High Voltage Level One Setup Time Prior to the Low−to−High Clock Transition
L = Low Voltage Level
l = Low Voltage Level One Setup Time Prior to the Low−to−High Clock Transition
NC = No Change, State Prior to Low−to−High Clock Transition
X = High or Low Voltage Level and Transitions are Acceptable
Z = High Impedance State
↑= Low−to−High Transition
↑= Not a Low−to−High Transition; For ICC Reasons, DO NOT FLOAT Inputs
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MAXIMUM RATINGS
Symbol Parameter Condition Value Unit
VCC DC Supply Voltage −0.5 to +6.5 V
VIDC Input Voltage −0.5 ≤ VI ≤ +6.5 V
VODC Output Voltage Output in 3−State −0.5 ≤ VO ≤ +6.5 V
Output in HIGH or LOW State
(Note 1) −0.5 ≤ VO ≤ VCC + 0.5 V
IIK DC Input Diode Current VI < GND −50 mA
IOK DC Output Diode Current VO < GND −50 mA
VO > VCC +50 mA
IODC Output Source/Sink Current ±50 mA
ICC DC Supply Current Per Supply Pin ±100 mA
IGND DC Ground Current Per Ground Pin ±100 mA
TSTG Storage Temperature Range −65 to +150 °C
TLLead Temperature, 1 mm from Case for
10 Seconds TL = 260 °C
TJJunction Temperature Under Bias TJ = 135 °C
qJA Thermal Resistance (Note 2) 110.7 °C/W
MSL Moisture Sensitivity Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. IO absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage Operating Functional 1.65
1.2 3.6
3.6
V
VIInput Voltage 0 5.5 V
VOOutput Voltage
HIGH or LOW State
3−State 0
0VCC
5.5
V
IOH HIGH Level Output Current
VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V −24
−12
mA
IOL LOW Level Output Current
VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V 24
12
mA
TAOperating Free−Air Temperature −40 +125 °C
Dt/DVInput Transition Rise or Fall Rate,
VCC = 1.65 to 2.7 V
VCC = 2.7 to 3.6 V 0
020
10
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions
−40 to +855C−40 to +1255C
Unit
Min Typ
(Note 3) Max Min Typ
(Note 3) Max
VIH HIGH−level input voltage VCC = 1.2 V 1.08 − − 1.08 − − V
VCC = 1.65 V to 1.95 V 0.65 x
VCC − − 0.65 x
VCC − −
VCC = 2.3 V to 2.7 V 1.7 − − 1.7 − −
VCC = 2.7 V to 3.6 V 2.0 − − 2.0 − −
VIL LOW−level input voltage VCC = 1.2 V − − 0.12 − − 0.12 V
VCC = 1.65 V to 1.95 V − − 0.35 x
VCC − − 0.35 x
VCC
VCC = 2.3 V to 2.7 V − − 0.7 − − 0.7
VCC = 2.7 V to 3.6 V − − 0.8 − − 0.8
VOH HIGH−level output voltage VI = VIH or VIL V
IO = −100 mA;
VCC = 1.65 V to 3.6 V VCC −
0.2 − − VCC −
0.3 − −
IO = −4 mA; VCC = 1.65 V 1.2 − − 1.05 − −
IO = −8 mA; VCC = 2.3 V 1.8 − − 1.65 − −
IO = −12 mA; VCC = 2.7 V 2.2 − − 2.05 − −
IO = −18 mA; VCC = 3.0 V 2.4 − − 2.25 − −
IO = −24 mA; VCC = 3.0 V 2.2 − − 2.0 − −
VOL LOW−level output voltage VI = VIH or VIL V
IO = 100 mA;
VCC = 1.65 V to 3.6 V − − 0.2 − − 0.3
IO = 4 mA; VCC = 1.65 V − − 0.45 − − 0.65
IO = 8 mA; VCC = 2.3 V − − 0.6 − − 0.8
IO = 12 mA; VCC = 2.7 V − − 0.4 − − 0.6
IO = 24 mA; VCC = 3.0 V − − 0.55 − − 0.8
IIInput leakage current VI = 5.5 V or GND;
VCC = 3.6 V −±0.1 ±5 − ±0.1 ±20 mA
IOZ OFF−state output current VI = VIH or VIL;
VO = 5.5 V or GND;
VCC = 3.6 V
−±0.1 ±5 − ±0.1 ±20 mA
IOFF Power−of f leakage current VI or VO = 5.5 V; VCC = 0.0 V −±0.1 ±10 − ±0.1 ±20 mA
ICC Supply current VI = VCC or GND; IO = 0 A;
VCC = 3.6 V − 0.1 10 − 0.1 40 mA
DICC Additional supply current per input pin;
VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.7 V to 3.6 V
− 5 500 − 5 5000 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. All typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
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AC ELECTRICAL CHARACTERISTICS (tR = tF = 2.5 ns)
Symbol Parameter Conditions
−40 to +855C−40 to +1255C
Unit
Min Typ
(Note 4) Max Min Typ
(Note 4) Max
tpd Propagation Delay (Note 5)
CP to On VCC = 1.2 V − 17.0 − − − −
ns
VCC = 1.65 V to 1.95 V 4.6 6.4 13.1 4.6 − 15.1
VCC = 2.3 V to 2.7 V 2.6 3.9 7.9 2.6 − 9.1
VCC = 2.7 V 1.5 3.7 8.0 1.5 − 10.0
VCC = 3.0 V to 3.6 V 1.5 3.5 7.0 1.5 − 9.0
ten Enable Time (Note 6)
OE to On VCC = 1.2 V − 19.0 − − − −
ns
VCC = 1.65 V to 1.95 V 1.5 7.0 17.1 1.5 − 19.8
VCC = 2.3 V to 2.7 V 1.5 4.0 9.4 1.5 − 10.9
VCC = 2.7 V 1.5 4.1 8.5 1.5 − 11.0
VCC = 3.0 V to 3.6 V 1.5 3.2 7.5 1.5 − 9.5
tdis Disable Time (Note 7)
OE to On VCC = 1.2 V − 9.0 − − − −
ns
VCC = 1.65 V to 1.95 V 2.5 4.1 10.1 2.5 − 11.6
VCC = 2.3 V to 2.7 V 1.0 2.3 5.7 1.0 − 6.6
VCC = 2.7 V 1.5 3.1 6.5 1.5 − 8.5
VCC = 3.0 V to 3.6 V 1.5 2.9 6.0 1.5 − 7.5
twPulse Width
Clock HIGH or LOW VCC = 1.65 V to 1.95 V 5.0 − − 5.0 − −
ns
VCC = 2.3 V to 2.7 V 4.0 − − 4.0 − −
VCC = 2.7 V 3.3 − − 3.3 − −
VCC = 3.0 V to 3.6 V 3.3 1.7 − 3.3 − −
tsu Set−up Time
Dn to CP VCC = 1.65 V to 1.95 V 4.0 − − 4.0 − −
ns
VCC = 2.3 V to 2.7 V 2.5 − − 2.5 − −
VCC = 2.7 V 2.0 − − 2.0 − −
VCC = 3.0 V to 3.6 V 2.0 0.3 − 2.0 − −
thHold Time
Dn to CP VCC = 1.65 V to 1.95 V 3.0 − − 3.0 − −
ns
VCC = 2.3 V to 2.7 V 2.0 − − 2.0 − −
VCC = 2.7 V 1.5 − − 1.5 − −
VCC = 3.0 V to 3.6 V 1.5 −0.2 − 1.5 − −
fmax Maximum Frequency VCC = 1.65 V to 1.95 V 100 − − 80 − −
MHz
VCC = 2.3 V to 2.7 V 125 − − 100 − −
VCC = 2.7 V 150 − − 120 − −
VCC = 3.0 V to 3.6 V 150 200 − 120 − −
tsk(0) Output Skew Time (Note 8) − − 1.0 − − 1.5 ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
5. tpd is the same as tPLH and tPHL.
6. ten is the same as tPZL and tPZH.
7. tdis is the same as tPLZ and tPHZ.
8. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
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DYNAMIC SWITCHING CHARACTERISTICS
Symbol Characteristic Condition
TA = +25°C
Unit
Min Typ Max
VOLP Dynamic LOW Peak Voltage
(Note 9) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V 0.8
0.6 V
VOLV Dynamic LOW Valley Voltage
(Note 9) VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V −0.8
−0.6 V
9. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol Parameter Condition Typical Unit
CIN Input Capacitance VCC = 3.3 V, VI = 0 V or VCC 5.0 pF
COUT Output Capacitance VCC = 3.3 V, VI = 0 V or VCC 6.0 pF
CPD Power Dissipation Capacitance
(Note 10) Per flip−flop; VI = GND or VCC pF
VCC = 1.65 V to 1.95 V 11.2
VCC = 2.3 V to 2.7 V 13.2
VCC = 3.0 V to 3.6 V 14.9
10.CPD is used to determine the dynamic power dissipation (PD in mW).
PD+CPD VCC 2 fi N)SǒCL VCC 2 foǓwhere:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of outputs switching
∑(CL x VCC2 x fo) = sum of the outputs
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WAVEFORM 3 − PULSE WIDTH
tR = tF = 2.5 ns (or fast as required) from 10% to 90%;
Output requirements: V
OL
≤ 0.8 V, V
OH
≥ 2.0 V
2.7 V
0 V
2.7 V
0 V
1.5 V
1.5 V
tw
1.5 V
1.5 V
tw
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
2.7 V
0 V
≈ 0 V
OE
On
tPZH
≈ 3.0 V
tPHZ
tPZL tPLZ
On
1.5V
1.5V
1.5 V
VCC
VOH - 0.3 V
VOL + 0.3 V
GND
1.5 V
CP
CP
WAVEFORM 1 − PROPAGATION DELAYS,
SETUP AND HOLD TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
2.7 V
0 V
Dn
CP
1.5 V
On
2.7 V
0V
VOH
VOL
tPLH, tPHL
th
ts
1.5 V
1.5 V
fmax
Symbol
VCC
3.3 V ± 0.3 V 2.7 V VCC < 2.7 V
Vmi 1.5 V 1.5 V VCC/2
Vmo 1.5 V 1.5 V VCC/2
VHZ VOL + 0.3 V VOL + 0.3 V VOL + 0.15 V
VLZ VOH − 0.3 V VOH − 0.3 V VOH − 015 V
Figure 3. AC Waveforms
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OPEN
PULSE
GENERATOR
RT
DUT
VCC
RL
R1
CL
6 V
GND
Supply Voltage Input Load VEXT
VCC (V) VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
1.2 VCC ≤ 2 ns 30 pF 1 kWOpen 2 x VCC GND
1.65 − 1.95 VCC ≤ 2 ns 30 pF 1 kWOpen 2 x VCC GND
2.3 − 2.7 VCC ≤ 2 ns 30 pF 500 WOpen 2 x VCC GND
2.7 2.7 V ≤ 2.5 ns 50 pF 500 WOpen 2 x VCC GND
3.0 − 3.6 2.7 V ≤ 2.5 ns 50 pF 500 WOpen 2 x VCC GND
Figure 4. Test Circuit
ORDERING INFORMATION
Device Package Shipping†
74LVC574ADTR2G TSSOP−20
(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
DIM
A
MIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B4.30 4.50 0.169 0.177
C1.20 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.27 0.37 0.011 0.015
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
110
1120
PIN 1
IDENT
A
B
−T−
0.100 (0.004)
C
DGH
SECTION N−N
K
K1
JJ1
N
N
M
F
−W−
SEATING
PLANE
−V−
−U−
S
U
M
0.10 (0.004) V S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E 6.40 0.252
--- ---
S
U0.15 (0.006) T
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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at www.onsemi.com/site/pdf/Patent− Marking.pdf . S CILLC reserves t he right to m ake changes wit hout further notice to any products h erein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all l iabilit y, including wit hout limitation special, consequential o r i ncident al d amages. “Typical” parameters which may be provided in S CILLC d at a sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application b y c ust omer’s technical e xperts. SCILLC does not c onvey a ny license under its p atent r ights n or t he r ights o f o t hers. S CILLC p roducts a re n ot d esigned, i ntended,
or authorized for use as c omponent s i n s yst ems i nt ended f or s urgic al i m plant i nt o the body, or other applications i nt ended to support or sustain l ife, o r f or any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC an d it s officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
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P
UBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
74LVC574A/D
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