FEATURES
eroflex Circuit Technology - Advanced Multichip Modules © SCD3853 REV B 5/18/99
CIRCUIT TECHNOLOGY
www.aeroflex.com
■2 – 128K x 8 SRAMs & 2 – 512K x 8 Flash Die in
One MCM
■Access Times of 25ns (SRAM) and 60ns (Flash)
or 35ns (SRAM) and 70 or 90ns (Flash)
■Organized as 128K x 16 of SRAM and 512K x 16
of Flash Memory with Separate Data Buses
■Both Blocks of Memory are User Configurable as
512KX8 AND 1MX8 Respectively
■Low Power CMOS
■Input and Output TTL Compatible Design
■MIL-PRF-38534 Compliant MCMs Available
■Decoupling Capacitors and Multiple Grounds for
Low Noise
■Industrial and Military Temperature Ranges
■Industry Standard Pinouts
■Packaging – Hermetic Ceramic
● 66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder,
Aeroflex code# "P3"
● 66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
● 68 Lead, .94" x .94" x .140" Single-Cavity Small
Outline Gull Wing, Aeroflex code# "F18" (Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
■DESC SMD – TBD
FLASH MEMORY FEATURES
■Sector Architecture (Each Die)
● 8 Equal Sectors of 64K bytes each
● Any combination of sectors can be erased with one
command sequence
■+5V Programing, +5V Supply
■Embedded Erase and Program Algorithms
■Hardware and Software Write Protection
■Internal Program Control Time.
■10,000 Erase / Program Cycles
Pin Description
FI/O0-15 Flash Data I/O
SI/O0-15 SRAM Data I/O
A0–18 Address Inputs
FWE1-2 Flash Write Enables
SWE1-2 SRAM Write Enables
FCE1-2 Flash Chip Enables
SCE1-2 SRAM Chip Enables
OE Output Enable
NC Not Connected
VCC Power Supply
GND Ground
128Kx8
FCE2
OE
A0 – A18
SI/O0-7 SI/O8-15 FI/O0-7 FI/O8-15
8 8 8 8
FCE1FWE2FWE1SWE2SWE1SCE1SCE2
Block Diagram – PGA Type Packages (P3 & P7) & CQFP (F18)
SRAM
128Kx8
SRAM
512Kx8
Flash
512Kx8
Flash
ACT–SF2816 High Speed
Note: Programming information available upon request
128Kx16 SRAM / 512Kx16 FLASH
Multichip Module
Aeroflex Circuit Technology SCD3853 REV B 5/18/99 Plainview NY (516) 694-6700
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Absolute Maximum Ratings
Symbol Rating Range Units
TCOperating Temperature -55 to +125 °C
TSTG Storage Temperature -65 to +150 °C
VGMaximum Signal Voltage to Ground -0.5 to +7 V
TLMaximum Lead Temperature (10 seconds) 300 °C
Parameter
Flash Data Retention 10 Years
Flash Endurance (Write/Erase Cycles) 10,000
Normal Operating Conditions
Symbol Parameter Minimum Maximum Units
VCC Power Supply Voltage +4.5 +5.5 V
VIH Input High Voltage +2.2 VCC + 0.3 V
VIL Input Low Voltage -0.5 +0.8 V
Capacitance
(VIN = 0V, f = 1MHz, TC = 25°C)
Symbol Parameter Maximum Units
CAD A0 – A18 Capacitance 50 pF
COEOE Capacitance 50 pF
CWE1,2 F/S Write Enable Capacitance 20 pF
CCE1,2 F/S Chip Enable Capacitance 20 pF
CI/OI/O0 – I/O15 Capacitance 20 pF
These parameters are guaranteed by design but not tested
DC Characteristics
(VCC = 5.0V, VSS = 0V, Tc = -55°C to +125°C, unless otherwise indicated)
Parameter Sym Conditions Min Max Units
Input Leakage Current ILI VCC = Max, VIN =0toVCC 10 µA
Output Leakage Current ILO FCE = SCE = VIH, OE = VIH,
VOUT =0toVCC
10 µA
SRAM Operating Supply Current x 16
Mode ICCx16 SCE = VIL, OE = VIH, f = 5MHz, VCC =
Max, FCE = VIH
325 mA
Standby Current ISB FCE = SCE = VIH, OE = VIH, f = 5MHz,
VCC = Max 40 mA
SRAM Output Low Voltage VOL IOL = 8 mA, VCC = Min, FCE = VIH 0.4 V
SRAM Output High Voltage VOH IOH = -4.0 mA, , VCC = Min, FCE = VIH 2.4 V
Flash Vcc Active Current for Read (1) ICC1 FCE = VIL, OE = VIH, SCE = VIH 130 mA
Flash Vcc Active Current for Program
or Erase (2) ICC2 FCE = VIL, OE = VIH, SCE = VIH 150 mA
Flash Output Low Voltage VOL IOL = 8 mA, VCC = Min, SCE = VIH 0.45 V
Flash Output High Voltage VOH IOH = -2.5 mA, , VCC = Min, SCE = VIH 0.85 x VCC V
Flash Low Vcc Lock Out Voltage VLKO 3.2 V
Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The
frequency component typically is less than 2mA/MHz, with OE at VIH 2) ICC active while Embedded Algorithim (program or
erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
Aeroflex Circuit Technology SCD3853 REV B 5/18/99 Plainview NY (516) 694-6700
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SRAM AC Characteristics
(VCC = 5.0V, VSS= 0V, Tc= -55°C to +125°C)
Read Cycle
Parameter Symbol –025
Min Max
–035
Min Max Units
Read Cycle Time tRC 25 35 ns
Address Access Time tAA 25 35 ns
Chip Select Access Time tACE 25 35 ns
Output Hold from Address Change tOH 0 0 ns
Output Enable to Output Valid tOE 15 20 ns
Chip Select to Output in Low Z * tCLZ 3 3 ns
Output Enable to Output in Low Z * tOLZ 0 0 ns
Chip Deselect to Output in High Z * tCHZ 12 20 ns
Output Disable to Output in High Z * tOHZ 12 20 ns
* Parameters guaranteed by design but not tested
Write Cycle
Parameter Symbol –025
Min Max
–035
Min Max Units
Write Cycle Time tWC 25 35 ns
Chip Select to End of Write tCW 20 25 ns
Address Valid to End of Write tAW 20 25 ns
Data Valid to End of Write tDW 15 20 ns
Write Pulse Width tWP 20 25 ns
Address Setup Time tAS 0 0 ns
Output Active from End of Write * tOW 0 0 ns
Write to Output in High Z * tWHZ 10 20 ns
Data Hold from Write Time tDH 0 0 ns
Address Hold Time tAH 0 0 ns
* Parameters guaranteed by design but not tested
Truth Table
Mode SCE OE SWE Data I/O Power
Standby HX X High Z Standby
Read L L HData Out Active
Output Disable LH H High Z Active
Write LXLData In Active
Aeroflex Circuit Technology SCD3853 REV B 5/18/99 Plainview NY (516) 694-6700
4
Timing Diagrams — SRAM
DI/O
tRC
tOH
tAA
Data ValidPrevious Data Valid
tOE
High Z
tOHZ
Read Cycle Timing Diagrams
Data Valid
tCLZ
SCE
OE
tACEtCHZ
UNDEFINED DON’T CARE
Read Cycle 2 (SWE = VIH)
Write Cycle (SCE Controlled, OE = VIH )
tCW
tAS tWP
tDW
tOW
SCE
SWE
Data Valid
Write Cycle (SWE Controlled, OE = VIH)
DI/O
AC Test Circuit
IOL
Parameter Typical Units
Input Pulse Level 0 – 3.0 V
Input Rise and Fall 5ns
Input and Output Timing Reference Level 1.5 V
Notes:
1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance
ZO=75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance
load circuit. 6) ATE Tester includes jig capacitance.
IOH
To Device Under Test VZ ~ 1.5 V (Bipolar Supply)
Current Source
Current Source
CL = 50 pF
tWC
tAWtAH
tRC
tAA
tOLZ
SEE NOTE
SEE NOTE
SEE NOTE
SEE NOTE
Note: Guaranteed by design, but not tested.
DI/O
tDH
tWHZ
SEE NOTE
Read Cycle 1 (SCE = OE = VIL, SWE = VIH)
Write Cycle Timing Diagrams
tWP
tDW
Data Valid
tWC
tAWtAH
DI/O
tDH
SCE
SWE
tCW
tAS
A0-18
A0-18
A0-18
A0-18
AC Test Conditions
Aeroflex Circuit Technology SCD3853 REV B 5/18/99 Plainview NY (516) 694-6700
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Flash AC Characteristics – Read Only Operations
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Parameter Symbol
JEDEC Stand’d
–60
Min Max
–70
Min Max
–90
Min Max Units
Read Cycle Time tAVAVtRC 60 70 90 ns
Address Access Time tAVQVtACC 60 70 90 ns
Chip Enable Access Time tELQVtCE60 70 90 ns
Output Enable to Output Valid tGLQVtOE30 35 35 ns
Chip Enable to Output High Z (1) tEHQZtDF20 20 20 ns
Output Enable High to Output High Z(1) tGHQZtDF20 20 20 ns
Output Hold from Address, CE or OE Change, Whichever is First tAXQXtOH000 ns
Note 1. Guaranteed by design, but not tested
Flash AC Characteristics – Write / Erase / Program Operations, FWE Controlled
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Parameter Symbol
JEDEC Stand’d
–60
Min Max
–70
Min Max
–90
Min Max Units
Write Cycle Time tAVAC tWC60 70 90 ns
Chip Enable Setup Time tELWLtCE000 ns
Write Enable Pulse Width tWLWHtWP40 45 45 ns
Address Setup Time tAVWLtAS000 ns
Data Setup Time tDVWHtDS40 45 45 ns
Data Hold Time tWHDXtDH 000 ns
Address Hold Time tWLAXtAH 45 45 45 ns
Write Enable Pulse Width High tWHWLtWPH20 20 20 ns
Duration of Byte Programming Operation tWHWH114 TYP 14 TYP 14 TYP µs
Sector Erase Time tWHWH230 30 30 Sec
Read Recovery Time before Write tGHWL000 µs
Vcc Setup Time tVCE50 50 50 µs
Chip Programming Time 50 50 50 Sec
Chip Enable Hold Time tOEH 110 10 10 ns
Chip Erase Time tWHWH3120 120 120 Sec
1. Toggle and Data Polling only.
Flash AC Characteristics – Write / Erase / Program Operations, FCE Controlled
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Parameter Symbol
JEDEC Stand’d
–60
Min Max
–70
Min Max
–90
Min Max Units
Write Cycle Time tAVAC tWC60 70 90 ns
Write Enable Setup Time tWLELtWS000 ns
Chip Enable Pulse Width tELEHtCP40 45 45 ns
Address Setup Time tAVELtAS000 ns
Data Setup Time tDVEHtDS40 45 45 ns
Data Hold Time tEHDXtDH 000 ns
Address Hold Time tELAXtAH 45 45 45 ns
Chip Enable Pulse Width High tEHELtCPH20 20 20 ns
Duration of Byte Programming tWHWH114 TYP 14 TYP 14 TYP µs
Sector Erase Time tWHWH230 30 30 Sec
Read Recovery Time tGHEL000 ns
Chip Programming Time 50 50 50 Sec
Chip Erase Time tWHWH3120 120 120 Sec
Aeroflex Circuit Technology SCD3853 REV B 5/18/99 Plainview NY (516) 694-6700
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AC Waveforms for Flash Memory Read Operations
tOHtCE
tOE
tACC
tRC
tDF
Output Valid High ZHigh Z
Outputs
OE
FWE
FCE
Addresses Addresses Stable
FWE
OE
FCE
Data
Addresses
5.0V
5555H PA
Data Polling
PA
D7 DOUTPDAOH
tWHWH1
tOE
tRC
tCE
tDF
tOH
tAH
tAS
tDH
tWPH
tWP
tDS
tCE
tWC
Write/Erase/Program
Operation for Flash Memory, FWE Controlled
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the deviced.
4. Dout is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
tGHWL
Aeroflex Circuit Technology SCD3853 REV B 5/18/99 Plainview NY (516) 694-6700
7
AC Waveforms Chip/Sector
Erase Operations for Flash Memory
Data
Addresses
VCC
5555H
Data Polling
tAH
FCE
tAS
FWE
5555H 5555H SA2AAAH 2AAAH
tGHWL
tWP
tWPH
tDS
tDH
tCE
tVCE
55H AAH80H 55H 10H/30HAAH
OE
Notes:
1. SA is the sector address for sector erase.
AC Waveforms for Data Polling
During Embedded Algorithm Operations for Flash Memory
tOE
tCH
tWHWH1 or 2
tOE
tOH
tDF
tCE
tOEH
*
* DQ7=Valid Data (The device has completed the Embedded operation).
DQ0–DQ6=Invalid
DQ7DQ7=
Valid Data
DQ0–DQ6
Valid Data
High Z
FCE
DQ7
OE
FWE
DQ0-DQ6
Aeroflex Circuit Technology SCD3853 REV B 5/18/99 Plainview NY (516) 694-6700
8
FWE
OE
FCE
Data
Addresses
5.0V
5555H PA
Data Polling
PA
D7 DOUTPDAOH
tWHWH1
tAHtAS
tDH
tCPH
tCP
tDS
tWS
tWC
tGHWL
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
Write/Erase/Program Operation for Flash Memory, FCE Controlled
Aeroflex Circuit Technology SCD3853 REV B 5/18/99 Plainview NY (516) 694-6700
9
Pin Numbers & Functions
66 Pins — PGA-Type
Pin # Function Pin # Function Pin # Function Pin # Function
1SI/O818 A12 35 FI/O952 FWE1
2SI/O919 Vcc 36 FI/O10 53 FCE1
3SI/O10 20 SCE137 A654 GND
4A13 21 NC 38 A755 FI/O3
5A14 22 SI/O339 NC 56 FI/O15
6A15 23 SI/O15 40 A857 FI/O14
7A16 24 SI/O14 41 A958 FI/O13
8A17 25 SI/O13 42 FI/O059 FI/O12
9SI/O026 SI/O12 43 FI/O160 A0
10 SI/O127 OE 44 FI/O261 A1
11 SI/O228 A18 45 VCC 62 A2
12 SWE229 SWE146 FCE263 FI/O7
13 SCE230 SI/O747 FWE264 FI/O6
14 GND 31 SI/O648 FI/O11 65 FI/O5
15 SI/O11 32 SI/O549 A366 FI/O4
16 A10 33 SI/O450 A4
17 A11 34 FI/O851 A5
All dimensions in inches
1.085 SQ
1.000
.600
TYP
1.000
.100 TYP
.020
.016
.100 TYP
.165
MIN
.160
Pin 56
Pin 66
Pin 11
Pin 1
Bottom View (P7 & P3)
MAX
MAX
.020
.016
.100
.025
.185
MAX
Side View
(P7)
Side View
(P3)
.050 DIA
.035
TYP
TYP TYP
TYP
"P7" — 1.08" SQ PGA Type Package (with shoulders on Pins 1, 11, 56 & 66)
"P3" — 1.08" SQ PGA Type Package Standard (without shoulders)
.145
MIN
Aeroflex Circuit Technology SCD3853 REV B 5/18/99 Plainview NY (516) 694-6700
10
Pin Numbers & Functions
68 Pins — Dual-Cavity CQFP
Pin # Function Pin # Function Pin # Function Pin # Function
1GND 18 GND 35 OE 52 GND
2FCE119 SI/O836 SCE253 FI/O7
3A520 SI/O937 A17 54 FI/O6
4A421 SI/O10 38 SWE255 FI/O5
5A322 SI/O11 39 FWE156 FI/O4
6A223 SI/O12 40 FWE257 FI/O3
7A124 SI/O13 41 A18 58 FI/O2
8A025 SI/O14 42 NC 59 FI/O1
9NC 26 SI/O15 43 NC 60 FI/O0
10 SI/O027 Vcc 44 FI/O15 61 VCC
11 SI/O128 A11 45 FI/O14 62 A10
12 SI/O229 A12 46 FI/O13 63 A9
13 SI/O330 A13 47 FI/O12 64 A8
14 SI/O431 A14 48 FI/O11 65 A7
15 SI/O532 A15 49 FI/O10 66 A6
16 SI/O633 A16 50 FI/O967 SWE1
17 SI/O734 SCE151 FI/O868 FCE2
.015
±.002
.050
TYP
All dimensions in inches
"F18" — CQFP Package
.015
.990 SQ
±.010
.950 SQ
MAX
.800 REF
See Detail “A”
±.002
Pin 60
Pin 44
Pin 43Pin 27
Pin 26
Pin 10
Pin 9
.890 SQ
MAX
Pin 61
.140
REF .640 SQ
REF
.008
±.002
Detail “A”
.010
±.008
.050
Metal spacer
REF
Aeroflex Circuit Technology SCD3853 REV B 5/18/99 Plainview NY (516) 694-6700
11
Ordering Information
Model Number DESC SMD Number Speed Package
ACT–SF2816N–26P3Q TBD 25(S) / 60(F) ns 1.08"sq PGA-Type
ACT–SF2816N–37P3Q TBD 35(S) / 70(F) ns 1.08"sq PGA-Type
ACT–SF2816N–39P3Q TBD 35(S) / 90(F) ns 1.08"sq PGA-Type
ACT–SF2816N–26P7Q TBD 25(S) / 60(F) ns 1.08"sq PGA-Type
ACT–SF2816N–37P7Q TBD 35(S) / 70(F) ns 1.08"sq PGA-Type
ACT–SF2816N–39P7Q TBD 35(S) / 90(F) ns 1.08"sq PGA-Type
ACT–SF2816N–26F18Q TBD 25(S) / 60(F) ns .94"sq CQFP
ACT–SF2816N–37F18Q TBD 35(S) / 70(F) ns .94"sq CQFP
ACT–SF2816N–39F18Q TBD 35(S) / 90(F) ns .94"sq CQFP
Note: (S) = Speed for SRAM, (F) = Speed for FLASH
Part Number Breakdown
ACT– SF28 16 N– 26 P7 Q
Aeroflex Circuit
Technology
Memory Type
SF = SRAM Flash Combo Module
Memory Depth
Memory Width, Bits
Memory Speed Code
Package Type & Size
C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screening *
Q = MIL-PRF-38534 Compliant / SMD
Screening
* Screened to the individual test methods of MIL-STD-883
Surface Mount Packages Thru-Hole Packages
F18 = .94"SQ 68 Lead Dual-Cavity
CQFP
P3 = 1.085"SQ PGA 66 Pins
with out shoulder
P7 = 1.085"SQ PGA 66 Pins
with shoulder
26 = 25ns SRAM & 60ns FLASH
37 = 35ns SRAM & 70ns FLASH
39 = 35ns SRAM & 90ns FLASH
Options, N = none
2 = 2M SRAM, 8 = Locations
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830
Telephone: (516) 694-6700
FAX: (516) 694-6715
Toll Free Inquiries: 1-(800) 843-1553
CIRCUIT TECHNOLOGY
Specifications subject to change without notice.
