Ultralow Distortion
Current Feedback Differential ADC Driver
Data Sheet
ADA4927-1/ADA4927-2
Rev. B Document Feedback
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FEATURES
Extremely low harmonic distortion
−105 dBc HD2 at 10 MHz
−91 dBc HD2 at 70 MHz
−87 dBc HD2 at 100 MHz
−103 dBc HD3 at 10 MHz
−98 dBc HD3 at 70 MHz
−89 dBc HD3 at 100 MHz
Better distortion at higher gains than VF amplifiers
Low input voltage noise: 1.4 nV/√Hz
High speed
−3 dB bandwidth of 2.3 GHz
0.1 dB gain flatness: 150 MHz
Slew rate: 5000 V/µs, 25% to 75%
Fast 0.1% settling time: 10 ns
Low input offset voltage: 0.3 mV typical
Externally adjustable gain
Stability and bandwidth controlled by feedback resistor
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Wide supply operation: +5 V to ±5 V
APPLICATIONS
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Differential line drivers
GENERAL DESCRIPTION
The ADA4927 is a low noise, ultralow distortion, high speed,
current feedback differential amplifier that is an ideal choice for
driving high performance ADCs with resolutions up to 16 bits
from dc to 100 MHz. The output common-mode level can easily be
matched to the required ADC input common-mode levels. The
internal common-mode feedback loop provides exceptional output
balance and suppression of even-order distortion products.
Differential gain configurations are easily realized using an
external feedback network comprising four resistors. The
current feedback architecture provides loop gain that is nearly
independent of closed-loop gain, achieving wide bandwidth,
low distortion, and low noise at higher gains and lower power
consumption than comparable voltage feedback amplifiers.
The ADA4927 is fabricated using the Analog Devices, Inc.,
silicon-germanium complementary bipolar process, enabling
very low levels of distortion with an input voltage noise of only
1.3 nV/√Hz.
FUNCTIONAL BLOCK DIAGRAMS
07574-001
ADA4927-1
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
–FB
+IN
–IN
+FB
PD
–VS
–VS
–VS
–VS
–OUT
+OUT
VOCM
+VS
+VS
+VS
+VS
Figure 1.
07574-002
ADA4927-2
2
1
3
4
5
6
18
17
16
15
14
13
+IN2
–FB2
+V
S1
+V
S1
+FB1
–IN1
–OUT2
PD2
–V
S2
–V
S2
V
OCM1
+OUT1
8
9
10
11
7
+FB2
+V
S2
+V
S2
V
OCM2
12
+OUT2
–IN2
20
19
21
PD1
–OUT1
–V
S1
22 –V
S1
23 –FB1
24 +IN1
Figure 2.
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130110 100 1k
FREQUENCY (MHz)
SPURI OUS- FREE DY NAM IC RANG E ( dBc)
07574-026
V
OUT
,
dm
= 2V p-p
G = 1
G = 10
G = 20
Figure 3. Spurious-Free Dynamic Range vs. Frequency at Various Gains
The low dc offset and excellent dynamic performance of the
ADA4927 make it well suited for a wide variety of data acquisition
and signal processing applications.
The ADA4927-1 is available in a Pb-free, 3 mm × 3 mm 16-lead
LFCSP, and the ADA4927-2 is available in a Pb-free, 4 mm × 4 mm
24-lead LFCSP. The pinouts are optimized to facilitate printed
circuit board (PCB) layout and to minimize distortion. They are
specified to operate over the −40°C to +105°C temperature range.
ADA4927-1/ADA4927-2 Data Sheet
Rev. B | Page 2 of 25
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±5 V Operation ............................................................................. 3
+5 V Operation ............................................................................. 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
Maximum Power Dissipation ..................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 16
Theory of Operation ...................................................................... 17
Definition of Terms .................................................................... 17
Applications Information .............................................................. 18
Analyzing an Application Circuit ............................................ 18
Setting the Closed-Loop Gain .................................................. 18
Estimating the Output Noise Voltage ...................................... 18
Impact of Mismatches in the Feedback Networks ................. 19
Calculating the Input Impedance for an Application Circuit
....................................................................................................... 19
Input Common-Mode Voltage Range ..................................... 21
Input and Output Capacitive AC Coupling ............................ 21
Setting the Output Common-Mode Voltage .......................... 21
Power-Down ............................................................................... 22
Layout, Grounding, and Bypassing .............................................. 23
High Performance ADC Driving ................................................. 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
5/2016—Rev. A to Rev. 0
Changes to Figure 1 and Figure 2 ................................................... 1
Changes to Figure 5 .......................................................................... 8
Changes to Figure 6 .......................................................................... 9
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
8/2009—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 24
10/2008—Revision 0: Initial Version
Data Sheet ADA4927-1/ADA4927-2
Rev. B | Page 3 of 25
SPECIFICATIONS
±5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = − 5 V, VOCM = 0 V, RF = 301 Ω, RG = 301 Ω, RT = 56.2 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 46 for signal definitions.
±DIN to VOUT, dm Performance
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, dm = 0.1 V p-p 2300 MHz
−3 dB Large Signal Bandwidth VOUT, dm = 2.0 V p-p 1500 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 0.1 V p-p, ADA4927-1 150 MHz
VOUT, dm = 0.1 V p-p, ADA4927-2 120 MHz
Slew Rate VOUT, dm = 2 V step, 25% to 75% 5000 V/µs
Settling Time to 0.1% VOUT, dm = 2 V step 10 ns
Overdrive Recovery Time VIN = 0 V to 0.9 V step, G = 10 10 ns
NOISE/HARMONIC PERFORMANCE
See Figure 45 for distortion test circuit
Second Harmonic VOUT, dm = 2 V p-p, 10 MHz −105 dBc
VOUT, dm = 2 V p-p, 70 MHz −91 dBc
VOUT, dm = 2 V p-p, 100 MHz −87 dBc
Third Harmonic VOUT, dm = 2 V p-p, 10 MHz −103 dBc
VOUT, dm = 2 V p-p, 70 MHz −98 dBc
VOUT, dm = 2 V p-p, 100 MHz −89 dBc
IMD f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p −94 dBc
f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p −85 dBc
Voltage Noise (RTI) f = 100 kHz, G = 28 1.4 nV/√Hz
Input Current Noise f = 100 kHz, G = 28 14 pA/√Hz
Crosstalk f = 100 MHz, ADA4927-2 −75 dB
INPUT CHARACTERISTICS
Offset Voltage VIP = VIN = VOCM = 0 V −1.3 +0.3 +1.3 mV
t
MIN
to t
MAX
variation
±1.5
µV/°C
Input Bias Current −15 +0.5 +15 µA
tMIN to tMAX variation ±0.1 µA/°C
Input Offset Current −10.5 −0.6 +10.5 µA
Input Resistance Differential 14 Ω
Common mode 120 kΩ
Input Capacitance Differential 0.5 pF
Input Common-Mode Voltage Range −3.5 +3.5 V
Common-Mode Rejection Ratio (CMRR) ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V −70 −93 dB
Open-Loop Transresistance DC 120 185 kΩ
OUTPUT CHARACTERISTICS
Output Voltage Swing Each single-ended output, RF = RG = 10 kΩ −3.8 +3.8 V
Linear Output Current 65 mA p-p
Output Balance Error ∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V, 10 MHz,
see Figure 44 for test circuit
−65 dB
ADA4927-1/ADA4927-2 Data Sheet
Rev. B | Page 4 of 25
VOCM to VOUT, cm Performance
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
Small Signal −3 dB Bandwidth VOUT, cm = 100 mV p-p 1300 MHz
Slew Rate VIN = −1.0 V to +1.0 V, 25% to 75% 1000 V/µs
Input Voltage Noise (RTI) f = 100 kHz 15 nV/√Hz
V
OCM
INPUT CHARACTERISTICS
Input Voltage Range ±3.5 V
Input Resistance 3.8 5.0 7.5 kΩ
Input Offset Voltage VOS, cm = VO UT, cm, VDIN+ = VDIN− = +VS/2 −10 −2 +5.2 mV
VOCM CMRR ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V −70 −97 dB
Gain ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V 0.90 0.97 1.00 V/V
General Performance
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range 4.5 11.0 V
Quiescent Current per Amplifier 20.0 22.1 mA
tMIN to tMAX variation ±9.0 µA/°C
Powered down 2.4 mA
Power Supply Rejection Ratio ΔVOUT, dm/ΔVS, ΔVS = 1 V −70 −89 dB
POWER-DOWN (PD)
PD Input Voltage Powered down <1.8 V
Enabled >3.2 V
Turn-Off Time To 0.1% 15 µs
Turn-On Time To 0.1% 400 ns
PD Pin Bias Current per Amplifier
Enabled PD = 5 V −2 +2 µA
Disabled PD = 0 V −110 −90 µA
OPERATING TEMPERATURE RANGE
−40
+105
°C
Data Sheet ADA4927-1/ADA4927-2
Rev. B | Page 5 of 25
+5 V OPERATION
TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = 2.5 V, RF = 301 Ω, RG = 301 Ω, RT = 56.2 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 46 for signal definitions.
±DIN to VOUT, dm Performance
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, dm = 0.1 V p-p 2000 MHz
−3 dB Large Signal Bandwidth VOUT, dm = 2.0 V p-p 1300 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 0.1 V p-p, ADA4927-1 150 MHz
VOUT, dm = 0.1 V p-p, ADA4927-2 110 MHz
Slew Rate VOUT, dm = 2 V step, 25% to 75% 4200 V/µs
Settling Time to 0.1% VOUT, dm = 2 V step 10 ns
Overdrive Recovery Time VIN = 0 V to 0.15 V step, G = 10 10 ns
NOISE/HARMONIC PERFORMANCE See Figure 45 for distortion test circuit
Second Harmonic VOUT, dm = 2 V p-p, 10 MHz −104 dBc
V
OUT, dm
= 2 V p-p, 70 MHz
−91
dBc
VOUT, dm = 2 V p-p, 100 MHz −86 dBc
Third Harmonic VOUT, dm = 2 V p-p, 10 MHz −95 dBc
VOUT, dm = 2 V p-p, 70 MHz −80 dBc
VOUT, dm = 2 V p-p, 100 MHz −76 dBc
IMD f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p −93 dBc
f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p −84 dBc
Voltage Noise (RTI) f = 100 kHz, G = 28 1.4 nV/√Hz
Input Current Noise f = 100 kHz, G = 28 19 pA/√Hz
Crosstalk f = 100 MHz, ADA4927-2 −75 dB
INPUT CHARACTERISTICS
Offset Voltage VIP = VIN = VOCM = 0 V −1.3 +0.3 +1.3 mV
tMIN to tMAX variation ±1.5 µV/°C
Input Bias Current −30 −12 +4.0 µA
t
MIN
to t
MAX
variation
±0.12
µA/°C
Input Offset Current −10.5 −0.8 +10.5 µA
Input Resistance Differential 14 Ω
Common mode 120 kΩ
Input Capacitance Differential 0.5 pF
Input Common-Mode Voltage Range 1.3 3.7 V
CMRR ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V −70 −96 dB
Open-Loop Transresistance DC 120 185 kΩ
OUTPUT CHARACTERISTICS
Output Voltage Swing
Each single-ended output
+1.0
+4.0
V
Linear Output Current 50 mA p-p
Output Balance Error ∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V, 10 MHz,
see Figure 44 for test circuit
−65 dB
ADA4927-1/ADA4927-2 Data Sheet
Rev. B | Page 6 of 25
VOCM to VOUT, cm Performance
Table 5.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
Small signal −3 dB Bandwidth VOUT, cm = 100 mV p-p 1300 MHz
Slew Rate VIN = 1.5 V to 3.5 V, 25% to 75% 1000 V/µs
Input Voltage Noise (RTI) f = 100 kHz 15 nV/√Hz
V
OCM
INPUT CHARACTERISTICS
Input Voltage Range 1.5 to 3.5 V
Input Resistance 3.8 5.0 7.5 kΩ
Input Offset Voltage VOS, cm = VOUT, cm, VDIN+ = VDIN− = +VS/2 −5.0 +2.0 +10 mV
VOCM CMRR ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V −70 −100 dB
Gain ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V 0.90 0.97 1.00 V/V
General Performance
Table 6.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range 4.5 11.0 V
Quiescent Current per Amplifier 20 21.6 mA
tMIN to tMAX variation ±7.0 µA/°C
Powered down 0.6 mA
Power Supply Rejection Ratio ΔVOUT, dm/ΔVS, ΔVS = 1 V −70 −89 dB
POWER-DOWN (PD)
PD Input Voltage Powered down <1.7 V
Enabled >3.0 V
Turn-Off Time 20 μs
Turn-On Time 500 ns
PD Pin Bias Current per Amplifier
Enabled PD = 5 V −2 +2 µA
Disabled PD = 0 V −105 −95 µA
OPERATING TEMPERATURE RANGE
−40
+105
°C
Data Sheet ADA4927-1/ADA4927-2
Rev. B | Page 7 of 25
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
Supply Voltage 11 V
Power Dissipation
See Figure 4
Input Currents +IN, −IN, PD ±5 mA
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD 51-7.
Table 8.
Package Type θJA Unit
16-Lead LFCSP (Exposed Pad) 87 °C/W
24-Lead LFCSP (Exposed Pad) 47 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4927 package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes the properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4927. Exceeding a
junction temperature of 150°C for an extended period can result
in changes in the silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, throughholes, ground, and power
planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the single 16-lead LFCSP
(87°C/W) and the dual 24-lead LFCSP (47°C/W) on a JEDEC
standard
4-layer board with the exposed pad soldered to a PCB pad that
is connected to a solid plane.
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–40 –20 020 40
AMBI ENT T E M P E RATURE (°C)
60 80 100
MAXIMUM POWER DISSIPATIO N (W)
07574-003
ADA4927-2
ADA4927-1
Figure 4. Maximum Power Dissipation vs.
Ambient Temperature for a 4-Layer Board
ESD CAUTION
ADA4927-1/ADA4927-2 Data Sheet
Rev. B | Page 8 of 25
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
07574-005
NOTES
1. CO NNECT THE EXPOSED PADDLE TO ANY PLANE
BET WEEN AND I N CLUDIN G +V
S
AND –V
S
.
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
–FB
+IN
–IN
+FB
PD
–V
S
–V
S
–V
S
–V
S
–OUT
+OUT
V
OCM
+V
S
+V
S
+V
S
+V
S
TOP VIEW
(No t t o Scale)
ADA4927-1
Figure 5. ADA4927-1 Pin Configuration
Table 9. ADA4927-1 Pin Function Descriptions
Pin No. Mnemonic Description
1 −FB Negative Output for Feedback Component Connection
2 +IN Positive Input Summing Node
3 −IN Negative Input Summing Node
4 +FB Positive Output for Feedback Component Connection
5 to 8 +VS Positive Supply Voltage
9 VOCM Output Common-Mode Voltage
10 +OUT Positive Output for Load Connection
11 −OUT Negative Output for Load Connection
12 PD Power-Down Pin
13 to 16 −VS Negative Supply Voltage
17 (EPAD) Exposed Pad (EPAD) Connect the exposed pad to any plane between and including +VS and −VS.
Data Sheet ADA4927-1/ADA4927-2
Rev. B | Page 9 of 25
TOP VI EW
(Not to Scale)
NOTES
1. CO NNECT THE EXPOSED PADDLE TO ANY PLANE
BET W E E N AND I NCL UDING +V
S
AND –V
S
.
07574-006
ADA4927-2
2
1
3
4
5
6
18
17
16
15
14
13
+IN2
–FB2
+V
S1
+V
S1
+FB1
–IN1
–OUT2
PD2
–V
S2
–V
S2
V
OCM1
+OUT1
8
9
10
11
7
+FB2
+V
S2
+V
S2
V
OCM2
12
+OUT2
–IN2
20
19
21
PD1
–OUT1
–V
S1
22 –V
S1
23 –FB1
24 +IN1
Figure 6. ADA4927-2 Pin Configuration
Table 10. ADA4927-2 Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN1 Negative Input Summing Node 1
2 +FB1 Positive Output Feedback 1
3, 4 +VS1 Positive Supply Voltage 1
5 −FB2 Negative Output Feedback 2
6 +IN2 Positive Input Summing Node 2
7 −IN2 Negative Input Summing Node 2
8 +FB2 Positive Output Feedback 2
9, 10 +VS2 Positive Supply Voltage 2
11 VOCM2 Output Common-Mode Voltage 2
12 +OUT2 Positive Output 2
13 −OUT2 Negative Output 2
14 PD2 Power-Down Pin 2
15, 16 −VS2 Negative Supply Voltage 2
17 VOCM1 Output Common-Mode Voltage 1
18 +OUT1 Positive Output 1
19 −OUT1 Negative Output 1
20 PD1 Power-Down Pin 1
21, 22 −VS1 Negative Supply Voltage 1
23 −FB1 Negative Output Feedback 1
24 +IN1 Positive Input Summing Node 1
25 (EPAD) Exposed Pad (EPAD) Connect the exposed pad to any plane between and including +VS and −VS.
ADA4927-1/ADA4927-2 Data Sheet
Rev. B | Page 10 of 25
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −V S = −5 V, VOCM = 0 V, RG = 301 Ω, RF = 301 Ω, RT = 56.2 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted.
Refer to Figure 43 for basic test setup. Refer to Figure 46 for signal definitions.
3
0
–3
–6
–9
–12110 100 1k 10k
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
07574-007
V
OUT
,
dm
= 100mV p - p
G = 1, RF = 301Ω
G = 10, RF = 442Ω
G = 20, RF = 604Ω
Figure 7. Small Signal Frequency Response for Various Gains
3
0
–3
–6
–9110 100 1k 10k
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
07574-008
V
OUT
,
dm
= 100mV p - p
V
S
= ±5V
V
S
= ±2. 5V
Figure 8. Small Signal Frequency Response for Various Supplies
3
0
–3
–6
–9
–12110 100 1k 10k
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
07574-009
V
OUT
,
dm
= 100mV p - p
T
A
+25° C
T
A
+105°C
T
A
–40°C
Figure 9. Small Signal Frequency Response for Various Temperatures
3
0
–3
–6
–9
–12110 100 1k 10k
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
07574-010
V
OUT
,
dm
= 2V p-p
G = 1, RF = 301Ω
G = 10, RF = 442Ω
G = 20, RF = 604Ω
Figure 10. Large Signal Frequency Response for Various Gains
3
0
–3
–6
–910 100 1k 10k
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
07574-011
VOUT,dm = 2V p-p
VS = ±5V
VS = ±2. 5V
Figure 11. Large Signal Frequency Response for Various Supplies
3
0
–3
–6
–9
–12110 100 1k 10k
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
07574-012
V
OUT
,
dm
= 2V p-p
T
A
+25° C
T
A
+105°C
T
A
–40°C
Figure 12. Large Signal Frequency Response for Various Temperatures
Data Sheet ADA4927-1/ADA4927-2
Rev. B | Page 11 of 25
3
0
–3
–6
–9
–12110 100 1k 10k
FREQUENCY (MHz)
07574-013
V
OUT
,
dm
= 100mV p - p
R
L
= 200Ω
R
L
= 1kΩ
CLOSED-LOOP GAIN (dB)
Figure 13. Small Signal Frequency Response for Various Loads
3
0
–3
–6
–9
–12110 100 1k 10k
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
07574-014
V
OUT
,
dm
= 100mV p - p
V
OCM
= –4V
V
OCM
= –3.5V
V
OCM
= 0V
V
OCM
= +3. 5V
V
OCM
= +4V
Figure 14. Small Signal Frequency Response at Various VOCM Levels
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5110 100 1k
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
07574-015
V
OUT
,
dm
= 100mV p - p
V
S
= ±5V, R
L
= 1kΩ
V
S
= ±2. 5V , R
L
= 1kΩ
V
S
= ±5V, R
L
= 200Ω
V
S
= ±2. 5V , R
L
= 200Ω
Figure 15. 0.1 dB Flatness Small Signal Frequency Response for Various
Loads and Supplies
3
0
–3
–6
–9
–12110 100 1k 10k
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
07574-016
V
OUT
,
dm
= 2V p-p
R
L
= 1kΩ
R
L
= 200Ω
Figure 16. Large Signal Frequency Response for Various Loads
3
0
–3
–6
–9
–12110 100 1k 10k
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
07574-017
V
OCM
= –3.5V
V
OCM
= 0V
V
OCM
= +3. 5V
V
OUT
,
dm
= 2V p-p
Figure 17. Large Signal Frequency Response at Various VOCM Levels
3
0
–3
–6
–9
–12110 100 1k 5k
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
07574-018
V
OUT
,
cm
= 100mV p - p
V
OCM
= 0V d c
V
OCM
= +2. 5V dc
V
OCM
= +4. 1V dc
V
OCM
= –2.5V dc
V
OCM
= –4.1V dc
Figure 18. VOCM Small Signal Frequency Response at Various DC Levels
ADA4927-1/ADA4927-2 Data Sheet
Rev. B | Page 12 of 25
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130110 100 1k
FREQUENCY (MHz)
HARMO NI C DISTORTI ON (d Bc)
07574-019
V
OUT
,
dm
= 2V p-p
HD2, R
L
= 1kΩ
HD3, R
L
= 1kΩ
HD2, R
L
= 200Ω
HD3, R
L
= 200Ω
Figure 19. Harmonic Distortion vs. Frequency at Various Loads
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130110 100 1k
FREQUENCY (MHz)
HARMO NI C DISTORTI ON (d Bc)
07574-020
V
OUT
,
dm
= 2V p-p
HD2, V
S
= ±5V
HD3, V
S
= ±5V
HD2, V
S
= ±2. 5V
HD3, V
S
= ±2. 5V
Figure 20. Harmonic Distortion vs. Frequency at Various Supplies
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–1.2 –1.0 –0.8 –0.6 –0.4 –0.2 00.2 0.4 0.6 0.8 1.0 1.2
V
OCM
(V)
HARMO NI C DISTORTI ON (d Bc)
07574-021
V
OUT
,
dm
= 2V p-p
HD2, 10M Hz
HD3, 10M Hz
Figure 21. Harmonic Distortion vs. VOCM at 10 MHz, ±2.5 V Supplies
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130110 100 1k
FREQUENCY (MHz)
HARMO NI C DISTORTI ON (d Bc)
07574-022
V
OUT
,
dm
= 2V p-p
HD2, G = 1
HD3, G = 1
HD2, G = 10
HD3, G = 10
HD2, G = 20
HD3, G = 20
Figure 22. Harmonic Distortion vs. Frequency at Various Gains
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–1300 1 2 3 4 5 6 7 8 9
V
OUT
,
dm
(V p-p)
HARMO NI C DISTORTI ON (d Bc)
07574-023
V
OUT
,
dm
= 2V p-p
HD2, V
S
= ±5V
HD3, V
S
= ±5V
HD2, V
S
= ±2. 5V
HD3, V
S
= ±2. 5V
Figure 23. Harmonic Distortion vs. VOUT, dm and Supply Voltage, f = 10 MHz
–40
–50
–60
–70
–80
–90
–100
–110
–120–4 –3 –2 –1 01 2 3 4
V
OCM
(V)
HARMO NI C DISTORTI ON (d Bc)
07574-024
V
OUT
,
dm
= 2V p-p
HD2, 10M Hz
HD3, 10M Hz
Figure 24. Harmonic Distortion vs. VOCM at 10 MHz, ±5 V Supplies
Data Sheet ADA4927-1/ADA4927-2
Rev. B | Page 13 of 25
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130110 100 1k
FREQUENCY (MHz)
HARMO NI C DISTORTI ON (d Bc)
07574-025
V
S
= ±2. 5V
HD2, V
OUT
,
dm
= 2V p-p
HD3, V
OUT
,
dm
= 2V p-p
HD2, V
OUT
,
dm
= 1V p-p
HD3, V
OUT
,
dm
= 1V p-p
Figure 25. Harmonic Distortion vs. Frequency at Various VOUT, dm
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130110 100 1k
FREQUENCY (MHz)
SPURI OUS- FREE DY NAM IC RANG E ( dBc)
07574-026
V
OUT
,
dm
= 2V p-p
G = 1
G = 10
G = 20
Figure 26. Spurious-Free Dynamic Range vs. Frequency at Various Gains
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90110 100 1k
FREQUENCY (MHz)
CMRR (dB)
07574-027
R
L
,
dm
= 200Ω
Figure 27. CMRR vs. Frequency
20
0
–20
–40
–60
–80
–100
–120
69.6 69.7 69.8 69.9 70.0 70.1 70.2 70.3 70.4 70.5
FREQUENCY (MHz)
NORM ALIZED SP E CTRUM ( dBc)
07574-028
V
OUT
,
dm
= 2V p-p
Figure 28. 70 MHz Intermodulation Distortion
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
0.1 110 100 1k
FREQUENCY (MHz)
CROSS TAL K ( dB)
07574-029
INPUT AMP 2 TO OUT P UT AMP1
INPUT AMP 1 TO OUT P UT AMP2
Figure 29. Crosstalk vs. Frequency for ADA4927-2
–50
–60
–70
–20
–30
–40
–80
–90110 100 1k
FREQUENCY (MHz)
PSRR (dB)
07574-030
RL, dm = 200Ω
VS = ±5V, –PSRR
VS = ±5V, +PSRR
Figure 30. Power Supply Rejection Ratio vs. Frequency
ADA4927-1/ADA4927-2 Data Sheet
Rev. B | Page 14 of 25
–50
–60
–70
–30
–40
–80110 100 1k
FREQUENCY (MHz)
OUT P UT BAL ANCE ( dB)
07574-031
R
L
,
dm
= 200Ω
Figure 31. Output Balance vs. Frequency
–30
–40
–50
0
–10
–20
–60
–70110 100 1k
FREQUENCY (MHz)
RETURN LO S S ( dB)
07574-032
S11
S22
RL, dm = 200Ω
INPUT SINGLE-ENDED, 50Ω LOAD TERMINATION
OUTPUT DIFFERENTIAL, 100Ω SOURCE TERMINATION
S11: COMMON-MODE-TO-COMMON-MODE
S22: DIFFERENTIAL-TO-DIFFERENTIAL
Figure 32. Return Loss (S11, S12) vs. Frequency
100
10
110 100 1k 10k 100k 1M 10M 100M
FREQUENCY ( Hz )
INPUT VOLTAGE NOISE (nV/ Hz)
07574-033
Figure 33. Voltage Noise Spectral Density, Referred to Input
1k
100
10
1
0.1
50
0
–50
–100
–150
–200
10 100 1k 10k 100k 1M 10M 100M 1G 10G
FREQUENCY ( Hz )
IMPEDANCE MAGNITUDE (kΩ)
IM PE DANCE P HAS E ( Degrees)
07574-034
MAGNITUDE
PHASE
Figure 34. Open-Loop Transimpedance Magnitude and Phase vs. Frequency
35
30
25
20
15
10
5
0
–5
–10
0.1 110 100 1k
FREQUENCY (MHz)
CLOSED-LOOP OUTPUT IMPEDANCE (Ω)
07574-035
V
OP
, V
S
= ±5V
V
ON
, V
S
= ±5V
V
OP
, V
S
= ±2. 5V
V
ON
, V
S
= ±2. 5V
Figure 35. Closed-Loop Output Impedance Magnitude vs. Frequency at
Various Supplies, G = 1
10
5
0
–5
–10010 20 30 40 50 60 70 80 90 100
TIME (ns)
VOLTAGE (V)
07574-036
VIN × 10
VOUT, dm
Figure 36. Overdrive Recovery, G = 10
Data Sheet ADA4927-1/ADA4927-2
Rev. B | Page 15 of 25
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–600 1 2 3 4 5
TIME (ns)
678910
DIFFERENTIAL OUTPUT VOLTAGE (mV)
07574-037
Figure 37. Small Signal Pulse Response
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–600 1 2 3 4 5
TIME (ns)
678910
DIFFERENTIAL OUTPUT VOLTAGE (mV)
07574-038
Figure 38. VOCM Small Signal Pulse Response
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–10 010 20 30 40
TIME (ns)
50 60 70 80 90
INPUT SIGNAL (mV )
ERROR ( %)
07574-039
ERROR
INPUT
Figure 39. Settling Time
1.0
0.5
0
–0.5
–1.001 2 3 4 5
TIME (ns)
678910
DIFFERENTIAL OUTPUT VOLTAGE (mV)
07574-040
Figure 40. Large Signal Pulse Response
1.5
1.0
0.5
0
–1.0
–0.5
–1.501 2 3 4 5
TIME (ns)
6 7 8 9 10
COMMON-MODE OUTPUT VOL T AGE (mV)
07574-041
Figure 41. VOCM Large Signal Pulse Response
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
–0.25
0 1 2 3 4 5
TIME (µs)
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
07574-042
PD VOLTAGE (V)
OUTPUT VOLTAGE (V)
PD
V
OUT
,
dm
Figure 42. PD Response Time
ADA4927-1/ADA4927-2 Data Sheet
Rev. B | Page 16 of 25
TEST CIRCUITS
ADA4927 1kΩ
+5V
–5V
301Ω
301Ω50Ω
301Ω
0.1µF
301Ω
DC-COUPLED
GENERATOR
56.2Ω
VIN
07574-043
Figure 43. Equivalent Basic Test Circuit, G = 1
ADA4927
+5V
0.1µF –5V
301Ω
301Ω
50Ω
301Ω
NETWORK
ANALYZER
OUTPUT
AC-COUPLED
301Ω
49.9Ω
49.9Ω
V
OCM
56.2Ω
V
IN
07574-044
DIFFERENTIAL
NETWORK
ANALYZER INPUT
DIFFERENTIAL
NETWORK
ANALYZER INPUT
50Ω
50Ω
Figure 44. Test Circuit for Output Balance, CMRR
ADA4927
+5V
–5V
301Ω
301Ω50Ω
301Ω
442Ω
442Ω
0.1µF
301Ω
VOCM
56.2Ω
25.5Ω
261Ω
200Ω HP
LP
2:1 50Ω
CT
VIN
LOW-PASS
FILTER
0.1µF
0.1µF
DUAL
FILTER
07574-045
DC-COUPLED
GENERATOR
Figure 45. Test Circuit for Distortion Measurements
Data Sheet ADA4927-1/ADA4927-2
Rev. B | Page 17 of 25
THEORY OF OPERATION
The ADA4927 differs from conventional operational amplifiers
in that it has two outputs whose voltages move in opposite
directions and an additional input, VOCM. Moreover, the ADA4927
uses a current feedback architecture. Like a traditional current
feedback operational amplifier, the ADA4927 relies on high
open-loop trans-impedance, T(s), and negative current feedback to
force the outputs to the desired voltages. The ADA4927 behaves
much like a standard current feedback operational amplifier and
facilitates single-ended-to-differential conversions, common-mode
level shifting, and amplifications of differential signals. Also, like
a current feedback operational amplifier, the ADA4927 has low
input impedance summing nodes, which are actually emitter-
follower outputs. The ADA4927 outputs are low impedance,
and the closed-loop output impedances are equal to the open-loop
output impedances divided by a factor of 1 + loop gain. Because
it uses current feedback, the ADA4927 manifests a nominally
constant feed-back resistance, bandwidth product. In other
words, the closed-loop bandwidth and stability of the ADA4927
depend primarily on the feedback resistor value. The closed-
loop gain equations for typical configurations are the same as
those of comparable voltage feedback differential amplifiers.
The chief difference is that the ADA4927 dynamic performance
depends on the feed-back resistor value rather than on the noise
gain. Because of this, the elements used in the feedback loops
must be resistive with values that ensure stability and sufficient
bandwidth.
Two feedback loops are employed to control the differential and
common-mode output voltages. The differential feedback loops
use a current feedback architecture with external resistors and
control only the differential output voltage. The common-mode
feedback loop is internal, uses voltage feedback, and controls only
the common-mode output voltage. This architecture makes it
easy to set the output common-mode level to any arbitrary
value within the specified limits. The output common-mode
voltage is forced, by the internal common-mode loop, to be
equal to the voltage applied to the VOCM input.
The internal common-mode feedback loop produces outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. This results
in differential outputs that are very close to the ideal of being
identical in amplitude and are exactly 180° apart in phase.
DEFINITION OF TERMS
+IN
–IN +OUT
–OUT
+D
IN
–
FB
+FB
–D
IN
V
OCM
R
G
R
F
R
G
V
OUT, dm
R
L, dm
R
F
ADA4927
07574-046
Figure 46. Circuit Definitions
Differential Voltage
Differential voltage refers to the difference between two
node voltages. For example, the output differential voltage (or
equivalently, output differential-mode voltage) is defined as
VOUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common ground reference.
Similarly, the differential input voltage is defined as
VIN, dm = (+DIN − (−DIN))
Common-Mode Voltage
Common-mode voltage refers to the average of two node voltages
with respect to the local ground reference. The output
common-mode voltage is defined as
VOUT, cm = (V+OUT + V−OUT)/2
Balance
Output balance is a measure of how close the differential signals
are to being equal in amplitude and opposite in phase. Output
balance is most easily determined by placing a well-matched
resistor divider between the differential voltage nodes and
comparing the magnitude of the signal at the divider midpoint
with the magnitude of the differential signal (see Figure 44). By
this definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage.
dmOUT
cmOUT
V
V
ErrorBalanceOutput
,
,
ADA4927-1/ADA4927-2 Data Sheet
Rev. B | Page 18 of 25
APPLICATIONS INFORMATION
ANALYZING AN APPLICATION CIRCUIT
The ADA4927 uses high open-loop transimpedance and negative
current feedback to control the differential output voltage in
such a way as to minimize the differential error currents. The
differential error currents are defined as the currents that flow
in and out of the differential inputs labeled +IN and −IN (see
Figure 46). For most purposes, these currents can be assumed
to be zero. The voltage between the +IN and −IN inputs is
internally bootstrapped to 0 V; therefore, the voltages at the
amplifier inputs are equal, and external analysis can be carried
out in a similar fashion to that of voltage feedback amplifiers.
Similarly, the difference between the actual output common-
mode voltage and the voltage applied to VOCM can also be assumed
to be zero. Starting from these principles, any application circuit
can be analyzed.
SETTING THE CLOSED-LOOP GAIN
Using the approach previously described, the differential gain of
the circuit in Figure 46 can be determined by
G
F
dmIN
dmOUT
R
R
V
V=
,
,
This presumes that the input resistors (RG) and feedback
resistors (RF) on each side are of equal value.
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4927 can be estimated
using the noise model in Figure 47. The input-referred noise
voltage density, vnIN, is modeled as a differential input, and the
noise currents, inIN− and inIN+, appear between each input and
ground. The output voltage due to vnIN is obtained by multiplying
vnIN by the noise gain, GN (defined in the GN equation). The
noise currents are uncorrelated with the same mean-square value,
and each produces an output voltage that is equal to the noise
current multiplied by the associated feedback resistance. The
noise voltage density at the VOCM pin is vnCM. When the feedback
networks have the same feedback factor, as in most cases, the
output noise due to vnCM is common mode. Each of the four
resistors contributes (4kTRxx)1/2. The noise from the feedback
resistors appears directly at the output, and the noise from each
gain resistor appears at the output multiplied by RF/RG. Table 11
summarizes the input noise sources, the multiplication factors,
and the output-referred noise density terms.
ADA4927
+
R
F2
V
nOD
V
nCM
V
OCM
V
nIN
R
F1
R
G2
R
G1
V
nRF1
V
nRF2
V
nRG1
V
nRG2
inIN+
inIN–
07574-047
Figure 47. Noise Model
Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks
Input Noise Contribution Input Noise Term
Input Noise
Voltage Density
Output
Multiplication Factor
Differential Output Noise
Voltage Density Term
Differential Input vnIN vnIN GN vnO1 = GN(vnIN)
Inverting Input inIN inIN × (RF2) 1 vnO2 = (inIN)(RF2)
Noninverting Input
i
nIN
i
nIN
× (R
F1
)
1
v
nO3
= (i
nIN
)(R
F1
)
VOCM Input vnCM vnCM 0 vnO4 = 0
Gain Resistor, RG1 vnRG1 (4kTRG1)1/2 RF1/RG1 vnO5 = (RF1/RG1)(4kTRG1)1/2
Gain Resistor, RG2 vnRG2 (4kTRG2)1/2 RF2/RG2 vnO6 = (RF2/RG2)(4kTRG2)1/2
Feedback Resistor, RF1 vnRF1 (4kTRF1)1/2 1 vnO7 = (4kTRF1)1/2
Feedback Resistor, RF2 vnRF2 (4kTRF2)1/2 1 vnO8 = (4kTRF2)1/2
Data Sheet ADA4927-1/ADA4927-2
Rev. B | Page 19 of 25
Table 12. Differential Input, DC-Coupled
Nominal Gain (dB) RF (Ω) RG (Ω) RIN, dm (Ω) Differential Output Noise Density (nV/√Hz)
0 301 301 602 8.0
20 442 44.2 88.4 21.8
26 604 30.1 60.2 37.9
Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω
Nominal Gain (dB) RF (Ω) RG1 (Ω) RT (Ω) RIN, cm (Ω) RG2 (Ω)1 Differential Output Noise Density (nV/√Hz)
0 309 301 56.2 401 328 8.1
20 511 39.2 158 73.2 77.2 18.6
26 806 28 649 54.2 74.4 29.1
1 RG2 = RG1 + (RS||RT).
Similar to the case of a conventional operational amplifier, the
output noise voltage densities can be estimated by multiplying
the input-referred terms at +IN and −IN by the appropriate output
factor,
where:
( )
21
N
ββ
G+
=2
is the circuit noise gain.
G1
F1
G1
1RR
R
β+
=
and
G2
F2
G2
2RR
R
β+
=
are the feedback factors.
When the feedback factors are matched, RF1/RG1 = RF2/RG2,
β1 = β2 = β, and the noise gain becomes
G
F
N
R
R
β
G+== 1
1
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
∑
=
=
8
1i
2
nOinOD
vv
Table 12 and Table 13 list several common gain settings, associated
resistor values, input impedance, and output noise density for
both balanced and unbalanced input configurations.
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
The gain from the VOCM pin to VO, dm is equal to
2(β1 − β2)/(β1 + β2)
When β1 = β2, this term goes to zero and there is no differential
output voltage due to the voltage on the VOCM input (including
noise). The extreme case occurs when one loop is open and the
other has 100% feedback; in this case, the gain from VOCM input
to VO, dm is either +2 or −2, depending on which loop is closed.
The feedback loops are nominally matched to within 1% in
most applications, and the output noise and offsets due to the
VOCM input are negligible. If the loops are intentionally mismatched
by a large amount, it is necessary to include the gain term from
VOCM to VO, dm and account for the extra noise. For example, if
β1 = 0.5 and β2 = 0.25, the gain from VOCM to VO, dm is 0.67. If the
VOCM pin is set to 2.5 V, a differential offset voltage is present at the
output of (2.5 V)(0.67) = 1.67 V. The differential output noise
contribution is (15 nV/√Hz)(0.67) = 10 nV/√Hz. Both of these
results are undesirable in most applications; therefore, it is best
to use nominally matched feedback factors.
Mismatched feedback networks also result in a degradation of
the ability of the circuit to reject input common-mode signals,
much the same as for a four-resistor difference amplifier made
from a conventional operational amplifier.
As a practical summarization of the previous issues, resistors of
1% tolerance produce a worst-case input CMRR of approximately
40 dB, a worst-case differential-mode output offset of 25 mV
due to a 2.5 V VOCM input, negligible VOCM noise contribution,
and no significant degradation in output balance error.
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 48, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = RG + RG = 2 × RG.
+VS
–VS
ADA4927
+IN
–IN
R
F
R
F
+D
IN
–D
IN
V
OCM
R
G
R
G
V
OUT, dm
07574-048
Figure 48. The ADA4927 Configured for Balanced (Differential) Inputs
ADA4927-1/ADA4927-2 Data Sheet
Rev. B | Page 20 of 25
For an unbalanced, single-ended input signal (see Figure 49),
the input impedance is
( )
+×
−
=
F
G
F
G
SEIN
RR
R
R
R
2
1
,
ADA4927
R
L
V
OUT, dm
+V
S
–V
S
RG
RG
RF
RF
VOCM
RIN, SE
07574-049
Figure 49. The ADA4927 with Unbalanced (Single-Ended) Input
The input impedance of the circuit is effectively higher than it
would be for a conventional operational amplifier connected as
an inverter because a fraction of the differential output voltage
appears at the inputs as a common-mode signal, partially boot-
strapping the voltage across the input resistor RG. The common-
mode voltage at the amplifier input terminals can be easily
determined by noting that the voltage at the inverting input is equal
to the noninverting output voltage divided down by the voltage
divider formed by RF and RG in the lower loop. This voltage is
present at both input terminals due to negative voltage feedback
and is in phase with the input signal, thus reducing the effective
voltage across RG in the upper loop and partially bootstrapping RG.
Terminating a Single-Ended Input
This section deals with how to properly terminate a single-
ended input to the ADA4927 with a gain of 1, RF = 348 Ω, and
RG = 348 Ω. An example using an input source with a terminated
output voltage of 1 V p-p and a source resistance of 50 Ω illustrates
the four simple steps that must be followed. Note that, because
the terminated output voltage of the source is 1 V p-p, the open
circuit output voltage of the source is 2 V p-p. The source shown
in Figure 50 indicates this open-circuit voltage.
1. The input impedance must be calculated using the following
formula:
Ω464
)348348(2 348
1
348
)(2
1=
+×
−
=
+×
−
=
FG
F
G
IN
RR
R
R
R
R
S
50Ω
V
S
2V p-p
R
IN
464Ω
ADA4927
R
L
V
OUT, dm
+V
S
–V
S
R
G
348Ω
R
G
348Ω
R
F
348Ω
R
F
348Ω
V
OCM
07574-050
Figure 50. Calculating Single-Ended Input Impedance RIN
2. To match the 50 Ω source resistance, the termination
resistor, RT, is calculated using RT||464 Ω = 50 Ω. The
closest standard 1% value for RT is 56.2 Ω.
ADA4927
R
L
V
OUT, dm
+V
S
–V
S
R
S
50Ω
R
G
348Ω
R
G
348Ω
R
F
348Ω
R
F
348Ω
V
OCM
V
S
2V p-p
R
IN
50Ω
R
T
56.2Ω
07574-051
Figure 51. Adding Termination Resistor RT
3. It can be seen from Figure 51 that the effective RG in the
upper feedback loop is now greater than the RG in the
lower loop due to the addition of the termination resistors.
To compensate for the imbalance of the gain resistors,
a correction resistor (RTS) is added in series with RG in the
lower loop. RTS is equal to the Thevenin equivalent of the
source resistance RS and the termination resistance RT and
is equal to RS||RT.
RS
50Ω
VS
2V p-p
R
T
56.2Ω
R
TH
26.5Ω
V
TH
1.06V p-p
07574-052
Figure 52. Calculating the Thevenin Equivalent
Data Sheet ADA4927-1/ADA4927-2
Rev. B | Page 21 of 25
RTS = RTH = RS||RT = 26.5 Ω. Note that VTH is greater than
1 V p-p, which was obtained with RT = 50 Ω. The modified
circuit with the Thevenin equivalent (closest 1% value used for
RTH) of the terminated source and RTS in the lower feedback
loop is shown in Figure 53.
ADA4927
RLVOUT, dm
+VS
–VS
RTH
26.7Ω
RG
348Ω
RG
348Ω
RF
348Ω
RF
348Ω
VOCM
VTH
1.06V p-p
RTS
26.7Ω
07574-053
Figure 53. Thevenin Equivalent and Matched Gain Resistors
Figure 53 presents a tractable circuit with matched
feedback loops that can be easily evaluated.
It is useful to point out two effects that occur with a
terminated input. The first is that the value of RG is increased
in both loops, lowering the overall closed-loop gain. The
second is that VTH is a little larger than 1 V p-p, as it is
when RT = 50 Ω. These two effects have opposite impacts
on the output voltage, and for large resistor values in the
feedback loops (~1 kΩ), the effects essentially cancel each
other out. For small RF and RG, or high gains, however, the
diminished closed-loop gain is not canceled completely by the
increased VTH. This can be seen by evaluating Figure 53.
The desired differential output in this example is 1 V p-p
because the terminated input signal is 1 V p-p and the closed-
loop gain = 1. The actual differential output voltage, however,
is equal to (1.06 V p-p)(348/374.7) = 0.984 V p-p. To obtain
the desired output voltage of 1 V p-p, a final gain adjustment
can be made by increasing RF without modifying any of the
input circuitry. This is discussed in Step 4.
4. The feedback resistor value is modified as a final gain
adjustment to obtain the desired output voltage.
To make the output voltage VOUT = 1 V p-p, RF must be
calculated using the following formula:
35
06.1
374.71
,
ppV
ppV
V
RRVDesired
R
TH
TS
G
dmOUT
F
The closest standard 1% values to 353 Ω are 348 Ω and
357 Ω. Choosing 357 Ω for RF gives a differential output
voltage of 1.01 V p-p. The closed-loop bandwidth is
diminished by a factor of approximately 348/357 from
what it would be with RF = 348 Ω due to the inversely
proportional relationship between RF and closed-loop
gain that is characteristic of current feedback amplifiers.
The final circuit is shown in Figure 54.
ADA4927
R
L
V
OUT, dm
1.01V p-p
+V
S
–V
S
R
S
50Ω
R
G
348Ω
R
G
348Ω
R
F
357Ω
R
F
357Ω
V
OCM
V
S
2V p-p
1V p-p
R
T
56.2Ω
R
TS
26.7Ω
07574-054
Figure 54. Terminated Single-Ended-to-Differential System with G = 1
INPUT COMMON-MODE VOLTAGE RANGE
The ADA4927 input common-mode range is centered between the
two supply rails, in contrast to other ADC drivers with level-shifted
input ranges, such as the ADA4937. The centered input common-
mode range is best suited to ac-coupled, differential-to-differential,
and dual supply applications.
For operation with ±5 V supplies, the input common-mode
range at the summing nodes of the amplifier is specified as
−3.5 V to +3.5 V and is specified as +1.3 V to +3.7 V with a
single +5 V supply. To avoid nonlinearities, the voltage swing
at the +IN and −IN terminals must be conned to these ranges.
INPUT AND OUTPUT CAPACITIVE AC COUPLING
Input ac coupling capacitors can be inserted between the source
and RG. This ac coupling blocks the flow of the dc common-
mode feedback current and causes the ADA4927 dc input
common-mode voltage to equal the dc output common-mode
voltage. These ac coupling capacitors must be placed in both
loops to keep the feedback factors matched.
Output ac coupling capacitors can be placed in series between
each output and respective load. See Figure 58 for an example that
uses input and output capacitive ac coupling.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM pin of the ADA4927 is internally biased with a voltage
divider comprising two 10 kΩ resistors at a voltage approximately
equal to the midsupply point, [(+VS) + (−VS)]/2. Because of this
internal divider, the VOCM pin sources and sinks current, depending
on the externally applied voltage and associated source resistance.
Relying on the internal bias results in an output common-mode
voltage that is within about 100 mV of the expected value.
In cases where accurate control of the output common-mode level
is required, it is recommended that an external source or resistor
divider be used with source resistance less than 100 Ω. The output
common-mode offset listed in the Specifications section presumes
that the VOCM input is driven by a low impedance voltage source.
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC; however, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 10 kΩ. If multiple
ADA4927 devices share one ADC reference output, a buffer may
be necessary to drive the parallel inputs.
ADA4927-1/ADA4927-2 Data Sheet
Rev. B | Page 22 of 25
POWER-DOWN
The power-down feature can reduce power consumption when
a particular device is not in use and does not place the output in
a high-Z state when asserted. The ADA4927 is generally enabled
by pulling the power-down pin to the positive supply. See the
Specifications tables for the specific voltages required to assert
and deassert the power-down feature.
Power-Down in Cold Applications
The power-down feature should not be used in applications in
which the ambient temperature falls below 0°C. Contact sales
for information regarding applications that require the power-
down feature to be used at ambient temperatures below 0°C.
Data Sheet ADA4927-1/ADA4927-2
Rev. B | Page 23 of 25
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4927 is sensitive to the PCB
environment in which it operates. Realizing the superior
performance requires attention to the details of high speed
PCB design. This section shows a detailed example of how the
ADA4927-1 was addressed.
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4927-1 as possible.
However, clear the area near the feedback resistors (RF), gain
resistors (RG), and the input summing nodes (Pin 2 and Pin 3) of
all ground and power planes (see Figure 55). Clearing the ground
and power planes minimizes any stray capacitance at these nodes
and prevents peaking of the response of the amplifier at high
frequencies. Whereas ideal current feedback amplifiers are
insensitive to summing node capacitance, real-world amplifiers
can exhibit peaking due to excessive summing node capacitance.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD 51-7.
07574-055
Figure 55. Ground and Power Plane Voiding in Vicinity of RF AND RG
Bypassed the power supply pins as close to the device as
possible and directly to a nearby ground plane. Use high
frequency ceramic chip capacitors. It is recommended that two
parallel bypass capacitors (1000 pF and 0.1 µF) be used for each
supply. The 1000 pF capacitor should be placed closer to the
device. Further away, provide low frequency bulk bypassing,
using 10 µF tantalum capacitors from each supply to ground.
Make signal routing short and direct to avoid parasitic effects.
Wherever complementary signals exist, provide a symmetrical
layout to maximize balanced performance. When routing
differential signals over a long distance, place PCB traces close
together, and twist any differential wiring such that the loop
area is minimized. Doing this reduces radiated energy and
makes the circuit less susceptible to interference.
1.30
0.80
0.80
1.30
07574-056
Figure 56. Recommended PCB Thermal Attach Pad Dimensions (Millimeters)
0.30
PLATED
VIA HOLE
1.30
GRO UND P LANE
POWER P LANE
BOTTOM METAL
TOP METAL
07574-057
Figure 57. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters)
ADA4927-1/ADA4927-2 Data Sheet
Rev. B | Page 24 of 25
HIGH PERFORMANCE ADC DRIVING
The ADA4927 is ideally suited for high gain, broadband ac-
coupled and differential-to-differential applications on a single
supply, though other applications are possible. Compared with
voltage feedback amplifiers, the current feedback architecture
provides superior distortion and bandwidth performance at
high gains. This is because the ideal current feedback amplifier
loop gain depends only on the feedback value and open-loop
transimpedance, T(s).
The circuit in Figure 58 shows a front-end connection for an
ADA4927 driving an AD9445, 14-bit, 105 MSPS ADC, with ac
coupling on the ADA4927 input and output. (The AD9445
achieves optimum performance when driven differentially.) The
ADA4927 eliminates the need for a transformer to drive
the ADC and performs a single-ended-to-differential conversion
and buffering of the driving signal.
The ADA4927 is configured with a single 5 V supply and gain
of 10 for a single-ended input to differential output. The 158 Ω
termination resistor, in parallel with the single-ended input
impedance of approximately 73.2 Ω, provides a 50 Ω termination
for the source. The additional 38.3 Ω at the inverting input closely
matches the parallel impedance of the 50 Ω source and the
termination resistor driving the noninverting input. Because of the
high gain, a few iterations of the termination technique described
in the Terminating a Single-Ended Input section are required.
Two objectives of the design are to make RF close to 500 Ω and
obtain resistor values that are close to standard 1% values.
In this example, the signal generator has a 1 V p-p symmetric,
ground-referenced bipolar output when terminated in 50 Ω.
The VOCM pin of the ADA4927 is bypassed for noise reduction
and left floating such that the internal divider sets the output
common-mode voltage nominally at midsupply. Because the
inputs are ac-coupled, no dc common-mode current flows in
the feedback loops, and a nominal dc level of midsupply is
present at the amplifier input terminals. Besides placing the
amplifier inputs at their optimum levels, the ac coupling technique
lightens the load on the amplifier and dissipates less power than
applications with dc-coupled inputs.
The output of the amplifier is ac-coupled to the ADC through a
second-order, low-pass filter with a cutoff frequency of 100 MHz.
This reduces the noise bandwidth of the amplifier and isolates
the driver outputs from the ADC inputs.
The AD9445 is configured for a 2 V p-p full-scale input by
connecting the SENSE pin to AGND, as shown in Figure 58.
VIN–
VIN+
47pF
30nH
30nH
24.3Ω
24.3Ω
50Ω
SIGNAL
GENERATOR
39.2Ω
39.2Ω
V
OCM
5V
ADA4927
+
158Ω
511Ω
38.3Ω
511Ω
14
BUFFER T/H
ADC
CLOCK/
TIMING REF
SENSEAGND
0.1µF0.1µF
0.1µF0.1µF 0.1µF
AD9445
3.3V ( A)
AVDD1
5V (A)
AVDD2
3.3V ( D)
DRVDD
07574-058
Figure 58. ADA4927 Driving an AD9445 ADC with AC-Coupled Input and Output
Data Sheet ADA4927-1/ADA4927-2
Rev. B | Page 25 of 25
OUTLINE DIMENSIONS
1.45
1.30 SQ
1.15
111808-A
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12 13
4
EXPOSED
PAD
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
0.50
0.40
0.30
SEATING
PLANE
0.05 M AX
0.02 NO M
0.20 REF
0.25 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
0.30
0.23
0.18
COMPLIANT
TO
JEDEC STANDARDS M O-220-WEE D.
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURAT ION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.80
0.75
0.70
Figure 59. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-21)
Dimensions shown in millimeters
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.18
COMPLIANT
TO
JEDEC STANDARDS M O-220- WGGD.
03-11-2013-A
BOTTOM VIEWTOP VI EW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70
0.20 REF
0.25 M IN
3.16 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
2.65
2.50 SQ
2.45
1
24
7
12
13
18
19
6
0.05 M AX
0.02 NO M
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURAT ION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 60. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
Ordering Quantity
Branding
ADA4927-1YCPZ-R2
−40°C to +105°C
16-Lead LFCSP_VQ
CP-16-21
250
H1N
ADA4927-1YCPZ-RL
−40°C to +105°C
16-Lead LFCSP_VQ
CP-16-21
5,000
H1N
ADA4927-1YCPZ-R7 −40°C to +105°C 16-Lead LFCSP_VQ CP-16-21 1,500 H1N
ADA4927-2YCPZ-R2 −40°C to +105°C 24-Lead LFCSP_VQ CP-24-7 250
ADA4927-2YCPZ-RL −40°C to +105°C 24-Lead LFCSP_VQ CP-24-7 5,000
ADA4927-2YCPZ-R7 −40°C to +105°C 24-Lead LFCSP_VQ CP-24-7 1,500
1 Z = RoHS Compliant Part.
©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07574-0-5/16(B)
