SEMICONDUCTOR TECHNICAL DATA Quad R-S Latches The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical "1" or high on the enable input; a logical "0" or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs. L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 * Double Diode Input Protection * Three-State Outputs with Common Enable * Outputs Capable of Driving Two Low-power TTL Loads or One Low- Power Schottky TTL Load Over the Rated Temperature Range * Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = - 55 to 125C for all packages. MC14043B S0 R0 S1 R1 S2 R2 S3 4 MC14044B 2 R0 Q0 3 S0 6 9 R1 Q1 7 12 VDD = PIN 16 VSS = PIN 8 NC = PIN 13 10 Q2 S1 R2 11 S2 14 TRUTH TABLE 1 Q3 S R E Q X X 0 High Impedance 15 R3 5 ENABLE 0 0 1 1 0 1 0 1 1 No Change 1 0 1 1 1 1 X = Don't Care R3 4 13 Q0 3 6 9 Q1 7 12 VDD = PIN 16 VSS = PIN 8 NC = PIN 2 10 Q2 11 14 TRUTH TABLE 1 Q3 S R E Q X X 0 High Impedance 15 S3 5 ENABLE 0 0 1 1 0 1 0 1 1 0 1 1 1 0 1 No Change X = Don't Care REV 3 1/94 MC14043B Motorola, Inc. 1995 MC14044B 162 MOTOROLA CMOS LOGIC DATA IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III IIIIII IIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIII IIIIII IIIIIIIIII IIII III III IIII III IIII III IIII III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIII IIIIII IIIIIIIIIIIIIIIIIIII IIII III IIII III IIII III III IIIIII IIIIIIII IIIIII IIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIII III IIII III IIII III III IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol - 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit "0" Level VOL 5.0 10 15 -- -- -- 0.05 0.05 0.05 -- -- -- 0 0 0 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 Vdc "1" Level VOH 5.0 10 15 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 5.0 10 15 -- -- -- 4.95 9.95 14.95 -- -- -- Vdc 5.0 10 15 -- -- -- 1.5 3.0 4.0 -- -- -- 2.25 4.50 6.75 1.5 3.0 4.0 -- -- -- 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 - 4.2 - 0.88 - 2.25 - 8.8 -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 -- -- -- -- IOL 5.0 10 15 0.64 1.6 4.2 -- -- -- 0.51 1.3 3.4 0.88 2.25 8.8 -- -- -- 0.36 0.9 2.4 -- -- -- mAdc Input Current Iin 15 -- 0.1 -- 0.00001 0.1 -- 1.0 Adc Input Capacitance (Vin = 0) Cin -- -- -- -- 5.0 7.5 -- -- pF Quiescent Current (Per Package) IDD 5.0 10 15 -- -- -- 1.0 2.0 4.0 -- -- -- 0.002 0.004 0.006 1.0 2.0 4.0 -- -- -- 30 60 120 Adc Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs all buffers switching) IT 5.0 10 15 Three-State Output Leakage Current ITL 15 Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL "1" Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Vdc Vdc IOH Source (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Sink mAdc IT = (0.58 A/kHz) f + IDD IT = (1.15 A/kHz) f + IDD IT = (1.73 A/kHz) f + IDD -- 0.1 -- 0.0001 0.1 Adc -- 3.0 Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.004. * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages - 12 mW/_C From 100_C To 125_C MOTOROLA CMOS LOGIC DATA MC14043B MC14044B 163 IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII v v IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIII IIIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIII IIIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Vin, Vout lin, lout PD Tstg TL Parameter Value Unit - 0.5 to + 18.0 V Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 V Input or Output Current (DC or Transient), per Pin 10 mA DC Supply Voltage Power Dissipation, per Package Storage Temperature 500 mW - 65 to + 150 _C 260 _C Lead Temperature (8-Second Soldering) * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) VDD Vdc Min Typ # Max 5.0 10 15 -- -- -- 100 50 40 200 100 80 5.0 10 15 -- -- -- 100 50 40 200 100 80 5.0 10 15 -- -- -- 175 75 60 350 175 120 tPHL 5.0 10 15 -- -- -- 175 75 60 350 175 120 ns Set, Set Pulse Width tW 5.0 10 15 200 100 70 80 40 30 -- -- -- ns Reset, Reset Pulse Width tW 5.0 10 15 200 100 70 80 40 30 -- -- -- ns Characteristic Symbol Output Rise Time tTLH = (1.35 ns/pF) CL + 32.5 ns tTLH = (0.60 ns/pF) CL + 20 ns tTLH = (0.40 ns/pF) CL + 20 ns Output Fall Time tTHL = (1.35 ns/pF) CL + 32.5 ns tTHL = (0.60 ns/pF) CL + 20 ns tTHL = (0.40 ns/pF) CL + 20 ns tTLH Propagation Delay Time tPLH = (0.90 ns/pF) CL + 130 ns tPLH = (0.36 ns/pF) CL + 57 ns tPLH = (0.26 ns/pF) CL + 47 ns tPHL = (0.90 ns/pF) CL + 130 ns tPHL = (0.90 ns/pF) CL + 57 ns tPHL = (0.26 ns/pF) CL + 47 ns tPLH Unit ns tTHL ns ns Three-State Enable/Disable Delay tPLZ, 5.0 -- 150 300 tPHZ, 10 -- 80 160 tPZL, 15 -- 55 110 tPZH * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ns AC WAVEFORMS MC14043B MC14044B 20 ns 50% 10% VSS 20 ns RESET 20 ns VDD 90% SET 20 ns 20 ns SET 20 ns 50% Q tPHL 10% VSS 50% RESET tTLH 90% 50% 10% tTLH VOH Q 50% VOL tTHL 90% 10% VSS VOH VOL tPLH tPLH MC14043B MC14044B 164 VSS 20 ns 90% VDD VDD 10% 10% VDD 90% 20 ns 90% tTHL 50% tPHL MOTOROLA CMOS LOGIC DATA THREE-STATE ENABLE/DISABLE DELAYS Set, Reset, Enable, and Switch Conditions for 3-State Tests MC14043B Test tPZH Enable VDD MC14044B S1 S2 Q S R S R Open Closed A VDD VSS VSS VDD tPZL Closed Open B VSS VDD VDD VSS tPHZ Open Closed A VDD VSS VSS VDD tPLZ Closed Open B VSS VDD VDD VSS S1 TO OUTPUT UNDER TEST 1k CL 50 pF S2 VSS VDD ENABLE 50% VSS tPZH VDD 90% QA 10% tPZL tPHZ VOL tPLZ VOH QB 10% VSS PIN ASSIGNMENT MC14043B MC14044B Q3 1 16 VDD Q3 1 16 VDD Q0 2 15 R3 NC 2 15 S3 R0 3 14 S3 S0 3 14 R3 S0 4 13 NC R0 4 13 Q0 E 5 12 S2 E 5 12 R2 S1 6 11 R2 R1 6 11 S2 R1 7 10 Q2 S1 7 10 Q2 VSS 8 9 Q1 VSS 8 9 Q1 NC = NO CONNECTION MOTOROLA CMOS LOGIC DATA MC14043B MC14044B 165 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V -A- 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. -B- C L DIM A B C D E F G H K L M N -T- K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C L S -T- SEATING PLANE K H G D 16 PL 0.25 (0.010) MC14043B MC14044B 166 J M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B- 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C -T- SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CMOS LOGIC DATA *MC14043B/D* MC14043B MC14044B MC14043B/D 167