MAX2369
Complete Dual-Band
Quadrature Transmitter
________________________________________________________________ Maxim Integrated Products 1
REF
N.C.
N.C.
N.C.
N.C.
TANK+
TANK-
IFLO
VCC
SHDN
I-
I+
RFL
RFH
LOCK
VCC
VCC
VCC
TXGATE
IFIN+
IFIN-
N.C.
N.C.
RBIAS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK
DI
CS
VCC
VCC
IFOUT+
IFOUT-
VGC
VCC
VCC
Q+
Q-
GND
GND
GND
GND
LOL
LOH
N.C.
VCC
GND
VCC
IFCP
VCC
MAX2369
+45 -45
90 0
090 /2
IFPLL
/2
Σ
Σ
19-1924; Rev 1; 10/01
General Description
The MAX2369 is a dual-band, triple-mode complete
transmitter for cellular phones. The device takes a differ-
ential I/Q baseband input and mixes it up to IF through a
quadrature modulator and IF variable-gain amplifier
(VGA). The signal is then routed to an external bandpass
filter and upconverted to RF through an SSB mixer and
RF VGA. The signal is further amplified with an on-board
PA driver.
The MAX2369 is designed for dual-band operation and
supports TDMA for the PCS band as well as TDMA and
AMPS for the cellular band. The desired mode of
operation is selected by loading data on the SPI™/
MICROWIRE™-compatible 3-wire serial bus. The
MAX2369 then routes the signals to the appropriate ports
depending on which band is selected. The MAX2369
includes two RF LO input ports and two PA driver ports,
eliminating the need for external switching circuitry.
The MAX2369 takes advantage of the serial bus to set
modes such as charge-pump current, high or low side-
band injection, and IF/RF gain balancing. It is packaged
in a small (7mm ✕7mm) 48-pin QFN package with
exposed paddle.
Applications
Dual-Band TDMA/Amps Handsets
GAIT Handsets
Triple-Mode, Dual-Mode, or Single-Mode
Mobile Phones
Satellite Phones
Wireless Data Links (WAN/LAN)
Wireless Local Area Networks (LANs)
High-Speed Data Modems
High-Speed Digital Cordless Phones
Wireless Local Loop (WLL)
Features
♦Dual-Band, Triple-Mode Operation
♦+7dBm Output Power with -34dBc ACPR
(NADC Modulation)
♦100dB Power Control Range
♦Supply Current Drops as Output Power Is Reduced
♦On-Chip IF VCO and IF PLL
♦QSPI/SPI/MICROWIRE-Compatible 3-Wire Bus
♦Digitally Controlled Operational Modes
♦+2.7V to +5.5V Operation
♦Single Sideband Upconverter Eliminates SAW
Filters
♦Power Control Distributed at IF and RF for
Optimum Dynamic Range
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configuration appears at end of data sheet.
Selector Guide appears at end of data sheet.
Functional Diagram
*Exposed paddle
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
PART TEMP. RANGE PIN-PACKAGE
MAX2369EGM -40°C to +85°C 48 QFN-EP*
MAX2369
Complete Dual-Band
Quadrature Transmitter
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(MAX2369 Test Fixture: VCC = VBATT = +2.75V, SHDN = TXGATE = +2.0V, VGC = +2.5V, RBIAS = 16kΩ, TA= -40°C to +85°C,
unless otherwise noted. Typical values are at TA= +25°C, and operating modes are defined in Table 6.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND...........................................................-0.3V to +3.6V
RFL, RFH.............................................................................+5.5V
DI, CLK, CS, VGC, SHDN, TXGATE,
LOCK.....................................................-0.3V to (VCC + 0.3V)
AC Input Pins (IFIN, Q, I, TANK, REF,
LOL, LOH) ...............................................................1.0V peak
Digital Input Current (SHDN, TXGATE,
CLK, DI, CS) ................................................................±10mA
Continuous Power Dissipation (TA= +70°C)
48-Pin QFN-EP (derate 27mW/°C above +70°C) ..............2.5W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
Operating Supply Voltage 2.7 3.0 V
VGC = 0.5V 80 106
VGC = 2.0V 85 112PCS mode
VGC = 2.5V 120 150
VGC = 0.5V 82 107
VGC = 2.0V 87 113
Cellular
digital mode VGC = 2.5V 123 155
VGC = 0.5V 77 101
VGC = 2.0V 80 105FM mode
VGC = 2.5V 105 133
mA
(Note 1)
Addition for IFLO buffer 6.5 11
TXGATE = 0.6V 16 25
Operating Supply Current
SHDN = 0.6V, sleep mode 0.5 20 µA
Logic High 2.0 V
Logic Low 0.6 V
Logic Input Current -5 +5 µA
VGC Input Current -12 +12 µA
VGC Input Resistance During Shutdown SHDN = 0.6V 200 280 kΩ
Lock Indicator High 50kΩ pullup load VCC - 0.4 V
Lock Indicator Low 50kΩ pullup load 0.4 V
MAX2369
Complete Dual-Band
Quadrature Transmitter
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(MAX2369 Evaluation Kit: 50Ωsystem, operating modes as defined in Table 6, input voltage at I and Q = 200mVRMS differential,
common mode = VCC/2, 300kHz quadrature CW tones, IF synthesizer locked with passive lead-lag second-order loop filter, REF =
200mVp-p at 19.44MHz, VCC = SHDN = CS = TXGATE = +2.75V, VBAT = +2.75V, IF output load = 400Ω, LOH, LOL input power =
-7dBm, fLOL = 1017.26MHz, fLOH = 2061.26MHz, IFIN = 125mVRMS at 181.26MHz, IS-136 TDMA modulation, fRFH = 1880MHz, fRFL
= 836MHz, TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
MODULATOR, QUADRATURE MODES (Digital Cellular, Digital PCS, FM IQ)
IF Frequency Range 120–235 MHz
I/Q Common-Mode Input
Voltage VCC = 2.7V to 3.0V (Notes 2, 3, 4) 1.35 VCC / 2 VCC –
1.25 V
IF Gain Control Range VGC = 0.5V to 2.5V, IFG = 100 85 dB
IF Output Power, Digital Mode VGC = 2.5V, IFG = 100 -10 dBm
Gain Variation Over Temperature Relative to +25°C, TA = -40°C to +85°C (Note 4) ±0.8 dB
RX Band Noise Power VGC = 2.5V, IFG = 100, FIF = 181.26MHz, noise
measured at FIF ± 20MHz -145 dBm/Hz
Carrier Suppression VGC = 2.5V, IFG = 100 30 49 dB
Sideband Suppression VGC = 2.5V, IFG = 100 30 38 dB
MODULATOR, FM MODE
IF Gain Control Range VGC = 0.5V to 2.5V, IFG = 100 85 dB
VGC = 2.5V, IFG = 111, I/Q modulation -8.5
Output Power VGC = 2.5V, IFG = 111, direct VCO modulation -5.5 dBm
UPCONVERTER AND PREDRIVER
IF Frequency Range 120–235 MHz
Low-Band Frequency Range RFL port 800–1000 MHz
High-Band Frequency Range RFH port 1700–2000 MHz
LOL Frequency Range 800–1150 MHz
LOH Frequency Range 1400–2300 MHz
VGC = 2.5V, NADC modulation, ACPR < -32dBc/
-55dBc at +30kHz/+60kHz offset 5.8 7
Output Power, RFL (Note 4)
VGC = 2.5V, FM mode 9 12
dBm
Output Power, RFH (Note 4) VGC = 2.6V, NADC modulation, ACPR = -32dB/
-55dBc at +30kHz/+60kHz offset 4 6.6 dBm
Power-Control Range VGC = 0.5V to 2.5V 30 dB
Gain Variation Over Temperature Relative to +25°C, TA = -40°C to +85°C (Note 4) ±3 dB
RFL -25
RF Image Rejection (Note 4) RFH -24 dBc
RFL, VGC = 2.5V -22
LO Leakage (Note 4) RFH, VGC = 2.6V -24 dBm
RFL, VGC = 2.5V -133
RX Band Noise Power RFH, VGC = 2.6V -134
dBm/
Hz
MAX2369
Complete Dual-Band
Quadrature Transmitter
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2369 Evaluation Kit: 50Ωsystem, operating modes as defined in Table 6, input voltage at I and Q = 200mVRMS differential,
common mode = VCC/2, 300kHz quadrature CW tones, IF synthesizer locked with passive lead-lag second-order loop filter, REF =
200mVp-p at 19.44MHz, VCC = SHDN = CS = TXGATE = +2.75V, VBAT = +2.75V, IF output load = 400Ω, LOH, LOL input power =
-7dBm, fLOL = 1017.26MHz, fLOH = 2061.26MHz, IFIN = 125mVRMS at 181.26MHz, IS-136 TDMA modulation, fRFH = 1880MHz, fRFL
= 836MHz, TA= +25°C, unless otherwise noted.)
Note 1: See Table 6 for register settings.
Note 2: ACPR is met over the specified VCM range.
Note 3: VCM must be supplied by the I/Q baseband source with ±6µA capability.
Note 4: Guaranteed by design and characterization.
Note 5: When enabled, turbolock is active during acquisition and injects boost current in addition to the normal charge-pump current.
Note 6: Charge Pump Compliance range is 0.5V to VCC - 0.5V.
PARAMETER CONDITIONS MIN TYP MAX UNITS
IF_PLL
Reference Frequency 5 30 MHz
Frequency Reference Signal
Level 0.1 0.6 Vp-p
IF Main Divide Ratio 256 16384
IF Reference Signal Ratio 2 2048
VCO Operating Range 240–470 MHz
IF LO Output Power BUF_EN = 1 -6 dBm
ICP = 00 148 200 260
ICP = 01 185 260 345
ICP = 10 295 400 515
Charge-Pump Source/Sink
Current
ICP = 11 385 530 700
µA
Turbolock Boost Current (Note 5) 385 530 700 µA
Charge-Pump Source/Sink
Matching
Locked, all values of ICP, over specified compliance
range (Note 6) 5%
Charge-Pump High-Z Leakage Over specified compliance range (Note 6) 10 nA
MAX2369
Complete Dual-Band
Quadrature Transmitter
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(MAX2369EVKIT, VCC = +2.8V, VBAT = 3.0V, TA= +25°C, unless otherwise noted.)
-10
-6
-8
-2
-4
2
0
4
8
6
10
0 200 300 400100 500 600 700 900800 1000
IF PLL SETTLING TIME
TIME (µs)
FREQUENCY DEVIATION (kHz)
MAX2369 toc01
f
IF
= 181.26MHz
TANK 1/S11 vs. FREQUENCY
MAX2369 toc02
4
5
1
2
3
z
0
= 200Ω
EQUIVALENT PARALLEL R-C
1: 200MHz, 1.76kΩ, 0.26pF
2: 260MHz, 1.66kΩ, 0.31pF
3: 330MHz, 1.58kΩ, 0.34pF
4: 780MHz, 1.21kΩ, 0.43pF
5: 1GHz, 0.94kΩ, 0.47pF
80
100
90
120
110
130
140
1.5 1.7 1.8 1.91.6 2.0 2.1 2.2 2.3 2.4 2.5 2.6
ICC vs. VGC INPUT
MAX2369 toc03
VGC (V)
ICC (mA)
CELLULAR
PCS
-30
-35
-40
-45
-50
-55
-60
-20
-25
-10
-15
-5
5
0
10
OUTPUT POWER vs. VGC INPUT
MAX2369 toc04
VGC (V)
OUTPUT POWER (dBm)
1.5 1.9 2.11.7 2.3 2.5
CELLULAR
PCS
-120
-80
-100
-40
-60
-20
0
0 1.0 1.50.5 2.0 2.5 3.0
IF OUTPUT POWER
vs. VGC INPUT AND IF DAC SETTING
MAX2369 toc05
VGC (V)
POUT (dBm)
011
111
100
101
110
001
000
010
-110
-90
-100
-40
-50
-60
-70
-80
-30
-20
-10
0
1.001.50.5 2.0 2.5 3.0
IF OUTPUT POWER vs. VGC INPUT
MAX2369 toc06
VGC (V)
IF POWER (dBm)
-40°C
+85°C
+25°C
-120
-80
-100
-40
-60
-20
0
0 1.0 1.50.5 2.0 2.5 3.0
IF OUTPUT POWER vs. VGC INPUT
MAX2369 toc07
VGC (V)
POUT (dBm)
2.7V, 3.0V, 3.3V
MAX2369
Complete Dual-Band
Quadrature Transmitter
6 _______________________________________________________________________________________
-3.0
-1.5
-2.0
-2.5
-1.0
-0.5
0
020155 10 253035404550
I/Q BASEBAND FREQUENCY RESPONSE
MAX23669 toc09
FREQUENCY (MHz)
(dBc)
-50
-150
0.001 0.01 0.1 1 10
PHASE NOISE LOW-BAND OSCILLATOR
vs. FREQUENCY OFFSET (181.26MHz)
-130
MAX2369 toc10
OFFSET FREQUENCY (MHz)
PHASE NOISE (dBc/Hz)
-110
-90
-70
-80
-100
-120
-140
-60
FCOMP = 360kHz
-90
-70
-80
-50
-60
-30
-40
-20
0
-10
10
1500 1700 1900 2100 2300 2500
RFH OUTPUT SPECTRUM
MAX2369 toc12
FREQUENCY (MHz)
AMPLITUDE (dBm)
IMAGE
DESIRED
LO
-80
-60
-70
-40
-50
-30
-20
-20 -16 -12 -8 -4 0 4 8
CASCADED ACPR/ALT vs. POWER (RFL)
MAX2369 toc13
POWER (dBm)
ACPR (dBc)
ACPR WITH ROOT RAISED
COSINE FILTER
ACPR WITHOUT FILTER
ALT WITH OR WITHOUT FILTER
-80
-60
-70
-40
-50
-30
-20
-24 -20 -16 -12 -8 -4 0 4 6
CASCADED ACPR/ALT vs. POWER (RFH)
MAX2369 toc14
POWER (dBm)
ACPR/ALT (dBc)
ACPR WITH ROOT RAISED
COSINE FILTER
ACPR WITHOUT ROOT
RAISED COSINE FILTER
ALT WITH OR WITHOUT ROOT
RAISED COSINE FILTER
LOL PORT S11
MAX2369 toc17
1: 700MHz, 72Ω –j51Ω
2: 966MHz, 60Ω –j46Ω
3: 1.22MHz, 52Ω –j38Ω
4: 1.5GHz, 40Ω –j25Ω
41
2
3
LOH PORT S11
MAX2369 toc18
1600MHz TO 2500MHz
1: 1.6GHz, 40Ω –j25Ω
2: 1.75GHz, 36Ω –j22Ω
3: 1.88GHz, 34Ω –j18Ω
4: 2.01GHz, 32Ω –j15Ω
5: 2.5GHz, 29Ω –j0Ω
4
5
1
2
3
Typical Operating Characteristics (continued)
(MAX2369EVKIT, VCC = +2.8V, VBAT = 3.0V, TA= +25°C, unless otherwise noted.)
-80
-60
-70
-40
-50
-20
-30
-10
10
0
20
500 700 900 1100 1300 1500
RFL OUTPUT SPECTRUM
MAX2369 toc11
FREQUENCY (MHz)
AMPLITUDE (dBm)
IMAGE
DESIRED
LO
MAX2369
Complete Dual-Band
Quadrature Transmitter
_______________________________________________________________________________________ 7
Pin Description
VGC
VCC
IFOUT+,
IFOUT-
VCC
RF and IF Variable-Gain Control Analog Input. VGC floats to +1.5V. Apply
+0.5V to +2.6V to control the gain of the RF and IF stages. An RC filter on this pin may be used
to reduce DAC noise or PDM clock spurs from this line.
20
Supply Pin for the IF VGA. Bypass with a capacitor as close to the pin as possible. The bypass
capacitor must not share its ground vias with any other branches.
21
Differential IF Outputs. These pins must be inductively pulled up to VCC. A differential IF band-
pass filter is connected between this port and IFIN+ and IFIN-. The pullup inductors can be part
of the filter structure. The differential output impedance of this port is nominally 600Ω. The trans-
mission lines from these pins should be short to minimize the pickup of spurious signals and
noise.
18, 19
Power supply. Bypass to ground with a 1000pF capacitor.16, 17
PIN NAME FUNCTION
1RFL
Transmitter RF Output for Cellular Band (800MHz to 1000MHz)—for both FM and digital modes.
This open-collector output requires a pullup inductor to the supply voltage, which is part of the
output matching network and may be connected directly to the battery.
2RFH
Transmitter RF Output for PCS Band (1700MHz to 2000MHz). This open collector output
requires a pullup inductor to the supply voltage. The pullup inductor is part of the output match-
ing network and may be connected directly to the battery.
Open-Collector Output Indicating Lock Status of the IF PLL. Requires a pullup resistor. Control
using configuration register bit LD_MODE.
LOCK3
4 VCC
Power Supply. Supply pin for the driver stage. VCC must be bypassed to system ground as
close to the pin as possible. The ground vias for the bypass capacitor should not be shared by
any other branch. Bypass to ground with 100pF and 100nF capacitors.
Power Supply. Connect to pin 4 for normal operation.VCC
5
6 VCC
Supply Pin for the Upconverter Stage. VCC must be bypassed to system ground as close to the
pin as possible. The ground vias for the bypass capacitor should not be shared by any other
branch.
Digital Input. A logic low on TXGATE shuts down everything except the IF PLL, IF VCO, and ser-
ial bus and registers. This mode is used for IF PLL settling before the transmit time slot.
TXGATE
7
8, 9 IFIN+, IFIN-
Differential Inputs to the RF Upconverter. These pins are internally biased to +1.5V. The input
impedance for these ports is nominally 400Ωdifferential. The IF filter should be AC-coupled to
these ports. Keep the differential lines as short as possible to minimize stray pickup and shunt
capacitance.
No Connection. Leave these pins floating.N.C.10, 11
12 RBIAS
Bias Resistor Pin. RBIAS is internally biased to a bandgap voltage of +1.18V. An external resistor
or current source must be connected to this pin to set the bias current for the upconverters and PA
driver stages. The nominal resistor value is 16kΩ. This value can be altered to optimize the linearity
of the driver stage.
Input Pins from the 3-Wire Serial Bus (SPI/QSPI/MICROWIRE compatible).
An R-C filter on each of these pins may be used to reduce noise.
CLK, DI, CS
13, 14, 15
MAX2369
Complete Dual-Band
Quadrature Transmitter
8 _______________________________________________________________________________________
Pin Description (continued)
PIN FUNCTION
23, 24 Differential Q-Channel Baseband Inputs to the Modulator. These pins go directly to the bases of
a differential pair and require an external common-mode bias voltage.
22 Supply for the I/Q Modulator. Bypass with capacitor as close to the pin as possible. The bypass
capacitor must not share its ground vias with any other branches.
30, 31 Differential Tank Pins for the IF VCO. These pins are internally biased to +1.6V.
29 Buffered LO Output. Control the output buffer using register bit BUF_EN and the divide ratio
using the register bit BUF_DIV.
28 Supply Pin to the VCO Section. Bypass as close to the pin as possible. The bypass capacitor
should not share its vias with any other branches.
27 Shutdown Input. A logic low on SHDN shuts down the entire IC. An R-C lowpass filter may be
used to reduce digital noise.
25, 26 Differential I-Channel Baseband Inputs to the Modulator. These pins go directly to the bases of
a differential pair and require an external common-mode bias voltage.
NAME
Q+, Q-
VCC
TANK-,
TANK+
IFLO
VCC
SHDN
I+, I-
GND DC and AC GND Return for the IC. Connect to PC board ground plane using multiple vias.
Exposed
paddle
GND
VCC
LOH
LOL
REF
VCC
IFCP
VCC
Ground. Connect to PC board ground plane.
40, 45, 46,
47, 48
Supply Pin. Bypass as close to the pin as possible. The bypass capacitor may share with sup-
ply pin for digital circuitry, pin 39.
41
High-band RF LO Input Port. AC-couple to this port.43
Low-band RF LO Input Port. AC-couple to this port.44
Reference Frequency Input. REF is internally biased to VCC - 0.7V and must be AC-coupled to
the reference source. This is a high-impedance port (25kΩII 3pF).
36
Supply for the IF Charge Pump. This supply can differ from the system VCC. Bypass as close to
the pin as possible. The bypass capacitor must not share its vias with any other branches.
37
High-Impedance Output of the IF Charge Pump. Connect to the tune input of the IF VCOs
through the IF PLL loop filter. Keep the line from IFCP to the tune input as short as possible to
prevent spurious pickup, and connect the loop filter as close to the tune input as possible.
38
Supply Pin for Digital Circuitry. Bypass as close to the pin as possible. The bypass capacitor
must not share its vias with any other branch.
39
32, 33, 34,
35, 42 No Connection. Leave these pins floating.N.C.
MAX2369
Complete Dual-Band
Quadrature Transmitter
_______________________________________________________________________________________ 9
Detailed Description
The MAX2369 complete quadrature transmitter accepts
differential I/Q baseband inputs with external common-
mode bias. A modulator upconverts this to IF frequency
in the 120MHz to 235MHz range. A gain control voltage
pin (VGC) controls the gain of both the IF and RF VGAs
simultaneously to achieve best noise and linearity per-
formance. The IF signal is brought off-chip for filtering,
then fed to a single sideband upconverter followed by
the RF VGA and PA driver. The RF upconverter requires
an external VCO for operation. The IF PLL and operat-
ing mode can be programmed by an SPI/QSPI/
MICROWIRE-compatible 3-wire interface.
The following sections describe each block in the
MAX2369 Functional Diagram.
I/Q Modulator
Differential in-phase (I) and quadrature-phase (Q) input
pins are designed to be DC-coupled and biased with the
baseband output from a digital-to-analog converter
(DAC). I and Q inputs need a DC bias of VCC/2 and a
current-drive capability of 6µA. Common-mode voltage
will work within a 1.35V to (VCC - 1.25V) range. Typically,
I and Q will be driven differentially with a 200mVRMS
baseband signal. Optionally, I and Q may be pro-
grammed for 100mVRMS operation with the IQ_LEVEL bit
in the configuration register. The IF VCO output is fed
into a divide-by-two/quadrature generator block to derive
quadrature components to drive the IQ modulator. The
output of the modulator is fed into the VGA.
IF VCO
The VCO oscillates at twice the desired IF frequency.
Oscillation frequency is determined by external tank
components (see Applications Information). Typical
phase-noise performance for the tank is shown in
Typical Operating Characteristics.
IFLO Output Buffer
IFLO provides a buffered LO output when BUF_EN is 1.
The IFLO output frequency is equal to the VCO fre-
quency when BUF_DIV is 0, and half the VCO frequen-
cy when BUF_DIV is 1. The output power is -6dBm. This
output is used in test mode.
IF PLL
The IF PLL uses a charge-pump output to drive a loop
filter. The loop filter will typically be a passive second-
order lead lag filter. Outside the filter’s bandwidth,
phase noise will be determined by the tank compo-
nents. The two components that contribute most signifi-
cantly to phase noise are the inductor and varactor.
Use high-Q inductors and varactors to maximize equiv-
alent parallel resistance. The ICP_MAX bit in the OPC-
TRL register can be set to 1 to increase the charge
pump current.
IF VGA
The IF VGA allows varying an IF output level that is con-
trolled by the VGC voltage. The voltage range on VGC
of +0.5V to +2.6V provides a gain-control range of
85dB. The IF output ports from the VGA are optimized
for IF frequency from 120MHz to 235MHz. IFOUT ports
support direct VCO FM modulation. The differential IF
output port has an output impedance of 600Ωwhen
pulled up to VCC through a choke.
Single Sideband Mixer
The RF transmit mixer uses a single sideband architec-
ture to eliminate an off-chip RF filter. The mixer is fol-
lowed by the RF VGA. The RF VGA is controlled by the
same VGC pin as the IF VGA to provide optimum lineari-
ty and noise performance. The total power control range
is >100dB.
PA Driver
The MAX2369 includes two power-amplifier (PA) drivers.
Each is optimized for the desired operating frequency.
RFL is optimized for cellular-band operation. RFH is opti-
mized for PCS operation. The PA drivers have open-col-
lector outputs and require pullup inductors. The pullup
inductors can act as the shunt element in a shunt series
match.
Programmable Registers
The MAX2369 includes five programmable registers
consisting of two divide registers, a configuration regis-
ter, an operational control register, and a test register.
Each register consists of 24 bits. The 4 least significant
bits (LSBs) are the register’s address. The 20 most sig-
nificant bits (MSBs) are used for register data. All regis-
ters contain some “don't care” bits. These can be either
a zero or a 1 and do not affect operation (Figure 1).
Data is shifted in MSB first, followed by the 4-bit
address. When CS is low, the clock is active and data
is shifted with the rising edge of the clock. When CS
transitions to high, the shift register is latched into the
register selected by the contents of the address bits.
Power-up defaults for the five registers are shown in
Table 1. The registers should be initialized according to
Table 2. The dividers and control registers are pro-
grammed from the SPI/QSPI/MICROWIRE-compatible
serial port.
MAX2369
Complete Dual-Band
Quadrature Transmitter
10 ______________________________________________________________________________________
The IFM register sets the main frequency divide ratio
for the IF PLL. The IFR register sets the reference fre-
quency divide ratio. The IF VCO frequency can be
determined by the following:
IF VCO frequency = fREF ✕(IFM / IFR)
where fREF is the external reference frequency.
The operational control register (OPCTRL) controls the
state of the MAX2369. See Table 3 for the function of
each bit.
The configuration register (CONFIG) sets the configura-
tion for the IF PLL and the baseband I/Q input levels
See Table 4 for a description of each bit.
The test register is not needed for normal use.
Power Management
Bias control is distributed among several functional
sections and can be controlled to accommodate many
different power-down modes as shown in Table 5.
The shutdown control bit is of particular interest since it
differs from the SHDN pin. When the shutdown control
bit is active (SHDN_BIT = 0), the serial interface is left
active so that the part can be turned on with the serial
bus while all other functions remain shut off. In contrast,
Table 1. Register Power-Up Default States Table 2. Register Initialization for FREF =
19.44MHz, FIF = 181.26MHz,
FCOMP = 360kHz
Figure 1. Register Configuration
MSB 24 BIT REGISTER LSB
DATA 20 BITS ADDRESS 4 BITS
B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A3 A2 A1 A0
IFM DIVIDE RATIO REGISTER (14 BITS) ADDRESS
X X X X X X B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 1 0
IFR DIVIDE RATIO REGISTER (11 BITS) ADDRESS
X X X X X X X X X B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 1 1
CONTROL REGISTER (16 BITS) ADDRESS
X X X X B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0
CONFIGURATION REGISTER (16 BITS) ADDRESS
X X X X B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 1
TEST REGISTER (8 BITS) ADDRESS
X X X X X X X X X X X X B7 B6 B5 B4 B3 B2 B1 B0 0 1 1 1
X = DON’T CARE
REGISTER DEFAULT ADDRESS FUNCTION
IFM 6519 dec 0010bIF M divider count
IFR 0492 dec 0011bIF R divider count
OPCTRL 892F hex 0100bOperational control
settings
CONFIG D03F hex 0101bConfiguration and
setup control
TEST 0000 hex 0111bTest-mode control
REGISTER DEFAULT ADDRESS FUNCTION
IFM 1007 dec 0010bIF M divider count
IFR 0054 dec 0011bIF R divider count
OPCTRL 890F hex 0100bOperational control
settings
CONFIG 903D hex 0101bConfiguration and
setup control
TEST 0000 hex 0111bTest-mode control
MAX2369
Complete Dual-Band
Quadrature Transmitter
______________________________________________________________________________________ 11
MAX2369
0
90
IF PLL
N.C.
REF
N.C.
N.C.
N.C.
TANK+
TANK-
IFLO
VCC
I-
I+
VCC
GND
RFL
RFH
GND GND GND N.C. VCC
VCC VCC VCC
GND VCC IFCP
V
CC
N.C.
IFIN-
IFIN+
LOCK
LOL LOH
N.C.
RBIAS
BIAS
CTRL
VCC
Q-Q+VCC
VCC
VCC
VCC
VCC
VGC
IFOUT-IFOUT+
VCC
VCC
VCC
DAC GAIN
CONTROL INPUT
CELLULAR
OUTPUT
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
242322212019181716151413
373839404142434445464748
45 -45
/2
/2
0
90
CLK DI CS
Σ
Σ
SHDN
LOGIC INPUT
SHDN
TXGATE
LOGIC INPUT
LOCK
OUTPUT
TXGATE
FRAC-N
PLL
TANK
LOOP
FILTER
VCC
VCC
VCC
VCC
PCS
OUTPUT
Figure 2. MAX2369 Typical Application Circuit
when the SHDN pin is low it shuts down everything. In
either case, PLL programming and register information
is lost. To retain the register information, use standby
mode (STBY = 0).
Signal Flow Control
Table 6 shows an example of key registers for triple-
mode operation.
Applications Information
The MAX2369 is designed for use in dual-band, triple-
mode systems. It is recommended for triple-mode hand-
sets. A typical application circuit is shown in Figure 2.
3-Wire Interface
Figure 3 shows the 3-wire interface timing diagram. The
3-wire bus is SPI/QSPI/MICROWIRE compatible.
Table 3. Operation Control Register (OPCTRL)
MAX2369
Complete Dual-Band
Quadrature Transmitter
12 ______________________________________________________________________________________
BIT
LOCATION
(0 = LSB)
0 shuts down everything except serial interface, and also resets all registers to
power-up state.
01SHDN_BIT
0 shuts down modulator and upconverter, leaving PLL locked and registers
active. This is the programmable equivalent to the TXGATE pin.
11
TXSTBY
0 shuts down everything except registers and serial interface.21
STBY
0 selects direct VCO modulation. (IF VCO is externally modulated and the I/Q
modulator is bypassed); 1 selects quadrature modulation.
31MOD_TYPE
10
9
8, 7, 6
5
12, 11
13
14
15
0 turns IFLO buffer off; 1 turns IFLO buffer on.
Set to 0 for normal operation.0UNUSED
Set to 0 for normal operation.0UNUSED
3-bit IF gain control. Alters IF gain by approximately 2dB per LSB (0 to 14dB).
Provides a means for adjusting balance between RF and IF gain for optimized
linearity.
100IFG
When this register is 1, the upper sideband is selected (LO below RF). When
this register is 0, the lower sideband is selected (LO above RF).
1SIDE_BAND
Sets operating mode according to the following:
00 = FM mode
01 = Cellular digital mode; RFL is selected
10 = Not used
11 = PCS mode; RFH is selected
01MODE
1 keeps IF turbo-mode current active even when frequency acquisition is
achieved. This mode is used when high operating IF charge-pump current is
needed.
0ICP_MAX
Set to 0 for normal operation.0UNUSED
4
1 selects LOL input port; 0 selects LOH port.1LO_SEL
FUNCTION
POWER-UP
STATE
BIT NAME
0BUF_EN
MAX2369
Complete Dual-Band
Quadrature Transmitter
______________________________________________________________________________________ 13
BIT NAME FUNCTION
IF_PLL_SHDN 10 shuts down the IF PLL. This mode is used with an external IF VCO and IF PLL.
UNUSED 1Set to 0 for normal operation.
UNUSED 0Set to 0 for normal operation.
ICP 00
A 2-bit register sets the IF charge-pump current as follows:
00 = 200µA
01 = 260µA
10 = 400µA
11 = 530µA
VCO_BYPASS 01 bypasses IF VCO and enables a buffered input for external VCO use.
BUF_DIV 01 selects ÷2 on IFLO port; 0 bypasses the divider.
IQ_LEVEL 11 selects 200mVRMS input mode; 0 selects 100mVRMS input mode.
UNUSED 00 Not used. Leave in the power-up/initialized state.
15
14
13
9, 8
10
11
12
7, 6
IF_PD_POL 1 5
IF phase-detector polarity; 1 selects positive polarity (increasing tuning voltage
on the VCO produces increasing frequency); 0 selects negative polarity
(increasing tuning voltage on the VCO produces decreasing frequency).
UNUSED 111 4, 3 ,2 Not used. Leave in the power-up/initialized state.
LD_MODE 1 0
Determines output mode for LOCK detector pin as follows:
0 = test mode, LD_MODE cannot be 0 for normal operation
1 = IF PLL lock detector
POWER-UP
STATE
BIT
LOCATION
(0 = LSB)
Table 4. Configuration Register (CONFIG)
Electromagnetic
Compliance Considerations
Two major concepts should be employed to produce a
noise-free and EMC-compliant transmitter: minimize cir-
cular current-loop area to reduce H-field radiation and
minimize voltage drops to reduce E-field radiation. To
minimize the circular current-loop area, bypass as
close to the part as possible and use the distributed
capacitance of a ground plane. To minimize voltage
drops, make VCC traces short and wide, and make RF
traces short.
The “don't care” bits in the registers should be zero in
order to minimize electromagnetic radiation due to
unnecessary bit banging. RC filtering can also be used
to slow the clock edges on the 3-wire interface, reduc-
ing high-frequency spectral content. RC filtering also
provides for transient protection against IEC802 testing
by shunting high frequencies to ground, while the
series resistance attenuates the transients for error-free
operation. The same applies to the override pins
(SHDN, TXGATE).
When floating the override pins, bypass to ground with
the capacitors as close to the part as possible.
High-frequency bypass capacitors are required close
to the pins with a dedicated via to ground. The 48-pin
QFN-EP package provides minimal inductance ground
by using an exposed paddle under the part. Provide at
least five low-inductance vias under the paddle to
ground to minimize ground inductance. Use a solid
ground plane wherever possible. Any cutout in the
ground plane may act as slot radiator and reduce its
shield effectiveness.
Keep the RF LO traces as short as possible to reduce
LO radiation and susceptibility to interference.
UNUSED 1 1 Set to 0 for normal operation.
MAX2369
Complete Dual-Band
Quadrature Transmitter
14 ______________________________________________________________________________________
Table 5. Power-Down Modes
Table 6. Register and Control Pin States for Key Operating Modes
X = Don’t care
OFF
POWER-DOWN MODES COMMENTS
UPCONVERTER
MODULATOR
SERIAL BUS
OPCTRL REG
IF LO BUFFER
IF VCO
IF PLL
IF PLL REGS
CONFIG REG
SHDN pin Ultra-low shutdown current XXXXXXXXX
TXGATE pin For punctured TX mode X X
IF PLL SHDN For external IF PLL use X X
TX STBY TX is off, but IF LO stays locked X X
REG STBY Shuts down, but preserves registers X X X X X
REG SHDN Serial bus is still active X X XXXXXX
OPCTRL REGISTER C O N T R O L
PINS
MODE DESCRIPTION
LO_SEL
MODE
MOD_TYPE
STBY
TXSTBY
SHDN_BIT
IF_PLL_SHDN
TXGATE
SHDN
PCS Digital RFH selected 0 11 1 1 1 1 1 H H
Cellular Digital RFL selected 1 01 1 1 1 1 1 H H
FM Direct VCO modulation, RFL selected 1 00 0 1 1 1 1 H H
FM_IQ FM with IQ modulation, RFL selected 1 00 1 1 1 1 1 H H
PCS TXGATE Gated transmission, PCS 0 11 1 1 X 1 1 L H
Cellular TXGATE Gated transmission, cellular digital 1 01 1 1 X 1 1 L H
Sleep Everything off X XX X X X X X X L
MAX2369
Complete Dual-Band
Quadrature Transmitter
______________________________________________________________________________________ 15
tCS tCH
tCWL
tCWH
DI
NOTE: THE 3-WIRE BUS IS SPI/QSPI/MICROWIRE-COMPATIBLE.
CLK
CS
tES
B19 (MSB) B18 B0 A3 A1 A0 (LSB) tCS > 50ns
tCH > 10ns
tCWH > 50ns
tES > 50ns
tCWL > 50ns
tEW > 50ns
tEW
Figure 3. 3-Wire Interface Diagram
IF Tank Design
The IF VCO tank (TANK+, TANK-) is fully differential.
The external tank components are shown in Figure 4.
The frequency of oscillation is determined by the follow-
ing equation:
CINT = Internal capacitance of TANK port
CD= Capacitance of varactor
CVAR = Equivalent variable tuning capacitance
CPAR = Parasitic capacitance due to PC board pads
and traces
CCENT = External capacitor for centering oscillation fre-
quency
CC= External coupling capacitor to the varactor
Internal to the IC, the charge pump will have a leakage
of less than 10nA. This is equivalent to a 300MΩshunt
resistor. The charge-pump output must see an
extremely high DC resistance of greater than 300MΩ.
This will minimize charge-pump spurs at the compari-
son frequency. Make sure there is no solder flux under
the varactor or loop filter.
Layout Issues
The MAX2369 EV kit can be used as a starting point for
layout. For best performance, take into consideration
power-supply issues, as well as the RF, LO, and IF lay-
out.
Power-Supply Layout
To minimize coupling between different sections of the
IC, the ideal power-supply layout is a star configuration,
which has a large decoupling capacitor at a central
VCC node. The VCC traces branch out from this node,
each going to a separate VCC node in the MAX2369
circuit. At the end of each trace is a bypass capacitor
with impedance to ground less than 1Ωat the frequen-
cy of interest. This arrangement provides local decou-
pling at each VCC pin. Use at least one via per bypass
capacitor for a low-inductance ground connection.
Matching Network Layout
The layout of a matching network can be very sensitive
to parasitic circuit elements. To minimize parasitic
inductance, keep all traces short and place compo-
nents as close to the IC as possible. To minimize para-
sitic capacitance, a cutout in the ground plane (and
any other planes) below the matching network compo-
nents can be used.
On the high-impedance ports (e.g., IF inputs and out-
puts), keep traces short to minimize shunt capacitance.
f
2(C C C C)L
C
CC
2(C + C )
OSC
INT CENT VAR PAR
VAR DC
DC
=
+++
=×
1
π
L
CD
CCENT CPAR
CC
CC
CD
MAX2369
CINT -Rn
Figure 4. Tank Port Oscillator
MAX2369
Complete Dual-Band
Quadrature Transmitter
Tank Layout
Keep the traces coming out of the tank short to reduce
series inductance and shunt capacitance. Keep the
inductor pads and coupling capacitor pads small to
minimize stray shunt capacitance.
Pin Configuration
REF
N.C.
N.C.
N.C.
N.C.
TANK +
TANK -
IFLO
VCC
SHDN
I-
I+
RFL
RFH
LOCK
VCC
VCC
VCC
TXGATE
IFIN+
IFIN-
N.C.
N.C.
RBIAS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK
DI
CS
VCC
VCC
IFOUT+
IFOUT-
VGC
VCC
VCC
Q+
Q-
GND
GND
GND
GND
LOL
LOH
N.C.
VCC
GND
VCC
IFCP
VCC
MAX2369
TOP VIEW
QFN-EP
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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