For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
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__________________General Description
The MAX5253 combines four low-power, voltage-output,
12-bit digital-to-analog converters (DACs) and four pre-
cision output amplifiers in a space-saving, 20-pin pack-
age. In addition to the four voltage outputs, each
amplifier’s negative input is also available to the user.
This facilitates specific gain configurations, remote
sensing, and high output drive capacity, making the
MAX5253 ideal for industrial-process-control applica-
tions. Other features include software shutdown, hard-
ware shutdown lockout, an active-low reset which clears
all registers and DACs to zero, a user-programmable
logic output, and a serial-data output.
Each DAC has a double-buffered input organized as an
input register followed by a DAC register. A 16-bit serial
word loads data into each input/DAC register. The serial
interface is compatible with SPI™/QSPI™ and
MICROWIRE™. It allows the input and DAC registers to
be updated independently or simultaneously with a sin-
gle software command. The DAC registers can be
simultaneously updated through the 3-wire serial inter-
face. All logic inputs are TTL/CMOS-logic compatible.
________________________Applications
Industrial Process Controls
Automatic Test Equipment
Digital Offset and Gain Adjustment
Motion Control
Remote Industrial Controls
Microprocessor-Controlled Systems
______________________________Features
♦Four 12-Bit DACs with Configurable
Output Amplifiers
♦+3.0V to +3.6V Single-Supply Operation
♦Low Supply Current: 0.82mA Normal Operation
3µA Shutdown Mode
♦Reference Inputs are High Impedance in Shutdown
♦Available in 20-Pin SSOP
♦Power-On Reset Clears all Registers and
DACs to Zero
♦SPI/QSPI and MICROWIRE Compatible
♦Simultaneous or Independent Control of DACs
Through 3-Wire Serial Interface
♦User-Programmable Digital Output
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
________________________________________________________________ Maxim Integrated Products 1
MAX5253
OUTA
FBA
FBB
FBC
FBD
DAC A
DAC B
DAC C
DAC D
REFAB
DAC A
REGISTER A
DECODE
CONTROL
INPUT
REGISTER A
DAC B
REGISTER B
INPUT
REGISTER B
DAC C
REGISTER C
INPUT
REGISTER C
DAC D
REGISTER D
INPUT
REGISTER D
16-BIT
SHIFT
REGISTER
SR
CONTROL LOGIC
OUTPUT
CS DIN SCLK
OUTB
OUTC
OUTD
DOUT PDL
CL VDD
AGND
DGND
UPO REFCD
_________________________________________________________________________Functional Diagram
19-1123; Rev 1; 10/02
PART
MAX5253ACPP
MAX5253BCPP 0°C to +70°C
0°C to +70°C
TEMP RANGE PIN-PACKAGE
20 Plastic DIP
20 Plastic DIP
_________________Ordering Information
Ordering Information continued at end of data sheet.
Pin Configuration appears at end of data sheet.
INL
(LSB)
±1/2
±1
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
MAX5253ACAP
MAX5253BCAP 0°C to +70°C
0°C to +70°C 20 SSOP
20 SSOP
±1/2
±1
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD = 1.25V, RL= 5kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND...............................................................-0.3V, +6V
VDD to DGND ..............................................................-0.3V, +6V
AGND to DGND ..................................................................±0.3V
REFAB, REFCD to AGND...........................-0.3V to (VDD + 0.3V)
OUT_, FB_ to AGND...................................-0.3V to (VDD + 0.3V)
Digital Inputs to DGND.............................................-0.3V to +6V
DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V)
Continuous Current into Any Pin.......................................±20mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 8.00mW/°C above +70°C) .................640mW
SSOP (derate 8.00mW/°C above +70°C) ......................640mW
CERDIP (derate 11.11mW/°C above +70°C).................889mW
Operating Temperature Ranges
MAX5253_C_P ......................................................0°C to +70°C
MAX5253_E_P ...................................................-40°C to +85°C
MAX5253BMJP................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Code-dependent, minimum at code 555 hex
VDD = +3.0V to +3.6V
(Note 1)
Guaranteed monotonic
CONDITIONS
kΩ8RREF
Reference Input Resistance
V0V
DD - 1.4VREF
Reference Input Range
LSB±0.35 ±1.0INLIntegral Nonlinearity
mVOffset Error ±1.0 ±6.0
LSB±4.0GEGain Error
µV/VPSRRPower-Supply Rejection Ratio 300
±0.25 ±0.5
Bits12NResolution
ppm/°C1Gain-Error Tempco
LSBGEGain Error ±4.0
ppm/°C6Offset-Error Tempco
LSB
±1.0
INL
Integral Nonlinearity
(Note 1)
LSB±1.0DNLDifferential Nonlinearity
±6.0 mVVOS
Offset Error
UNITSMIN TYP MAXSYMBOLPARAMETER
MAX5253BC/E
STATIC PERFORMANCE—ANALOG SECTION
MATCHING PERFORMANCE (TA= +25°C)
REFERENCE INPUT
MAX5253AC/E
MAX5253BMJP ±2.0
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD = 1.25V, RL= 5kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
(Note 4)
(Note 3)
CS = VDD, DIN = 100kHz
VREF = 0.67VP-P
Rail-to-Rail®(Note 2)
To ±1/2LSB, VSTEP = 1.25V
VIN = 0V or VDD
VREF = 1VP-P at 25kHz
ISINK = 2mA
ISOURCE = 2mA
CONDITIONS
mA0.82 0.98IDD
Supply Current
V3.0 3.6VDD
Supply Voltage
nV-s5Digital Crosstalk
nV-s5Digital Feedthrough
µs20
Start-Up Time Exiting
Shutdown Mode
µA0 0.1Current into FB_
V0 to VDD
Output Voltage Swing
µs16Output Settling Time
V/µs0.6SRVoltage Output Slew Rate
V0.13 0.4VOL
Output Low Voltage
VVDD - 0.5VOH
Output High Voltage
kHz650Reference -3dB Bandwidth
pF8CIN
Input Capacitance
µA0.01 ±0.1IIN
Input Leakage Current
V0.8VIL
Input Low Voltage
dB72SINAD
Signal-to-Noise Plus
Distortion Ratio
V2.0VIH
Input High Voltage
UNITSMIN TYP MAXSYMBOLPARAMETER
Input code = all 0s, VREF = 1.6VP-P at 1kHz dB-84Reference Feedthrough
(Note 4) µA320Supply Current in Shutdown
µA0.01 ±1Reference Current in Shutdown
Note 1: Guaranteed from code 11 to code 4095 in unity-gain configuration.
Note 2: Accuracy is better than 0.5LSB for VOUT = 6mV to VDD - 80mV, guaranteed by PSR test on endpoints.
Note 3: Remains operational with supply voltage as low as +2.7V.
Note 4: RL= ∞, digital inputs at DGND or VDD.
RL= ∞µA0.01 ±1
OUT_ Leakage Current
in Shutdown
MULTIPLYING-MODE PERFORMANCE
DIGITAL INPUTS
DIGITAL OUTPUTS
DYNAMIC PERFORMANCE
POWER SUPPLIES
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
0
-4
-8
-12
-16
-20
100 560k 1.12M 1.68M 2.24M 2.8M
MAX5253-06
RELATIVE OUTPUT (dB)
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
FREQUENCY (Hz)
REFAB SWEPT 0.67VP-P
RL = 5kΩ
CL = 100pF
INL (LSB)
-5
0 0.5 1.0 1.5 2.0
REFERENCE VOLTAGE (V)
MAX5253-01
2.5
1
0
-1
-2
-3
-4
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE
RL = 5kΩ
1000
950
900
850
800
750
700
650
600
550
500
-55 -40 -20 0 20 40 60 80 125100
MAX5253-04
SUPPLY CURRENT (µA)
SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
CODE = FFF HEX
__________________________________________Typical Operating Characteristics
(VDD = +3.3V, TA = +25°C, unless otherwise noted.)
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(VDD = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD =1.25V, RL= 5kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise
noted. Typical values are at TA= +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
CONDITIONS
tD02
SCLK Fall to DOUT Valid
Propagation Delay
tD01
SCLK Rise to DOUT Valid
Propagation Delay
ns100tCP
SCLK Clock Period
ns0tDH
DIN Hold Time
ns40tDS
DIN Setup Time
ns0tCSH
SCLK Rise to CS Rise Hold Time
ns40tCSS
CS Fall to SCLK Rise Setup Time
ns40tCH
SCLK Pulse Width High
ns40tCL
SCLK Pulse Width Low
UNITSMIN TYP MAXSYMBOLPARAMETER
ns100tCSW
CS Pulse Width High
ns40tCS1
CS Rise to SCLK Rise Hold Time
ns40tCS0
SCLK Rise to CS Fall Delay
CL= 200pF
CL= 200pF
120
120 ns
ns
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
_______________________________________________________________________________________ 5
2.7 2.8 3.02.9 3.1 3.2 3.3 3.4 3.6
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5253-05
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
3.5
1000
950
900
850
800
750
700
600
650
500
550 CODE = FFF HEX
0
-10
0.01 0.1 1 10 100
FULL-SCALE ERROR
vs. LOAD
-7
MAX5253-03
LOAD (kΩ)
FULL-SCALE ERROR (LSB)
-3
-4
-5
-6
-8
-9
-2
-1
____________________________Typical Operating Characteristics (continued)
(VDD = +3.3V, TA = +25°C, unless otherwise noted.)
0.50
0
0.1 1 10 100
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. LOAD
0.05
0.10
0.15
0.20
0.25
0.30
MAX5253-02
FREQUENCY (kHz)
THD + NOISE (%)
0.35
0.40
0.45 DAC CODE = ALL 1s
REFAB = 1VP-P
RL = 5kΩ
CL = 100pF
-100
0.5 1.6 3.8
OUTPUT FFT PLOT
-60
0
MAX5253-10
FREQUENCY (kHz)
SIGNAL AMPLITUDE (dB)
2.7 4.9 6.0
-20
-40
-80
VREF = 1kHz, 0.006V TO 1.6V
RL = 5kΩ
CL = 100pF
-100
0.5 1.2 2.6
REFERENCE FEEDTHROUGH
AT 1kHz
-60
0
MAX5253-11
FREQUENCY (kHz)
SIGNAL AMPLITUDE (dB)
1.9 3.3 4.0
-20
-40
-80
REFAB INPUT SIGNAL
VREF = 1.6VP-P AT 1kHz
RL = 5kΩ
CL = 100pF
OUTA FEEDTHROUGH
10µs/div
MAJOR-CARRY TRANSITION
MAX5253-07
OUTB,
AC-COUPLED
50mV/div
CS
5V/div
VREF = 1.25V, RL = 5kΩ, CL = 100pF
2µs/div
OUTA,
AC-COUPLED
10mV/div
DIGITAL FEEDTHROUGH (SCLK = 100kHz)
MAX5253-08
SCLK,
2V/div
CS = PDL = CL = 3.3V, DIN = 0V
DAC A CODE SET TO 800 HEX
VREF = 1.25V, RL = 5kΩ, CL = 100pF
DAC A CODE SWITCHING FROM 00B HEX TO FFF HEX
DAC B CODE SET TO 800 HEX
10µs/div
GND
OUTB,
AC COUPLED
10mV/div
ANALOG CROSSTALK
MAX5253-12
OUTA,
500mV/div
VREF = 1.25V, RL = 5kΩ, CL = 100pF
SWITCHING FROM CODE 000 HEX TO FB4 HEX
OUTPUT AMPLIFIER GAIN = +2.6
10µs/div
DYNAMIC RESPONSE
MAX5253-13
OUTA,
500mV/div
VREF = 1.25V, RL = 5kΩ, CL = 100pF
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
6 _______________________________________________________________________________________
____________________________Typical Operating Characteristics (continued)
(VDD = +3.3V, TA = +25°C, unless otherwise noted.)
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
Serial-Data InputDIN9
Serial Clock InputSCLK10
Digital GroundDGND11
Serial-Data OutputDOUT12
User-Programmable Logic OutputUPO13
DAC B Output Amplifier FeedbackFBB5
Reference Voltage Input for DAC A and DAC BREFAB6
Clears All DACs and Registers. Resets all outputs (OUT_, UPO, DOUT) to 0, active low.
CL
7
Chip-Select Input. Active low.
CS
8
DAC B Output VoltageOUTB4
DAC A Output VoltageOUTA3
PIN
DAC A Output Amplifier FeedbackFBA2
Analog GroundAGND1
FUNCTIONNAME
Power-Down Lockout. Active low. Locks out software shutdown if low.
PDL
14
Reference Voltage Input for DAC C and DAC DREFCD15
DAC C Output Amplifier FeedbackFBC16
DAC C Output VoltageOUTC17
DAC D Output VoltageOUTD18
DAC D Output Amplifier FeedbackFBD19
Positive Power SupplyVDD
20
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
8 _______________________________________________________________________________________
_______________Detailed Description
The MAX5253 contains four 12-bit, voltage-output digi-
tal-to-analog converters (DACs) that are easily
addressed using a simple 3-wire serial interface. It
includes a 16-bit data-in/data-out shift register, and
each DAC has a doubled-buffered input composed of
an input register and a DAC register (see Functional
Diagram). In addition to the four voltage outputs, each
amplifier’s negative input is available to the user.
The DACs are inverted R-2R ladder networks that con-
vert 12-bit digital inputs into equivalent analog output
voltages in proportion to the applied reference voltage
inputs. DACs A and B share the REFAB reference input,
while DACs C and D share the REFCD reference input.
The two reference inputs allow different full-scale output
voltage ranges for each pair of DACs. Figure 1 shows a
simplified circuit diagram of one of the four DACs.
Reference Inputs
The two reference inputs accept positive DC and AC
signals. The voltage at each reference input sets the
full-scale output voltage for its two corresponding
DACs. The reference input voltage range is 0V to (VDD
- 1.4V). The output voltages (VOUT_) are represented by
a digitally programmable voltage source as:
VOUT_ = (VREF x NB / 4096 ) x Gain
where NB is the numeric value of the DAC’s binary
input code (0 to 4095), VREF is the reference voltage,
and Gain is the externally set voltage gain.
The impedance at each reference input is code-depen-
dent, ranging from a low value of 10kΩwhen both
DACs connected to the reference have an input code
of 555 hex, to a high value exceeding several gigohms
(leakage current) with an input code of 000 hex. Because
the input impedance at the reference pins is code-
dependent, load regulation of the reference source is
important.
The REFAB and REFCD reference inputs have a 10kΩ
guaranteed minimum input impedance. When the two
reference inputs are driven from the same source, the
effective minimum impedance is 5kΩ. Driving the
REFAB and REFCD pins separately improves reference
accuracy.
In shutdown mode, the MAX5253’s REFAB and REFCD
inputs enter a high-impedance state with a typical input
leakage current of 0.01µA.
The reference input capacitance is also code depen-
dent and typically ranges from 20pF with an input code
of all 0s to 100pF with an input code of all 1s.
Output Amplifiers
All MAX5253 DAC outputs are internally buffered by pre-
cision amplifiers with a typical slew rate of 0.6V/µs.
Access to the inverting input of each output amplifier
provides the user greater flexibility in output gain setting/
signal conditioning (see the Applications Information sec-
tion).
With a full-scale transition at the MAX5253 output, the
typical settling time to ±1/2LSB is 16µs when loaded
with 5kΩin parallel with 100pF (loads less than 2kΩ
degrade performance).
The MAX5253 output amplifier’s output dynamic
responses and settling performances are shown in the
Typical Operating Characteristics.
Shutdown Mode
The MAX5253 features a software-programmable shut-
down that reduces supply current to a typical value of
3µA. The power-down lockout (PDL) pin must be high to
enable the shutdown mode. Writing 1100XXXXXXXXXXXX
as the input-control word puts the MAX5253 in shutdown
mode (Table 1).
OUT_
FB_
SHOWN FOR ALL 1s ON DAC
D0 D9 D10 D11
2R 2R 2R 2R 2R
RRR
REF_
AGND
Figure 1. Simplified DAC Circuit Diagram
In shutdown mode, the MAX5253 output amplifiers and
the reference inputs enter a high-impedance state. The
serial interface remains active. Data in the input regis-
ters is retained in shutdown, allowing the MAX5253 to
recall the output states prior to entering shutdown. Exit
shutdown mode by either recalling the previous config-
uration or by updating the DACs with new data. When
powering up the device or bringing it out of shutdown,
allow 20µs for the outputs to stabilize.
Serial-Interface Configurations
The MAX5253’s 3-wire serial interface is compatible
with both MICROWIRE (Figure 2) and SPI/QSPI
(Figure 3). The serial input word consists of two address
bits and two control bits followed by 12 data bits
(MSB first), as shown in Figure 4. The 4-bit address/
control code determines the MAX5253’s response out-
lined in Table 1. The connection between DOUT and
the serial-interface port is not necessary, but may be
used for data echo. Data held in the MAX5253’s shift
register can be shifted out of DOUT and returned to the
microprocessor (µP) for data verification.
The MAX5253’s digital inputs are double buffered.
Depending on the command issued through the serial
interface, the input register(s) can be loaded without
affecting the DAC register(s), the DAC register(s) can
be loaded directly, or all four DAC registers can be
updated simultaneously from the input registers
(Table 1).
Serial-Interface Description
The MAX5253 requires 16 bits of serial data. Table 1
lists the serial-interface programming commands. For
certain commands, the 12 data bits are “don’t cares.”
Data is sent MSB first and can be sent in two 8-bit
packets or one 16-bit word (CS must remain low until
16 bits are transferred). The serial data is composed of
two DAC address bits (A1, A0) and two control bits
(C1,C0), followed by the 12 data bits D11…D0 (Figure
4). The 4-bit address/control code determines:
•The register(s) to be updated
•The clock edge on which data is to be clocked out
through the serial-data output (DOUT)
•The state of the user-programmable logic output
(UPO)
•If the part is to go into shutdown mode (assuming
PDL is high)
•How the part is configured when exiting shutdown
mode
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
_______________________________________________________________________________________ 9
SCLK
DIN
DOUT*
CS
SK
SO
SI*
I/O
MAX5253 MICROWIRE
PORT
*THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5253,
BUT CAN BE USED FOR READBACK PURPOSES.
Figure 2. Connections for MICROWIRE
DOUT*
DIN
SCLK
CS
MISO*
MOSI
SCK
I/O
SPI/QSPI
PORT
SS
+3.3V
CPOL = 0, CPHA = 0
*THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5253,
BUT CAN BE USED FOR READBACK PURPOSES.
MAX5253
Figure 3. Connections for SPI/QSPI
Figure 4. Serial-Data Format
MSB ..................................................................................LSB
16 Bits of Serial Data
Address
Bits
Control
Bits
Data Bits
MSB.............................................LSB
A1 A0 C1 C0 D11................................................D0
12 Data Bits
4 Address/
Control Bits
MAX5253
Figure 5 shows the serial-interface timing requirements.
The chip-select pin (CS) must be low to enable the
DAC’s serial interface. When CS is high, the interface
control circuitry is disabled. CS must go low at least
tCSS before the rising serial clock (SCLK) edge to prop-
erly clock in the first bit. When CS is low, data is
clocked into the internal shift register through the serial-
data input pin (DIN) on SCLK’s rising edge. The maxi-
mum guaranteed clock frequency is 10MHz. Data is
latched into the appropriate MAX5253 input/DAC regis-
ters on CS’s rising edge.
The programming command Load-All-DACs-From-Shift-
Register allows all input and DAC registers to be simul-
taneously loaded with the same digital code from the
input shift register. The no operation (NOP) command
leaves the register contents unaffected and is useful
when the MAX5253 is configured in a daisy chain (see
the Daisy Chaining Devices section). The command to
change the clock edge on which serial data is shifted
out of DOUT also loads data from all input registers to
their respective DAC registers.
Serial-Data Output (DOUT)
The serial-data output, DOUT, is the internal shift regis-
ter’s output. The MAX5253 can be programmed so that
data is clocked out of DOUT on SCLK’s rising edge
(Mode 1) or falling edge (Mode 0). In Mode 0, output
data at DOUT lags input data at DIN by 16.5 clock
cycles, maintaining compatibility with Microwire,
SPI/QSPI, and other serial interfaces. In Mode 1, output
data lags input data by 16 clock cycles. On power-up,
DOUT defaults to Mode 0 timing.
User-Programmable Logic Output (UPO)
The user-programmable logic output, UPO, allows an
external device to be controlled through the MAX5253
serial interface (Table 1).
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
10 ______________________________________________________________________________________
Table 1. Serial-Interface Programming Commands
00 No operation (NOP) to DAC registers
00
11
UPO goes low (default)
Enter shutdown mode (provided PDL = 1)
10 Load all DAC registers from shift register (exit shutdown mode).
Load input register A; DAC registers unchanged.
Load input register B; DAC registers unchanged.
Load input register C; DAC registers unchanged.
Load input register D; DAC registers unchanged.
Load input register A; all DAC registers updated.
Load input register B; all DAC registers updated.
Load input register C; all DAC registers updated.
Load input register D; all DAC registers updated.
01
01
00
01
10
11
00
01
10
11
Update all DAC registers from their respective input registers (exit
shutdown mode).
UPO goes high
00
10
00
00
00
10
01
01
01
01
11
11
11
11
XXXXXXXXXXXX
16-BIT SERIAL WORD
XXXXXXXXXXXX
XXXXXXXXXXXX
12-bit DAC data
XXXXXXXXXXXX
XXXXXXXXXXXX
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
10 XXXXXXXXXXXX Mode 0, DOUT clocked out on SCLK’s falling edge. All DAC registers
updated (default).
XXXXXXXXXXXX
11 Mode 1, DOUT clocked out on SCLK’s rising edge. All DAC registers
updated.
10
10
“X” = Don’t care
A1 A0 C1 C0 D11.................D0
MSB LSB
FUNCTION
Power-Down Lockout (
PDL
)
The power-down lockout pin PDL disables software
shutdown when low. When in shutdown, transitioning
PDL from high to low wakes up the part with the output
set to the state prior to shutdown. PDL could also be
used to asynchronously wake up the device.
Daisy-Chaining Devices
Any number of MAX5253s can be daisy chained by
connecting the DOUT pin of one device to the DIN pin
of the following device in the chain (Figure 7).
Since the MAX5253’s DOUT pin has an internal active
pull-up, the DOUT sink/source capability determines
the time required to discharge/charge a capacitive
load. Refer to the serial-data-out VOH and VOL specifi-
cations in the Electrical Characteristics.
Figure 8 shows an alternate method of connecting sev-
eral MAX5253s. In this configuration, the data bus is
common to all devices; data is not shifted through a
daisy chain. More I/O lines are required in this configu-
ration because a dedicated chip-select input (CS) is
required for each IC.
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
______________________________________________________________________________________ 11
CS
SCLK
DIN
DOUT
(MODE 1)
MSB FROM
PREVIOUS WRITE
MSB FROM
PREVIOUS WRITE
COMMAND
EXECUTED
9
816
1
A0
A1 D0
C1 C0 D11 D10 D9 D6 D5 D4 D3 D2 D1
D8 D7
DOUT
(MODE 0) A0
A1 D0 A1
C1 C0 D11 D10 D9 D6 D5 D4 D3 D2 D1
D8 D7
A0
A1 D0 A1
C1 C0 D11 D10 D9 D6 D5 D4 D3 D2 D1
D8 D7
DATA PACKET (N)
DATA PACKET (N-1) DATA PACKET (N)
DATA PACKET (N-1) DATA PACKET (N)
Figure 5. Serial-Interface Timing Diagram
SCLK
DIN
DOUT
tCSO
tCSS tCL
tCH tCP
tDO1
tCSW
tCS1
tDO2
tCSH
tDS tDH
CS
Figure 6. Detailed Serial-Interface Timing Diagram
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
12 ______________________________________________________________________________________
DIN
CS
TO OTHER
SERIAL DEVICES
MAX5253
SCLK
DIN
CS
DOUT
MAX5253
SCLK
DIN
CS
DOUT
MAX5253
SCLK
DIN
CS
DOUT
SCLK
Figure 7. Daisy-Chaining MAX5253s
TO OTHER
SERIAL DEVICES
MAX5253
DIN
SCLK
CS
MAX5253
DIN
SCLK
CS
MAX5253
DIN
SCLK
CS
DIN
SCLK
CS1
CS2
CS3
Figure 8. Multiple MAX5253s Sharing a Common DIN Line
__________Applications Information
Unipolar Output
For a unipolar output, the output voltages and the refer-
ence inputs have the same polarity. Figure 9 shows the
MAX5253 unipolar output circuit, which is also the typi-
cal operating circuit. Table 2 lists the unipolar output
codes.
For rail-to-rail outputs, see Figure 10. This circuit shows
the MAX5253 with the output amplifiers configured with
a closed-loop gain of +2.6 to provide 0V to 3.25V full-
scale range when a 1.25V reference is used.
Bipolar Output
The MAX5253 outputs can be configured for bipolar
operation using Figure 11’s circuit.
VOUT = VREF [(2NB / 4096) - 1]
where NB is the numeric value of the DAC’s binary
input code. Table 3 shows digital codes (offset binary)
and corresponding output voltages for Figure 11’s
circuit.
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
______________________________________________________________________________________ 13
Table 2. Unipolar Code Table
Table 3. Bipolar Code Table
DAC CONTENTS ANALOG OUTPUT
MSB LSB
4095
1111 1111 1111 +VREF (——— )
4096
2049
1000 0000 0001 +VREF (——— )
4096
2048 +VREF
1000 0000 0000 +VREF (——— )= ————
4096 2
2047
0111 1111 1111 +VREF (——— )
4096
1
0000 0000 0001 +VREF (——— )
4096
0000 0000 0000 0V
DAC CONTENTS ANALOG OUTPUT
MSB LSB
2047
1111 1111 1111 +VREF (——— )
2048
1
1000 0000 0001 +VREF (——— )
2048
1000 0000 0000 0V
1
0111 1111 1111 -VREF (——— )
2048
2047
0000 0000 0001 -VREF (——— )
2048
2048
0000 0000 0000 -VREF (——— )= -VREF
2048
MAX5253
DAC A
DAC B
DAC C
DAC D
OUTA
FBA
FBB
FBC
FBD
OUTB
OUTC
OUTD
DGNDAGND
REFAB REFCD
REFERENCE INPUTS +3.3V
VDD
Figure 9. Unipolar Output Circuit
MAX5253
Using an AC Reference
In applications where the reference has AC signal com-
ponents, the MAX5253 has multiplying capability within
the reference input range specifications. Figure 12
shows a technique for applying a sine-wave signal to
the reference input where the AC signal is offset before
being applied to REFAB/REFCD. The reference voltage
must never be more negative than DGND.
The MAX5253’s total harmonic distortion plus noise
(THD + N) is typically less than -72dB, given a 1V sig-
nal swing and input frequencies up to 25kHz. The typi-
cal -3dB frequency is 650kHz, as shown in the Typical
Operating Characteristics graphs.
Digitally Programmable Current Source
The circuit of Figure 13 places an NPN transistor
(2N3904 or similar) within the op-amp feedback loop to
implement a digitally programmable, unidirectional cur-
rent source. This circuit can be used to drive 4mA to
20mA current loops, which are commonly used in
industrial-control applications. The output current is cal-
culated with the following equation:
IOUT = (VREF / R) x (NB / 4096)
where NB is the numeric value of the DAC’s binary
input code and R is the sense resistor shown in
Figure 13.
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
14 ______________________________________________________________________________________
MAX5253
DAC A
DAC B
DAC C
DAC D
VREFAB = VREFCD = 1.25V
OUTA
10kΩ
10kΩ
10kΩ
10kΩ
16kΩ
16kΩ
16kΩ
16kΩ
OUTB
OUTC
OUTD
DGNDAGND
REFAB REFCD
REFERENCE INPUTS +3.3V
VDD FBA
FBB
FBC
FBD
Figure 10. Unipolar Rail-to-Rail Output Circuit
DAC
VOUT
+5V
-5V
R1 = R2 = 10kΩ ± 0.1%
MAX5253
REF_
R1 R2
FB_
OUT_
Figure 11. Bipolar Output Circuit
DAC_ OUT_
MAX5253
10kΩ
26kΩ
REF_ VDD
AGND DGND
+3.3V
AC
REFERENCE
INPUT
500mVP-P
1/2 MAX492
Figure 12. AC Reference Input Circuit
Power-Supply Considerations
On power-up, all input and DAC registers are cleared
(set to zero code) and DOUT is in Mode 0 (serial data
is shifted out of DOUT on the clock’s falling edge).
For rated MAX5253 performance, limit REFAB/REFCD
to less than 1.4V below VDD. Bypass VDD with a 4.7µF
capacitor in parallel with a 0.1µF capacitor to AGND.
Use short lead lengths and place the bypass capaci-
tors as close to the supply pins as possible.
Grounding and Layout Considerations
Digital or AC transient signals between AGND and
DGND can create noise at the analog outputs. Tie
AGND and DGND together at the DAC, then tie this
point to the highest-quality ground available.
Good printed circuit board ground layout minimizes
crosstalk between DAC outputs, reference inputs, and
digital inputs. Reduce crosstalk by keeping analog
lines away from digital lines. Wire-wrapped boards are
not recommended.
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
______________________________________________________________________________________ 15
DAC_
MAX5253
REF_
OUT_
R
IOUT
2N3904
VL
FB_
Figure 13. Digitally Programmable Current Source
__________________Pin Configuration
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
VDD
FBD
OUTD
OUTCOUTB
OUTA
FBA
AGND
TOP VIEW
FBC
REFCD
PDL
UPOCS
CL
REFAB
FBB
12
11
9
10
DOUT
DGNDSCLK
DIN
DIP/SSOP
MAX5253
MAX5253
+3V, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
_Ordering Information (continued) ___________________Chip Information
PART
MAX5253BC/D
MAX5253AEPP -40°C to +85°C
0°C to +70°C
TEMP RANGE PIN-PACKAGE
Dice*
20 Plastic DIP
INL
(LSBs)
±1
±1/2
*Dice are specified at TA= +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883.
MAX5253BEPP
MAX5253AEAP
MAX5253BEAP -40°C to +85°C
-40°C to +85°C
-40°C to +85°C 20 Plastic DIP
20 SSOP
20 SSOP
±1
±1/2
±1
MAX5253BMJP -55°C to +125°C 20 CERDIP** ±2
L
DIM
A
A1
B
C
D
E
e
H
L
α
DIM
D
D
D
D
D
MIN
0.068
0.002
0.010
0.004
0.205
0.301
0.025
0˚
MIN
0.239
0.239
0.278
0.317
0.397
MAX
0.078
0.008
0.015
0.008
0.209
0.311
0.037
8˚
MAX
0.249
0.249
0.289
0.328
0.407
MIN
1.73
0.05
0.25
0.09
5.20
7.65
0.63
0˚
MIN
6.07
6.07
7.07
8.07
10.07
MAX
1.99
0.21
0.38
0.20
5.38
7.90
0.95
8˚
PINS
14
16
20
24
28
MAX
6.33
6.33
7.33
8.33
10.33
INCHES
INCHES
MILLIMETERS
MILLIMETERS
α
SSOP
SHRINK
SMALL-OUTLINE
PACKAGE
HE
D
A
A1
C
B
0.65 BSC0.0256 BSC
21-0056A
e
SEE VARIATIONS
TRANSISTOR COUNT: 4337
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
