CDB4382A Evaluation Board for CS4382A Features Description Demonstrates recommended layout and grounding arrangements CS8416 receives S/PDIF, & EIAJ-340 compatible digital audio Headers for external audio input for either PCM or DSD(R) Requires only a digital signal source and Power supplies for a complete digital-to-analog converter system The CDB4382A evaluation board is an excellent means for quickly evaluating the CS4382A 24-bit, 48-pin, 8channel D/A converter. Evaluation requires an analog signal analyzer, a digital signal source, a PC for controlling the CS4382A (only required for control port mode), and a power supply. Analog line-level outputs are provided via RCA phono jacks. The CS8416 digital audio receiver IC provides the system timing necessary to operate the digital-to-analog converter and will accept S/PDIF and EIAJ-340-compatible audio data. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development. ORDERING INFORMATION CDB4382A Evaluation Board Hardware or Software Board Control Inputs for PCM Clocks and Data CS8416 Digital Audio Interface CS4382A Analog Outputs and Filtering Inputs for DSD Clocks and Data http://www.cirrus.com Copyright (c) Cirrus Logic, Inc. 2008 (All Rights Reserved) MAY '08 DS618DB3 CDB4382A TABLE OF CONTENTS 1. CS4382A DIGITAL-TO-ANALOG CONVERTER ................................................................................... 4 2. CS8416 DIGITAL AUDIO RECEIVER .................................................................................................... 4 3. INPUT FOR CLOCKS AND DATA ......................................................................................................... 4 4. INPUT FOR CONTROL DATA ............................................................................................................... 4 5. POWER SUPPLY CIRCUITRY ............................................................................................................... 5 6. GROUNDING AND POWER SUPPLY DECOUPLING .......................................................................... 5 7. ANALOG OUTPUT FILTERING ............................................................................................................. 5 8. PERFORMANCE PLOTS ....................................................................................................................... 7 9. SCHEMATICS ..................................................................................................................................... 17 10. REVISION HISTORY ......................................................................................................................... 30 LIST OF FIGURES Figure 1.FFT (48 kHz, 0 dB) ....................................................................................................................... 7 Figure 2.FFT (48 kHz, -60 dB) .................................................................................................................... 7 Figure 3.FFT (48 kHz, No Input) ................................................................................................................. 7 Figure 4.FFT (48 kHz Out-of-Band, No Input) ............................................................................................. 7 Figure 5.FFT (48 kHz, -60 dB Wideband) ................................................................................................... 8 Figure 6.FFT (IMD 48 kHz) ......................................................................................................................... 8 Figure 7.48 kHz, THD+N vs. Input Freq ...................................................................................................... 8 Figure 8.48 kHz, THD+N vs. Level ............................................................................................................. 8 Figure 9.48 kHz, Fade-to-Noise Linearity ................................................................................................... 8 Figure 10.48 kHz, Frequency Response ..................................................................................................... 8 Figure 11.48 kHz, Crosstalk ........................................................................................................................ 9 Figure 12.48 kHz, Impulse Response ......................................................................................................... 9 Figure 13.48 kHz, Impulse Prefilter ............................................................................................................. 9 Figure 14.Dynamic Range 48 kHz ............................................................................................................ 10 Figure 15.FFT (96 kHz, 0 dB) ................................................................................................................... 10 Figure 16.FFT (96 kHz, -60 dB) ................................................................................................................ 10 Figure 17.FFT (96 kHz, No Input) ............................................................................................................. 11 Figure 18.FFT (96 kHz Out-of-Band, No Input) ......................................................................................... 11 Figure 19.FFT (96 kHz, -60 dB Wideband) ............................................................................................... 11 Figure 20.FFT (IMD 96 kHz) ..................................................................................................................... 11 Figure 21.96 kHz, THD+N vs. Input Freq .................................................................................................. 11 Figure 22.96 kHz, THD+N vs. Level ......................................................................................................... 11 Figure 23.96 kHz, Fade-to-Noise Linearity ............................................................................................... 12 Figure 24.96 kHz, Frequency Response ................................................................................................... 12 Figure 25.96 kHz, Crosstalk ...................................................................................................................... 12 Figure 26.96 kHz, Impulse Response ....................................................................................................... 12 Figure 27.96 kHz, Impulse Prefilter ........................................................................................................... 12 Figure 28.Dynamic Range 96 kHz ............................................................................................................ 13 Figure 29.FFT (192 kHz, 0 dB) ................................................................................................................. 13 Figure 30.FFT (192 kHz, -60 dB) .............................................................................................................. 13 Figure 31.FFT (192 kHz, No Input) ........................................................................................................... 14 Figure 32.FFT (192 kHz Out-of-Band, No Input) ....................................................................................... 14 Figure 33.FFT (192 kHz, -60 dB Wideband) ............................................................................................. 14 Figure 34.FFT (IMD 192 kHz) ................................................................................................................... 14 Figure 35.192 kHz, THD+N vs. Input Freq ................................................................................................ 14 Figure 36.192 kHz, THD+N vs. Level ....................................................................................................... 14 Figure 37.192 kHz, Fade-to-Noise Linearity ............................................................................................. 15 Figure 38.192 kHz, Frequency Response ................................................................................................. 15 Figure 39.192 kHz, Crosstalk .................................................................................................................... 15 DS618DB3 2 CDB4382A Figure 40.192 kHz, Impulse Response ..................................................................................................... 15 Figure 41.192 kHz, Impulse Prefilter ......................................................................................................... 15 Figure 42.Dynamic Range 192 kHz .......................................................................................................... 16 Figure 43.System Block Diagram and Signal Flow ................................................................................... 17 Figure 44.CS4382A ................................................................................................................................... 18 Figure 45.Analog Output Pairs 1 & 2 ........................................................................................................ 19 Figure 46.Analog Output Pairs 3 & 4 ........................................................................................................ 20 Figure 47.Mute Circuits ............................................................................................................................. 21 Figure 48.CS8416 S/PDIF Input ............................................................................................................... 22 Figure 49.PCM Input Header and Muxing ................................................................................................. 23 Figure 50.DSD Input Header ..................................................................................................................... 24 Figure 51.Control Input ............................................................................................................................. 25 Figure 52.Power Inputs ............................................................................................................................. 26 Figure 53.Silkscreen Top .......................................................................................................................... 27 Figure 54.Top Side .................................................................................................................................... 28 Figure 55.Bottom Side .............................................................................................................................. 29 LIST OF TABLES Table 1. System Connections ..................................................................................................................... 5 Table 2. CDB4382A Jumper Settings ......................................................................................................... 6 DS618DB3 3 CDB4382A CDB4382A SYSTEM OVERVIEW The CDB4382A evaluation board is an excellent means of quickly evaluating the CS4382A. The CS8416 digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply external PCM or DSD clocks and data through PCB headers for system development. The CDB4382A uses the CDB4385 as a base PCB board. For this reason, there may be additional circuitry on board which is not populated as it has no function for this device. The CDB4382A schematic has been partitioned into the nine schematics shown in Figures 44 through 52. Each partitioned schematic is represented in the system diagram shown in Figure 43. Notice that the system diagram also includes the interconnections between the partitioned schematics. 1. CS4382A DIGITAL-TO-ANALOG CONVERTER A description of the CS4382A is included in the CS4382A datasheet. 2. CS8416 DIGITAL AUDIO RECEIVER The system receives and decodes the standard S/PDIF data format using a CS8416 digital audio receiver (Figure 48). The outputs of the CS8416 include a serial bit clock, serial data, left-right clock, and a 128/256 Fs master clock. The CS8416 data format is fixed to IS. The operation of the CS8416 and a discussion of the digital audio interface are included in the CS8416 datasheet. The evaluation board has been designed such that the input can be either optical or coaxial (See Figure 48). However, both inputs cannot be driven simultaneously. Switch position 7 of S1 sets the output MCLK-to-LRCK ratio of the CS8416. This switch should be set to 256 (closed) for inputs Fs 96 kHz and 128 (open) for Fs 64 kHz. The 8416 must be manually reset using `HW RST' (S2) or through the software when this switch is changed. 3. INPUT FOR CLOCKS AND DATA The evaluation board has been designed to allow interfacing to external systems via headers J11 and J7. Header J11 allows the evaluation board to accept externally generated PCM clocks and data. The schematic for the clock/data input is shown in Figure 49. Switch position 6 of S1 selects the source as either CS8416 (open) or header J11 (closed). Header J7 allows the evaluation board to accept externally generated DSD data and clocks. The schematic for the clock/data input is shown in Figure 50. A synchronous MCLK must still be provided via Header J11. Switch position 8 of S1 selects either PCM (open) or DSD (closed). Please see the CS4382A datasheet for more information. 4. INPUT FOR CONTROL DATA The evaluation board can be run in either a stand-alone mode or with a PC. Stand-alone mode uses the CS4382A in hardware mode and the mode pins are configured using switch positions 1 through 5 of S1. PC mode uses software to setup the CS4382A through IC(R) using the PC's serial or USB ports. PC mode is automatically selected when the serial or USB port is attached and the CDB4382A software is running. Header J15 offers the option for external input of RST and SPITM/IC clocks and data. The board is set up at the factory to use the on-board microcontroller in conjunction with the supplied software. To use an external control DS618DB3 4 CDB4382A source, remove the shunts on J15 and place a ribbon cable so the signal lines are on the center row and the grounds are on the right side. R116 and R119 should be populated with 2 k resistors when using an external IC source that does not already provide pull-ups. 5. POWER SUPPLY CIRCUITRY Power is supplied to the evaluation board by four binding posts: GND, +5V, +12V, and -12V (See Figure 52). The `+5V' terminal supplies VA and the rest of the +5 V circuitry on the board. The +3.3 V circuitry is powered from a regulator. The +2.5 V required for VD is also provided from an on-board regulator. The +5 V supply should be set within the recommended values for VA stated in the CS4382A datasheet. WARNING: Refer to the CS4382A datasheet for maximum allowable voltage levels. Operation outside this range can cause permanent damage to the device. 6. GROUNDING AND POWER SUPPLY DECOUPLING As with any high-performance converter, the CS4382A requires careful attention to power supply and grounding arrangements to optimize performance. Figure 44 details the connections to the CS4382A and Figures 53, 54, and 55 show the component placement and top and bottom layout. The decoupling capacitors are located as close to the CS4382A as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise. 7. ANALOG OUTPUT FILTERING The analog output on the CDB4382A has been designed according to the CS4382A datasheet. This output circuit includes an active 2-pole, 50-kHz filter which uses the multiple-feedback topology. CONNECTOR INPUT/OUTPUT SIGNAL PRESENT +5V Input + 5 V power GND Input Ground connection from power supply +12V Input +12 V positive supply for the on-board filtering -12V Input -12 V negative supply for the on-board filtering S/PDIF IN - J9 Input Digital audio interface input via coax S/PDIF IN - OPT1 Input Digital audio interface input via optical PCM INPUT - J11 Input Input for master, serial, left/right clocks and serial data DSD INPUT - J7 Input Input for DSD serial clock and DSD data OUTA1-B4 Output RCA line level analog outputs Table 1. System Connections DS618DB3 5 CDB4382A JUMPER / SWITCH PURPOSE POSITION FUNCTION SELECTED J15 Selects source of control data *shunts on Left shunts removed *Control from PC and on-board microcontroller External control input using center and right columns J16 JTAG micro programming - Reserved for factory use only S2 Resets CS8416 and CS4382A S1 The CS8416 must be reset if switch S1 is changed CS4382A mode settings M0-M4 1-5 Default: M0, M4 open (HI) M1, M2, M3 closed (LO) Sets clock source 6 Sets clock source for CS4382A *open = RX(CS8416), closed = EXT(J11) Sets MCLK ratio of CS8416 7 Selects 128x (open) or 256x (*closed) MCLK/LRCK ratio output for CS8416 Selects PCM or DSD mode 8 For PCM input set to *Open, for DSD set to Closed *Default Factory Settings Table 2. CDB4382A Jumper Settings DS618DB3 6 CDB4382A 8. PERFORMANCE PLOTS The plots in the following section were acheived using an Audio Precision System 2700 and a randomly chosen production CDB4382A. In some cases the performance may be limited by the CDB4382A. All measurements were taken at room temp using the standard AP filter options (20 Hz to 22 kHz) with default board settings and nominal datasheet voltages applied unless otherwise noted. The impulse response plots were taken both pre-and post filtering as the off-chip filter was degrading the performance at higher sample rates. The pre-filter impulse response plots were taken directly at the output pins of the DAC (with the analog filter still connected) to show the effect of the CDB's analog filtering on the impulse response (as the analog filtering adds its own signature to the impulse response of the DAC, and in the case of the higher sampling rates it was band-limiting it). +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 d B r A -60 -80 d B r -90 A -70 -70 -80 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k -150 20 Hz 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 1. FFT (48 kHz, 0 dB) Figure 2. FFT (48 kHz, -60 dB) +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 d B r d B r -70 -80 A -70 -80 A -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 20 50 100 200 500 1k 2k 5k Hz Figure 3. FFT (48 kHz, No Input) DS618DB3 10k 20k -150 20k 40k 60k 80k 100k 120k Hz Figure 4. FFT (48 kHz Out-of-Band, No Input) 7 CDB4382A +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 d B r -60 d B r -70 -80 A -70 -80 A -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 20 50 100 200 500 1k 2k 5k 10k -150 20k 2k 4k 6k 8k 10k Hz Figure 5. FFT (48 kHz, -60 dB Wideband) d B r A 12k 14k 16k 18k 20k Hz Figure 6. FFT (IMD 48 kHz) +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 d B r -60 A -70 -50 -60 -70 -80 -80 -90 -90 -100 -100 -110 -110 -120 20 50 100 200 500 1k 2k 5k 10k -120 -120 20k -100 -80 -60 -40 -20 +0 dBFS Hz Figure 7. 48 kHz, THD+N vs. Input Freq Figure 8. 48 kHz, THD+N vs. Level +5 +40 +35 +4 +30 +25 +3 +20 +2 +15 +10 +1 d B r +5 +0 d B r A -5 A +0 -1 -10 -15 -2 -20 -3 -25 -30 -4 -35 -40 -140 -120 -100 -80 -60 -40 -20 dBFS Figure 9. 48 kHz, Fade-to-Noise Linearity DS618DB3 +0 -5 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 10. 48 kHz, Frequency Response 8 CDB4382A +0 3 -10 2.5 -20 2 -30 -40 1.5 -50 1 -60 500m -70 d B V -80 -90 0 -500m -100 -1 -110 -1.5 -120 -2 -130 -140 -2.5 -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz -3 0 500u 1m 1.5m 2m 2.5m 3m sec Figure 11. 48 kHz, Crosstalk Figure 12. 48 kHz, Impulse Response 3 2.5 2 1.5 1 500m V 0 -500m -1 -1.5 -2 -2.5 -3 0 500u 1m 1.5m 2m 2.5m 3m sec Figure 13. 48 kHz, Impulse Prefilter DS618DB3 9 CDB4382A Figure 14. Dynamic Range 48 kHz +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 d B r A -60 -80 d B r -90 A -70 -70 -80 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -150 20 -140 50 100 200 500 1k 2k Hz 5k 10k 20k -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 15. FFT (96 kHz, 0 dB) DS618DB3 Figure 16. FFT (96 kHz, -60 dB) 10 CDB4382A +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 d B r -60 d B r -70 -70 -80 -80 A A -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 -150 20 50 100 200 500 1k 2k 5k 10k 20k 20k 40k 60k Figure 17. FFT (96 kHz, No Input) +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -60 d B r -70 -70 -80 -80 A A -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 50 100 200 500 1k 2k 5k 10k 20k 40k 2k 4k 6k Figure 19. FFT (96 kHz, -60 dB Wideband) A 8k 10k 12k 14k 16k 18k 20k Hz Hz d B r 120k -50 -60 -150 20 100k Figure 18. FFT (96 kHz Out-of-Band, No Input) -50 d B r 80k Hz Hz Figure 20. FFT (IMD 96 kHz) +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -60 d B r -70 A -80 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 20 50 100 200 500 1k 2k 5k Hz Figure 21. 96 kHz, THD+N vs. Input Freq DS618DB3 10k 20k -120 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 22. 96 kHz, THD+N vs. Level 11 CDB4382A +5 +40 +35 +4 +30 +25 +3 +20 +2 +15 +10 +1 d B r +5 +0 d B r A -5 A +0 -1 -10 -15 -2 -20 -3 -25 -30 -4 -35 -40 -140 -120 -100 -80 -60 -40 -20 -5 20 +0 50 100 200 500 1k 2k 5k 10k 20k Hz dBFS Figure 23. 96 kHz, Fade-to-Noise Linearity Figure 24. 96 kHz, Frequency Response +0 3 -10 2.5 -20 2 -30 1.5 -40 -50 1 -60 d B 500m -70 V 0 -80 -500m -90 -100 -1 -110 -1.5 -120 -2 -130 -2.5 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k -3 0 250u 500u 750u 1m 1.25m 1.5m sec Hz Figure 25. 96 kHz, Crosstalk Figure 26. 96 kHz, Impulse Response 3 2.5 2 1.5 1 500m V 0 -500m -1 -1.5 -2 -2.5 -3 0 250u 500u 750u 1m 1.25m 1.5m sec Figure 27. 96 kHz, Impulse Prefilter DS618DB3 12 CDB4382A Figure 28. Dynamic Range 96 kHz +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 d B r A -60 -80 d B r -90 A -70 -70 -80 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 20 50 100 200 500 1k 2k 5k Hz 10k 20k -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 29. FFT (192 kHz, 0 dB) DS618DB3 Figure 30. FFT (192 kHz, -60 dB) 13 CDB4382A +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 d B r d B r -70 -70 -80 -80 A A -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 -150 -150 20 50 100 200 500 1k 2k 5k 10k 20k 20k 40k 60k Figure 31. FFT (192 kHz, No Input) +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -80 -70 -80 A A -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 50 100 200 500 1k 2k 5k 10k 20k 50k -150 90k 2k 4k 6k Hz A +0 +0 -10 -20 -20 -30 -30 -40 -40 -50 -60 d B r -70 A -80 12k 14k 16k 18k 20k -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 50 100 200 500 1k 2k 5k 10k Hz Figure 35. 192 kHz, THD+N vs. Input Freq DS618DB3 10k Figure 34. FFT (IMD 192 kHz) -10 -120 20 8k Hz Figure 33. FFT (192 kHz, -60 dB Wideband) d B r 120k -60 d B r -70 -150 20 100k Figure 32. FFT (192 kHz Out-of-Band, No Input) -60 d B r 80k Hz Hz 20k -120 -120 -100 -80 -60 -40 -20 +0 dBFS Figure 36. 192 kHz, THD+N vs. Level 14 CDB4382A +5 +40 +35 +4 +30 +25 +3 +20 +2 +15 +10 +1 d B r +5 +0 d B r A -5 A -10 -15 +0 -1 -2 -20 -3 -25 -30 -4 -35 -40 -140 -120 -100 -80 -60 -40 -20 -5 20 +0 50 100 dBFS 200 500 1k 2k 5k 10k 20k Hz Figure 37. 192 kHz, Fade-to-Noise Linearity Figure 38. 192 kHz, Frequency Response +0 3 -10 2.5 -20 2 -30 1.5 -40 -50 1 -60 d B 500m -70 V 0 -80 -500m -90 -100 -1 -110 -1.5 -120 -2 -130 -2.5 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k -3 0 200u 400u 600u sec Hz Figure 39. 192 kHz, Crosstalk Figure 40. 192 kHz, Impulse Response 3 2.5 2 1.5 1 500m V 0 -500m -1 -1.5 -2 -2.5 -3 0 200u 400u 600u sec Figure 41. 192 kHz, Impulse Prefilter DS618DB3 15 CDB4382A Figure 42. Dynamic Range 192 kHz DS618DB3 16 DS618DB3 9. SCHEMATICS Power Serial Control Port Figure 51 on page 25 Figure 52 on page 26 Differential to Single-Ended Analog Outputs PCM HEADER PCM mux PCM Clocks/Data CS4382A Figure 49 on page 23 Figure 44 on page 18 A1, B1 Figure 45 on page 19 2 A2, B2 Figure 45 on page 19 2 A3, B3 Figure 46 on page 20 2 A4, B4 Figure 46 on page 20 Hardware Control Switches Figure 51 on page 25 DSD clk_enable DSD Clocks/Data PCM source select CS8416 S/PDIF Input DSD input enable PCM Clocks/Data Figure 48 on page 22 2 PCM Clocks/Data M0 - M4 switches (for stand-alone mode) Figure 49 on page 23 CS8416 clock setting Figure 43. System Block Diagram and Signal Flow I2C/SPI Header DSD HEADER Figure 50 on page 24 CDB4382A 17 18 CDB4382A DS618DB3 Figure 44. CS4382A DS618DB3 19 CDB4382A Figure 45. Analog Output Pairs 1 & 2 20 CDB4382A DS618DB3 Figure 46. Analog Output Pairs 3 & 4 CDB4382A Figure 47. Mute Circuits DS618DB3 21 22 CDB4382A DS618DB3 Figure 48. CS8416 S/PDIF Input DS618DB3 CDB4382A 23 Figure 49. PCM Input Header and Muxing 24 CDB4382A DS618DB3 Figure 50. DSD Input Header 25 CDB4382A DS618DB3 Figure 51. Control Input 26 CDB4382A DS618DB3 Figure 52. Power Inputs DS618DB3 CDB4382A 27 Figure 53. Silkscreen Top 28 CDB4382A DS618DB3 Figure 54. Top Side DS618DB3 29 CDB4382A Figure 55. Bottom Side CDB4382A 10.REVISION HISTORY Release DB1 DB2 DB3 Changes Initial Release Added Performance Plots Added USB support to Section 4. Input for Control Data Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). 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IC is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc DS618DB3 30