Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
http://www.cirrus.com
Evaluation Board for CS4382A
Features
Demonstrates recommended layout and
grounding arrangements
CS8416 receives S/PDIF, & EIAJ-340
compatible digital audio
Headers for external audio input for either PCM
or DSD®
Requires only a digital signal source and Power
supplies for a complete digital-to-analog
converter system
Description
The CDB4382A evaluation board is an excellent means
for quickly evaluating the CS4382A 24-bit, 48-pin, 8-
channel D/A converter. Evaluation requires an analog
signal analyzer, a digital signal source, a PC for control-
ling the CS4382A (only required for control port mode),
and a power supply. Analog line-level outputs are pro-
vided via RCA phono jacks.
The CS8416 digital audio receiver IC provides the sys-
tem timing necessary to operate the digital-to-analog
converter and will accept S/PDIF and EIAJ-340-com-
patible audio data. The evaluation board may also be
configured to accept external timing and data signals for
operation in a user application during system
development.
ORDERING INFORMATION
CDB4382A Evaluation Board
CS4382A Analog Outputs
and Filtering
Inputs for PCM
Clocks and Data
CS8416
Digital Audio
Interface
Hardware or
Software Board
Control
Inputs for DSD
Clocks and Data
MAY '08
DS618DB3
CDB4382A
DS618DB3 2
CDB4382A
TABLE OF CONTENTS
1. CS4382A DIGITAL-TO-ANALOG CONVERTER ................................................................................... 4
2. CS8416 DIGITAL AUDIO RECEIVER .................................................................................................... 4
3. INPUT FOR CLOCKS AND DATA ......................................................................................................... 4
4. INPUT FOR CONTROL DATA ............................................................................................................... 4
5. POWER SUPPLY CIRCUITRY ............................................................................................................... 5
6. GROUNDING AND POWER SUPPLY DECOUPLING .......................................................................... 5
7. ANALOG OUTPUT FILTERING ............................................................................................................. 5
8. PERFORMANCE PLOTS ....................................................................................................................... 7
9. SCHEMATICS ..................................................................................................................................... 17
10. REVISION HISTORY ............... ... .... ... ................................ ... .... ... ... ... ... .... ... ... ... ................................ 30
LIST OF FIGURES
Figure 1.FFT (48 kHz, 0 dB) ....................................................................................................................... 7
Figure 2.FFT (48 kHz, -60 dB) .................................................................................................................... 7
Figure 3.FFT (48 kHz, No Input) ................................................................................................................. 7
Figure 4.FFT (48 kHz Out-of-Band, No Input) ............................................................................................. 7
Figure 5.FFT (48 kHz, -60 dB Wideband) ................................................................................................... 8
Figure 6.FFT (IMD 48 kHz) ......................................................................................................................... 8
Figure 7.48 kHz, THD+N vs. Input Freq ...................................................................................................... 8
Figure 8.48 kHz, THD+N vs. Level ............................................................................................................. 8
Figure 9.48 kHz, Fade-to-Noise Linearity ................................................................................................... 8
Figure 10.48 kHz, Frequency Response ..................................................................................................... 8
Figure 11.48 kHz, Crosstalk ........................................................................................................................ 9
Figure 12.48 kHz, Impulse Response ......................................................................................................... 9
Figure 13.48 kHz, Impulse Prefilter ............................................................................................................. 9
Figure 14.Dynamic Range 48 kHz ............................................................................................................ 10
Figure 15.FFT (96 kHz, 0 dB) ................................................................................................................... 10
Figure 16.FFT (96 kHz, -60 dB) ................................................................................................................ 10
Figure 17.FFT (96 kHz, No Input) ............................................................................................................. 11
Figure 18.FFT (96 kHz Out-of-Band, No Input) .. .... ... ... ... .... ... ... ................... .................... ......................... 11
Figure 19.FFT (96 kHz, -60 dB Wideband) ............................................................................................... 11
Figure 20.FFT (IMD 96 kHz) ..................................................................................................................... 11
Figure 21.96 kHz, THD+N vs. Input Freq .................................................................................................. 11
Figure 22.96 kHz, THD+N vs. Level ......................................................................................................... 11
Figure 23.96 kHz, Fade-to-Noise Linearity ............................................................................................... 12
Figure 24.96 kHz, Frequency Response ................................................................................................... 12
Figure 25.96 kHz, Crosstalk ...................................................................................................................... 12
Figure 26.96 kHz, Impulse Response ....................................................................................................... 12
Figure 27.96 kHz, Impulse Prefilter ........................................................................................................... 12
Figure 28.Dynamic Range 96 kHz ............................................................................................................ 13
Figure 29.FFT (192 kHz, 0 dB) ................................................................................................................. 13
Figure 30.FFT (192 kHz, -60 dB) .............................................................................................................. 13
Figure 31.FFT (192 kHz, No Input) ........................................................................................................... 14
Figure 32.FFT (192 kHz Out-of-Band, No Input) ....................................................................................... 14
Figure 33.FFT (192 kHz, -60 dB Wideband) ............................................................................................. 14
Figure 34.FFT (IMD 192 kHz) ................................................................................................................... 14
Figure 35.192 kHz, THD+N vs. Input Freq ................................................................................................ 14
Figure 36.192 kHz, THD+N vs. Level ....................................................................................................... 14
Figure 37.192 kHz, Fade-to-Noise Linearity ............................................................................................. 15
Figure 38.192 kHz, Frequency Response ................................................................................................. 15
Figure 39.192 kHz, Crosstalk .................................................................................................................... 15
DS618DB3 3
CDB4382A
Figure 40.192 kHz, Impulse Response ..................................................................................................... 15
Figure 41.192 kHz, Impulse Prefilter ......................................................................................................... 15
Figure 42.Dynamic Range 192 kHz .......................................................................................................... 16
Figure 43.System Block Diagram and Signal Flow ................................................................................... 17
Figure 44.CS4382A ................................................................................................................................... 18
Figure 45.Analog Output Pairs 1 & 2 ..... ... ... ... ... ....................................................................................... 19
Figure 46.Analog Output Pairs 3 & 4 ..... ... ... ... ... ....................................................................................... 20
Figure 47.Mute Circuits ............................................................................................................................. 21
Figure 48.CS8416 S/PDIF Input ............................................................................................................... 22
Figure 49.PCM Input Header and Muxing ................................................................................................. 23
Figure 50.DSD Input Header ..................................................................................................................... 24
Figure 51.Control Input ............................................................................................................................. 25
Figure 52.Power Inputs ............................................................................................................................. 26
Figure 53.Silkscreen Top .......................................................................................................................... 27
Figure 54.Top Side .................................................................................................................................... 28
Figure 55.Bottom Side .............................................................................................................................. 29
LIST OF TABLES
Table 1. System Connections ...................... ... ... ................................................................. ... ..................... 5
Table 2. CDB4382A Jumper Settings ......................................................................................................... 6
DS618DB3 4
CDB4382A
CDB4382A SYSTEM OVERVIEW
The CDB4382A evalua tion board i s an excellent mean s of quickly evaluating the CS4382A. The CS8416 digital au-
dio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio
test equipment. The evaluation board also allows the user to supply external PCM or DSD clocks and data through
PCB headers for system development.
The CDB4382A uses the CDB4385 as a base PCB board. For this reason, there may be additional circuitry on board
which is not populated as it has no function for this device.
The CDB4382A schematic has been partitioned into the nine schematics shown in Figures 44 through 52. Each par-
titioned schematic is represented in the system diagram shown in Figure 43. Notice that the system diagram also
includes the interconnections between the partitioned schematics.
1. CS4382A DIGITAL-TO-ANALOG CONVERTER
A description of the CS4382A is inclu ded in the CS4382A datasheet.
2. CS8416 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8416 digital audio receiver
(Figure 48). The ou tputs of the CS8416 include a seria l bit clock, serial data, left-r ight clock, and a 128/256 Fs mas-
ter clock. The CS8416 data for mat is fixe d to I ²S. The oper ation of the CS8416 and a discussion of the digital audi o
interface are included in the CS8416 datasheet.
The evaluation board has been designed such that the input can be either optical or coaxia l (See Figure 48). How-
ever, both inputs cannot be driven simultaneously.
Switch position 7 of S1 sets the output MCLK-to-LRCK ratio of the CS8416. This switch should be set to 256 (closed)
for inputs Fs ≤96 kHz and 128 (open) for Fs ≥64 kHz. The 8416 must be manually reset using ‘HW RST’ (S2) or
through the software when this switch is changed.
3. INPUT FOR CLOCKS AND DATA
The evaluatio n board has been des igned to allow interfac ing to external systems via headers J11 and J7. Header
J11 allows the evaluation board to accept externally generated PCM clocks and data. The schematic for the
clock/data input is shown in Figure 49. Switch position 6 of S1 selects the source as either CS841 6 (open) or header
J11 (closed).
Header J7 allows the evaluatio n board to accept externally gener ated DSD data and clocks. The sche matic for the
clock/data input is shown in Figure 50. A synchronous MCLK must still be provided via Header J11. Switch position
8 of S1 selects either PCM (open) or DSD (clo sed).
Please see the CS4382A datasheet for more information.
4. INPUT FOR CONTROL DATA
The evaluation board can be run in either a stand-alone mode or with a PC. Stand-alone mode uses the CS4382A
in hardware mode and the mode pins are configured using switch positions 1 through 5 of S1. PC mode uses soft-
ware to setup the CS4382A through I²C® using the PC’s serial or USB ports. PC mode is automatically selected
when the serial or USB port is attached and the CDB4382A software is running.
Header J15 offers the option for external input of RST and SPI™/I²C clocks and data. The board is set up at the
factory to use the on-board microcontroller in conjunction with the supplied software. To use an external control
DS618DB3 5
CDB4382A
source, remove the shunts on J15 and place a ribbon cable so the signal lines are on the center row and the grounds
are on the right side. R116 a nd R119 should b e populated with 2 kΩ resistors when using an external I²C source
that does not already provide pull-ups.
5. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by four binding posts: GND, +5V, +12V, and -12V (See Figure 52). The
‘+5V’ terminal supplies VA and the rest of the +5 V circuitry on the board. The +3.3 V circuitry is powered from a
regulator. Th e +2.5 V required for V D is also prov ided from an on-board regulator. The +5 V supply should be set
within the recommended values for VA stated in the CS4382A datasheet.
WARNING:Refer to the CS4382A datasheet for maximum allowable voltage levels. Operation outside this range
can cause permanent damage to the device.
6. GROUNDING AND POWER SUPPLY DECOUPLING
As with any high-pe rformance converter, the CS438 2A requires ca reful attention to po wer supply and gro unding ar-
rangements to optimize per formance. Figure 44 details the connections to the CS4382A and Figures 53, 54, and 55
show the component placement and top and bottom layout. The decoupling capacitors are located as close to the
CS4382A as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated
noise.
7. ANALOG OUTPUT FILTERING
The analog output on the CDB4382A has been designed according to the CS4382A datasheet. This output circuit
includes an active 2-pole, 50-kHz filter which uses the multiple-feedback topology.
Table 1. System Connections
CONNECTOR INPUT/OUTPUT SIGNAL PRESENT
+5V Input + 5 V power
GND Input Ground connection from power supply
+12V Input +12 V positive supply for the on-board filtering
-12V Input -12 V negative supply for the on-board filtering
S/PDIF IN - J9 Input Digital audio interface input via coax
S/PDIF IN - OPT1 Input Digital audio interface input via optical
PCM INPUT - J11 Input Input for master, serial, left/right clocks and serial data
DSD INPUT - J7 Input Input for DSD serial clock and DSD data
OUTA1-B4 Output RCA line level analog outputs
DS618DB3 6
CDB4382A
Table 2. CDB4382A Jumper Settings
JUMPER /
SWITCH PURPOSE POSITION FUNCTION SELECTED
J15 Selects source of control
data *shunts on Left
shunts removed *Control from PC and on-board microcontroller
External control input using center and right columns
J16 JTAG micro programming - Reserved for factory use only
S2 Resets CS8416 and
CS4382A The CS8416 must be reset if switch S1 is changed
S1
CS4382A mode settings
M0-M4 1-5 Default: M0, M4 open (HI)
M1, M2, M3 closed (LO)
Sets clock source 6 Sets clock source for CS4382A
*open = RX(CS8416), closed = EXT(J11)
Sets MCLK ratio of CS8416 7 Selects 128x (open) or 256x (*closed) MCLK/LRCK
ratio output for CS8416
Selects PCM or DSD mode 8 For PCM input set to *Open, for DSD set to Closed
*Default Factory Settings
DS618DB3 7
CDB4382A
8. PERFORMANCE PLOTS
The plots in the following section were ache ived using an Audio Precision System 2700 and a randomly chosen p ro-
duction CDB4382A. In some cases the performance may be limited by the CDB4382A. All measurements were
taken at room temp using the standard AP filter options (20 Hz to 22 kHz) with default board settings and nominal
datasheet voltag e s ap plie d unle ss oth e rwis e no te d.
The impulse response plots were taken both pre-and post filtering as the off-chip filter was degrading the perfor-
mance at higher sample rates. The pre-filter impulse response plots were taken directly at the output pins of the
DAC (with the analog filter still connected) to show the effect of the CDB’s analog filtering on the impulse response
(as the analog filtering adds its own signature to the impulse response of the DAC, and in the case of the higher
sampling rates it was band-limiting it).
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d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz -150
+0
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-90
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d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 1. FFT (48 kHz, 0 dB) Figure 2. FFT (48 kHz, -60 dB)
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+0
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d
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A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
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+0
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d
B
r
A
20k 120k40k 60k 80k 100k
Hz
Figure 3. FFT (48 kHz, No Input) Figure 4. FFT (48 kHz Out-of-Band, No Input)
DS618DB3 8
CDB4382A
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+0
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d
B
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A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
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+0
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d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
Figure 5. FFT (48 kHz, -60 dB Wideband) Figure 6. FFT (IMD 48 kHz)
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+0
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d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
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+0
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d
B
r
A
-120 +0-100 -80 -60 -40 -20
dBFS
Figure 7. 48 kHz, THD+N vs. Input Freq Figure 8. 48 kHz, THD+N vs. Level
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+40
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-10
-5
+0
+5
+10
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+30
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d
B
r
A
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dBFS
-5
+5
-4
-3
-2
-1
+0
+1
+2
+3
+4
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 9. 48 kHz, Fade-to-Noise Linearity Figure 10. 48 kHz, Frequency Response
DS618DB3 9
CDB4382A
-150
+0
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-110
-100
-90
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-50
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-20
-10
d
B
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-3
3
-2.5
-2
-1.5
-1
-500m
0
500m
1
1.5
2
2.5
V
03m500u 1m 1.5m 2m 2.5m
sec
Figure 11. 48 kHz, Crosstalk Figure 12. 48 kHz, Impulse Response
-3
3
-2.5
-2
-1.5
-1
-500m
0
500m
1
1.5
2
2.5
V
03m500u 1m 1.5m 2m 2.5m
sec
Figure 13. 48 kHz, Impulse Prefilter
DS618DB3 11
CDB4382A
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d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
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+0
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d
B
r
A
20k 120k40k 60k 80k 100k
Hz
Figure 17. FFT (96 kHz, No Input) Figure 18. FFT (96 kHz Out-of-Band, No Input)
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+0
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d
B
r
A
20 40k50 100 200 500 1k 2k 5k 10k 20k
Hz
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+0
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-10
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
Figure 19. FFT (96 kHz, -60 dB Wideband) Figure 20. FFT (IMD 96 kHz)
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+0
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-90
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-50
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d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
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+0
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-90
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-50
-40
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-10
d
B
r
A
-120 +0-100 -80 -60 -40 -20
dBFS
Figure 21. 96 kHz, THD+N vs. Input Freq Figure 22. 96 kHz, THD+N vs. Level
DS618DB3 12
CDB4382A
-5
+5
-4
-3
-2
-1
+0
+1
+2
+3
+4
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
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+40
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-20
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-10
-5
+0
+5
+10
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+30
+35
d
B
r
A
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dBFS
Figure 23. 96 kHz, Fade-to-Noise Linearity Figure 24. 96 kHz, Frequency Response
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+0
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-100
-90
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-10
d
B
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-3
3
-2.5
-2
-1.5
-1
-500m
0
500m
1
1.5
2
2.5
V
01.5m250u 500u 750u 1m 1.25m
sec
Figure 25. 96 kHz, Crosstalk Figure 26. 96 kHz, Impulse Response
-3
3
-2.5
-2
-1.5
-1
-500m
0
500m
1
1.5
2
2.5
V
01.5m250u 500u 750u 1m 1.25m
sec
Figure 27. 96 kHz, Impulse Prefilter
DS618DB3 13
CDB4382A
Figure 28. Dynamic Range 96 kHz
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B
r
A
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Hz -150
+0
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d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 29. FFT (192 kHz, 0 dB) Figure 30. FFT (192 kHz, -60 dB)
DS618DB3 14
CDB4382A
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d
B
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A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
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d
B
r
A
20k 120k40k 60k 80k 100k
Hz
Figure 31. FFT (192 kHz, No Input) Figure 32. FFT (192 kHz Out-of-Band, No Input)
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A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
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d
B
r
A
20 90k50 100 200 500 1k 2k 5k 10k 20k 50k
Hz
Figure 33. FFT (192 kHz, -60 dB Wideband) Figure 34. FFT (IMD 192 kHz)
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+0
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d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
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+0
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d
B
r
A
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dBFS
Figure 35. 192 kHz, THD+N vs. Input Freq Figure 36. 192 kHz, THD+N vs. Level
DS618DB3 15
CDB4382A
-40
+40
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-15
-10
-5
+0
+5
+10
+15
+20
+25
+30
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d
B
r
A
-140 +0-120 -100 -80 -60 -40 -20
dBFS
-5
+5
-4
-3
-2
-1
+0
+1
+2
+3
+4
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 37. 192 kHz, Fade-to-Noise Linearity Figure 38. 192 kHz, Frequency Response
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+0
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d
B
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-3
3
-2.5
-2
-1.5
-1
-500m
0
500m
1
1.5
2
2.5
V
0600u200u 400u
sec
Figure 39. 192 kHz, Crosstalk Figure 40. 192 kHz, Impulse Response
-3
3
-2.5
-2
-1.5
-1
-500m
0
500m
1
1.5
2
2.5
V
0600u200u 400u
sec
Figure 41. 192 kHz, Impu lse Prefilter
DS618DB3 17
CDB4382A
9. SCHEMATICS
CS4382A
CS8416
S/PDIF
Input
Serial Control Por t
PCM mux
I2C/SPI Header
Power
DSD
Clocks/Data
DSD HEADER
2
2
DSD clk_enable
PCM Clocks/Data
DSD input enable
M0 - M4 switches
(for stand-alone mode)
PCM source select
CS8416 clock
setting
Hardwa re Control
Switches
PCM HEADER
2
2
A1, B1
A2, B2
A3, B3
A4, B4
Differential to Single-Ended
Analog Output s
PCM Clocks/Data
PCM Clocks/Data
Figure 52 on page 2 6
Figure 45 on page 19
Figure 45 on page 19
Figure 46 o n pa ge 2 0
Figure 46 on page 20
Figure 51 on page 25
Figure 49
on page 23
Figure 49
on page 23
Figure 48
on page 22
Figure 51 on page 25Figure 50 on page 24
Figure 44 on page 18
Figure 43. System Block Diagram and Signal Flow
DS618DB3 30
CDB4382A
10.REVISION HISTORY
Release Changes
DB1 Initial Release
DB2 Added Performance Plots
DB3 Added USB support to Section 4. Input for Control Data
Contacting Cirrus Logic Support
For all product questions and inq uiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without not ice and is pr ovided "AS IS" witho ut warr anty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by C irrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringemen t of patents or o ther righ ts of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any paten ts, mask wo rk rights,
copyrights, tradem arks, trade secrets or oth er intellectual prop erty rights. Cirrus ow ns the copyrights a ssociated with the information contained herein and gives con-
sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJ URY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT-
ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND
CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED W ARRANTIES OF M ERCHANTABIL ITY
AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CI RRUS PRODUCT THAT IS US ED IN SUCH A MANNER. IF THE CUSTOMER OR
CUSTOMER ’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODU CTS IN CRITICAL APPLIC ATIONS, CUSTOMER AGREES, BY SUCH USE, TO
FULLY INDEMNI FY CI RRUS , I TS OF FI CERS, DI RE CTORS , EMPLOYEE S, DIST RIB UTORS AND OTHER AGE NTS FROM ANY AND ALL LI A BIL I TY, I NCLUD-
ING ATTORNE YS ’ FEES AND COSTS, THAT MA Y RE S ULT FROM OR ARIS E IN CO NNECTION WITH THE SE US ES .
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
DSD is a registered tradem ar k of So ny K ab ush iki K aish a TA So ny Co m p an y.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc
