_______________General Description
The MAX197 multi-range, 12-bit data-acquisition sys-
tem (DAS) requires only a single +5V supply for opera-
tion, yet accepts signals at its analog inputs that may
span both above the power-supply rail and below
ground. This system provides 8 analog input channels
that are independently software programmable for a
variety of ranges: ±10V, ±5V, 0V to +10V, or 0V to +5V.
This increases effective dynamic range to 14 bits, and
provides the user flexibility to interface 4mA-to-20mA,
±12V, and ±15V powered sensors to a single +5V sys-
tem. In addition, the converter is overvoltage tolerant to
±16.5V; a fault condition on any channel does not
affect the conversion result of the selected channel.
Other features include a 5MHz bandwidth track/hold, a
100ksps throughput rate, software-selectable internal or
external clock and acquisition, 8+4 parallel interface,
and an internal 4.096V or an external reference.
A hardware SHDN pin and two programmable power-
down modes (STBYPD, FULLPD) are provided for low-
current shutdown between conversions. In STBYPD
mode, the reference buffer remains active, eliminating
start-up delays.
The MAX197 employs a standard microprocessor (µP)
interface. A three-state data I/O port is configured to
operate with 8-bit data buses, and data-access and
bus-release timing specifications are compatible with
most popular µPs. All logic inputs and outputs are
TTL/CMOS compatible.
The MAX197 is available in 28-pin DIP, wide SO, SSOP,
and ceramic SB packages.
For a different combination of ranges (±4V, ±2V, 0V to
4V, 0V to 2V), refer to the MAX199 data sheet. For 12-bit
bus interface, refer to the MAX196 and MAX198 data
sheets.
________________________Applications
Industrial-Control Systems
Robotics
Data-Acquisition Systems
Automatic Testing Systems
Medical Instruments
Telecommunications
____________________________Features
♦12-Bit Resolution, 1/2LSB Linearity
♦Single +5V Operation
♦Software-Selectable Input Ranges:
±10V, ±5V, 0V to 10V, 0V to 5V
♦Fault-Protected Input Multiplexer (±16.5V)
♦8 Analog Input Channels
♦6µs Conversion Time, 100ksps Sampling Rate
♦Internal or External Acquisition Control
♦Internal 4.096V or External Reference
♦Two Power-Down Modes
♦Internal or External Clock
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
________________________________________________________________ Maxim Integrated Products 1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DGND
VDD
REF
REFADJ
INT
CH7
AGND
CH6
CH5
CH4
CH3
CH2
CH1
CH0
D0/D8
D1/D9
D2/D10
D3/D11
D4
D5
D6
D7
SHDN
HBEN
RD
WR
CS
CLK
DIP/SO/SSOP/Ceramic SB
TOP VIEW
MAX197
__________________Pin Configuration
19-0381; Rev 2; 9/01
PART
MAX197ACNI
MAX197BCNI
MAX197ACWI 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP RANGE PIN-PACKAGE
28 Narrow Plastic DIP
28 Narrow Plastic DIP
28 Wide SO
______________Ordering Information
MAX197BCWI 0°C to +70°C 28 Wide SO
MAX197ACAI 0°C to +70°C 28 SSOP
MAX197BCAI 0°C to +70°C 28 SSOP
MAX197BC/D 0°C to +70°C Dice*
Ordering Information continued at end of data sheet.
*Dice are specified at TA= +25°C, DC parameters only.
EVALUATION KIT
MANUAL AVAILABLE
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Functional Diagram appears at end of data sheet.
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA= TMIN to TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND............................................................-0.3V to +7V
AGND to DGND.....................................................-0.3V to +0.3V
REF to AGND..............................................-0.3V to (VDD + 0.3V)
REFADJ to AGND.......................................-0.3V to (VDD + 0.3V)
Digital Inputs to DGND...............................-0.3V to (VDD + 0.3V)
Digital Outputs to DGND............................-0.3V to (VDD + 0.3V)
CH0–CH7 to AGND ..........................................................±16.5V
Continuous Power Dissipation (TA= +70°C)
Narrow Plastic DIP (derate 14.29mW/°C above +70°C)....1143mW
Wide SO (derate 12.50mW/°C above +70°C)..............1000mW
SSOP (derate 9.52mW/°C above +70°C) ......................762mW
Narrow Ceramic SB (derate 20.00mW/°C above +70°C)..1600mW
Operating Temperature Ranges
MAX197_C_ _ .......................................................0°C to +70°C
MAX197_E_ _.....................................................-40°C to +85°C
MAX197_M_ _..................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
MAX197A
Internal CLK mode/internal acquisition
control (Note 4)
External CLK mode/external acquisition
control
External CLK mode/external acquisition control
50kHz, VIN = ±5V (Note 3)
Bipolar
Unipolar
Up to the 5th harmonic
Bipolar
MAX197B
Unipolar
CONDITIONS
10
ps<50
Aperture Jitter
ns15Aperture Delay
dB-86Channel-to-Channel Crosstalk
dB80SFDRSpurious-Free Dynamic Range
dB-85 -78THDTotal Harmonic Distortion
dB
70
LSB
±1/2
INLIntegral Nonlinearity
Bits12Resolution
±0.5 LSB
±0.1
Channel-to-Channel Offset
Error Matching
±10
±5
±1
LSB±1DNLDifferential Nonlinearity
LSB
±3
Offset Error ±5
UNITSMIN TYP MAXSYMBOLPARAMETER
MAX197A
MAX197B
MAX197A
MAX197B
Bipolar
Unipolar
Bipolar
Unipolar
5ppm/°C
3
Gain Temperature Coefficient
(Note 2)
±10
MAX197A
±7
MAX197B
MAX197A
MAX197B
LSB
±7
Gain Error
(Note 2)
±10
69
SINADSignal-to-Noise + Distortion Ratio
ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10Vp-p, fSAMPLE = 100ksps)
MAX197A
MAX197B
ns
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA= TMIN to TMAX, unless otherwise noted.)
fCLK = 2.0MHz
TA= +25°C
(Note 5)
Unipolar
CONDITIONS
mA30Output Short-Circuit Current
ppm/°C40REF Output Tempco
V4.076 4.096 4.116VREF
REF Output Voltage
pF40Input Capacitance
µs3Track/Hold Acquisition Time
05
V
010
Input Voltage Range
(See Table 1)
1.25
-3dB rolloff 2.5
UNITSMIN TYP MAXSYMBOLPARAMETER
MHz
5
Small-Signal Bandwidth 2.5
Bipolar
Unipolar
-600 360
0V to 10V range
-1200 720
0V to 5V range
-10V to 10V range
-5V to 5V range
Bipolar
µA
720
Input Current
Unipolar
360
16 kΩ
21
Input Dynamic Resistance
Bipolar -5 5
-10 10
0mA to 0.5mA output current (Note 6) mV7.5Load Regulation
V2.465 2.500 2.535REFADJ Output Voltage
µF4.7Capacitive Bypass at REF
With recommended circuit (Figure 1) %±1.5REFADJ Adjustment Range
V/V1.6384Buffer Voltage Gain
V2.4 4.18Input Voltage Range
µA
400
Input Current VREF = 4.18V
1
VVDD - 50mV
REFADJ Threshold for
Buffer Disable
Normal or STANDBY power-down mode kΩ10
Input Resistance FULL power-down mode 5 MΩ
ANALOG INPUT
INTERNAL REFERENCE
REFERENCE INPUT (Buffer disabled, reference input applied to REF pin)
±10V range
±5V range
0V to 10V range
0V to 5V range
Normal or STANDBY
power-down mode
FULL power-down
mode
TC VREF
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA= TMIN to TMAX, unless otherwise noted.)
Internal acquisition 3.0 5.0
External reference = 4.096V
After FULLPD or STBYPD
External acquisition (Note 9)
CONDITIONS
Full power-down mode (FULLPD) (Note 7)
5
µs
3.0
tACQI
Acquisition Time
LSB
±1/2
PSRR
Power-Supply Rejection Ratio
(Note 8)
3.0
tACQE
External CLK µs
V4.75 5.25VDD
Supply Voltage
6.0
tCONV
Conversion Time Internal CLK, CCLK = 100pF 6.0 7.7 10.0
To 0.1mV REF bypass
capacitor fully discharged ms
8
Reference Buffer Settling
120
60
Normal mode, bipolar ranges
700 850
Normal mode, unipolar ranges
UNITSMIN TYP MAXSYMBOLPARAMETER
Standby power-down (STBYPD)
mA
18
IDD
Supply Current 610
µA
Internal reference ±1/2
CCLK = 100pF MHz1.25 1.56 2.00fCLK
Internal Clock Frequency
0.1 2.0fCLK
External Clock Frequency Range MHz
External CLK
Internal CLK
Power-up (Note 10) µs200
Bandgap Reference
Start-Up Time
External CLK ksps
100
Throughput Rate Internal CLK, CCLK = 100pF 62
CREF = 4.7µF
CREF = 33µF
V2.4VINH
Input High Voltage
V0.8VINL
Input Low Voltage
VIN = 0V or VDD µA±10IIN
Input Leakage Current
(Note 5) pF15CIN
Input Capacitance
VDD = 4.75V, ISINK = 1.6mA V0.4VOL
Output Low Voltage
VDD = 4.75V, ISOURCE = 1mA VVDD - 1VOH
Output High Voltage
(Note 5) pF15COUT
Three-State Output Capacitance
POWER REQUIREMENTS
TIMING
DIGITAL INPUTS (D7–D0, CLK, RD, WR, CS, HBEN, SHDN) (Note 11)
DIGITAL OUTPUTS (D7–D4, D3/D11, D2/D10, D1/D9, D0/D8, INT)
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
_______________________________________________________________________________________ 5
Note 1: Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the ±10V input range.
Note 2: External reference: VREF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Note 3: Ground "on" channel; sine wave applied to all "off" channels.
Note 4: Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5: Guaranteed by design. Not tested.
Note 6: Use static loads only.
Note 7: Tested using internal reference.
Note 8: PSRR measured at full-scale.
Note 9: External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD
= high control byte.
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with tR= tF= 5ns from a voltage level of 0.8V to 2.4V.
Note 12: tDO and tDO1 are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V
or 2.4V.
Note 13: tTR is defined as the time required for the data lines to change by 0.5V.
TIMING CHARACTERISTICS
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA= TMIN to TMAX, unless otherwise noted.)
(Note 13) ns
70
CONDITIONS
tTR
RD High to Output Disable
ns120tINT1
RD Low to INT High Delay
ns80tCS
CS Pulse Width
UNITSMIN TYP MAXSYMBOLPARAMETER
ns80tWR
WR Pulse Width
ns0tCSWS
ns0tCSWH
CS to WR Hold Time
CS to WR Setup Time
ns0tCSRS
ns0tCSRH
CS to RD Hold Time
CS to RD Setup Time
ns100tCWS
ns50tCWH
CLK to WR Hold Time
CLK to WR Setup Time
ns60tDS
ns0tDH
Data Valid to WR Hold
Data Valid to WR Setup
Figure 2, CL= 100pF (Note 12)
Figure 2, CL= 100pF (Note 12)
ns120tDO
ns120tDO1
HBEN High or HBEN Low to
Output Valid
RD Low to Output Data Valid
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
6 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
-0.150
0 1000 3000
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
-0.050
0.250
MAX197-1
DIGITAL CODE
INTEGRAL NONLINEARITY (LSB)
2000 4000
0.150
0.050
-0.100
0.000
0.200
0.100
0
-120
05025
FFT PLOT
-100
-60
-40
-20
FREQUENCY (kHz)
AMPLITUDE (dB)
-80
fTONE = 10kHz
fSAMPLE = 100kHz
MAX197-2
10.0
1 10 100
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCY
10.5
MAX197-3
INPUT FREQUENCY (kHz)
EFFECTIVE NUMBER OF BITS
11.0
11.5
12.0
FSAMPLE = 100kHz
4.100
4.080
-55 -35 45 105 125
TEMPERATURE (°C)
VREF (V)
-15 525 65
85
4.095
4.090
4.085
REFERENCE OUTPUT VOLTAGE (VREF)
vs. TEMPERATURE
MAX197-4
REFADJ
AV = 1.6384
REF
+2.5V
INTERNAL
REFERENCE
0.33
0.27
-70 -50 50 110 130
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL
GAIN-ERROR MATCHING (LSB)
-30 -10 10 30 70 90
0.32
0.30
0.29
0.28
0.31
CHANNEL-TO-CHANNEL
GAIN-ERROR MATCHING vs. TEMPERATURE
MAX197-7
MAX197-5
-70 -50 50 110 130
TEMPERATURE (°C)
PSRR (LSB)
-30 -10 10 30 70 90
0.2
0.4
-0.2
-0.4
-0.6
0
POWER-SUPPLY REJECTION RATIO
vs. TEMPERATURE
100Hz
120Hz
VDD = 5V ±0.25V
MAX197-6
0.10
-70 -50 50 110 130
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL
OFFSET-ERROR MATCHING (LSB)
-30 -10 10 30 70 90
0.20
0.16
0.14
0.12
0.18
CHANNEL-TO-CHANNEL
OFFSET-ERROR MATCHING vs. TEMPERATURE
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
Digital GroundDGND28
+5V Supply. Bypass with 0.1µF capacitor to AGND.VDD
27
INT goes low when conversion is complete and output data is ready.INT
24
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND. Connect
to VDD when using an external reference at the REF pin.
REFADJ25
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a
4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal
buffer by pulling REFADJ to VDD.
REF26
Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high).D2/D1012
Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high).D1/D913
Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB.D0/D814
Analog GroundAGND15
Analog Input ChannelsCH0–CH716–23
Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus;
when low, the 8 LSBs are available on the bus.
HBEN5
Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low.
SHDN
6
Three-State Digital I/OD7–D47–10
Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high).D3/D1111
If CS is low, a falling edge on RD will enable a read operation on the data bus.RD
4
When CS is low, in the internal acquisition mode, a rising edge on WR latches in configuration data and starts an
acquisition plus a conversion cycle. When CS is low, in the external acquisition mode, the first rising edge on
WR starts an acquisition and a second rising edge on WR ends acquisition and starts a conversion cycle.
WR
3
PIN
Chip Select, active low.
CS
2
Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode,
place a capacitor from this pin to ground to set the internal clock frequency; fCLK = 1.56MHz typical with
CCLK = 100pF.
CLK1
FUNCTIONNAME
100kΩ510kΩ
24kΩ
REFADJ
+5V
0.01µF
MAX197
Figure 1. Reference-Adjust Circuit
3kΩ
3kΩ
DOUT
DOUT
+5V
a. HIGH-Z TO VOH AND VOL TO VOH b. HIGH-Z TO VOL AND VOH TO VOL
CLOAD CLOAD
Figure 2. Load Circuits for Enable Time
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
8 _______________________________________________________________________________________
_______________Detailed Description
Converter Operation
The MAX197, a multi-range, fault-tolerant ADC, uses
successive approximation and internal input track/hold
(T/H) circuitry to convert an analog signal to a 12-bit
digital output. The parallel-output format provides easy
interface to microprocessors (µPs). Figure 3 shows the
MAX197 in its simplest operational configuration.
Analog-Input Track/Hold
In the internal acquisition control mode (control bit D5
set to 0), the T/H enters its tracking mode on WR’s ris-
ing edge, and enters its hold mode when the internally
timed (6 clock cycles) acquisition interval ends. A low
impedance input source, which settles in less than
1.5µs, is required to maintain conversion accuracy at
the maximum conversion rate.
In the external acquisition control mode (D5 = 1), the
T/H enters its tracking mode on the first WR rising edge
and enters its hold mode when it detects the second WR
rising edge with D5 = 0. See the External Acquisition
section.
Input Bandwidth
The ADC’s input tracking circuitry has a 5MHz small-
signal bandwidth. When using the internal acquisition
mode with an external clock frequency of 2MHz, a
100ksps throughput rate can be achieved. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended (MAX274/MAX275 continuous-time filters).
Input Range and Protection
Figure 4 shows the equivalent input circuit. With VREF =
4.096V, the MAX197 can be programmed for input
ranges of ±10V, ±5V, 0V to 10V, or 0V to 5V by setting the
appropriate control bits (D3, D4) in the control byte (see
Tables 2 and 3). The full-scale input voltage depends on
the voltage at REF (Table 1). When an external reference
is applied at REFADJ, the voltage at REF is given by VREF
= 1.6384 x VREFADJ (2.4V < VREF < 4.18V).
DGND
VDD
REF
REFADJ
INT
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
AGND
28
27
26
4.7µF
0.1µF
+5V
+4.096V
OUTPUT STATUS
25
24
23
22
21
20
19
18
17
16
1
2
µP
CONTROL
INPUTS
3
4
5
6
CLK
CS
WR
RD
HBEN
SHDN
D7
D6
D5
D4
D3/D11
D2/D10
D1/D9
D0/D8
100pF
µP DATA BUS
15
7
8
9
10
11
12
13
14
ANALOG
INPUTS
MAX197
Figure 3. Operational Diagram
5.12kΩ
8.67kΩ
12.5kΩ
CH_
S1
S2
S3
S4
BIPOLAR
UNIPOLAR
VOLTAGE
REFERENCE
T/H
OUT
HOLDTRACK
TRACKHOLD
OFF
ON
CHOLD
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
Figure 4. Equivalent Input Circuit
RANGE (V)
ZERO SCALE
(V) -FULL SCALE +FULL SCALE
0 to 5 0 — VREF x 1.2207
0 to 10 0 — VREF x 2.4414
±5 —-VREF x 1.2207 VREF x 1.2207
±10 —-VREF x 2.4414 VREF x 2.4414
Table 1. Full Scale and Zero Scale
The input channels are overvoltage protected to
±16.5V. This protection is active even if the device is in
power-down mode.
Even with VDD = 0V, the input resistive network provides
current-limiting that adequately protects the device.
Digital Interface
Input data (control byte) and output data are multiplexed
on a three-state parallel interface. This parallel I/O can
easily be interfaced with a µP. CS, WR, and RD control
the write and read operations. CS is the standard chip-
select signal, which enables a µP to address the MAX197
as an I/O port. When high, it disables the WR and RD
inputs and forces the interface into a high-Z state.
Input Format
The control byte is latched into the device, on pins
D7–D0, during a write cycle. Table 2 shows the control-
byte format.
Output Data Format
The output data format is binary in unipolar mode and
twos-complement binary in bipolar mode. When read-
ing the output data, CS, and RD must be low. When
HBEN is low, the lower eight bits are read. When HBEN
is high, the upper four MSBs are available and the out-
put data bits D4–D7 are either set low (in unipolar
mode) or set to the value of the MSB (in bipolar mode)
(Table 6).
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
_______________________________________________________________________________________ 9
Table 2. Control-Byte Format
D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB)
PD1 PD0 ACQMOD RNG BIP A2 A1 A0
Table 4. Clock and Power-Down Selection
PD1 PD0 DEVICE MODE
0 0 Normal Operation / External Clock Mode
0 1 Normal Operation / Internal Clock Mode
1 0 Standby Power-Down (STBYPD); clock mode
is unaffected
1 1 Full Power-Down (FULLPD); clock mode is
unaffected
Table 3. Range and Polarity Selection
BIP RNG INPUT RANGE (V)
0 0 0 to 5
0 1 0 to 10
1 0 ±5
1 1 ±10
Table 5. Channel Selection
A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
0 0 0 —
0 0 1 —
0 1 0 —
0 1 1 —
1 0 0 —
1 0 1 —
1 1 0 —
1 1 1 —
BIT NAME DESCRIPTION
7, 6 PD1, PD0 These two bits select the clock and power-down modes (Table 4).
5ACQMOD 0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition
4RNG Selects the full-scale voltage magnitude at the input (Table 3).
3BIP Selects unipolar or bipolar conversion mode (Table 3).
2, 1, 0 A2, A1, A0 These are address bits for the input mux to select the “on” channel (Table 5).
MAX197
How to Start a Conversion
Conversions are initiated with a write operation, which
selects the mux channel and configures the MAX197 for
either unipolar or bipolar input range. A write pulse (WR
+ CS) can either start an acquisition interval or initiate a
combined acquisition plus conversion. The sampling
interval occurs at the end of the acquisition interval.
The ACQMOD bit in the input control byte offers two
options for acquiring the signal: internal or external.
The conversion period lasts for 12 clock cycles in either
internal or external clock or acquisition mode.
Writing a new control byte during conversion cycle will
abort conversion and start a new acquisition interval.
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this six-clock-cycle acquisition interval (3µs with
fCLK = 2MHz) ends. See Figure 5.
External Acquisition
Use the external acquisition timing mode for precise con-
trol of the sampling aperture and/or independent control
of acquisition and conversion times. The user controls
acquisition and start-of-conversion with two separate
write pulses. The first pulse, written with ACQMOD = 1,
starts an acquisition interval of indeterminate length. The
second write pulse, written with ACQMOD = 0, termi-
nates acquisition and starts conversion on WR’s rising
edge (Figure 6). However, if the second control byte
contains ACQMOD = 1, an indefinite acquisition interval
is restarted.
The address bits for the input mux must have the same
values on the first and second write pulses. Power-
down mode bits (PD0, PD1) can assume new values on
the second write pulse (see Power-Down Mode).
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
10 ______________________________________________________________________________________
tCS
tCSWS tWR
tACQI tCONV
tDH
tDS
tINT1
tD0 tD01 tTR
HGH-ZHGH-Z
tCSRS tCSRH
CS
WR
D7–D0
INT
RD
HBEN
DOUT
ACQMOD ="0"
HIGH / LOW
BYTE VALID HIGH / LOW
BYTE VALID
CONTROL
BYTE
tCSWH
Figure 5. Conversion Timing Using Internal Acquisition Mode
Table 6. Data-Bus Output
PIN HBEN = LOW HBEN = HIGH
D0 B0 (LSB) B8
D1 B1 B9
D2 B2 B10
D3 B3 B11 (MSB)
D4 B4 B11 (BIP = 1) / 0 (BIP = 0)
D5 B5 B11 (BIP = 1) / 0 (BIP = 0)
D6 B6 B11 (BIP = 1) / 0 (BIP = 0)
D7 B7 B11 (BIP = 1) / 0 (BIP = 0)
How to Read a Conversion
A standard interrupt signal, INT, is provided to allow the
device to flag the µP when the conversion has ended
and a valid result is available. INT goes low when con-
version is complete and the output data is ready
(Figures 5 and 6). It returns high on the first read cycle
or if a new control byte is written.
Clock Modes
The MAX197 operates with either an internal or an
external clock. Control bits (D6, D7) select either inter-
nal or external clock mode. Once the desired clock
mode is selected, changing these bits to program
power-down will not affect the clock mode. In each
mode, internal or external acquisition can be used. At
power-up, external clock mode is selected.
Internal Clock Mode
Select internal clock mode to free the µP from the
burden of running the SAR conversion clock. To select
this mode, write the control byte with D7 = 0 and D6 = 1.
A 100pF capacitor between the CLK pin and ground
sets this frequency to 1.56MHz nominal. Figure 7
shows a linear relationship between the internal clock
period and the value of the external capacitor used.
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
______________________________________________________________________________________ 11
tCS
tCSWS tWR
tACQI tCONV
tDH
tDS
tINT1
tD0 tD01 tTR
tCSHW
tCSRS tCSRH
ACQMOD = "1"
CS
WR
D7–D0
INT
RD
HBEN
DOUT
ACQMOD = "0"
HIGH / LOW
BYTE VALID HIGH / LOW
BYTE VALID
CONTROL
BYTE
CONTROL
BYTE
Figure 6. Conversion Timing Using External Acquisition Mode
2000
0
0 50 250 350
500
CLOCK PIN CAPACITANCE (pF)
INTERNAL CLOCK PERIOD (ns)
100 150 200 300
1500
1000
Figure 7. Internal Clock Period vs. Clock Pin Capacitance
MAX197
External Clock Mode
Select external clock mode by writing the control byte
with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR
timing relationships in internal and external acquisition
modes, with an external clock. A 100kHz to 2.0MHz
external clock with 45% to 55% duty cycle is required
for proper operation. Operating at clock frequencies
lower than 100kHz will cause a voltage droop across
the hold capacitor, and subsequently degrade perfor-
mance.
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
12 ______________________________________________________________________________________
WR
CLK
CLK
WR
WR GOES HIGH WHEN CLK IS HIGH
WR GOES HIGH WHEN CLK IS LOW
tCWS
tCWH
ACQUISITION STARTS
ACQUISITION STARTS
CONVERSION STARTS
CONVERSION STARTS
ACQUISITION ENDS
ACQUISITION ENDS
ACQMOD = "0"
ACQMOD = "0"
Figure 8a. External Clock and WR Timing (Internal Acquisition Mode)
WR
CLK
CLK
WR
WR GOES HIGH WHEN CLK IS HIGH
WR GOES HIGH WHEN CLK IS LOW
tDH
tDH tCWH
tCWS
ACQUISITION STARTS
ACQUISITION STARTS
CONVERSION STARTS
CONVERSION STARTS
ACQUISITION ENDS
ACQUISITION ENDS
ACQMOD = "1"
ACQMOD = "1" ACQMOD = "0"
ACQMOD = "0"
Figure 8b. External Clock and WR Timing (External Acquisition Mode)
__________Applications Information
Power-On Reset
At power-up, the internal power-supply circuitry sets INT
high and puts the device in normal operation/external
clock mode. This state is selected to keep the internal
clock from loading the external clock driver when the
part is used in external clock mode.
Internal or External Reference
The MAX197 can operate with either an internal or an
external reference. An external reference can be connect-
ed to either the REF pin or to the REFADJ pin (Figure 9).
To use the REF input directly, disable the internal buffer
by tying REFADJ to VDD. Using the REFADJ input elimi-
nates the need to buffer the reference externally.
When the reference is applied at REFADJ, bypass
REFADJ with a 0.01µF capacitor to AGND.
The REFADJ internal buffer gain is trimmed to 1.6384 to
provide 4.096V at the REF pin from a 2.5V reference.
Internal Reference
The internally trimmed 2.50V reference is gained
through the REFADJ buffer to provide 4.096V at REF.
Bypass the REF pin with a 4.7µF capacitor to AGND
and the REFADJ pin with a 0.01µF capacitor to AGND.
The internal reference voltage is adjustable to ±1.5%
(±65 LSBs) with the reference-adjust circuit of Figure 1.
External Reference
At REF and REFADJ, the input impedance is a mini-
mum of 10kΩfor DC currents. During conversions, an
external reference at REF must be able to deliver
400µA DC load currents, and must have an output
impedance of 10Ωor less. If the reference has higher
input impedance or is noisy, bypass it close to the REF
pin with a 4.7µF capacitor to AGND.
With an external reference voltage of less than 4.096V
at the REF pin or less than 2.5V at the REFADJ pin, the
increase in the ratio of the RMS noise to the LSB value
(FS / 4096) results in performance degradation (loss of
effective bits).
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
______________________________________________________________________________________ 13
REF
10kΩ
2.5V
26
CREF
4.7µF
0.01µF
25REFADJ
AV = 1.638
MAX197
Figure 9a. Internal Reference
REF
10kΩ
2.5V
26
CREF
4.7µF
2.5V
25REFADJ
AV = 1.638
0.01µF
MAX197
Figure 9c. External Reference, Reference at REFADJ
REF
VDD
10kΩ
2.5V
26 4.096V
CREF
4.7µF
25REFADJ
AV = 1.638
MAX197
Figure 9b. External Reference, Reference at REF
MAX197
Power-Down Mode
To save power, you can put the converter into low-
current shutdown mode between conversions. Two
programmable power-down modes are available, in
addition to a hardware shutdown. Select STBYPD or
FULLPD by programming PD0 and PD1 in the input
control byte. When software power-down is asserted, it
becomes effective only after the end of conversion. In all
power-down modes, the interface remains active and
conversion results may be read. Input overvoltage pro-
tection is active in all power-down modes. The device
returns to normal operation on the first WR falling edge
during write operation.
For hardware-controlled (FULLPD) power-down, pull
the SHDN pin low. When hardware shutdown is assert-
ed, it becomes effective immediately and the conver-
sion is aborted.
Choosing Power-Down Modes
The bandgap reference and reference buffer remain
active in STBYPD mode, maintaining the voltage on the
4.7µF capacitor at the REF pin. This is a “DC” state that
does not degrade after power-down of any duration.
Therefore, you can use any sampling rate with this
mode, without regard to start-up delays.
However, in FULLPD mode, only the bandgap refer-
ence is active. Connect a 33µF capacitor between REF
and AGND to maintain the reference voltage between
conversion and to reduce transients when the buffer is
enabled and disabled. Throughput rates down to 1ksps
can be achieved without allotting extra acquisition time
for reference recovery prior to conversion. This allows
conversion to begin immediately after power-down
ends. If the discharge of the REF capacitor during
FULLPD exceeds the desired limits for accuracy (less
than a fraction of an LSB), run a STBYPD power-down
cycle prior to starting conversions. Take into account
that the reference buffer recharges the bypass capaci-
tor at an 80mV/ms slew rate and add 50µs for settling
time. Throughput rates of 10ksps offer typical supply
currents of 470µA, using the recommended 33µF
capacitor value.
Auto-Shutdown
Selecting STBYPD on every conversion automatically
shuts the MAX197 down after each conversion without
requiring any start-up time on the next conversion.
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
14 ______________________________________________________________________________________
OUTPUT CODE
INPUT VOLTAGE (LSB)
0FS
FS - 3/2 LSB
1 LSB =
FULL-SCALE
TRANSITION
123
11... 111
11... 110
11... 101
00... 011
00... 010
00... 001
00... 000
FS
4096
Figure 10. Unipolar Transfer Function
OUTPUT CODE
INPUT VOLTAGE (LSB)
0V +FS - 1 LSB
1 LSB =
-FS
011... 111
011... 110
000... 001
000... 000
111... 111
100... 010
100... 001
100... 000
2FS
4096
Figure 11. Bipolar Transfer Function
Transfer Function
Output data coding for the MAX197 is binary in unipo-
lar mode with 1LSB = (FS / 4096) and two’s-comple-
ment binary in bipolar mode with 1LSB = ((2 x |FS|) /
4096). Code transitions occur halfway between succes-
sive-integer LSB values. Figures 10 and 11 show the
input/output (I/O) transfer functions for unipolar and
bipolar operations, respectively. For full-scale (FS) val-
ues, see Table 1.
Layout, Grounding, and Bypassing
Careful printed circuit board layout is essential for best
system performance. For best performance, use a
ground plane. To reduce crosstalk and noise injection,
keep analog and digital signals separate. Digital
ground lines can run between digital signal lines to
minimize interference. Connect analog grounds and
DGND in a star configuration to AGND. For noise-free
operation, ensure the ground return from AGND to the
supply ground is low impedance and as short as possi-
ble. Connect the logic grounds directly to the supply
ground. Bypass VDD with 0.1µF and 4.7µF capacitors
to AGND to minimize high- and low-frequency fluctua-
tions. If the supply is excessively noisy, connect a 5Ω
resistor between the supply and VDD, as shown in
Figure 12.
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
______________________________________________________________________________________ 15
_Ordering Information (continued)
28 Narrow Ceramic SB**-55°C to +125°CMAX197BMYI
28 Narrow Ceramic SB**-55°C to +125°CMAX197AMYI
28 SSOP-40°C to +85°CMAX197BEAI
28 SSOP-40°C to +85°CMAX197AEAI
28 Wide SO-40°C to +85°CMAX197BEWI
28 Wide SO
28 Narrow Plastic DIP
28 Narrow Plastic DIP-40°C to +85°C
-40°C to +85°C
-40°C to +85°CMAX197AEWI
MAX197BENI
MAX197AENI
PIN-PACKAGETEMP RANGEPART
VDD
GND
DGND
DGNDAGND
+5V
+5V
SUPPLY
R* = 5Ω
DIGITAL
CIRCUITRY
4.7µF
0.1µF
MAX197
**
* OPTIONAL
** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE
Figure 12. Power-Supply Grounding Connection
TRANSISTOR COUNT: 2956
SUBSTRATE CONNECTED TO GND
___________________Chip Topography
CH5
CH6
CH7
INT
REFADJ
0.231"
(5.870mm)
0.144"
(3.659mm)
D2
CH0
CH1D0
D1
AGND
CH4
CH3
CH2
VCC
VDD
REFDGND
CLKWR
CS
RD
HBEN
SHDN
D7
D6
D5
D4
D3
** Contact factory for availability and processing to MIL-STD-883.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
_________________________________________________________Functional Diagram
T/H
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
MUX
4
4
12
8
10kΩ
8
8
8
SUCCESSIVE-
APPROXIMATION
REGISTER
CHARGE REDISTRIBUTION
12-BIT DAC
CLOCK
SIGNAL
CONDITIONING
BLOCK
AND
OVERVOLTAGE
TOLERANT
MUX
CONTROL LOGIC
AND
LATCHES
REF REFADJ
+2.5V
REFERENCE
D0–D7
8-BIT DATA BUS
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
CLK
CS
WR
RD
SHDN
INT
VDD
AGND
DGND
HBEN
MAX197
AV =
1.638
COMP
