NID9N05ACLG - ON Semiconductor L.L.C.

November, 2011 − Rev. 9

1Publication Order Number:

NID9N05CL/D

NID9N05CL, NID9N05ACL

Power MOSFET

9.0 A, 52 V, N−Channel, Logic Level,

Clamped MOSFET w/ESD Protection

in a DPAK Package

Benefits

•High Energy Capability for Inductive Loads

•Low Switching Noise Generation

Features

•Diode Clamp Between Gate and Source

•ESD Protection − HBM 5000 V

•Active Over−Voltage Gate to Drain Clamp

•Scalable to Lower or Higher RDS(on)

•Internal Series Gate Resistance

•Pb−Free Packages are Available

Applications

•Automotive and Industrial Markets:

Solenoid Drivers, Lamp Drivers, Small Motor Drivers

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Rating Symbol Value Unit

Drain−to−Source Voltage Internally Clamped VDSS 52−59 V

Gate−to−Source Voltage − Continuous VGS ±15 V

Drain Current − Continuous @ TA = 25°C

Drain Current − Single Pulse (tp = 10 ms)

IDM

9.0

Total Power Dissipation @ TA = 25°C PD1.74 W

Operating and Storage Temperature Range TJ, Tstg −55 to 175 °C

Single Pulse Drain−to−Source Avalanche

Energy − Starting TJ = 125°C

(VDD = 50 V, ID(pk) = 1.5 A, VGS = 10 V,

RG = 25 W)

EAS 160 mJ

Thermal Resistance, Junction−to−Case

Junction−to−Ambient (Note 1)

Junction−to−Ambient (Note 2)

RqJC

RqJA

5.2

100

°C/W

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from Case for 10 seconds

TL260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. When surface mounted to a FR4 board using 1″ pad size, (Cu area 1.127 in2).

2. When surface mounted to a FR4 board using minimum recommended pad

size, (Cu area 0.412 in2).

Device Package Shipping†

ORDERING INFORMATION

NID9N05CLT4 DPAK

DPAK

CASE 369C

STYLE 2

MPWR

Drain

(Pins 2, 4)

Source

(Pin 3)

Gate

(Pin 1)

MARKING

DIAGRAM

Y = Year

WW = Work Week

xxxxx = 05CL or 05ACL

G = Pb−Free Package

Overvoltage

Protection

ESD Protection

http://onsemi.com

1 = Gate

2 = Drain

3 = Source

4 = Drain

NID9N05CL DPAK

YWW

D9N

xxxxxG

VDSS

(Clamped) RDS(ON) TYP

ID MAX

(Limited)

52 V 90 mW9.0 A

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

NID9N05CLG DPAK

(Pb−Free)

75 Units/Rail

NID9N05CLT4G DPAK

(Pb−Free)

2500/Tape & Reel

NID9N05ACLT4G

NID9N05ACLG

NID9N05CL, NID9N05ACL

http://onsemi.com

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Note 3)

(VGS = 0 V, ID = 1.0 mA, TJ = 25°C)

(VGS = 0 V, ID = 1.0 mA, TJ = −40°C to 125°C)

Temperature Coefficient (Negative)

V(BR)DSS 52

50.8

−

−10

59.5

−

mV/°C

Zero Gate Voltage Drain Current

(VDS = 40 V, VGS = 0 V)

(VDS = 40 V, VGS = 0 V, TJ = 125°C)

IDSS

−

Gate−Body Leakage Current

(VGS = ±8 V, VDS = 0 V)

(VGS = ±14 V, VDS = 0 V)

IGSS

−

±22

±10

−

ON CHARACTERISTICS (Note 3)

Gate Threshold Voltage (Note 3)

(VDS = VGS, ID = 100 mA)

Threshold Temperature Coefficient (Negative)

VGS(th) 1.3

−

1.75

−4.5

2.5

−

mV/°C

Static Drain−to−Source On−Resistance (Note 3)

(VGS = 4.0 V, ID = 1.5 A)

(VGS = 3.5 V, ID = 0.6 A)

(VGS = 3.0 V, ID = 0.2 A)

(VGS = 12 V, ID = 9.0 A)

(VGS = 12 V, ID = 12 A)

RDS(on)

−

153

175

−

181

364

1210

−

Forward Transconductance (Note 3) (VDS = 15 V, ID = 9.0 A) gFS −24 −Mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

(VDS = 40 V, VGS = 0 V, f = 10 kHz)

Ciss −155 250 pF

Output Capacitance Coss −60 100

Transfer Capacitance Crss −25 40

Input Capacitance

(VDS = 25 V, VGS = 0 V, f = 10 kHz)

Ciss −175 −pF

Output Capacitance Coss −70 −

Transfer Capacitance Crss −30 −

3. Pulse Test: Pulse Width ≤300 ms, Duty Cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperatures.

NID9N05CL, NID9N05ACL

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ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic UnitMaxTypMinSymbol

SWITCHING CHARACTERISTICS (Note 4)

Turn−On Delay Time

(VGS = 10 V, VDD = 40 V,

ID = 9.0 A, RG = 9.0 W)

td(on) −130 200 ns

Rise Time tr−500 750

Turn−Off Delay Time td(off) −1300 2000

Fall Time tf−1150 1850

Turn−On Delay Time

(VGS = 10 V, VDD = 15 V,

ID = 1.5 A, RG = 2 kW)

td(on) −200 −ns

Rise Time tr−500 −

Turn−Off Delay Time td(off) −2500 −

Fall Time tf−1800 −

Turn−On Delay Time

(VGS = 10 V, VDD = 15 V,

ID = 1.5 A, RG = 50 W)

td(on) −120 −ns

Rise Time tr−275 −

Turn−Off Delay Time td(off) −1600 −

Fall Time tf−1100 −

Gate Charge

(VGS = 4.5 V, VDS = 40 V,

ID = 9.0 A) (Note 3)

QT−4.5 7.0 nC

Q1−1.2 −

Q2−2.7 −

Gate Charge

(VGS = 4.5 V, VDS = 15 V,

ID = 1.5 A) (Note 3)

QT−3.6 −nC

Q1−1.0 −

Q2−2.0 −

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage (IS = 4.5 A, VGS = 0 V) (Note 3)

(IS = 4.0 A, VGS = 0 V)

(IS = 4.5 A, VGS = 0 V, TJ = 125°C)

VSD −

−

0.86

0.845

0.725

1.2

−

Reverse Recovery Time

(IS = 4.5 A, VGS = 0 V,

dIs/dt = 100 A/ms) (Note 3)

trr −700 −ns

ta−200 −

tb−500 −

Reverse Recovery Stored Charge QRR −6.5 −mC

ESD CHARACTERISTICS

Electro−Static Discharge

Capability

Human Body Model (HBM) ESD 5000 − − V

Machine Model (MM) 500 − −

3. Pulse Test: Pulse Width ≤300 ms, Duty Cycle ≤ 2%.

4. Switching characteristics are independent of operating junction temperatures.

NID9N05CL, NID9N05ACL

http://onsemi.com

0.15

1210

0.1

0.05

0614

0.2

0.35

2.5

1.5

0.5 100

10,000

1,000,000

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

ID, DRAIN CURRENT (AMPS)

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

ID, DRAIN CURRENT (AMPS)

0.3

108

0.1

0612

Figure 3. On−Resistance versus

Gate−to−Source Voltage

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

ID, DRAIN CURRENT (AMPS)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

Figure 5. On−Resistance Variation with

Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 6. Drain−to−Source Leakage Current

versus Voltage

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

RDS(on), DRAIN−TO−SOURCE RESISTANCE

(NORMALIZED)

IDSS, LEAKAGE (nA)

−50 50250−25 75 125100

403020 50

8 V

VDS ≥ 10 V

TJ = 25°C

TJ = −55°C

TJ = 100°C

VGS = 12 V

150 175

VGS = 0 V

ID = 9 A

VGS = 12 V

0.2

0.5

VGS = 10 V

ID = 4.5 A

TJ = 25°C

TJ = 150°C

TJ = 100°C

TJ = 25°C

1000

6.5 V 5 V

4 V

3.8 V

4567 23 5

0.4

0.25

0.3

6 V

TJ = 25°C

4.6 V

4.2 V

3.4 V

3.2 V

2.8 V

978

VGS = 4 V

28418

0.4

100,000

25 35

NID9N05CL, NID9N05ACL

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Crss

020304050

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

Figure 7. Capacitance Variation

200

300

100

VGS = 0 V

TJ = 25°C

Coss

Ciss

400

500

Frequency = 10 kHz

VDS

VGS

0.4

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 8. Gate−To−Source and Drain−To−Source

Voltage versus Total Charge

IS, SOURCE CURRENT (AMPS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

RG, GATE RESISTANCE (OHMS)

1 10 100

10,000

100

t, TIME (ns)

VGS = 0 V

TJ = 25°C

Figure 10. Diode Forward Voltage versus Current

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

312 5

1.2

ID = 9 A

TJ = 25°C

Qgd

Qgs

td(off)

td(on)

1000

VDD = 40 V

ID = 9 A

VGS = 10 V

1.00.80.6

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

NID9N05CL, NID9N05ACL

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SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain−to−source voltage and

drain current that a transistor can handle safely when it is

forward biased. Curves are based upon maximum peak

junction temperature and a case temperature (TC) of 25°C.

Peak repetitive pulsed power limits are determined by using

the thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal Resistance −

General Data and Its Use.”

Switching between the off−state and the on−state may

traverse any load line provided neither rated peak current

(IDM) nor rated voltage (VDSS) is exceeded and the

transition time (tr,tf) do not exceed 10 ms. In addition the total

power averaged over a complete switching cycle must not

exceed (TJ(MAX) − TC)/(RqJC).

A Power MOSFET designated E−FET can be safely used

in switching circuits with unclamped inductive loads. For

reliable operation, the stored energy from circuit inductance

dissipated in the transistor while in avalanche must be less

than the rated limit and adjusted for operating conditions

differing from those specified. Although industry practice is

to rate in terms of energy, avalanche energy capability is not

a constant. The energy rating decreases non−linearly with an

increase of peak current in avalanche and peak junction

temperature.

Although many E−FETs can withstand the stress of

drain−to−source avalanche at currents up to rated pulsed

current (IDM), the energy rating is specified at rated

continuous current (ID), in accordance with industry custom.

The energy rating must be derated for temperature as shown

in the accompanying graph (Figure 12). Maximum energy at

currents below rated continuous ID can safely be assumed to

equal the values indicated.

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

0.1 1 100

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 12. Thermal Response

100

ID, DRAIN CURRENT (AMPS)

RDS(on) LIMIT

THERMAL LIMIT

PACKAGE LIMIT

0.1

VGS = 12 V

SINGLE PULSE

TC = 25°C

1 ms

100 ms

10 ms dc

10 ms

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

(NORMALIZED)

t, TIME (s)

0.1

1.0

0.01

0.2

D = 0.5

0.05

0.01

SINGLE PULSE

RqJC(t) = r(t) RqJC

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t1

TJ(pk) − TC = P(pk) RqJC(t)

P(pk)

DUTY CYCLE, D = t1/t2

1100.10.010.0010.00010.00001

0.1

NID9N05CL, NID9N05ACL

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PACKAGE DIMENSIONS

DPAK (SINGLE GAUGE)

CASE 369C

ISSUE D

STYLE 2:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

0.005 (0.13) C

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

D0.235 0.245 5.97 6.22

E0.250 0.265 6.35 6.73

A0.086 0.094 2.18 2.38

b0.025 0.035 0.63 0.89

c2 0.018 0.024 0.46 0.61

b2 0.030 0.045 0.76 1.14

c0.018 0.024 0.46 0.61

e0.090 BSC 2.29 BSC

b3 0.180 0.215 4.57 5.46

L4 −−− 0.040 −−− 1.01

L0.055 0.070 1.40 1.78

L3 0.035 0.050 0.89 1.27

Z0.155 −−− 3.93 −−−

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-

MENSIONS b3, L3 and Z.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS, OR BURRS. MOLD

FLASH, PROTRUSIONS, OR GATE BURRS SHALL

NOT EXCEED 0.006 INCHES PER SIDE.

5. DIMENSIONS D AND E ARE DETERMINED AT THE

OUTERMOST EXTREMES OF THE PLASTIC BODY.

6. DATUMS A AND B ARE DETERMINED AT DATUM

PLANE H.

12 3

5.80

0.228

2.58

0.102

1.60

0.063

6.20

0.244

3.00

0.118

6.17

0.243

ǒmm

inchesǓ

SCALE 3:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

H0.370 0.410 9.40 10.41

A1 0.000 0.005 0.00 0.13

L1 0.108 REF 2.74 REF

L2 0.020 BSC 0.51 BSC

DETAIL A

SEATING

PLANE

L2 GAUGE

PLANE

DETAIL A

ROTATED 90 CW5

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

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NID9N05CL/D

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