For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
MAX5631/MAX5632/
MAX5633
General Description
The MAX5631/MAX5632/MAX5633 are 16-bit digital-to-
analog converters (DACs) with 32 sample-and-hold
(SHA) outputs for applications where a high number of
programmable voltages are required. These devices
include a clock oscillator and a sequencer that updates
the DAC with codes from an internal SRAM. No external
components are required to set offset and gain.
The MAX5631/MAX5632/MAX5633 feature a -4.5V to
+9.2V output voltage range. Other features include a
200µV/step resolution, with output linearity error, typi-
cally 0.005% of full-scale range (FSR). The 100kHz
refresh-rate updates each SHA every 320µs, resulting
in negligible output droop. Remote ground sensing
allows the outputs to be referenced to the local ground
of a separate device.
These devices are controlled through a 20MHz
SPI/QSPI™/MICROWIRE®-compatible 3-wire serial
interface. Immediate Update Mode allows any chan-
nel’s output to be updated within 20µs. Burst Mode
allows multiple values to be loaded into memory in a
single, high-speed data burst. All channels are updated
within 330µs after data has been loaded.
Each device features an output clamp and output resis-
tors for filtering. The MAX5631 features a 50Ωoutput
impedance and is capable of driving up to 250pF of out-
put capacitance. The MAX5632 features a 500Ωoutput
impedance and is capable of driving up to 10nF of output
capacitance. The MAX5633 features a 1kΩoutput imped-
ance and is capable of driving up to 10nF of output
capacitance.
The MAX5631/MAX5632/MAX5633 are available in 12mm
x 12mm, 64-pin TQFP, and 10mm x 10mm, 68-pin thin
QFN packages.
________________________Applications
MEMS Mirror Servo Control
Industrial Process Control
Automatic Test Equipment
Instrumentation
Features
oIntegrated 16-Bit DAC and 32-Channel SHA with
SRAM and Sequencer
o32 Voltage Outputs
o0.005% Output Linearity
o200µV Output Resolution
oFlexible Output Voltage Range
oRemote Ground Sensing
oFast Sequential Loading: 1.3µs per Register
oBurst and Immediate Mode Addressing
oNo External Components Required for Setting
Gain and Offset
oIntegrated Output Clamp Diodes
oThree Output Impedance Options:
MAX5631 (50Ω), MAX5632 (500Ω), and
MAX5633 (1kΩ)
19-2171; Rev 4; 9/12
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Pin Configurations
Ordering Information
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor, Corp.
PART TEMP RANGE* PIN-PACKAGE
MAX5631UCB+D 0°C to +85°C 64 TQFP
MAX5631UTK+ 0°C to +85°C 68 TQFN-EP**
MAX5632UCB+D 0°C to +85°C 64 TQFP
MAX5632UTK+ 0°C to +85°C 68 TQFN-EP**
MAX5633UCB+D 0°C to +85°C 64 TQFP
MAX5633UTK+ 0°C to +85°C 68 TQFN-EP**
Pin Configurations continued at end of data sheet.
5859606162 5455565763
38
39
40
41
42
43
44
45
46
47
ECLK
OUT0
VREF
TQFP
TOP VIEW
AGND
OUT31
OUT30
OUT29
OUT28
OUT27
OUT26
AGND
OUT25
5253 49
5051
OUT24
OUT23
OUT22
OUT21
CL
CL
OUT2
OUT1
OUT4
OUT3
AGND
OUT5
OUT7
OUT6
OUT9
OUT8
CH
OUT10
VSS
CH
VSS
OUT20
OUT19
OUT18
OUT17
OUT16
AGND
VDD
OUT15
33
34
35
36
37 OUT14
OUT13
OUT12
OUT11
CL
IMMED
VLOGIC
SCLK
DIN
CS
VSS
AGND
VLSHA
DGND
CLKSEL
RST
VLDAC
GS
N.C.
48 VDD
N.C.
64
CH
VDD
2322212019 2726252418 2928 32313017
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
MAX5631
MAX5632
MAX5633
+
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
For other temperature-range options, contact factory.
**
EP = Exposed pad.
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
2Maxim Integrated
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, VAGND = VDGND = VGS = 0V, RL ≥10MΩ, CL= 50pF,
CLKSEL = +5V, fECLK = 400kHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND.......................................................-0.3V to +12.2V
VSS to AGND .........................................................-6.0V to +0.3V
VDD to VSS ...........................................................................+15V
VLDAC, VLOGIC, VLSHA to AGND or DGND ..............-0.3V to +6V
REF to AGND............................................................-0.3V to +6V
GS to AGND................................................................VSS to VDD
CL and CH to AGND...................................................VSS to VDD
Logic Inputs to DGND ..............................................-0.3V to +6V
DGND to AGND........................................................-0.3V to +2V
Maximum Current Into OUT_ ............................................±10mA
Maximum Current Into Logic Inputs .................................±20mA
Continuous Power Dissipation (TA= +70°C)
64-Pin TQFP (derate 13.3mW/°C above +70°C) ............1066mW
68-Pin TQFN-EP (derate 28.6mW/°C above +70°C) ......2285mW
Operating Temperature Range...............................0°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Resolution N 16
Bits
Output Range VOUT_ (Note 1)
VSS
+
0.75
VDD -
2.4 V
Offset Voltage Code = 4F2C hex
±15 ±200
mV
Offset Voltage Tempco
±50 µV/°C
Gain Error (Note 2) ±1 %
Gain Tempco ±5
ppm/°C
Integral Linearity Error INL VOUT_ = -3.25V to +7.6V
0.005 0.015 %FSR
Differential Linearity Error DNL VOUT_ = -3.25V to +7.6V. Monotonicity
guaranteed to 14 bits ±1±4
LSB
Maximum Output Drive Current IOUT Sinking and sourcing ±2mA
MAX5631 35 50 65
MAX5632 350
500 650
DC Output Impedance ROUT
MAX5633 700
1000 1300
Ω
MAX5631
250
pF
MAX5632 10Maximum Capacitive Load
MAX5633 10 nF
DC Crosstalk Internal oscillator enabled (Note 3) -90 dB
Power-Supply Rejection Ratio PSRR Internal oscillator enabled -80 dB
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
3
Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, VAGND = VDGND = VGS = 0V, RL ≥10MΩ, CL= 50pF,
CLKSEL = +5V, fECLK = 400kHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
DYNAMIC CHARACTERISTICS
Sample-and-Hold Settling (Note 4)
0.08
%
SCLK Feedthrough 0.5
fSEQ Feedthrough 0.5
Hold-Step
0.25
1mV
Droop Rate VOUT_ = 0V (Note 5), TA = +25°C 1 40
Output Noise
250
µVRMS
REFERENCE INPUT
Input Resistance 7kΩ
Reference Input Voltage VREF 2.5 V
GROUND-SENSE INPUT
Input Voltage Range VGS
-0.5
0.5 V
Input Bias Current IGS -0.5V ≤ VGS ≤ 0.5V -60 0 µA
GS Gain (Note 6)
0.998
1
1.002
V/V
DIGITAL INTERFACE DC CHARACTERISTICS
Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Input Current ±1µA
TIMING CHARACTERISTICS (FIGURE 2)
Sequencer Clock Frequency fSEQ Internal oscillator 80
100 120
External Clock Frequency fECLK (Note 7)
480
SCLK Frequency fSCLK 20
SCLK Pulse Width High tCH 15 ns
SCLK Pulse Width Low tCL 15 ns
CS Low to SCLK High Setup
Time tCSSO 15 ns
CS High to SCLK High Setup
Time tCSS1 15 ns
SCLK High to CS Low Hold Time
tCSH0 10 ns
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
4Maxim Integrated
Note 1: The nominal zero-scale (code = 0) voltage is -4.0535V. The nominal full-scale (code = FFFF hex) voltage is +9.0535V. The
output voltage is limited by the Output Range specification, restricting the useable range of DAC codes. The nominal zero-
scale voltage may be achieved when VSS < -4.9V, and the nominal full-scale voltage may be achieved when VDD > +11.5V.
Note 2: Gain is calculated from measurements
for voltages VDD = 10V and VSS = -4V at codes C000 hex and 4F2C hex,
for voltages VDD = 11.6V and VSS = -2.9V at codes FFFF hex and 252E hex,
for voltages VDD = 9.25V and VSS = -5.25V at codes D4F6 hex and 0 hex, and
for voltages VDD = 8.55V and VSS = -2.75V at codes C74A hex and 281C hex.
Note 3: Steady-state change in any output with an 8V change in an adjacent output.
Note 4: Settling during the first update for an 8V step. The output will settle to within the linearity specification on subsequent
updates. Tested with an external sequencer clock frequency of 480kHz.
Note 5: External clock mode with the external clock not toggling.
Note 6: The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F2C hex.
Note 7: The sequencer runs at fSEQ = fECLK/4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is
limited by acceptable droop and update time after a Burst Mode Update.
Note 8: VDD rise to CS low = 500µs maximum.
Note 9: Guaranteed by gain-error test.
Note 10: The serial interface is inactive. VIH = VLOGIC, VIL = 0V.
Note 11: The serial interface is active. VIH = VLOGIC, VIL = 0V.
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +10V, VSS = -4V, VLOGIC = VLDAC = VLSHA = +5V, VREF = +2.5V, VAGND = VDGND = VGS = 0V, RL ≥10MΩ, CL= 50pF,
CLKSEL = +5V, fECLK = 400kHz, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK High to CS High Hold Time
tCSH1 0ns
DIN to SCLK High Setup Time tDS 15 ns
DIN to SCLK High Hold Time tDH 0ns
RST to CS Low (Note 8) 500 µs
POWER SUPPLIES
Positive Supply Voltage VDD (Note 9)
8.55
10 11.6 V
Negative Supply Voltage VSS (Note 9)
-5.25
-4
-2.75
V
Supply Difference VDD - VSS (Note 9) 14.5 V
Logic Supply Voltage
VLOGIC,
VLDAC,
VLSHA
4.75
5 5.25 V
Positive Supply Current IDD 32 42
mA
Negative Supply Current ISS 32 40
mA
(Note 10) 1 1.5
Logic Supply Current
ILOGIC
fSCLK = 20MHz (Note 11) 2 3
mA
-0.007
-0.003
-0.005
0.001
-0.001
0.005
0.003
0.007
4018 19520 2727111769 35021 42723 58268
INTEGRAL NONLINEARITY vs. CODE
MAX5631 toc01
INPUT CODE
INTEGRAL NONLINEARITY (%)
-1.4
-0.6
-1.0
0.2
-0.2
1.0
0.6
1.4
DIFFERENTIAL NONLINEARITY vs. CODE
MAX5631 toc02
INPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
4018 19520 2727111769 35021 42723 58268
0
0.002
0.006
0.004
0.008
0.010
-40 10-15 35 60 85
INTEGRAL NONLINEARITY VS.
TEMPERATURE
MAX5631 toc03
TEMPERATURE (°C)
INTEGRAL NONLINEARITY (%)
0.5
0.6
0.8
0.7
0.9
1.0
-40 10-15 35 60 85
DIFFERENTIAL NONLINEARITY VS.
TEMPERATURE
MAX5631 toc04
TEMPERATURE (°C)
DIFFERENTIAL NONLINEARITY (LSB)
-20
-18
-14
-16
-12
-10
-40 10-15 35 60 85
OFFSET VOLTAGE VS.
TEMPERATURE
MAX5631 toc05
TEMPERATURE (°C)
OFFSET VOLTAGE (mV)
VDD = +8.55V
VSS = -4V
CODE = 4F2C hex
DROOP RATE vs. TEMPERATURE
TEMPERATURE (°C)
-40 35 60-15 10 85
DROOP RATE (mV/s)
100
0.0001
0.001
0.010
0.100
10
1
MAX5631 toc06
CODE = 4F2C hex
EXTERNAL CLOCK MODE
NO CLOCK APPLIED
0
0.01
0.03
0.02
0.04
0.05
-40 10-15 35 60 85
GAIN ERROR VS. TEMPERATURE
MAX5631 toc07
TEMPERATURE (°C)
GAIN ERROR (%)
CODE = C168 hex
OFFSET CODE = 4F2C hex
10 100
0
-10
-20
-30
-40
-60
-50
-70
-80
0.01 0.1 1
POSITIVE SUPPLY PSRR VS.
FREQUENCY
MAX5361 toc08
FREQUENCY (kHz)
PSRR (dB)
-90
-90
0
0.001 0.01 0.1 1 10 100
NEGATIVE SUPPLY PSRR VS.
FREQUENCY
-10
-20
MAX5631 toc09
FREQUENCY (kHz)
PSRR (dB)
-40
-30
-70
-80
-60
-50
Typical Operating Characteristics
(VDD = +10V, VSS = -4V, VREF = +2.5V, VGS = 0V, TA = +25°C, unless otherwise noted.)
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
5
Maxim Integrated
Typical Operating Characteristics (continued)
(VDD = +10V, VSS = -4V, VREF = +2.5V, VGS = 0V, TA = +25°C, unless otherwise noted.)
400
500
700
600
800
900
LOGIC SUPPLY CURRENT vs.
LOGIC SUPPLY VOLTAGE
MAX5631 toc10
LOGIC SUPLY VOLTAGE (V)
LOGIC SUPPLY CURRENT (µA)
4.75 5.255.00 5.50
INTERFACE INACTIVE
0
400
200
800
600
1000
1200
LOGIC SUPPLY CURRENT VS.
LOGIC INPUT HIGH VOLTAGE
MAX5631 toc11
LOGIC INPUT HIGH VOLTAGE (V)
LOGIC SUPPLY CURRENT (µA)
2.0 3.0 3.52.5 4.0 4.5 5.0
fSCLK = 20MHz
20
22
24
26
28
30
32
34
36
-40 -15 10 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
MAX5631 toc12
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
ISS
IDD
INTERFACE INACTIVE
POSITIVE SETTLING TIME
(8V STEP)
MAX5631 toc13
VOUT_
ECLK
0
5V/div
3.5V
1µs/div
NEGATIVE SETTLING TIME
(8V STEP)
MAX5631 toc14
VOUT_
ECLK
0
5V/div
3.5V
1µs/div
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
6Maxim Integrated
POSITIVE SETTLING TIME
(100mV STEP)
MAX5631 toc15
VOUT_
ECLK
0
50mV/div
AC COUPLED
3.5V
1µs/div
NEGATIVE SETTLING TIME
(100mV STEP)
MAX5631 toc16
VOUT_
ECLK
0
50mV/div
AC COUPLED
3.5V
1µs/div
OUTPUT NOISE
MAX5631 toc17
250µs/div
OUT_
1mV/div
Pin Description
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
7
Maxim Integrated
PIN
TQFP TQFN
NAME FUNCTION
1, 2 1, 2, 17, 34, 51, 68 N.C. No Connection. Not internally connected.
3 3 GS Ground-Sensing Input
44V
LDAC +5V DAC Power Supply
55RST Reset Input
66CS Chip-Select Input
7 7 DIN Serial Data Input
8 8 SCLK Serial Clock Input
99V
LOGIC +5V Logic Power Supply
10 10 IMMED Immediate Update Mode
11 11 ECLK External Sequencer Clock Input
12 12 CLKSEL Clock-Select Input
13 13 DGND Digital Ground
14 14 VLSHA +5V Sample-and-Hold Power Supply
15, 25, 40, 55, 62 15, 26, 42, 58, 65 AGND Analog Ground
16, 32, 46 16, 33, 48 VSS Negative Power Supply
17, 39, 48 18, 41, 50 VDD Positive Power Supply
18, 33, 49 19, 35, 52 CL Output Clamp Low Voltage
19 20 OUT0 Output 0
20 21 OUT1 Output 1
21 22 OUT2 Output 2
22 23 OUT3 Output 3
23 24 OUT4 Output 4
24 25 OUT5 Output 5
26 27 OUT6 Output 6
27 28 OUT7 Output 7
28 29 OUT8 Output 8
29 30 OUT9 Output 9
30 31 OUT10 Output 10
31, 47, 64 32, 49, 67 CH Output Clamp High Voltage
34 36 OUT11 Output 11
35 37 OUT12 Output 12
36 38 OUT13 Output 13
37 39 OUT14 Output 14
38 40 OUT15 Output 15
41 43 OUT16 Output 16
42 44 OUT17 Output 17
43 45 OUT18 Output 18
44 46 OUT19 Output 19
45 47 OUT20 Output 20
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
8Maxim Integrated
Pin Description (continued)
PIN
TQFP TQFN
NAME FUNCTION
50 53 OUT21 Output 21
51 54 OUT22 Output 22
52 55 OUT23 Output 23
53 56 OUT24 Output 24
54 57 OUT25 Output 25
56 59 OUT26 Output 26
57 60 OUT27 Output 27
58 61 OUT28 Output 28
59 62 OUT29 Output 29
60 63 OUT30 Output 30
61 64 OUT31 Output 31
63 66 REF Reference Voltage Input
——EP
Exposed Pad (TQFN Only). Internally connected
to GND. Connect to a large ground plane to
maximize thermal performance. Not intended as
a electrical connection point.
Figure 1. Functional Diagram
CLOCK
ECLK
CLKSEL
SEQUENCER
SERIAL
INTERFACE
LAST
ADDRESS
SEQUENTIAL
ADDRESS
16-BIT
DAC
GAIN AND
OFFSET
CORRECTION
16 x 32
SRAM
CS
SCLK
DIN
ADDR SELECT
WRITE ENABLE
DATA READY
READ ENABLE
CH
CL
REF
GS
OUT0
OUT31
SAMPLE
D[15:0]
IMMED
RST
2: 1
M
U
X
R
E
G
I
S
T
E
R
R
E
G
I
S
T
E
R
SAMPLE-
AND-HOLD
ARRAY
MAX5631
MAX5632
MAX5633
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
9
Maxim Integrated
Detailed Description
Digital-to-Analog Converter
The MAX5631/MAX5632/MAX5633 16-bit digital-to-ana-
log converters (DAC) are composed of two matched
sections. The four MSBs are derived through 15 identi-
cal matched resistors and the lower 12 bits are derived
through a 12-bit inverted R-2R ladder.
Sample-and-Hold Amplifiers
The MAX5631/MAX5632/MAX5633 contain 32 buffered
sample/hold circuits with internal hold capacitors.
Internal hold capacitors minimize leakage current,
dielectric absorption, feedthrough, and required board
space. MAX5631/MAX5632/MAX5633 provide a very low
1mV/s droop rate.
Output
The MAX5631/MAX5632/MAX5633 include output buffers
on each channel. The device contains output resistors in
series with the buffer output (Figure 3) for ease of output
filtering and capacitive load driving stability.
Output loads increase the analog supply current (IDD
and ISS). Excessively loading the outputs drastically
increases power dissipation. Do not exceed the maxi-
mum power dissipation specified in the
Absolute
Maximum Ratings
.
The maximum output voltage range depends on the
analog supply voltages available and the output clamp
voltages (see
Output Clamp
).
The device has a fixed theoretical output range deter-
mined by the reference voltage, gain, and midscale offset.
The output voltage for a given input code is calculated
with the following:
where code is the decimal value of the DAC input
code, VREF is the reference voltage, and VGS is the
Vcode V
V
OUT REF
GS
=⎛
⎝
⎜⎞
⎠
⎟××
×
()
+
65535 5 2428 .-
1.6214 VREF
VVVVV
SS OUT DD
+
()
≤≤
()
075 24..
_-
Table 1. Code Table
DAC INPUT CODE
MSB LSB
NOMINAL OUTPUT
VOLTAGE (V) VREF = +2.5V
1111 1111 1111 1111 9.0535 Full-scale output
1100 0111 0100 1010 6.15 Maximum output with VDD = 8.55V
1000 0000 0000 0000 2.5 Midscale output
0100 1111 0010 1100 0 VOUT_ = 0. All outputs default to this code after power-up
0010 1000 0001 1100 -2.0 Minimum output with VSS = -2.75V
0000 0000 0000 0000 -4.0535 Zero-scale output
tCSHO tCH
tCSSO tCL
tDH
tDS
tCSH1
tCSS1
CS
SCLK
DIN B23 B22 B0
Figure 2. Serial Interface Timing Diagram
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
10 Maxim Integrated
voltage at the ground-sense input. With a 2.5V refer-
ence, the nominal endpoints are -4.0535V and
+9.0535V (Table 1). Note that these are “virtual” inter-
nal endpoint voltages and cannot be reached with all
combinations of negative and positive power-supply
voltages. The nominal, useable DAC endpoint codes
for the selected power supplies may be calculated as:
lower endpoint code = 32768 - ((2.5V - (VSS + 0.75) /
200µV) (result ≥0)
upper endpoint code = 32768 + ((VDD - 2.4 - 2.5V) /
200µV) (result ≤65535)
The resistive voltage-divider formed by the output resis-
tor (RO) and the load impedance (RL), scales the out-
put voltage. Determine VOUT_ as follows:
Ground Sense
The MAX5631/MAX5632/MAX5633 include a ground-
sense input (GS), which allows the output voltages to
be referenced to a remote ground. The voltage at GS is
added to the output voltage with unity gain. Note that
the resulting output voltage must be within the valid
output voltage range set by the power supplies.
Output Clamp
The MAX5631/MAX5632/MAX5633 clamps the output
between two externally applied voltages. Internal
diodes at each channel restrict the output voltage to:
The clamping diodes allow the MAX5631/MAX5632/
MAX5633 to drive devices with restricted input ranges.
The diodes also allow the outputs to be clamped during
power-up or fault conditions. To disable output clamp-
ing, connect CH to VDD and CL to VSS, setting the
clamping voltages beyond the maximum output voltage
range.
Serial Interface
The MAX5631/MAX5632/MAX5633 are controlled by an
SPI, QSPI, and MICROWIRE-compatible 3-wire inter-
face. Serial data is clocked into the 24-bit shift register
in an MSB-first format, with the 16-bit DAC data pre-
ceding the 5-bit SRAM address, 2-bit control, and a fill
0 (Figure 4). The input word is framed by CS. The first
VVV VV
CH OUT CL
+
()
≥≥
()
−07 07..
_
Scaling Factor R
RR
V V scaling factor
L
LO
OUT CHOLD
=+
=×
_
DATA ADDRESS CONTROL
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D0 A4 A3 A2 A1 A0 C1 C0 0
MSB LSB
Figure 4. Input Word Sequence
Figure 3. Analog Block Diagram
GS
DAC
DATA
CH
OUT_
GAIN
AND
OFFSET CHOLD
VREF
RO
ONE OF 32 SHA CHANNELS
16-BIT
DAC
RL
CL
AV = 1
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
11
Maxim Integrated
rising edge of SCLK after CS goes low will clock in the
MSB of the input word.
When each serial word is complete, the value is stored
in the SRAM at the address indicated and the control
bits are saved. Note that data may be corrupted if CS is
not held low for an integer multiple of 24 bits.
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. Their switching
threshold is compatible with TTL and most CMOS logic
levels.
Serial Input Data Format and
Control Codes
The 24-bit serial input format, shown in Figure 4, compris-
es of 16 data bits (D15–D0), five address bits (A4–A0),
two control bits (C1, C0), and a fill zero. The address
code selects the output channel as shown in Table 2. The
control code configures the device as follows:
1) If C1 = 1, Immediate Update Mode is selected.
If C1 = 0, Burst Mode is selected.
2) If C0 = 0, the internal sequencer clock is selected. If
C0 = 1, the external sequencer clock is selected.
This must be repeated with each data word to main-
tain external input.
A4 A3 A2 A1 A0 OUTPUT
00000OUT0 selected
00001OUT1 selected
00010OUT2 selected
00011OUT3 selected
00100OUT4 selected
00101OUT5 selected
00110OUT6 selected
00111OUT7 selected
01000OUT8 selected
01001OUT9 selected
01010OUT10 selected
01011OUT11 selected
01100OUT12 selected
01101OUT13 selected
01110OUT14 selected
01111OUT15 selected
10000OUT16 selected
10001OUT17 selected
10010OUT18 selected
10011OUT19 selected
10100OUT20 selected
10101OUT21 selected
10110OUT22 selected
10111OUT23 selected
11000OUT24 selected
11001OUT25 selected
11010OUT26 selected
11011OUT27 selected
11100OUT28 selected
11101OUT29 selected
11110OUT30 selected
11111OUT31 selected
Table 2. Channel/Output Selection
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
12 Maxim Integrated
The operating modes can also be selected externally
through CLKSEL and IMMED. In the case where the
control bit in the serial word and the external signal
conflict, the signal that is a logic “1” is dominant.
Modes of Operation
The MAX5631/MAX5632/MAX5633 feature three modes
of operation:
1) Sequence Mode
2) Immediate Update Mode
3) Burst Mode
Sequence Mode
Sequence mode is the default operating mode. The
internal sequencer continuously scrolls through the
SRAM, updating each of the 32 SHAs. At each SRAM
address location, the stored 16-bit DAC code is loaded
to the DAC. Once settled, the DAC output is acquired
by the corresponding SHA. Using the internal
sequencer clock, the process typically takes 320µs to
update all 32 SHAs (10µs per channel). Using an exter-
nal sequencer clock the update process takes 128
clock cycles (four clock cycles per channel).
Immediate Update Mode
Immediate update mode is used to change the con-
tents of a single SRAM location, and update the corre-
sponding SHA output. In Immediate Update Mode, the
selected output is updated before the sequencer
resumes operation. Select Immediate Update Mode by
driving either IMMED or C1 high.
The sequencer is interrupted when CS is taken low. The
input word is then stored in the proper SRAM address.
The DAC conversion and SHA sample in progress are
completed transparent to the serial bus activity. The
SRAM location of the addressed channel is then modi-
fied with the new data. The DAC and SHA are updated
with the new voltage. The sequencer then resumes
scrolling at the interrupted SRAM address.
This operation can take up to two cycles of the 10µs
sequencer clock. Up to one cycle is needed to allow the
sequencer to complete the operation in progress before
it is freed to update the new channel. An additional
cycle is required to read the new data from memory,
update the DAC, and strobe the sample-and-hold. The
sequencer resumes scrolling from the location at which
it was interrupted. Normal sequencing is suppressed
while loading data, thus preventing other channels from
being refreshed. Under conditions of extremely frequent
Immediate Updates (i.e., 1000 successive updates), this
can result in unacceptable droop.
Figure 5 shows an example of an immediate update
operation. In this example, data for channel 20 is
loaded while channel 7 is being refreshed. The
sequencer operation is interrupted, and no other chan-
nels are refreshed as long as CS is held low. Once CS
returns high, and the remainder of an fSEQ period (if
any) has expired, channel 20 is updated to the new
data. Once channel 20 has been updated, the
sequencer resumes normal operation at the interrupted
channel 7.
7123 SKIP 20 7 8 9
24-BIT
WORD
CS
DIN
CHANNEL 20
UPDATED
INTERRUPTED
CHANNEL REFRESHED
1/fSEQ
LOAD ADDRESS 20
SHA ARRAY
UPDATE
SEQUENCE
Figure 5. Immediate Update Mode Timing Example
SKIP6 7 SKIP SKIP 7 8 5 6
CS
DIN
33 CYCLES TO UPDATE
ALL CHANNELS
1/fSEQ
LOAD MULTIPLE
ADDRESSES
SHA ARRAY
UPDATE
SEQUENCE
7
Figure 6. Burst Mode Timing Example
UPDATE MODE UPDATE TIME
Immediate Update Mode 2/fSEQ
Burst Mode 33/fSEQ
Table 3. Update Mode
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
13
Maxim Integrated
Burst Mode
Burst Mode allows multiple SRAM locations to be
loaded at high speed. During Burst Mode, the output
voltages are not updated until the data burst is com-
plete and control returns to the sequencer. Select Burst
Mode by driving both IMMED and C1 low.
The sequencer is interrupted when CS is taken low. All
or part of the memory can be loaded while CS is low.
Each data word is loaded into its specified SRAM
address. The DAC conversion and SHA sample in
progress are completely transparent to the serial bus
activity. When CS is taken high, the sequencer resumes
scrolling at the interrupted SRAM address. New values
are updated when their turn comes up in the sequence.
After Burst Mode is used, it is recommended that at
least one full sequencer loop (320µs) is allowed to
occur before the serial port is accessed again. This
ensures that all outputs are updated before the
sequencer is interrupted.
Figure 6 shows an example of a burst mode operation.
As with the immediate update example, CS falls while
channel 7 is being refreshed. Data for multiple chan-
nels is loaded, and no channels are refreshed as long
as CS remains low. Once CS returns high, sequencing
resumes with channel 7 and continues normal refresh
operation. Thirty-three fSEQ cycles are required before
all channels have been updated.
External Sequencer Clock
An external clock may be used to control the
sequencer, altering the output update rate. The
sequencer runs at 1/4 the frequency of the supplied
clock (ECLK). The external clock option is selected by
driving either C0 or CLKSEL high.
When CLKSEL is asserted, the internal clock oscillator
is disabled. This feature allows synchronizing the
sequencer to other system operations, or shutting down
of the sequencer altogether during high-accuracy sys-
tem measurements. The low 1mV/s droop of these
devices ensures that no appreciable degradation of the
output voltages occurs, even during extended periods
of time when the sequencer is disabled.
Power-On Reset
A power-on reset (POR) circuit sets all channels to 0V
(code 4F2C hex) in sequence, requiring 320µs. This
prevents damage to downstream ICs due to arbitrary
reference levels being presented following system
power-up. This same function is available by driving
RST low. During the reset operation, the sequencer is
run by the internal clock, regardless of the state of
CLKSEL. The reset process cannot be interrupted, seri-
al inputs will be ignored until the entire reset process is
complete.
Applications Information
Power Supplies and Bypassing
Grounding and power-supply decoupling strongly influ-
ence device performance. Digital signals may couple
through the reference input, power supplies, and
ground connection. Proper grounding and layout can
reduce digital feedthrough and crosstalk. At the device
level, a 0.1µF capacitor is required for the VDD, VSS,
and VL_ pins. They should be placed as close to the
pins as possible. More substantial decoupling at the
board level is recommended and is dependent on the
number of devices on the board (Figure 7).
The MAX5631/MAX5632/MAX5633 have three separate
+5V logic power supplies, VLDAC, VLOGIC, and VLSHA.
VLDAC powers the 16-bit digital-to-analog converter,
VLSHA powers the control logic of the SHA array, and
VLOGIC powers the serial interface, sequencer, internal
clock and SRAM. Additional filtering of VLDAC and
VLSHA improves the overall performance of the device.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
64 TQFP C64+8 21-0083 90-0141
68 TQFN-EP T6800+3 21-0142 90-0100
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
14 Maxim Integrated
Figure 7. Typical Operating Circuit
CS
DIN
SCLK
IMMED
CLKSEL
REF
GS
RST
ECLK
VLOGIC VLDAC VLSHA
0.1µF
+5V
0.1µF
+10V
VDD
MAX5631
MAX5632
MAX5633
OUT31
OUT0
OUT1
DGND AGND
0.1µF
VSS CL
+2.5V
-4V
Pin Configurations (continued)
58
59
60
61
62
54
55
56
57
63
38
39
40
41
42
43
44
45
46
47
TQFN-EP
TOP VIEW
52
53
35
36
37
48
49
50
64
65
66
67
23
22
21
20
19
27
26
25
24
18
29
28
32
33
31
30
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
+
MAX5631
MAX5632
MAX5633
ECLK
OUT0 VREF
AGND
OUT31
OUT30
OUT29
OUT28
OUT27
OUT26
AGND
OUT25
OUT24
OUT23
OUT22
OUT21
CL
CL
OUT2
OUT1
OUT4
OUT3
AGND
OUT5
OUT7
OUT6
OUT9
OUT8
CH
OUT10
VSS
34
N.C.
CH
VSS
OUT20
OUT19
OUT18
OUT17
OUT16
AGND
VDD
OUT15
OUT14
OUT13
OUT12
OUT11
CL
IMMED
VLOGIC
SCLK
DIN
CS
VSS
17
N.C.
AGND
VLSHA
DGND
CLKSEL
RST
VLDAC
GS
N.C. VDD
51 N.C.
N.C.
CH
68 N.C.
VDD
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________
15
© 2012 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 10/01 Initial release —
3 1/05 Updated the operating temperature range in the Ordering Information and updated
the Typical Operating Characteristics.1, 2, 6
4 9/12 Removed leaded options and added lead-free notation in Ordering Information.1