1
LTC1419
1419fb
14-Bit, 800ksps Sampling
A/D Converter with Shutdown
■
Sample Rate: 800ksps
■
Power Dissipation: 150mW
■
81.5dB S/(N + D) and 93dB THD
■
No Missing Codes
■
No Pipeline Delay
■
Nap and Sleep Shutdown Modes
■
Operates with 2.5V Internal 15ppm/°C
Reference or External Reference
■
True Differential Inputs Reject Common Mode Noise
■
20MHz Full-Power Bandwidth Sampling
■
Bipolar Input Range: ±2.5V
■
28-Pin SSOP and SO Packages
The LTC
®
1419 is a 1µs, 800ksps, 14-bit sampling
A/D converter that draws only 150mW from ±5V supplies.
This easy-to-use device includes a high dynamic range
sample-and-hold and a precision reference. Two digitally
selectable power shutdown modes provide flexibility for
low power systems.
The LTC1419 has a full-scale input range of ±2.5V. Out-
standing AC performance includes 81.5dB S/(N + D) and
93dB THD with a 100kHz input; 80dB S/(N + D) and 86dB
THD at the Nyquist input frequency of 400kHz.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 20MHz
bandwidth. The 60dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
The ADC has a µP compatible, 14-bit parallel output port.
There is no pipeline delay in the conversion results. A
separate convert start input and data ready signal (BUSY)
ease connections to FIFOs, DSPs and microprocessors.
■
Telecommunications
■
Digital Signal Processing
■
Multiplexed Data Acquisition Systems
■
High Speed Data Acquisition
■
Spectrum Analysis
■
Imaging Systems
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+A
IN
–A
IN
V
REF
REFCOMP
AGND
D13(MSB)
D12
D11
D10
D9
D8
D7
D6
DGND
AV
DD
DV
DD
V
SS
BUSY
CS
CONVST
RD
SHDN
D0
D1
D2
D3
D4
D5
LTC1419
1µF10µF
DIFFERENTIAL
ANALOG INPUT
(–2.5V TO 2.5V)
V
REF
OUTPUT
2.50V
10µF
10µF
5V
–5V
14-BIT
PARALLEL
BUS
µP CONTROL
LINES
1419 TA01
800kHz, 14-Bit Sampling A/D Converter
INPUT FREQUENCY (Hz)
1k
EFFECTIVE BITS
SIGNAL/(NOISE + DISTORTION) (dB)
14
13
12
11
10
9
8
7
6
5
4
3
2
86
80
74
68
62
10k 100k
1419 TA02
1M 2M
fSAMPLE = 800kHz
Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5581252.
2
LTC1419
1419fb
AVDD = VDD = DVDD (Notes 1, 2)
Supply Voltage (V
DD
) ................................................ 6V
Negative Supply Voltage (V
SS
) ............................... –6V
Total Supply Voltage (V
DD
to V
SS
) .......................... 12V
Analog Input Voltage
(Note 3).............................(V
SS
– 0.3V) to (V
DD
+ 0.3V)
Digital Input Voltage (Note 4) ......... (V
SS
– 0.3V) to 10V
Digital Output Voltage ........ (V
SS
– 0.3V) to (V
DD
+ 0.3V)
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1419C .............................................. 0°C to 70°C
LTC1419I........................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER
PART NUMBER
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6)
Consult factory for Military grade parts.
T
JMAX
= 125°C, θ
JA
= 95°C/W (G)
T
JMAX
= 125°C, θ
JA
= 130°C/W (SW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+A
IN
–A
IN
V
REF
REFCOMP
AGND
D13(MSB)
D12
D11
D10
D9
D8
D7
D6
DGND
AV
DD
DV
DD
V
SS
BUSY
CS
CONVST
RD
SHDN
D0
D1
D2
D3
D4
D5
SW PACKAGE
28-LEAD PLASTIC SO
G PACKAGE
28-LEAD PLASTIC SSOP
TOP VIEW
LTC1419ACG
LTC1419ACSW
LTC1419AIG
LTC1419AISW
LTC1419CG
LTC1419CSW
LTC1419IG
LTC1419ISW
LTC1419 LTC1419A
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Resolution (No Missing Codes) ●13 14 Bits
Integral Linearity Error (Note 7) ●±0.8 ±2±0.6 ±1.25 LSB
Differential Linearity Error ●±0.7 ±1.5 ±0.5 ±1 LSB
Offset Error (Note 8) ●±5±20 ±5±20 LSB
Full-Scale Error Internal Reference ±10 ±60 ±10 ±60 LSB
External Reference = 2.5V ±5±5 LSB
Full-Scale Tempco I
OUT(REF)
= 0 ±15 ±15 ppm/°C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Analog Input Range (Note 9) 4.75V ≤ V
DD
≤ 5.25V, –5.25 ≤ V
SS
≤ –4.75V ●±2.5 V
I
IN
Analog Input Leakage Current CS = High ●±1µA
C
IN
Analog Input Capacitance Between Conversions 15 pF
During Conversions 5 pF
t
ACQ
Sample-and-Hold Acquisition Time ●90 300 ns
t
AP
Sample-and-Hold Aperture Delay Time –1.5 ns
t
jitter
Sample-and-Hold Aperture Delay Time Jitter 2 ps
RMS
CMRR Analog Input Common Mode Rejection Ratio –2.5V < (– A
IN
= A
IN
) < 2.5V 60 dB
CO VERTER CHARACTERISTICS
U
The ● denotes specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
A ALOG I PUT
UU
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
3
LTC1419
1419fb
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Positive Supply Voltage (Note 10) 4.75 5.25 V
V
SS
Negative Supply Voltage (Note 10) –4.75 –5.25 V
I
DD
Positive Supply Current ●11 20 mA
Nap Mode SHDN = 0V, CS = 0V 1.5 mA
Sleep Mode SHDN = 0V, CS = 5V 250 µA
I
SS
Negative Supply Current ●19 30 mA
Nap Mode SHDN = 0V, CS = 0V 100 µA
Sleep Mode SHDN = 0V, CS = 5V 1 µA
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
S/(N + D) Signal-to-(Noise + Distortion) Ratio 100kHz Input Signal ●78 81.5 dB
390kHz Input Signal 80.0 dB
THD Total Harmonic Distortion 100kHz Input Signal, First 5 Harmonics ●–93 –86 dB
390kHz Input Signal, First 5 Harmonics – 86 dB
SFDR Spurious Free Dynamic Range 100kHz Input Signal ●–95 –86 dB
IMD Intermodulation Distortion f
IN1
= 29.37kHz, f
IN2
= 32.446kHz – 86 dB
Full-Power Bandwidth 20 MHz
Full-Linear Bandwidth S/(N + D) ≥ 77dB 1 MHz
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
REF
Output Voltage I
OUT
= 0 2.480 2.500 2.520 V
V
REF
Output Tempco I
OUT
= 0 ±15 ppm/°C
V
REF
Line Regulation 4.75V ≤ V
DD
≤ 5.25V, –5.25 ≤ V
SS
≤ –4.75V 0.05 LSB/V
V
REF
Output Resistance –0.1mA ≤ ⏐I
OUT
⏐ ≤ 0.1mA 2 kΩ
REFCOMP Output Voltage I
OUT
= 0 4.06 V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
DD
= 5.25V ●2.4 V
V
IL
Low Level Input Voltage V
DD
= 4.75V ●0.8 V
I
IN
Digital Input Current V
IN
= 0V to V
DD
●±10 µA
C
IN
Digital Input Capacitance 5pF
V
OH
High Level Output Voltage V
DD
= 4.75V
I
O
= –10µA 4.5 V
I
O
= – 200µA●4.0 V
V
OL
Low Level Output Voltage V
DD
= 4.75V
I
O
= 160µA 0.05 V
I
O
= 1.6mA ●0.10 0.4 V
I
OZ
Hi-Z Output Leakage D13 to D0 V
OUT
= 0V to V
DD
, CS High ●±10 µA
C
OZ
Hi-Z Output Capacitance D13 to D0 CS High (Note 9 ) ●15 pF
I
SOURCE
Output Source Current V
OUT
= 0V – 10 mA
I
SINK
Output Sink Current V
OUT
= V
DD
10 mA
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
DY A IC ACCURACY
U
W
(Note 5)
I TER AL REFERE CE CHARACTERISTICS
UU U
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
POWER REQUIRE E TS
WU
4
LTC1419
1419fb
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended +A
IN
input with – A
IN
grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 650ns after the start of the conversion or after BUSY rises.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
P
DIS
Power Dissipation ●150 240 mW
Nap Mode SHDN = 0V, CS = 0V 7.5 12 mW
Sleep Mode SHDN = 0V, CS = 5V 1.2 mW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency ●800 kHz
t
CONV
Conversion Time ●950 1150 ns
t
ACQ
Acquisition Time ●90 300 ns
t
ACQ + CONV
Acquisition + Conversion Time ●1040 1250 ns
t
1
CS to RD Setup Time (Notes 9, 10) ●0ns
t
2
CS↓ to CONVST↓ Setup Time (Notes 9, 10) ●40 ns
t
3
CS↓ to SHDN↓ Setup Time (Notes 9, 10) 40 ns
t
4
SHDN↑ to CONVST↓ Wake-Up Time (Note 10) 400 ns
t
5
CONVST Low Time (Notes 10, 11) ●40 ns
t
6
CONVST to BUSY Delay C
L
= 25pF 20 ns
●50 ns
t
7
Data Ready Before BUSY↑20 50 ns
●15 ns
t
8
Delay Between Conversions (Note 10) ●40 ns
t
9
Wait Time RD↓ After BUSY↑(Note 9) ●–5 ns
t
10
Data Access Time After RD↓C
L
= 25pF 15 25 ns
●35 ns
C
L
= 100pF 20 35 ns
●50 ns
t
11
Bus Relinquish Time 10 20 ns
0°C ≤ T
A
≤ 70°C●25 ns
–40°C ≤ T
A
≤ 85°C●30 ns
t
12
RD Low Time ●t
10
ns
t
13
CONVST High Time ●40 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
DD
without latchup.
Note 4: When these pin voltages are taken below V
SS
, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
SS
without latchup. These pins are not clamped
to V
DD
.
Note 5: V
DD
= 5V, V
SS
= – 5V, f
SAMPLE
= 800kHz, t
r
= t
f
= 5ns unless
otherwise specified.
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
POWER REQUIRE E TS
WU
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
TI I G CHARACTERISTICS
UW
5
LTC1419
1419fb
TYPICAL PERFORMANCE CHARACTERISTICS
UW
S/(N + D) vs Input Frequency
and Amplitude Distortion vs Input Frequency
Spurious-Free Dynamic Range
vs Input Frequency
Differential Nonlinearity
vs Output Code
Integral Nonlinearity
vs Output Code
Input Common Mode Rejection
vs Input Frequency
INPUT FREQUENCY (Hz)
SIGNAL/(NOISE + DISTORTION) (dB)
90
80
70
60
50
40
30
20
10
0
1k 100k 1M 2M
1419 G01
10k
VIN = 0dB
VIN = –20dB
VIN = –60dB
INPUT FREQUENCY (Hz)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
1419 G03
THD
2ND
3RD
1k 100k 1M 2M10k
Signal-to-Noise Ratio
vs Input Frequency
INPUT FREQUENCY (Hz)
SIGNAL-TO -NOISE RATIO (dB)
1k
0
90
80
70
60
50
40
30
20
10
1419 G02
100k 1M 2M10k
Intermodulation Distortion Plot
INPUT FREQUENCY (Hz)
10k
SPURIOUS-FREE DYNAMIC RANGE (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
100k 1M 2M
1419 G04
FREQUENCY (kHz)
0
–120
AMPLITUDE (dB)
–100
–80
–60
–40
100 200 300 400
1419 G05
–20
0
50 150 250 350
f
SAMPLE
= 800kHz
f
IN1
= 95.8984375kHz
f
IN2
= 104.1015625kHz
OUTPUT CODE
0
–1.0
DNL ERROR (LSBs)
–0.5
0
0.5
1.0
4096 8192
1419 G06
12288 16384
Power Supply Feedthrough
vs Ripple Frequency
OUTPUT CODE
0
–1.0
INL ERROR (LSBs)
–0.5
0
0.5
1.0
4096 8192
1419 G07
12288 16384
RIPPLE FREQUENCY (Hz)
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1k 100k 1M 2M
1419 G08
10k
VSS
DGND
VDD
INPUT FREQUENCY (Hz)
1
COMMON MODE REJECTION (dB)
80
70
60
50
40
30
20
10
0
10 100
1419 G09
1000 10000
6
LTC1419
1419fb
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): Chip Select. The input must be low for the
ADC to recognize CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and
SHDN low select the quick wake-up nap mode. CS high
and SHDN low select sleep mode.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
valid on the rising edge of BUSY.
VSS (Pin 26): –5V Negative Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
DVDD (Pin 27): 5V Positive Supply. Short to Pin 28.
AVDD (Pin 28): 5V Positive Supply. Bypass to AGND
with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
+A
IN (Pin 1): ±2.5V Positive Analog Input.
–A
IN (Pin 2): ±2.5V Negative Analog Input.
VREF (Pin 3): 2.5V Reference Output. Bypass to AGND
with 1µF.
REFCOMP (Pin 4): 4.06V Reference Output. Bypass to
AGND with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs. The
output format is 2’s complement.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 to D0 (Pins 15 to 20): Three-State Data Outputs. The
output format is 2’s complement.
SHDN (Pin 21): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for
nap mode and CS = 1 for sleep mode.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
14-BIT CAPACITIVE DAC COMPREF AMP
2.5V REF
REFCOMP
(4.096V)
C
SAMPLE
C
SAMPLE
•
•
•
D13
D0
BUSY
CONTROL LOGIC
CSCONVST RDSHDN
INTERNAL
CLOCK
ZEROING SWITCHES
DV
DD
V
SS
AV
DD
+A
IN
–A
IN
V
REF
AGND
DGND
14
1419 BD
+
–
SUCCESSIVE APPROXIMATION
REGISTER OUTPUT LATCHES
2k
FU CTIO AL BLOCK DIAGRA
UU W
UU
U
PI FU CTIO S
7
LTC1419
1419fb
Load Circuits for Access Timing Load Circuits for Output Float Delay
TEST CIRCUITS
1k CLCL
DBN
(A) Hi-Z TO VOH (B) Hi-Z TO VO
DBN
1k
5V
1419 TC01
1k 100pF 100pF
DBN
(A) V
OH
TO Hi-Z (B) V
OL
TO Hi-Z
DBN
1k
5V
1419 TC02
APPLICATIONS INFORMATION
WUUU
CONVERSION DETAILS
The LTC1419 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs (please refer to Digital Interface section for
the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion, the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun, it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
Referring to Figure 1, the +A
IN
and –A
IN
inputs are con-
nected to the sample-and-hold capacitors (C
SAMPLE
) dur-
ing the acquire phase and the comparator offset is nulled by
the zeroing switches. In this acquire phase, a minimum
delay of 200ns will provide enough time for the sample-
and-hold capacitors to acquire the analog signal. During
the convert phase, the comparator zeroing switches open,
putting the comparator into compare mode. The input
switches the C
SAMPLE
capacitors to ground, transferring
the differential analog input charge onto the summing
junction. This input charge is successively compared with
the binary weighted charges supplied by the differential
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the differential
DAC output balances the +A
IN
and –A
IN
input charges.
The SAR contents (a 14-bit data word) which represents
the difference of +A
IN
and –A
IN
are loaded into the 14-bit
output latches.
DYNAMIC PERFORMANCE
The LTC1419 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
Figure 1. Simplified Block Diagram
COMP
+C
SAMPLE
–C
DAC
•
•
•
D13
D0
ZEROING SWITCHES
HOLD
HOLD
+A
IN
–A
IN
+C
DAC
–C
SAMPLE
14
1419 F01
+
–
SAR OUTPUT
LATCHES
+V
DAC
–V
DAC
HOLD
HOLD
SAMPLE
SAMPLE
8
LTC1419
1419fb
APPLICATIONS INFORMATION
WUUU
frequencies outside the fundamental. Figure 2 shows a
typical LTC1419 FFT plot.
Effective Number of Bits
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 800kHz, the LTC1419 maintains near ideal ENOBs
up to the Nyquist input frequency of 400kHz (refer to
Figure 3).
FREQUENCY (kHz)
0
AMPLITUDE (dB)
–60
–40
–20
300
1419 F02a
–80
–100
100 200 400
250
50 150 350
–120
–140
0
f
SAMPLE
= 800kHz
f
IN
= 99.804687kHz
SFDR = 98dB
THD = –93.3dB
Figure 2a. LTC1419 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
FREQUENCY (kHz)
0
AMPLITUDE (dB)
–60
–40
–20
300
1419 F02b
–80
–100
100 200 400
250
50 150 350
–120
–140
0
f
SAMPLE
= 800kHz
f
IN
= 375kHz
SFDR = 88.3dB
SINAD = 80.1
Figure 2b. LTC1419 Nonaveraged, 4096 Point FFT,
Input Frequency = 375kHz
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical spectral content with
a 800kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 400kHz.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD Log VVV Vn
V
=+++…
20 234
1
222 2
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs Input Frequency is
shown in Figure 4. The LTC1419 has good distortion
performance up to the Nyquist frequency and beyond.
INPUT FREQUENCY (Hz)
1k
EFFECTIVE BITS
SIGNAL/(NOISE + DISTORTION) (dB)
14
13
12
11
10
9
8
7
6
5
4
3
2
86
80
74
68
62
10k 100k
1419 TA02
1M 2M
fSAMPLE = 800kHz
Figure 3. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
9
LTC1419
1419fb
APPLICATIONS INFORMATION
WUUU
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include
(fa + fb). If the two input sine waves are equal in magni-
tude, the value (in decibels) of the 2nd order IMD products
can be expressed by the following formula:
IMD fa fb Log+
()
=20 Amplitude at (fa + fb)
Amplitude at fa
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 77dB (12.5 effective bits).
The LTC1419 has been designed to optimize input band-
width, allowing the ADC to undersample input signals with
frequencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
Driving the Analog Input
The differential analog inputs of the LTC1419 are easy to
drive. The inputs may be driven differentially or as a single-
ended input (i.e., the –A
IN
input is grounded). The +A
IN
and – A
IN
inputs are sampled at the same instant. Any
unwanted signal that is common mode to both inputs will
be reduced by the common mode rejection of the sample-
and-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1419
inputs can be driven directly. As source impedance in-
creases so will acquisition time (see Figure 6). For mini-
mum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
Figure 5. Intermodulation Distortion Plot
FREQUENCY (kHz)
0
–120
AMPLITUDE (dB)
–100
–80
–60
–40
100 200 300 400
1419 G05
–20
0
50 150 250 350
fSAMPLE = 800kHz
fIN1 = 95.8984375kHz
fIN2 = 104.1015625kHz
INPUT FREQUENCY (Hz)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
1419 G03
THD
2ND
3RD
1k 100k 1M 2M10k
10
LTC1419
1419fb
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
starts (settling time must be 200ns for full throughput
rate).
APPLICATIONS INFORMATION
WUUU
LT
®
1220: 30MHz unity-gain bandwidth voltage feedback
amplifier. ±5V to ±15V supplies. Excellent DC specifica-
tions.
LT1223: 100MHz video current feedback amplifier. ±5V
to ±15V supplies, 6mA supply current. Low distortion at
frequencies above 400kHz. Low noise. Good for AC
applications.
LT1227: 140MHz video current feedback amplifier. ±5V
to ±15V supplies, 10mA supply current. Lowest distor-
tion at frequencies above 400kHz. Low noise. Best for AC
applications.
LT1229/LT1230: Dual/quad 100MHz current feedback
amplifiers. ±2V to ±15V supplies, 6mA supply current
each amplifier. Low noise. Good AC specs.
LT1360: 50MHz voltage feedback amplifier. ±5V to ±15V
supplies, 3.8mA supply current. Good AC and DC specs.
LT1363: 70MHz, 1000V/µs op amps, 6.3mA supply cur-
rent. Good AC and DC specs.
LT1364/LT1365: Dual and quad 70MHz, 1000V/µs op
amps. 6.3mA supply current per amplifier.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1419 noise and distortion. The small-signal band-
width of the sample-and-hold circuit is 20MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
SOURCE RESISTANCE (kΩ)
0.01
ACQUISITION TIME (µs)
1
1419 F06
0.1
0.01 0.1 110
100
10
Figure 6. tACQ vs Source Resistance
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
low output impedance (<100Ω) at the closed-loop band-
width frequency. For example, if an amplifier is used in a
gain of +1 and has a unity-gain bandwidth of 50MHz, then
the output impedance at 50MHz should be less than
100Ω. The second requirement is that the closed-loop
bandwidth must be greater than 20MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.
The best choice for an op amp to drive the LTC1419 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifi-
cations are most critical and time domain applications
where DC accuracy and settling time are most critical.
The following
list is a summary of the op amps that are
suitable for driving the LTC1419. More detailed informa-
tion is available in the Linear Technology databooks, the
LinearView
TM
CD-ROM and on our web site at www.linear-
tech. com. Figure 7. RC Input Filter
LTC1419
+A
IN
–A
IN
V
REF
REFCOMP
AGND
1419 F07
1
2
3
4
5
10µF
1000pF
50Ω
ANALOG INPUT
LinearView is a trademark of Linear Technology Corporation.
11
LTC1419
1419fb
many applications. For example, Figure 7 shows a 1000pF
capacitor from +A
IN
to ground and a 100Ω source resistor
to limit the input bandwidth to 1.6MHz. The 1000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sam-
pling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors can
also generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
Input Range
The ±2.5V input range of the LTC1419 is optimized for low
noise and low distortion. Most op amps also perform well
over this same range, allowing direct coupling to the
analog inputs and eliminating the need for special transla-
tion circuitry.
Some applications may require other input ranges. The
LTC1419 differential inputs and reference circuitry can
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
Internal Reference
The LTC1419 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmed to 2.500V. It is connected internally to a reference
amplifier and is available at V
REF
(Pin 3) see Figure 8a. A
APPLICATIONS INFORMATION
WUUU
1
2
3
0.1µF10µF
ANALOG
INPUT
1419 F08b
LT1019A-2.5
V
OUT
V
IN
5V +A
IN
–A
IN
V
REF
LTC1419
AGND
REFCOMP
5
4
+
Figure 8b. Using the LT1019-2.5 as an External Reference
2k resistor is in series with the output so that it can be
easily overdriven by an external reference or other
circuitry, see Figure 8b. The reference amplifier gains the
voltage at the V
REF
pin by 1.625 to create the required
internal reference voltage. This provides buffering be-
tween the V
REF
pin and the high speed capacitive DAC. The
reference amplifier compensation pin (REFCOMP, Pin 4)
must be bypassed with a capacitor to ground. The refer-
ence amplifier is stable with capacitors of 1µF or greater.
For the best noise performance, a 10µF ceramic or 10µF
tantalum in parallel with a 0.1µF ceramic is recommended.
The V
REF
pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1419 reference amplifier will limit the
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed for after a reference adjustment.
Figure 8a. LTC1419 Reference Circuit Figure 9. Driving VREF with a DAC
LTC1419
+A
IN
ANALOG INPUT
1.25V TO 3V
DIFFERENTIAL –A
IN
V
REF
REFCOMP
AGND
1419 F09
1
2
3
4
5
10µF
LTC1450 1.25V TO 3V
R2
40k
R3
64k
REFERENCE
AMP
10µF
REFCOMP
AGND
V
REF
R1
2k BANDGAP
REFERENCE
3
4
5
2.500V
4.0625V
LTC1419
1419 F08a
12
LTC1419
1419fb
APPLICATIONS INFORMATION
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Differential Inputs
The LTC1419 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of +A
IN
– (–A
IN
) independent of the
common mode voltage (see Figure 11a). The common
mode rejection holds up to extremely high frequencies,
see Figure 10a. The only requirement is that both inputs
can not exceed the AV
DD
or AV
SS
power supply voltages.
Integral nonlinearity errors (INL) and differential nonlin-
earity errors (DNL) are independent of the common mode
voltage, however, the bipolar zero error (BZE) will vary.
The change in BZE is typically less than 0.1% of the
common mode voltage. Dynamic performance is also
affected by the common mode voltage. THD will degrade
as the inputs approach either power supply rail, from 86dB
with a common mode of 0V to 76dB with a common mode
of 2.5V or –2.5V.
Figure 10b. Selectable 0V to 5V or ±2.5V Input Range
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 10b shows a circuit that
converts a 0V to 5V analog input signal with only an
additional buffer that is not in the signal path.
Full-Scale and Offset Adjustment
Figure 11a shows the ideal input/output characteristics
for the LTC1419. The code transitions occur midway
between successive integer LSB values (i.e., –FS +
0.5LSB, –FS + 1.5LSB, – FS + 2.5LSB,... FS – 1.5LSB,
FS –
0.5LSB). The output is two’s complement binary with
1LSB = FS – (–FS)/16384 = 5V/16384 = 305.2µV.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
ANALOG
INPUT
1419 F11b
1
2
3
R4
100Ω
R7
50k
R3
24k
5V
R6
24k
R8
50k
R5
47k
4
5
0.1µF
10µF
+A
IN
–A
IN
V
REF
REFCOMP
AGND
LTC1419
+
Figure 11b. Offset and Full-Scale Adjust Circuit
Figure 10a. CMRR vs Input Frequency Figure 11a. LTC1419 Transfer Characteristics
1419 F11a
011...111
011...110
000...001
000...000
111...111
111...110
100...001
100...000
FS – 1LSB
–(FS – 1LSB)
INPUT VOLTAGE [+A
IN
– (–A
IN
)]
OUTPUT CODE
INPUT FREQUENCY (Hz)
1
COMMON MODE REJECTION (dB)
80
70
60
50
40
30
20
10
0
10 100
1419 G09
1000 10000
LTC1419
+AIN
ANALOG INPUT
–AIN
VREF
0V TO
5V
REFCOMP
AGND
1419 F10
1
2
3
±2.5V
4
5
10µF
–
+
13
LTC1419
1419fb
APPLICATIONS INFORMATION
WUUU
applied to the –A
IN
input. For zero offset error, apply
–152µV (i.e., – 0.5LSB) at +A
IN
and adjust the offset at the
–A
IN
input until the output code flickers between 0000
0000 0000 00 and 1111 1111 1111 11. For full-scale
adjustment, an input voltage of 2.499544V (FS/2 – 1.5LSBs)
is applied to +A
IN
and R2 is adjusted until
the output code flickers between 0111 1111 1111 10 and
0111 1111 1111 11.
BOARD LAYOUT AND GROUNDING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1419, a printed circuit board
with ground plane is required. Layout should ensure that
digital and analog signal lines are separated as much as
possible. Particular care should be taken not to run any
digital track alongside an analog signal track or under-
neath the ADC.The analog input should be screened by
AGND.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all
other analog grounds should be connected to this single
analog ground point. The REFCOMP bypass capacitor and
the DV
DD
bypass capacitor should also be connected to
this analog ground plane. No other digital grounds should
be connected to this analog ground plane. Low impedance
analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil
width for these tracks should be as wide as possible. In
applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation com-
parator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate the ADC data bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC1419 has differential inputs to minimize noise
coupling. Common mode noise on the +A
IN
and –A
IN
leads will be rejected by the input CMRR. The –A
IN
input
can be used as a ground sense for the +A
IN
input; the
LTC1419 will hold and convert the difference voltage
between +A
IN
and – A
IN
. The leads to + A
IN
(Pin 1) and – A
IN
(Pin 2) should be kept as short as possible. In applications
where this is not possible, the + A
IN
and – A
IN
traces should
be run side by side to equalize coupling.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the V
DD
and REFCOMP pins
as shown in the Typical Application on the fist page of this
data sheet. Surface mount ceramic capacitors such as
Murata GRM235Y5V106Z016 provide excellent bypass-
ing in a small board space. Alternatively, 10µF tantalum
capacitors in parallel with 0.1µF ceramic capacitors can be
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
Example Layout
Figures 13a, 13b, 13c and 13d show the schematic and
layout of a suggested evaluation board. The layout demon-
strates the proper use of decoupling capacitors and ground
plane with a 2-layer printed circuit board.
Figure 12. Power Supply Grounding Practice
1419 F12
+A
IN
AGNDREFCOMP V
SS
AV
DD
LTC1419 DIGITAL
SYSTEM
ANALOG
INPUT
CIRCUITRY
54
226 28
DV
DD
27
DGND
14
1
10µF
–A
IN
10µF10µF
ANALOG GROUND PLANE
+
–
14
LTC1419
1419fb
APPLICATIONS INFORMATION
WUUU
+
–
+V
IN
GND
A
+
A
–
AGND DGND
V
CC
V
CC
V
CC
V
SS
JP4
V
LOGIC
R14
20Ω
U4
LTC1419
B[00:13]
U5
74HC574
U6
74HC574
56
14
HC14
U7F HC14
U7C 98
HC14
U7D
J6-13
J6-14
J6-11
J6-12
J6-9
J6-10
J6-7
J6-8
J6-5
J6-6
J6-3
J6-4
J6-1
J6-2
J6-15
J6-16
J6-17
J6-18
D13
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D13
RDY
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D13
RDY
DGND
DGND
LED
JP1
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D[00:13]
R0 1.2k
R1
R2
R3
R4
R5
R6
R8
R7
R9
R10
R11
R12
R13
HEADER
18-PIN
11 10
HC14
U7E
R21
1k
12
7
13
V
LOGIC
V
CC
GND
U7G
HC14
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D12
D11
D10
D09
D08
D07
D06
D00
D01
D02
D03
D04
D05
D13
19
18
17
16
15
14
13
12
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
0E
0E
DATA READY
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTOR VALUES IN OHMS, 1/10W, 5%
2. ALL CAPACITOR VALUES IN µF, 25V, 20% AND IN pF, 50V, 10%
V
CC
V
SS
CLK
J7
V
IN
U2 LT1121-5
D15
SS12
R17
10k
R18
10k
R19
51Ω
R16
51Ω
R15
51Ω
R20
1M
U7A
V
LOGIC
JP5C
JP5B
JP5A
CS
RD
SHDN
U7B
HC14 HC14
C6
1000pF
C11
1000pF
C7
1000pF
C8
1µF
16V
C13
10µF
16V
C9
10µF
16V
C15
0.1µF
C16
15pF
C5
10µF
16V
C2
22µF
10V
C10
10µF
10V
C1
22µF
10V
C12
0.1µF
C14
0.1µF
GND TABGND
1
24
3
C4
0.1µF
C3
0.1µF
U3
LT1363
V–
V+
2
3
123 4
6
7
8
1
4
J3
7V TO
15V
J4 JP2
J5
JP3 V
OUT
V
OUT
J2
1
2
3
4
25
24
23
22
21
28
27
26
5
14
6
7
8
9
10
11
12
13
15
16
17
18
19
20
B13
B12
B11
B10
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
B00
B01
B02
B03
B04
B05
B13
B12
B11
B10
B09
B08
B07
B06
1
11
2
3
4
5
6
7
8
9
1
11
2
3
4
5
6
7
8
9
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
+A
IN
–A
IN
V
REF
REFCOMP
BUSY
CS
CONVST
RD
SHDN
AV
DD
DV
DD
V
SS
AGND
DGND
+
+
V
SS
J1
–7V TO
–15V
D14
SS12
–V
IN
IN OUT
21
5
GND
U1
79L05
+
DC124 SCHEM
Figure 13a. Suggested Evaluation Circuit Schematic
15
LTC1419
1419fb
APPLICATIONS INFORMATION
WUUU
Figure 13b. Suggested Evaluation Circuit Board—Component Side Silkscreen
Figure 13c. Suggested Evaluation Circuit Board—Component Side Layout
16
LTC1419
1419fb
APPLICATIONS INFORMATION
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DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a
conversion.
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 0.95µs and a maximum conversion time over the
full operating temperature range of 1.15µs. No external
adjustments are required. The guaranteed maximum
acquisition time is 300ns. In addition, a throughput time of
1.25µs and a minimum sampling rate of 800ksps are
guaranteed.
Power Shutdown
The LTC1419 provides two power shutdown modes, nap
and sleep, to save power during inactive periods. The nap
t3
CS
SHDN
1419 F14a
Figure 14a. CS to SHDN Timing
mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up time
from nap to active is 400ns. In sleep mode, the reference
is shut down and only a small current remains, about
250µA. Wake-up time from sleep mode is much slower
since the reference circuit must power up and settle to
0.005% for full 14-bit accuracy. Sleep mode wake-up
time is dependent on the value of the capacitor connected
to the REFCOMP (Pin 4). The wake-up time is 10ms with
the recommended 10µF capacitor.
Shutdown is con-
trolled by Pin 21 (SHDN); the ADC is in shutdown when it
is low. The shutdown mode is selected with Pin 20 (CS);
low selects nap.
Figure 13d. Suggested Evaluation Circuit Board—Solder Side Layout
17
LTC1419
1419fb
APPLICATIONS INFORMATION
WUUU
In slow memory and ROM modes (Figures 19 and 20), CS
is tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
In slow memory mode, the processor applies a logic low
to RD (= CONVST), starting the conversion. BUSY goes
low, forcing the processor into a WAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results ap-
pear on the data outputs; BUSY goes high, releasing the
processor and the processor takes RD (= CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD (= CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
t3
SHDN
CONVST
1419 F14b
Figure 14b. SHDN to CONVST Wake-Up Timing
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY
is low during a conversion.
Figures 16 through 20 show several different modes of
operation. In modes 1a and 1b (Figures 16 and 17), CS
and RD are both tied low. The falling edge of CONVST
starts the conversion. The data outputs are always enabled
and data can be latched with the BUSY rising edge. Mode
1a shows operation with a narrow logic low CONVST
pulse. Mode 1b shows a narrow logic high CONVST pulse.
In mode 2 (Figure 18), CS is tied low. The falling edge of
the CONVST signal again starts the conversion. Data
outputs are in three-state until read by the MPU with the
RD signal. Mode 2 can be used for operation with a shared
MPU databus.
t
1
CS
RD
1419 F15
Figure 15. CS to CONVST Set-Up Timing
Figure 16. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA (N – 1)
DB13 TO DB0
CONVST
CS = RD = 0
BUSY
1419 F16
t
5
t
CONV
t
6
t
8
t
7
DATA
(SAMPLE N)
(CONVST = )
18
LTC1419
1419fb
APPLICATIONS INFORMATION
WUUU
DATA (N – 1)
DB13 TO DB0
CONVST
BUSY
1419 F17
tCONV
t6
t13
t7
CS = RD = 0
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA
t5
t6
t6
t8
Figure 17. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST = )
RD = CONVST
CS = 0
BUSY
1419 F19
tCONV
(SAMPLE N)
t6
DATA (N – 1)
DB13 TO DB0
DATA DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA N
DB13 TO DB0
t11
t8
t10 t7
Figure 19. Slow Memory Mode Timing
CONVST
CS = 0
BUSY
1419 F18
t5
tCONV
(SAMPLE N)
t8
t13
t6
t9
t12
DATA N
DB13 TO DB0
t11
t10
RD
DATA
Figure 18. Mode 2. CONVST Starts a Conversion. Data is Read by RD
19
LTC1419
1419fb
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
RD = CONVST
BUSY
CS = 0
1419 F20
tCONV
(SAMPLE N)
t6
DATA (N – 1)
DB13 TO DB0
DATA DATA N
DB13 TO DB0
t10
t11
t8
Figure 20. ROM Mode Timing
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
G28 SSOP 1098
0.13 – 0.22
(0.005 – 0.009)
0° – 8°
0.55 – 0.95
(0.022 – 0.037)
5.20 – 5.38**
(0.205 – 0.212)
7.65 – 7.90
(0.301 – 0.311)
12345678 9 10 11 12 1413
10.07 – 10.33*
(0.397 – 0.407)
2526 22 21 20 19 18 17 16 1523242728
1.73 – 1.99
(0.068 – 0.078)
0.05 – 0.21
(0.002 – 0.008)
0.65
(0.0256)
BSC 0.25 – 0.38
(0.010 – 0.015)
NOTE: DIMENSIONS ARE IN MILLIMETERS
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
*
**
20
LTC1419
1419fb
© LINEAR TECHNOLOGY CORPORATION 1997
LT 0506 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
(408) 432-1900
FAX: (408) 434-0507
●
TELEX: 499-3977
●
www.linear-tech.com
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
SW Package
28-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
PART NUMBER DESCRIPTION COMMENTS
LTC1278/79 Single Supply, 500ksps/600ksps ADCs Low Power, 5V or ±5V Supply
LTC1400 High Speed, Serial 12-Bit ADC 400ksps, Complete with Internal Reference, SO-8 Package
LTC1409 Low Power, 12-Bit, 800ksps Sampling ADC Best Dynamic Performance, f
SAMPLE
≤ 800ksps, 80mW Dissipation
LTC1410 12-Bit, 1.25Msps Sampling ADC with Shutdown Best Dynamic Performance, THD = 84dB and SINAD = 71dB at Nyquist
LTC1415 Single 5V, 12-Bit 1.25Msps ADC Single Supply, 55mW Dissipation
LTC1604 16-Bit 333ksps ADC ±2.5V Inputs, Pin Compatible with the LTC1608
LTC1605 Single 5V, 16-Bit 100ksps ADC Low Power, ±10V Inputs
LTC1606 16-Bit 250ksps ADC ±10V Inputs, Pin Compatible with the LTC1605
LTC1608 16-Bit 500ksps ADC ±2.5V Inputs, Pin Compatible with the LTC1604
RELATED PARTS
S28 (WIDE) 1098
0° – 8° TYP
NOTE 1
0.009 – 0.013
(0.229 – 0.330)
0.016 – 0.050
(0.406 – 1.270)
0.291 – 0.299**
(7.391 – 7.595)
× 45°
0.010 – 0.029
(0.254 – 0.737)
0.037 – 0.045
(0.940 – 1.143)
0.004 – 0.012
(0.102 – 0.305)
0.093 – 0.104
(2.362 – 2.642)
0.050
(1.270)
BSC 0.014 – 0.019
(0.356 – 0.482)
TYP
NOTE 1
0.697 – 0.712*
(17.70 – 18.08)
12345678
0.394 – 0.419
(10.007 – 10.643)
910
2526
11 12
22 21 20 19 18 17 16 152324
1413
2728
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
