Rev: 1.00b 12/2002 1/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
250 MHz–133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS88018/32/36BT is a 9,437,184-bit (8,388,608-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV
. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode pin
low places the RAM in Flow Through mode, causing output
data to bypass the Data Output Register. Holding FT high
places the RAM in Pipeline mode, activating the rising-edge-
triggered Data Output Register.
SCD Pipelined Reads
The GS88018/32/36BT is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88018/32/36BT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.4
6.0
3.8
6.7
4.0
7.5
ns
ns
3.3 V Curr (x18)
Curr (x32/x36)
280
330
255
300
230
270
200
230
185
215
165
190
mA
mA
2.5 V Curr (x18)
Curr (x32/x36)
275
320
250
295
230
265
195
225
180
210
165
185
mA
mA
Flow
Through
2-1-1-1
tKQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V Curr (x18)
Curr (x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
2.5 V Curr (x18)
Curr (x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
Rev: 1.00b 12/2002 2/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
GS88018B 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
VDD
NC
VSS
DQB5
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
VSS
VDDQ
VDDQ
VSS
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
VSS
VDDQ
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
A17
A10
A11
A12
A13
A14
A16
A6
A7
E1
E2
NC
NC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADV
A8
A9
A15
512K x 18
Top View
DQA9
A18
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC 10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
Rev: 1.00b 12/2002 3/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
GS88032B 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
VSS
VDDQ
VDDQ
VSS
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
VSS
VDDQ
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
A17
A10
A11
A12
A13
A14
A16
A6
A7
E1
E2
BD
BC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADV
A8
A9
A15
256K x 32
Top View
DQB5
NC
DQB7
DQB8
DQB6
DQA6
DQA5
DQA8
DQA7
NC
DQC7
DQC8
DQC6
DQD6
DQD8
DQD7
NC
DQC5
NC 10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
Rev: 1.00b 12/2002 4/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
GS88036B 100-Pin TQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
VSS
VDDQ
VDDQ
VSS
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
VSS
VDDQ
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
A17
A10
A11
A12
A13
A14
A16
A6
A7
E1
E2
BD
BC
BB
BA
E3
CK
GW
BW
VDD
VSS
G
ADSC
ADSP
ADV
A8
A9
A15
256K x 36
Top View
DQB5
DQB9
DQB7
DQB8
DQB6
DQA6
DQA5
DQA8
DQA7
DQA9
DQC7
DQC8
DQC6
DQD6
DQD8
DQD7
DQD9
DQC5
DQC9
10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FT
Rev: 1.00b 12/2002 5/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
TQFP Pin Description
Symbol Type Description
A0, A1I Address field LSBs and Address Counter preset Inputs
A2–A17 I Address Inputs
A18 I Address Input
DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
I/O Data Input and Output pin
NC —No Connect
BW IByte Write—Writes all enabled bytes; active low
BA, BB, BC, BDI Byte Write Enable for DQA, DQB Data I/Os; active low
CK I Clock Input Signal; active high
GW I Global Write Enable—Writes all bytes; active low
E1, E3I Chip Enable; active low
E2I Chip Enable; active high
GI Output Enable; active low
ADV I Burst address counter advance enable; active low
ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low
ZZ I Sleep Mode control; active high
FT I Flow Through or Pipeline mode; active low
LBO I Linear Burst Order mode; active low
VDD I Core power supply
VSS I I/O and Core Ground
VDDQ I Output driver power supply
Rev: 1.00b 12/2002 6/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
GS88018/32/36B Block Diagram
A1
A0 A0
A1
D0
D1 Q1
Q0
Counter
Load
DQ
DQ
Register
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
E1
G
ZZ Power Down
Control
Memory
Array
36 36
4
A
QD
E2
E3
DQx1–DQx9
Note: Only x36 version shown for simplicity.
DCD=1
BA
BB
BC
BD
FT
Rev: 1.00b 12/2002 7/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
Note:
There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Byte Write Truth Table
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Mode Pin Functions
Mode Name Pin
Name State Function
Burst Order Control LBO L Linear Burst
H Interleaved Burst
Power Down Control ZZ L or NC Active
H Standby, IDD = ISB
Function GW BW BABBBCBDNotes
Read H H X X X X 1
Read HLHHHH1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4
Write all bytesHLLLLL2, 3, 4
Write all bytesLXXXXX
Linear Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Rev: 1.00b 12/2002 8/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
Synchronous Truth Table
Operation Address
Used
State
Diagram
Key5
E1E2ADSP ADSC ADV W3DQ4
Deselect Cycle, Power Down None X H X X L X X High-Z
Deselect Cycle, Power Down None X L F L X X X High-Z
Deselect Cycle, Power Down None X L F H L X X High-Z
Read Cycle, Begin Burst External R L T L X X X Q
Read Cycle, Begin Burst External R L T H L X F Q
Write Cycle, Begin Burst External W L T H L X T D
Read Cycle, Continue Burst Next CR X X H H L F Q
Read Cycle, Continue Burst Next CR H X X H L F Q
Write Cycle, Continue Burst Next CW X X H H L T D
Write Cycle, Continue Burst Next CW H X X H L T D
Read Cycle, Suspend Burst Current X X H H H F Q
Read Cycle, Suspend Burst Current H X X H H F Q
Write Cycle, Suspend Burst Current X X H H H T D
Write Cycle, Suspend Burst Current H X X H H T D
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1; E = F (False) if E2 = 0
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.00b 12/2002 9/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
First Write First Read
Burst Write Burst Read
Deselect
R
W
CRCW
X
X
WR
R
WR
XX
X
Simple Synchronous OperationSimple Burst Synchronous Operation
CR
R
CW CR
CR
Simplified State Diagram
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.00b 12/2002 10/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
First Write First Read
Burst Write Burst Read
Deselect
R
W
CRCW
X
X
WR
R
WR
X
X
X
CR
R
CW CR
CR
W
CW
W
CW
Simplified State Diagram with G
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.00b 12/2002 11/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
VDD Voltage on VDD Pins –0.5 to 4.6 V
VDDQ Voltage in VDDQ Pins –0.5 to 4.6 V
VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V
VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V
IIN Input Current on Any Pin +/–20 mA
IOUT Output Current on Any I/O Pin +/–20 mA
PDPackage Power Dissipation 1.5 W
TSTG Storage Temperature –55 to 125 oC
TBIAS Temperature Under Bias –55 to 125 oC
Rev: 1.00b 12/2002 12/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
Power Supply Voltage Ranges
Parameter Symbol Min. Typ. Max. Unit Notes
3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V
2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V
3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V
2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
VDDQ3 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage VIH 2.0 —VDD + 0.3 V1
VDD Input Low Voltage VIL –0.3 —0.8 V 1
VDDQ I/O Input High Voltage VIHQ 2.0 —VDDQ + 0.3 V1,3
VDDQ I/O Input Low Voltage VILQ –0.3 —0.8 V 1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
VDDQ2 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage VIH 0.6*VDD —VDD + 0.3 V1
VDD Input Low Voltage VIL –0.3 —0.3*VDD V1
VDDQ I/O Input High Voltage VIHQ 0.6*VDD —VDDQ + 0.3 V1,3
VDDQ I/O Input Low Voltage VILQ –0.3 —0.3*VDD V1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Rev: 1.00b 12/2002 13/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
Note: These parameters are sample tested.
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Recommended Operating Temperatures
Parameter Symbol Min. Typ. Max. Unit Notes
Ambient Temperature (Commercial Range Versions) TA02570°C2
Ambient Temperature (Industrial Range Versions) TA–40 25 85 °C2
Note:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 45pF
Input/Output Capacitance CI/O VOUT = 0 V 67pF
Package Thermal Characteristics
Rating Layer Board Symbol Max Unit Notes
Junction to Ambient (at 200 lfm) single RΘJA 40 °C/W 1,2
Junction to Ambient (at 200 lfm) four RΘJA 24 °C/W 1,2
Junction to Case (TOP) —RΘJC 9°C/W 3
20% tKC
V
SS – 2.0 V
50%
VSS
VIH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKC
VDD + 2.0 V
50%
VDD
VIL
Rev: 1.00b 12/2002 14/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
AC Test Conditions
Parameter Conditions
Input high level VDD – 0.2 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDD/2
Output reference level VDDQ/2
Output load Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA
ZZ Input Current IIN1
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
–1 uA
–1 uA
1 uA
100 uA
FT Input Current IIN2
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–100 uA
–1 uA
1 uA
1 uA
Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA
Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V —
Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V —
Output Low Voltage VOL IOL = 8 mA —0.4 V
DQ
VDDQ/2
50Ω30pF*
Output Load 1
* Distributed Test Jig Capacitance
Rev: 1.00b 12/2002 15/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
Operating Currents
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
Parameter Test Conditions Mode Symbol
-250 -225 -200 -166 -150 -133
Unit
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
Operating
Current
3.3 V
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
(x32/
x36)
Pipeline IDD
IDDQ
290
40
300
40
265
35
275
35
240
30
250
30
205
25
215
25
190
25
200
25
170
20
180
20 mA
Flow Through IDD
IDDQ
180
20
190
20
170
20
180
20
165
15
175
15
155
15
165
15
150
15
160
15
140
10
150
10 mA
(x18)
Pipeline IDD
IDDQ
260
20
270
20
235
20
245
20
215
15
225
15
185
15
195
15
170
15
180
15
155
10
165
10 mA
Flow Through IDD
IDDQ
165
10
175
10
155
10
165
10
150
10
160
10
140
10
150
10
135
10
145
10
125
10
135
10 mA
Operating
Current
2.5 V
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
(x32/
x36)
Pipeline IDD
IDDQ
290
30
300
30
265
30
275
30
240
25
250
25
205
20
215
20
190
20
200
20
170
15
180
15 mA
Flow Through IDD
IDDQ
180
20
190
20
170
20
180
20
165
15
175
15
155
15
165
15
150
15
160
15
140
10
150
10 mA
(x18)
Pipeline IDD
IDDQ
260
15
270
15
235
15
245
15
215
15
225
15
185
10
195
10
170
10
180
10
155
10
165
10 mA
Flow Through IDD
IDDQ
165
10
175
10
155
10
165
10
150
10
160
10
140
10
150
10
135
10
145
10
125
10
135
10 mA
Standby
Current ZZ ≥ VDD – 0.2 V —
Pipeline ISB 40 50 40 50 40 50 40 50 40 50 40 50 mA
Flow Through ISB 40 50 40 50 40 50 40 50 40 50 40 50 mA
Deselect
Current
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
—
Pipeline IDD 85 90 80 85 75 80 64 70 60 65 50 55 mA
Flow Through IDD 60 65 60 65 50 55 50 55 50 55 45 50 mA
Rev: 1.00b 12/2002 16/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
AC Electrical Characteristics
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Parameter Symbol -250 -225 -200 -166 -150 -133 Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Pipeline
Clock Cycle Time tKC 4.0 —4.4 —5.0 —6.0 —6.7 —7.5 —ns
Clock to Output Valid tKQ —2.5 —2.7 —3.0 —3.4 —3.8 —4.0 ns
Clock to Output Invalid tKQX 1.5 —1.5 —1.5 —1.5 —1.5 —1.5 —ns
Clock to Output in Low-Z tLZ11.5 —1.5 —1.5 —1.5 —1.5 —1.5 —ns
Setup time tS 1.2 —1.3 —1.4 —1.5 —1.5 —1.5 —ns
Hold time tH 0.2 —0.3 —0.4 —0.5 —0.5 —0.5 —ns
Flow
Through
Clock Cycle Time tKC 5.5 —6.0 —6.5 —7.0 —7.5 —8.5 —ns
Clock to Output Valid tKQ —5.5 —6.0 —6.5 —7.0 —7.5 —8.5 ns
Clock to Output Invalid tKQX 3.0 —3.0 —3.0 —3.0 —3.0 —3.0 —ns
Clock to Output in Low-Z tLZ13.0 —3.0 —3.0 —3.0 —3.0 —3.0 —ns
Setup time tS 1.5 —1.5 —1.5 —1.5 —1.5 —1.5 —ns
Hold time tH 0.5 —0.5 —0.5 —0.5 —0.5 —0.5 —ns
Clock HIGH Time tKH 1.3 —1.3 —1.3 —1.3 —1.5 —1.7 —ns
Clock LOW Time tKL 1.5 —1.5 —1.5 —1.5 —1.7 —2—ns
Clock to Output in
High-Z tHZ11.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns
G to Output Valid tOE —2.5 —2.7 —3.2 —3.5 —3.8 —4.0 ns
G to output in Low-Z tOLZ10—0—0—0—0—0—ns
G to output in High-Z tOHZ1—2.5 —2.7 —3.0 —3.0 —3.0 —3.0 ns
ZZ setup time tZZS25—5—5—5—5—5—ns
ZZ hold time tZZH21—1—1—1—1—1—ns
ZZ recovery tZZR 20 —20 —20 —20 —20 —20 —ns
Rev: 1.00b 12/2002 17/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
Pipeline Mode Timing
Begin Read A Cont Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect
tKQXtKQ
tLZ
tH
tS
tOHZtOE
tH
tS
tH
tS
tH
tS
tH
tS
tHtS
tS
tH
tS
tHtS
tH
tS
Burst ReadBurst ReadSingle Write
tKCtKC
tKLtKL
tKH
Single WriteSingle Read
tKH
Single Read
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3)
ABC
Deselected with E1
E1 masks ADSP
E2 and E3 only sampled with ADSP and ADSC
ADSC initiated read
CK
ADSP
ADSC
ADV
A0–An
GW
BW
Ba–Bd
E1
E2
E3
G
DQa–DQd
Rev: 1.00b 12/2002 18/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
Flow Through Mode Timing
Begin Read A Cont Cont1 Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont2 Deselect
tKQX
tHZtKQ
tLZtH
tS
tOHZtOE
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKCtKC
tKLtKL
tKHtKH
ABC
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
E2 and E3 only sampled with ADSC
ADSC initiated read
Deselected with E1
Fixed High
CK
ADSP
ADSC
ADV
A0–An
GW
BW
Ba–Bd
E1
E2
E3
G
DQa–DQd
Rev: 1.00b 12/2002 19/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.
CK
ADSP
ADSC
tH tKH tKL
tKC
tS
ZZ tZZR
tZZH
tZZS
~
~
~
~~
~~
~~
~~
~
Snooze
Sleep Mode Timing Diagram
~
~
~
~
~
~
~
~
~
~
Rev: 1.00b 12/2002 20/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
TQFP Package Drawing
D1
D
E1
E
Pin 1
b
e
c
L
L1
A2
A1
Y
θ
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Symbol Description Min. Nom. Max
A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45
b Lead Width 0.20 0.30 0.40
c Lead Thickness 0.09 —0.20
D Terminal Dimension 21.9 22.0 22.1
D1 Package Body 19.9 20.0 20.1
E Terminal Dimension 15.9 16.0 16.1
E1 Package Body 13.9 14.0 14.1
e Lead Pitch —0.65 —
L Foot Length 0.45 0.60 0.75
L1 Lead Length —1.00 —
Y Coplanarity 0.10
θLead Angle 0°—7°
Rev: 1.00b 12/2002 21/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
Org Part Number1Type Package Speed2
(MHz/ns) TA3Status
512K x 18 GS88018BT-250 Pipeline/Flow Through TQFP 250/5.5 C
512K x 18 GS88018BT-225 Pipeline/Flow Through TQFP 225/6 C
512K x 18 GS88018BT-200 Pipeline/Flow Through TQFP 200/6.5 C
512K x 18 GS88018BT-166 Pipeline/Flow Through TQFP 166/7 C
512K x 18 GS88018BT-150 Pipeline/Flow Through TQFP 150/7.5 C
512K x 18 GS88018BT-133 Pipeline/Flow Through TQFP 133/8.5 C
256K x 32 GS88032BT-250 Pipeline/Flow Through TQFP 250/5.5 C
256K x 32 GS88032BT-225 Pipeline/Flow Through TQFP 225/6 C
256K x 32 GS88032BT-200 Pipeline/Flow Through TQFP 200/6.5 C
256K x 32 GS88032BT-166 Pipeline/Flow Through TQFP 166/7 C
256K x 32 GS88032BT-150 Pipeline/Flow Through TQFP 150/7.5 C
256K x 32 GS88032BT-133 Pipeline/Flow Through TQFP 133/8.5 C
256K x 36 GS88036BT-250 Pipeline/Flow Through TQFP 250/5.5 C
256K x 36 GS88036BT-225 Pipeline/Flow Through TQFP 225/6 C
256K x 36 GS88036BT-200 Pipeline/Flow Through TQFP 200/6.5 C
256K x 36 GS88036BT-166 Pipeline/Flow Through TQFP 166/7 C
256K x 36 GS88036BT-150 Pipeline/Flow Through TQFP 150/7.5 C
256K x 36 GS88036BT-133 Pipeline/Flow Through TQFP 133/8.5 C
512K x 18 GS88018BT-250I Pipeline/Flow Through TQFP 250/5.5 I
512K x 18 GS88018BT-225I Pipeline/Flow Through TQFP 225/6 I
512K x 18 GS88018BT-200I Pipeline/Flow Through TQFP 200/6.5 I
512K x 18 GS88018BT-166I Pipeline/Flow Through TQFP 166/7 I
512K x 18 GS88018BT-150I Pipeline/Flow Through TQFP 150/7.5 I
512K x 18 GS88018BT-133I Pipeline/Flow Through TQFP 133/8.5 I
256K x 32 GS88032BT-250I Pipeline/Flow Through TQFP 250/5.5 I
256K x 32 GS88032BT-225I Pipeline/Flow Through TQFP 225/6 I
256K x 32 GS88032BT-200I Pipeline/Flow Through TQFP 200/6.5 I
256K x 32 GS88032BT-166I Pipeline/Flow Through TQFP 166/7 I
256K x 32 GS88032BT-150I Pipeline/Flow Through TQFP 150/7.5 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88018BT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.00b 12/2002 22/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
256K x 32 GS88032BT-133I Pipeline/Flow Through TQFP 133/8.5 I
256K x 36 GS88036BT-250I Pipeline/Flow Through TQFP 250/5.5 I
256K x 36 GS88036BT-225I Pipeline/Flow Through TQFP 225/6 I
256K x 36 GS88036BT-200I Pipeline/Flow Through TQFP 200/6.5 I
256K x 36 GS88036BT-166I Pipeline/Flow Through TQFP 166/7 I
256K x 36 GS88036BT-150I Pipeline/Flow Through TQFP 150/7.5 I
256K x 36 GS88036BT-133I Pipeline/Flow Through TQFP 133/8.5 I
Ordering Information for GSI Synchronous Burst RAMs
Org Part Number1Type Package Speed2
(MHz/ns) TA3Status
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88018BT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.00b 12/2002 23/23 © 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88018/32/36BT-250/225/200/166/150/133
9Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content Page;Revisions;Reason
88018B_r1 • Creation of new datasheet
