MT48H16M16LFBF-6 IT:H TR - MICRON TECHNOLOGY

Mobile Low-Power SDR SDRAM

MT48H16M16LF – 4 Meg x 16 x 4 banks

MT48H8M32LF – 2 Meg x 32 x 4 banks

Features

• VDD/VDDQ = 1.7–1.95V

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal, pipelined operation; column address can

be changed every clock cycle

• Four internal banks for concurrent operation

• Programmable burst lengths: 1, 2, 4, 8, and continu-

ous

• Auto precharge, includes concurrent auto precharge

• Auto refresh and self refresh modes

• LVTTL-compatible inputs and outputs

• On-chip temperature sensor to control self refresh

rate

• Partial-array self refresh (PASR)

• Deep power-down (DPD)

• Selectable output drive strength (DS)

• 64ms refresh period

Options Marking

• VDD/VDDQ: 1.8V/1.8V H

• Addressing

– Standard addressing option LF

• Configuration

– 16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16

– 8 Meg x 32 (2 Meg x 32 x 4 banks) 8M32

• Plastic “green” packages

– 54-ball VFBGA (8mm x 9mm)1BF

– 90-ball VFBGA (8mm x 13mm)2B5

• Timing – cycle time

– 6ns @ CL = 3 -6

– 7.5ns @ CL = 3 -75

• Operating temperature range

– Commercial (0˚C to +70˚C) None

– Industrial (–40˚C to +85˚C) IT

• Revision :H

Notes: 1. Available only for x16 configuration.

2. Available only for x32 configuration.

Table 1: Configuration Addressing

Architecture 16 Meg x 16 8 Meg x 32

Number of banks 4 4

Bank address balls BA0, BA1 BA0, BA1

Row address balls A[12:0] A[11:0]

Column address balls A[8:0] A[8:0]

Table 2: Key Timing Parameters

Speed

Grade

Clock Rate (MHz) Access Time

CL = 2 CL = 3 CL = 2 CL = 3

-6 104 166 8.0ns 5.0ns

-75 104 133 8.0ns 5.4ns

Note: 1. CL = CAS (READ) latency

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Features

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Products and specifications discussed herein are subject to change by Micron without notice.

Figure 1: 256Mb Mobile LPSDR Part Numbering

MT 48 H 16M16 LF BF -6 IT :H

Micron Technology

Product Family

48 = Mobile SDR SDRAM

Operating Voltage

H = 1.8V/1.8V

Configuration

16 Meg x 16

8 Meg x 32

Addressing

LF = Mobile standard addressing

Revision

Operating Temperature

Blank = Commercial (0°C to +70°C)

IT = Industrial (–40°C to +85°C)

Cycle Time

-6 = 6ns tCK, CL = 3

-75 = 7.5ns tCK, CL = 3

Package Codes

BF = 8mm x 9mm VFBGA “green”

B5 = 8mm x 13mm VFBGA “green”

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the

part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Features

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Contents

General Description ......................................................................................................................................... 8

Functional Block Diagram ................................................................................................................................ 9

Ball Assignments and Descriptions ................................................................................................................. 10

Package Dimensions ....................................................................................................................................... 13

Electrical Specifications .................................................................................................................................. 15

Absolute Maximum Ratings ........................................................................................................................ 15

Electrical Specifications – IDD Parameters ........................................................................................................ 17

Electrical Specifications – AC Operating Conditions ......................................................................................... 20

Output Drive Characteristics ........................................................................................................................... 23

Functional Description ................................................................................................................................... 26

Commands .................................................................................................................................................... 27

COMMAND INHIBIT .................................................................................................................................. 28

NO OPERATION (NOP) ............................................................................................................................... 28

LOAD MODE REGISTER (LMR) ................................................................................................................... 28

ACTIVE ...................................................................................................................................................... 28

READ ......................................................................................................................................................... 29

WRITE ....................................................................................................................................................... 30

PRECHARGE .............................................................................................................................................. 31

BURST TERMINATE ................................................................................................................................... 31

AUTO REFRESH ......................................................................................................................................... 31

SELF REFRESH ........................................................................................................................................... 32

DEEP POWER-DOWN ................................................................................................................................. 32

Truth Tables ................................................................................................................................................... 33

Initialization .................................................................................................................................................. 38

Mode Register ................................................................................................................................................ 40

Burst Length .............................................................................................................................................. 41

Burst Type .................................................................................................................................................. 41

CAS Latency ............................................................................................................................................... 43

Operating Mode ......................................................................................................................................... 43

Write Burst Mode ....................................................................................................................................... 43

Extended Mode Register ................................................................................................................................. 44

Temperature-Compensated Self Refresh ...................................................................................................... 44

Partial-Array Self Refresh ............................................................................................................................ 45

Output Drive Strength ................................................................................................................................ 45

Bank/Row Activation ...................................................................................................................................... 46

READ Operation ............................................................................................................................................. 47

WRITE Operation ........................................................................................................................................... 56

Burst Read/Single Write .............................................................................................................................. 63

PRECHARGE Operation .................................................................................................................................. 64

Auto Precharge ........................................................................................................................................... 64

AUTO REFRESH Operation ............................................................................................................................. 76

SELF REFRESH Operation ............................................................................................................................... 78

Power-Down .................................................................................................................................................. 80

Deep Power-Down ......................................................................................................................................... 81

Clock Suspend ............................................................................................................................................... 82

Revision History ............................................................................................................................................. 85

Rev. J, Production – 09/10 ........................................................................................................................... 85

Rev. I, Production – 11/09 ........................................................................................................................... 85

Rev. H, Production – 10/09 .......................................................................................................................... 85

Rev. G, Production – 8/09 ............................................................................................................................ 85

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Features

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Rev. F, Production – 6/09 ............................................................................................................................. 85

Rev. E, Production – 4/09 ............................................................................................................................ 85

Rev. D, Production – 1/09 ............................................................................................................................ 85

Rev. C, Production – 12/08 .......................................................................................................................... 85

Rev. B, Preliminary – 10/08 .......................................................................................................................... 85

Rev. A, Advance – 9/08 ................................................................................................................................ 85

Revision History for Commands, Operations, and Timing Diagrams ............................................................. 85

Update – 10/08 ........................................................................................................................................... 85

Update – 7/08 ............................................................................................................................................. 86

Update – 5/08 ............................................................................................................................................. 86

Update – 4/08 ............................................................................................................................................. 86

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Features

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List of Figures

Figure 1: 256Mb Mobile LPSDR Part Numbering ............................................................................................... 2

Figure 2: Functional Block Diagram ................................................................................................................. 9

Figure 3: 54-Ball VFBGA (Top View) ............................................................................................................... 10

Figure 4: 90-Ball VFBGA (Top View) ............................................................................................................... 11

Figure 5: 54-Ball VFBGA (8mm x 9mm) .......................................................................................................... 13

Figure 6: 90-Ball VFBGA (8mm x 13mm) ......................................................................................................... 14

Figure 7: Typical Self Refresh Current vs. Temperature .................................................................................... 19

Figure 8: ACTIVE Command .......................................................................................................................... 28

Figure 9: READ Command ............................................................................................................................. 29

Figure 10: WRITE Command ......................................................................................................................... 30

Figure 11: PRECHARGE Command ................................................................................................................ 31

Figure 12: Initialize and Load Mode Register .................................................................................................. 39

Figure 13: Mode Register Definition ............................................................................................................... 40

Figure 14: CAS Latency .................................................................................................................................. 43

Figure 15: Extended Mode Register Definition ................................................................................................ 44

Figure 16: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 46

Figure 17: Consecutive READ Bursts .............................................................................................................. 48

Figure 18: Random READ Accesses ................................................................................................................ 49

Figure 19: READ-to-WRITE ............................................................................................................................ 50

Figure 20: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 51

Figure 21: READ-to-PRECHARGE .................................................................................................................. 51

Figure 22: Terminating a READ Burst ............................................................................................................. 52

Figure 23: Alternating Bank Read Accesses ..................................................................................................... 53

Figure 24: READ Continuous Page Burst ......................................................................................................... 54

Figure 25: READ – DQM Operation ................................................................................................................ 55

Figure 26: WRITE Burst ................................................................................................................................. 56

Figure 27: WRITE-to-WRITE .......................................................................................................................... 57

Figure 28: Random WRITE Cycles .................................................................................................................. 58

Figure 29: WRITE-to-READ ............................................................................................................................ 58

Figure 30: WRITE-to-PRECHARGE ................................................................................................................. 59

Figure 31: Terminating a WRITE Burst ............................................................................................................ 60

Figure 32: Alternating Bank Write Accesses ..................................................................................................... 61

Figure 33: WRITE – Continuous Page Burst ..................................................................................................... 62

Figure 34: WRITE – DQM Operation ............................................................................................................... 63

Figure 35: READ With Auto Precharge Interrupted by a READ ......................................................................... 65

Figure 36: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 66

Figure 37: READ With Auto Precharge ............................................................................................................ 67

Figure 38: READ Without Auto Precharge ....................................................................................................... 68

Figure 39: Single READ With Auto Precharge .................................................................................................. 69

Figure 40: Single READ Without Auto Precharge ............................................................................................. 70

Figure 41: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 71

Figure 42: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 71

Figure 43: WRITE With Auto Precharge ........................................................................................................... 72

Figure 44: WRITE Without Auto Precharge ..................................................................................................... 73

Figure 45: Single WRITE With Auto Precharge ................................................................................................. 74

Figure 46: Single WRITE Without Auto Precharge ............................................................................................ 75

Figure 47: Auto Refresh Mode ........................................................................................................................ 77

Figure 48: Self Refresh Mode .......................................................................................................................... 79

Figure 49: Power-Down Mode ........................................................................................................................ 80

Figure 50: Clock Suspend During WRITE Burst ............................................................................................... 82

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Features

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Figure 51: Clock Suspend During READ Burst ................................................................................................. 83

Figure 52: Clock Suspend Mode ..................................................................................................................... 84

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Features

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List of Tables

Table 1: Configuration Addressing ................................................................................................................... 1

Table 2: Key Timing Parameters ....................................................................................................................... 1

Table 3: VFBGA Ball Descriptions ................................................................................................................... 12

Table 4: Absolute Maximum Ratings .............................................................................................................. 15

Table 5: DC Electrical Characteristics and Operating Conditions ..................................................................... 15

Table 6: Capacitance ..................................................................................................................................... 16

Table 7: IDD Specifications and Conditions (x16) ............................................................................................. 17

Table 8: IDD Specifications and Conditions (x32) ............................................................................................. 17

Table 9: IDD7 Specifications and Conditions (x16 and x32) ............................................................................... 18

Table 10: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 20

Table 11: AC Functional Characteristics ......................................................................................................... 21

Table 12: Target Output Drive Characteristics (Full Strength) ........................................................................... 23

Table 13: Target Output Drive Characteristics (Three-Quarter Strength) .......................................................... 24

Table 14: Target Output Drive Characteristics (One-Half Strength) .................................................................. 25

Table 15: Truth Table – Commands and DQM Operation ................................................................................. 27

Table 16: Truth Table – Current State Bank n, Command to Bank n .................................................................. 33

Table 17: Truth Table – Current State Bank n, Command to Bank m ................................................................. 35

Table 18: Truth Table – CKE ........................................................................................................................... 37

Table 19: Burst Definition Table ..................................................................................................................... 42

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Features

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General Description

The 256Mb Mobile LPSDR is a high-speed CMOS, dynamic random-access memory

containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a

synchronous interface (all signals are registered on the positive edge of the clock signal,

CLK). Each of the x16’s 67,108,864-bit banks is organized as 8192 rows by 512 columns

by 16 bits. Each of the x32’s 67,108,864-bit banks is organized as 4096 rows by 512 col-

umns by 32 bits.

Note:

1. Throughout the data sheet, various figures and text refer to DQs as DQ. DQ should be

interpreted as any and all DQ collectively, unless specifically stated otherwise. Addition-

ally, the x16 is divided into two bytes: the lower byte and the upper byte. For the lower

byte (DQ[7:0]), DQM refers to LDQM. For the upper byte (DQ[15:8]), DQM refers to

UDQM. The x32 is divided into four bytes. For DQ[7:0], DQM refers to DQM0. For

DQ[15:8], DQM refers to DQM1. For DQ[23:16], DQM refers to DQM2, and for

DQ[31:24], DQM refers to DQM3.

2. Complete functionality is described throughout the document; any page or diagram

may have been simplified to convey a topic and may not be inclusive of all require-

ments.

3. Any specific requirement takes precedence over a general statement.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

General Description

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Functional Block Diagram

Figure 2: Functional Block Diagram

RAS#

CAS#

CLK

CS#

WE#

CKE

Control

logic

Mode register

Command

decode

Address

BA0, BA1

DQM

I/O gating

DQM mask logic

read data latch

write drivers

Column

decoder

Bank0

memory

array

Bank0

row

address

latch

and

decoder

Sense amplifiers

Bank1Bank2Bank3

EXT mode

Data

output

Data

input

Row

address

MUX

Refresh

counter

Address

Bank

control

logic

Column/

address

counter/

latch

BA1 BA0 Bank

0 0 0

0 1 1

1 0 2

1 1 3

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Functional Block Diagram

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Ball Assignments and Descriptions

Figure 3: 54-Ball VFBGA (Top View)

VSS

DQ14

DQ12

DQ10

DQ8

UDQM

A12

VSS

DQ15

DQ13

DQ11

DQ9

DNU1

CLK

A11

VSSQ

VDDQ

VSSQ

VDDQ

VSS

CKE

VDDQ

VSSQ

VDDQ

VSSQ

VDD

CAS#

BA0

DQ0

DQ2

DQ4

DQ6

LDQM

RAS#

BA1

VDD

DQ1

DQ3

DQ5

DQ7

WE#

CS#

A10

VDD

1 2 3 4 5 6 7 8 9

Note: 1. The E2 pin must be connected to VSS, VSSQ, or left floating.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Ball Assignments and Descriptions

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Figure 4: 90-Ball VFBGA (Top View)

DQ26

DQ28

VSSQ

VDDQ

VSS

CLK

DQM1

VDDQ

VSSQ

DQ11

DQ13

DQ24

VDDQ

DQ27

DQ29

DQ31

DQM3

CKE

DNU1

DQ8

DQ10

DQ12

VDDQ

DQ15

VSS

VSSQ

DQ25

DQ30

A12

VSS

DQ9

DQ14

VSSQ

VSS

VDD

VDDQ

DQ22

DQ17

A10

A13

BA0

CAS#

VDD

DQ6

DQ1

VDDQ

VDD

DQ23

VSSQ

DQ20

DQ18

DQ16

DQM2

BA1

CS#

WE#

DQ7

DQ5

DQ3

VSSQ

DQ0

DQ21

DQ19

VDDQ

VSSQ

VDD

A11

RAS#

DQM0

VSSQ

VDDQ

DQ4

DQ2

1 2 3 4 5 6 7 8 9

Note: 1. The K2 pin must be connected to VSS, VSSQ, or left floating.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Ball Assignments and Descriptions

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Table 3: VFBGA Ball Descriptions

Symbol Type Description

CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive

edge of CLK. CLK also increments the internal burst counter and controls the output regis-

ters.

CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the

clock provides precharge power-down and SELF REFRESH operation (all banks idle), active

power-down (row active in any bank), deep power-down (all banks idle), or CLOCK SUSPEND

operation (burst/access in progress). CKE is synchronous except after the device enters power-

down and self refresh modes, where CKE becomes asynchronous until after exiting the same

mode. The input buffers, including CLK, are disabled during power-down and self refresh

modes, providing low standby power.

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command de-

coder. All commands are masked when CS# is registered HIGH. CS# provides for external

bank selection on systems with multiple banks. CS# is considered part of the command code.

CAS#, RAS#,

WE#

Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being en-

tered.

LDQM,

UDQM

(54-ball)

DQM[3:0]

(90-ball)

Input Input/Output mask: DQM is sampled HIGH and is an input mask signal for write accesses and

an output enable signal for read accesses. Input data is masked during a WRITE cycle. The

output buffers are High-Z (two-clock latency) during a READ cycle. For the x16, LDQM corre-

sponds to DQ[7:0] and UDQM corresponds to DQ[16:8]. For the x32, DQM0 corresponds to

DQ[7:0], DQM1 corresponds to DQ[15:8], DQM2 corresponds to DQ[23:16], and DQM3 corre-

sponds to DQ[31:24]. DQM[3:0] (or LDQM and UDQM if x16) are considered same state when

referenced as DQM.

BA0, BA1 Input Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRE-

CHARGE command is being applied. BA0 and BA1 become “Don’t Care” when registering an

ALL BANK PRECHARGE (A10 HIGH).

A[13:0] Input Address inputs: Addresses are sampled during the ACTIVE command (row) and READ/WRITE

command [column); column address A[9:0] (x16); with A10 defining auto precharge] to select

one location out of the memory array in the respective bank. A10 is sampled during a PRE-

CHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selec-

ted by BA0, BA1. The address inputs also provide the op-code during a LOAD MODE REGIS-

TER command. The maximum address range is dependent upon configuration. Unused ad-

dress pins become RFU.1

DQ[31:0] I/O Data input/output: Data bus.

VDDQ Supply DQ power: Provide isolated power to DQ for improved noise immunity.

VSSQ Supply DQ ground: Provide isolated ground to DQ for improved noise immunity.

VDD Supply Core power supply.

VSS Supply Ground.

DNU – Do not use: Must be grounded or left floating.

NC – Internally not connected. These balls can be left unconnected but it is recommended that

they be connected to VSS.

Note: 1. Balls marked RFU may or may not be connected internally. These balls should not be

used. Contact the factory for details.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Ball Assignments and Descriptions

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Package Dimensions

Figure 5: 54-Ball VFBGA (8mm x 9mm)

Ball A1 ID

Seating

plane

0.65 ±0.05

Solder ball

material: SAC105.

Dimensions apply

to solder balls

post-reflow on

Ø0.4 SMD ball pads.

0.1 A

9 ±0.1

0.8 TYP

1.0 MAX

6.4 CTR

Ball A1 ID

0.8 TYP

8 ±0.1

6.4 CTR

54X Ø0.45

0.25 MIN

9 8 7 3 2 1

Note: 1. All dimensions are in millimeters.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Package Dimensions

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Figure 6: 90-Ball VFBGA (8mm x 13mm)

Ball A1 ID

1.0 MAX

13 ±0.1

Ball A1 ID

9 8 7 3 2 1

0.8 TYP

8 ±0.1

0.65 ±0.05

Seating

plane

11.2 CTR

6.4 CTR

0.1 A

90X Ø0.45

Solder ball

material: SAC105.

Dimensions apply to

solder balls post-

reflow on Ø0.4

SMD ball pads.

0.25 MIN

0.8 TYP

Note: 1. All dimensions are in millimeters.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Package Dimensions

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Electrical Specifications

Absolute Maximum Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other condi-

tions above those indicated in the operational sections of this specification is not im-

plied. Exposure to absolute maximum rating conditions for extended periods may affect

reliability.

Table 4: Absolute Maximum Ratings

Voltage/Temperature Symbol Min Max Unit

Voltage on VDD/VDDQ supply relative to VSS VDD/VDDQ –0.35 +2.7 V

Voltage on inputs, NC, or I/O balls relative to VSS VIN –0.35 +2.7

Storage temperature (plastic) TSTG –55 +150 ˚C

Note: 1. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed

VDD.

Table 5: DC Electrical Characteristics and Operating Conditions

Notes 1 and 2 apply to all parameters and conditions; VDD/VDDQ = 1.7–1.95V

Parameter/Condition Symbol Min Max Unit Notes

Supply voltage VDD 1.7 +1.95 V

I/O supply voltage VDDQ 1.7 +1.95 V

Input high voltage: Logic 1; All inputs VIH 0.8 × VDDQ VDDQ + 0.3 V 3

Input low voltage: Logic 0; All inputs VIL –0.3 +0.3 V 3

Output high voltage VOH 0.9 × VDDQ – V 4

Output low voltage VOL – +0.2 V 4

Input leakage current:

Any input 0V ≤ VIN ≤ VDD (All other balls not under test = 0V)

IL–1.0 +1.0 μA

Output leakage current: DQ are disabled; 0V ≤ VOUT ≤ VDDQ IOZ –1.5 +1.5 μA

Operating temperature: Industrial TA–40 +85 ˚C

Commercial TA0 +70 ˚C

Notes: 1. All voltages referenced to VSS.

2. A full initialization sequence is required before proper device operation is ensured.

3. VIH overshoot: VIH,max = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot

be greater than one-third of the cycle rate. VIL undershoot: VIL,min = –2V for a pulse

width ≤3ns.

4. IOUT = 4mA for full drive strength. Other drive strengths require appropriate scale.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications

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Table 6: Capacitance

Note 1 applies to all parameters and conditions

Parameter Symbol Min Max Unit

Input capacitance: CLK CL1 2.0 5.0 pF

Input capacitance: All other input-only balls CL2 2.0 5.0 pF

Input/output capacitance: DQ CL0 2.5 6.0 pF

Note: 1. This parameter is sampled. VDD, VDDQ = +1.8V; TA = 25˚C; ball under test biased at 0.9V, f

= 1 MHz.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications

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Electrical Specifications – IDD Parameters

Table 7: IDD Specifications and Conditions (x16)

Note 1 applies to all parameters and conditions; VDD/VDDQ = 1.70–1.95V

Parameter/Condition Symbol

Max

Unit Notes-6 -75

Operating current: Active mode; Burst = 1; READ or WRITE; tRC = tRC

(MIN)

IDD1 50 45 mA 2, 3, 4

Standby current: Power-down mode; All banks idle; CKE = LOW IDD2P 300 300 μA 5

Standby current: Nonpower-down mode; All banks idle; CKE = HIGH IDD2N 15 12 mA

Standby current: Active mode; CKE = LOW; CS# = HIGH; All banks ac-

tive; No accesses in progress

IDD3P 3 3 mA 3, 4, 6

Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks ac-

tive after tRCD met; No accesses in progress

IDD3N 20 20 mA 3, 4, 6

Operating current: Burst mode; READ or WRITE; All banks active, half

of DQ toggling every cycle

IDD4 80 70 mA 2, 3, 4

Auto refresh current: CKE = HIGH; CS# = HIGH tRFC = tRFC (MIN) IDD5 90 85 mA 2, 3, 4, 6

tRFC = 7.8125μs IDD6 1 1 mA 2, 3, 4, 7

Deep power-down IZZ 10 10 μA 5, 8

Table 8: IDD Specifications and Conditions (x32)

Note 1 applies to all parameters and conditions; VDD/VDDQ = 1.70–1.95V

Parameter/Condition Symbol

Max

Unit Notes-6 -75

Operating current: Active mode; Burst = 1; READ or WRITE; tRC = tRC

(MIN)

IDD1 75 60 mA 2, 3, 4

Standby current: Power-down mode; All banks idle; CKE = LOW IDD2P 300 300 μA 5

Standby current: Nonpower-down mode; All banks idle; CKE = HIGH IDD2N 15 12 mA

Standby current: Active mode; CKE = LOW; CS# = HIGH; All banks ac-

tive; No accesses in progress

IDD3P 3 3 mA 3, 4, 6

Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks ac-

tive after tRCD met; No accesses in progress

IDD3N 20 20 mA 3, 4, 6

Operating current: Burst mode; READ or WRITE; All banks active, half

of DQ toggling every cycle

IDD4 100 85 mA 2, 3, 4

Auto refresh current: CKE = HIGH; CS# = HIGH tRFC = tRFC (MIN) IDD5 90 85 mA 2, 3, 4, 6

tRFC = 7.8125μs IDD6 1 1 mA 2, 3, 4, 7

Deep power-down IZZ 10 10 μA 5, 8

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications – IDD Parameters

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Table 9: IDD7 Specifications and Conditions (x16 and x32)

Notes 1, 5, 9, and 10 apply to all parameters and conditions; VDD/VDDQ = 1.70–1.95V

Parameter/Condition Symbol IDD7 Unit

Self refresh:

CKE = LOW; tCK = tCK (MIN);

Address and control inputs are stable;

Data bus inputs are stable

Full array, 85˚C IDD7 300 μA

Full array, 45˚C 190 μA

1/2 array, 85˚C 250 μA

1/2 array, 45˚C 150 μA

1/4 array, 85˚C 230 μA

1/4 array, 45˚C 130 μA

1/8 array, 85˚C 220 μA

1/8 array, 45˚C 120 μA

1/16 array, 85˚C 200 μA

1/16 array, 45˚C 110 μA

Notes: 1. A full initialization sequence is required before proper device operation is ensured.

2. IDD is dependent on output loading and cycle rates. Specified values are obtained with

minimum cycle time and the outputs open.

3. The IDD current will increase or decrease proportionally according to the amount of fre-

quency alteration for the test condition.

4. Address transitions average one transition every two clocks.

5. Measurement is taken 500ms after entering into this operating mode to provide tester

measuring unit settling time.

6. Other input signals can transition only one time for every two clocks and are otherwise

at valid VIH or VIL levels.

7. CKE is HIGH during REFRESH command period tRFC (MIN) else CKE is LOW. The IDD7 limit

is a nominal value and does not result in a fail value.

8. Typical values at 25˚C (not a maximum value).

9. Enables on-die refresh and address counters.

10. Values for IDD7 85˚C full array and partial array are guaranteed for the entire tempera-

ture range. All other IDD7 values are estimated.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications – IDD Parameters

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Figure 7: Typical Self Refresh Current vs. Temperature

260

240

220

200

180

160

140

120

100

-40° -30° -20° -10° 0° 10° 20° 30° 40° 50° 60° 70° 80° 90° 100° 110°

IDD6 (µA)

Temperature (°C) Full array

1/2 array

1/4 array

1/8 array

1/16 array

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications – IDD Parameters

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Electrical Specifications – AC Operating Conditions

Table 10: Electrical Characteristics and Recommended AC Operating Conditions

Notes 1–5 apply to all parameters and conditions

Parameter Symbol

-6 -75

Unit NotesMin Max Min Max

Access time from CLK (positive edge) CL = 3 tAC – 5 – 5.4 ns

CL = 2 – 8 – 8

Address hold time tAH 1 – 1 – ns

Address setup time tAS 1.5 – 1.5 – ns

CLK high-level width tCH 2.5 – 2.5 – ns

CLK low-level width tCL 2.5 – 2.5 – ns

Clock cycle time CL = 3 tCK 6 – 7.5 – ns 6

CL = 2 9.6 – 9.6 –

CKE hold time tCKH 1 – 1 – ns

CKE setup time tCKS 1.5 – 1.5 – ns

CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.5 – 0.5 – ns

CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 – 1.5 – ns

Data-in hold time tDH 1 – 1 – ns

Data-in setup time tDS 1.5 – 1.5 – ns

Data-out High-Z time CL = 3 tHZ – 5 – 5.4 ns 7

CL = 2 – 8 – 8 ns

Data-out Low-Z time tLZ 1 – 1 – ns

Data-out hold time (load) tOH 2.5 – 2.5 – ns

Data-out hold time (no load) tOHn1.8 – 1.8 – ns

ACTIVE-to-PRECHARGE command tRAS 52.5 120,000 52.5 120,000 ns

ACTIVE-to-ACTIVE command period tRC 60 – 67.5 – ns 8

ACTIVE-to-READ or WRITE delay tRCD 18 – 19.2 – ns

Refresh period (8192 rows) tREF – 64 – 64 ms 9

AUTO REFRESH period tRFC 72 – 72 – ns

PRECHARGE command period tRP 18 – 19.2 – ns

ACTIVE bank a to ACTIVE bank b command tRRD 2 – 2 – tCK

Transition time tT 0.3 1.2 0.3 1.2 ns 10

WRITE recovery time tWR 15 – 15 – ns 11

Exit SELF REFRESH-to-ACTIVE command tXSR 112.5 – 112.5 – ns 12

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications – AC Operating Conditions

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Table 11: AC Functional Characteristics

Notes 1–5 apply to all parameters and conditions

Parameter Symbol -6 -75 Unit Notes

Last data-in to burst STOP command tBDL 1 1 tCK 13

READ/WRITE command to READ/WRITE command tCCD 1 1 tCK 13

Last data-in to new READ/WRITE command tCDL 1 1 tCK 13

CKE to clock disable or power-down entry mode tCKED 1 1 tCK 14

Data-in to ACTIVE command tDAL 5 5 tCK 15, 17

Data-in to PRECHARGE command tDPL 2 2 tCK 16, 17

DQM to input data delay tDQD 0 0 tCK 13

DQM to data mask during WRITEs tDQM 0 0 tCK 13

DQM to data High-Z during READs tDQZ 2 2 tCK 13

WRITE command to input data delay tDWD 0 0 tCK 13

LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 tCK

CKE to clock enable or power-down exit mode tPED 1 1 tCK 14

Last data-in to PRECHARGE command tRDL 2 2 tCK 16, 17

Data-out High-Z from PRECHARGE command CL = 3 tROH 3 3 tCK 13

CL = 2 2 2 tCK

Notes: 1. A full initialization sequence is required before proper device operation is ensured.

2. The minimum specifications are used only to indicate cycle time at which proper opera-

tion over the full temperature range (–40˚C ≤ TA ≤ +85˚C industrial temperature) is en-

sured.

3. In addition to meeting the transition rate specification, the clock and CKE must transit

between VIH and VIL (or between VIL and VIH) in a monotonic manner.

4. Outputs measured for 1.8V at 0.9V with equivalent load:

20pF

Test loads with full DQ driver strength. Performance will vary with actual system DQ bus

capacitive loading, termination, and programmed drive strength.

5. AC timing tests have VIL and VIH with timing referenced to VIH/2 = crossover point. If the

input transition time is longer than tTmax, then the timing is referenced at VIL,max and

VIH,min and no longer at the VIH/2 crossover point.

6. The clock frequency must remain constant (stable clock is defined as a signal cycling

within timing constraints specified for the clock ball) during access or precharge states

(READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce

the data rate.

7. tHZ defines the time at which the output achieves the open circuit condition; it is not a

reference to VOH or VOL. The last valid data element will meet tOH before going High-Z.

8. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-

cesses to a particular row address may result in reduction of the product lifetime.

9. This device requires 8192 AUTO REFRESH cycles every 64ms (tREF). Providing a distrib-

uted AUTO REFRESH command every 7.8125μs meets the refresh requirement and en-

sures that each row is refreshed. Alternatively, 8192 AUTO REFRESH commands can be

issued in a burst at the minimum cycle rate (tRFC), one time for every 64ms.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications – AC Operating Conditions

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10. AC characteristics assume tT = 1ns. For command and address input slew rates <0.5V/ns,

timing must be derated. Input setup times require an additional 50ps for each 100

mV/ns reduction in slew rate. Input hold times remain unchanged. If the slew rate ex-

ceeds 4.5V/ns, functionality is uncertain.

11. For auto precharge mode, the precharge timing budget (tRP) begins at tRP – (1 × tCKns),

after the first clock delay and after the last WRITE is executed.

12. CLK must be toggled a minimum of two times during this period.

13. Required clocks are specified by JEDEC functionality and are not dependent on any tim-

ing parameter.

14. Timing is specified by tCKS. Clock(s) specified as a reference only at minimum cycle rate.

15. Timing is specified by tWR plus tRP. Clock(s) specified as a reference only at minimum cy-

cle rate.

16. Timing is specified by tWR.

17. Based on tCK (MIN), CL = 3.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Electrical Specifications – AC Operating Conditions

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Output Drive Characteristics

Table 12: Target Output Drive Characteristics (Full Strength)

Notes 1–2 apply to all parameters and conditions; characteristics are specified under best and worst process variations/

conditions

Voltage (V)

Pull-Down Current (mA) Pull-Up Current (mA)

Min Max Min Max

0.00 0.00 0.00 0.00 0.00

0.10 2.80 18.53 –2.80 –18.53

0.20 5.60 26.80 –5.60 –26.80

0.30 8.40 32.80 –8.40 –32.80

0.40 11.20 37.05 –11.20 –37.05

0.50 14.00 40.00 –14.00 –40.00

0.60 16.80 42.50 –16.80 –42.50

0.70 19.60 44.57 –19.60 –44.57

0.80 22.40 46.50 –22.40 –46.50

0.85 23.80 47.48 –23.80 –47.48

0.90 23.80 48.50 –23.80 –48.50

0.95 23.80 49.40 –23.80 –49.40

1.00 23.80 50.05 –23.80 –50.05

1.10 23.80 51.35 –23.80 –51.35

1.20 23.80 52.65 –23.80 –52.65

1.30 23.80 53.95 –23.80 –53.95

1.40 23.80 55.25 –23.80 –55.25

1.50 23.80 56.55 –23.80 –56.55

1.60 23.80 57.85 –23.80 –57.85

1.70 23.80 59.15 –23.80 –59.15

1.80 23.80 60.45 –23.80 –60.45

1.90 23.80 61.75 –23.80 –61.75

Notes: 1. Table values based on nominal impedance of 25Ω (full drive strength) at VDDQ/2.

2. The full variation in drive current, from minimum to maximum (due to process, voltage,

and temperature) will lie within the outer bounding lines of the I-V curves.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Output Drive Characteristics

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Table 13: Target Output Drive Characteristics (Three-Quarter Strength)

Notes 1–2 apply to all parameters and conditions; characteristics are specified under best and worst process variations/

conditions

Voltage (V)

Pull-Down Current (mA) Pull-Up Current (mA)

Min Max Min Max

0.00 0.00 0.00 0.00 0.00

0.10 1.96 12.97 –1.96 –12.97

0.20 3.92 18.76 –3.92 –18.76

0.30 5.88 22.96 –5.88 –22.96

0.40 7.84 25.94 –7.84 –25.94

0.50 9.80 28.00 –9.80 –28.00

0.60 11.76 29.75 –11.76 –29.75

0.70 13.72 31.20 –13.72 –31.20

0.80 15.68 32.55 –15.68 –32.55

0.85 16.66 33.24 –16.66 –33.24

0.90 16.66 33.95 –16.66 –33.95

0.95 16.66 34.58 –16.66 –34.58

1.00 16.66 35.04 –16.66 –35.04

1.10 16.66 35.95 –16.66 –35.95

1.20 16.66 36.86 –16.66 –36.86

1.30 16.66 37.77 –16.66 –37.77

1.40 16.66 38.68 –16.66 –38.68

1.50 16.66 39.59 –16.66 –39.59

1.60 16.66 40.50 –16.66 –40.50

1.70 16.66 41.41 –16.66 –41.41

1.80 16.66 42.32 –16.66 –42.32

1.90 16.66 43.23 –16.66 –43.23

Notes: 1. Table values based on nominal impedance of 37Ω (three-quarter drive strength) at

VDDQ/2.

2. The full variation in drive current, from minimum to maximum (due to process, voltage,

and temperature) will lie within the outer bounding lines of the I-V curves.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Output Drive Characteristics

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Table 14: Target Output Drive Characteristics (One-Half Strength)

Notes 1–3 apply to all parameters and conditions; characteristics are specified under best and worst process variations/

conditions

Voltage (V)

Pull-Down Current (mA) Pull-Up Current (mA)

Min Max Min Max

0.00 0.00 0.00 0.00 0.00

0.10 1.27 8.42 –1.27 –8.42

0.20 2.55 12.30 –2.55 –12.30

0.30 3.82 14.95 –3.82 –14.95

0.40 5.09 16.84 –5.09 –16.84

0.50 6.36 18.20 –6.36 –18.20

0.60 7.64 19.30 –7.64 –19.30

0.70 8.91 20.30 –8.91 –20.30

0.80 10.16 21.20 –10.16 –21.20

0.85 10.80 21.60 –10.80 –21.60

0.90 10.80 22.00 –10.80 –22.00

0.95 10.80 22.45 –10.80 –22.45

1.00 10.80 22.73 –10.80 –22.73

1.10 10.80 23.21 –10.80 –23.21

1.20 10.80 23.67 –10.80 –23.67

1.30 10.80 24.14 –10.80 –24.14

1.40 10.80 24.61 –10.80 –24.61

1.50 10.80 25.08 –10.80 –25.08

1.60 10.80 25.54 –10.80 –25.54

1.70 10.80 26.01 –10.80 –26.01

1.80 10.80 26.48 –10.80 –26.48

1.90 10.80 26.95 –10.80 –26.95

Notes: 1. Table values based on nominal impedance of 55Ω (one-half drive strength) at VDDQ/2.

2. The full variation in drive current, from minimum to maximum (due to process, voltage,

and temperature) will lie within the outer bounding lines of the I-V curves.

3. The I-V curve for one-quarter drive strength is approximately 50% of one-half drive

strength.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Output Drive Characteristics

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Functional Description

Mobile LPSDR devices are quad-bank DRAM that operate at 1.8V and include a syn-

chronous interface. All signals are registered on the positive edge of the clock signal,

CLK.

Read and write accesses to the device are burst oriented; accesses start at a selected lo-

cation and continue for a programmed number of locations in a programmed se-

quence. Accesses begin with the registration of an ACTIVE command, followed by a

READ or WRITE command. The address bits registered coincident with the ACTIVE

command are used to select the bank and row to be accessed (BA0 and BA1 select the

bank). The address bits registered coincident with the READ or WRITE command are

used to select the starting column location for the burst access.

The device provides for programmable READ or WRITE burst lengths. An auto pre-

charge function may be enabled to provide a self-timed row precharge that is initiated

at the end of the burst sequence.

The device uses an internal pipelined architecture that enables changing the column

address on every clock cycle to achieve high-speed, fully random access. Precharging

one bank while accessing one of the other three banks will hide the precharge cycles.

The device is designed to operate in 1.8V memory systems. An auto refresh mode is pro-

vided, along with power-saving, power-down, and deep power-down modes. All inputs

and outputs are LVTTL-compatible.

The device offers substantial advances in DRAM operating performance, including the

ability to synchronously burst data at a high data rate with automatic column-address

generation, the ability to interleave between internal banks in order to hide precharge

time, and the capability to randomly change column addresses on each clock cycle dur-

ing a burst access.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Functional Description

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Commands

The following table provides a quick reference of available commands, followed by a

written description of each command. Additional Truth Tables (Table 16 (page 33), Ta-

ble 17 (page 35), and Table 18 (page 37)) provide current state/next state informa-

tion.

Table 15: Truth Table – Commands and DQM Operation

Note 1 applies to all parameters and conditions

Name (Function) CS# RAS# CAS# WE# DQM ADDR DQ Notes

COMMAND INHIBIT (NOP) H X X X X X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (select bank and activate row) L L H H X Bank/row X 2

READ (select bank and column, and start READ burst) L H L H L/H Bank/col X 3

WRITE (select bank and column, and start WRITE burst) L H L L L/H Bank/col Valid 3

BURST TERMINATE or deep power-down

(enter deep power-down mode)

L H H L X X X 4, 5

PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 6

AUTO REFRESH or SELF REFRESH (enter self refresh mode) L L L H X X X 7, 8

LOAD MODE REGISTER L L L L X Op-code X 9

Write enable/output enable X X X X L X Active 10

Write inhibit/output High-Z X X X X H X High-Z 10

Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.

2. A[0:n] provide row address (where An is the most significant address bit), BA0 and BA1

determine which bank is made active.

3. A[0:i] provide column address (where i = the most significant column address for a given

device configuration). A10 HIGH enables the auto precharge feature (nonpersistent),

while A10 LOW disables the auto precharge feature. BA0 and BA1 determine which

bank is being read from or written to.

4. This command is BURST TERMINATE when CKE is HIGH and DEEP POWER-DOWN when

CKE is LOW.

5. The purpose of the BURST TERMINATE command is to stop a data burst, thus the com-

mand could coincide with data on the bus. However, the DQ column reads a “Don’t

Care” state to illustrate that the BURST TERMINATE command can occur when there is

no data present.

6. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: all banks pre-

charged and BA0, BA1 are “Don’t Care.”

7. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

8. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” ex-

cept for CKE.

9. A[11:0] define the op-code written to the mode register.

10. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock

delay).

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Commands

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COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands from being executed by

the device, regardless of whether the CLK signal is enabled. The device is effectively de-

selected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to the selected device

(CS# is LOW). This prevents unwanted commands from being registered during idle or

wait states. Operations already in progress are not affected.

LOAD MODE REGISTER (LMR)

The mode registers are loaded via inputs A[n:0] (where An is the most significant ad-

dress term), BA0, and BA1(see Mode Register (page 40)). The LOAD MODE REGISTER

command can only be issued when all banks are idle and a subsequent executable com-

mand cannot be issued until tMRD is met.

ACTIVE

The ACTIVE command is used to activate a row in a particular bank for a subsequent

access. The value on the BA0, BA1 inputs selects the bank, and the address provided se-

lects the row. This row remains active for accesses until a PRECHARGE command is is-

sued to that bank. A PRECHARGE command must be issued before opening a different

row in the same bank.

Figure 8: ACTIVE Command

CS#

WE#

CAS#

RAS#

CKE

CLK

Address Row address

Don’t Care

HIGH

BA0, BA1 Bank address

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Commands

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READ

The READ command is used to initiate a burst read access to an active row. The values

on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-

umn location. The value on input A10 determines whether auto precharge is used. If au-

to precharge is selected, the row being accessed is precharged at the end of the READ

burst; if auto precharge is not selected, the row remains open for subsequent accesses.

Read data appears on the DQ subject to the logic level on the DQM inputs two clocks

earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be High-

Z two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data.

Figure 9: READ Command

CS#

WE#

CAS#

RAS#

CKE

CLK

Column address

A101

BA0, BA1

Don’t Care

HIGH

EN AP

DIS AP

Bank address

Address

Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Commands

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WRITE

The WRITE command is used to initiate a burst write access to an active row. The values

on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-

umn location. The value on input A10 determines whether auto precharge is used. If au-

to precharge is selected, the row being accessed is precharged at the end of the write

burst; if auto precharge is not selected, the row remains open for subsequent accesses.

Input data appearing on the DQ is written to the memory array, subject to the DQM in-

put logic level appearing coincident with the data. If a given DQM signal is registered

LOW, the corresponding data is written to memory; if the DQM signal is registered

HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that

byte/column location.

Figure 10: WRITE Command

DIS AP

EN AP

CS#

WE#

CAS#

RAS#

CKE

CLK

Column address

Don’t Care

HIGH

Bank address

Address

BA0, BA1

Valid address

A101

Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Commands

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PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or

the open row in all banks. The bank(s) will be available for a subsequent row access a

specified time (tRP) after the PRECHARGE command is issued. Input A10 determines

whether one or all banks are to be precharged, and in the case where only one bank is

precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated as

“Don’t Care.” After a bank has been precharged, it is in the idle state and must be acti-

vated prior to any READ or WRITE commands are issued to that bank.

Figure 11: PRECHARGE Command

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

Don’t Care

HIGH

All banks

Bank selected

Address

BA0, BA1 Bank address

Valid address

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or continu-

ous page bursts. The most recently registered READ or WRITE command prior to the

BURST TERMINATE command is truncated.

AUTO REFRESH

AUTO REFRESH is used during normal operation and is analogous to CAS#-BEFORE-

RAS# (CBR) REFRESH in FPM/EDO DRAM. Addressing is generated by the internal re-

fresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH

command.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Commands

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SELF REFRESH

The SELF REFRESH command is used to place the device in self refresh mode. The self

refresh mode is used to retain data in the SDRAM while the rest of the system is pow-

ered down. When in self refresh mode, the device retains data without external clocking.

The SELF REFRESH command is initiated like an AUTO REFRESH command, except

that CKE is disabled (LOW). After the SELF REFRESH command is registered, the inputs

become “Don’t Care,” with the exception of CKE, which must remain LOW.

DEEP POWER-DOWN

The DEEP POWER-DOWN (DPD) command is used to enter deep power-down mode,

achieving maximum power reduction by eliminating the power to the memory array. To

enter DPD, all banks must be idle. While CKE is LOW, hold CS# and WE# LOW, and hold

RAS# and CAS# HIGH at the rising edge of the clock. To exit DPD, assert CKE HIGH.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Commands

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Truth Tables

Table 16: Truth Table – Current State Bank n, Command to Bank n

Notes 1–6 apply to all parameters and conditions

Current State CS# RAS# CAS# WE# Command/Action Notes

Any H X X X COMMAND INHIBIT (NOP/continue previous operation)

L H H H NO OPERATION (NOP/continue previous operation)

Idle L L H H ACTIVE (select and activate row)

L L L H AUTO REFRESH 7

L L L L LOAD MODE REGISTER 7

L L H L PRECHARGE 8

Row active L H L H READ (select column and start READ burst) 9

L H L L WRITE (select column and start WRITE burst) 9

L L H L PRECHARGE (deactivate row in bank or banks) 10

Read

(auto precharge disabled)

L H L H READ (select column and start new READ burst) 9

L H L L WRITE (select column and start WRITE burst) 9

L L H L PRECHARGE (truncate READ burst, start PRECHARGE) 10

L H H L BURST TERMINATE 9, 11

Write

(auto precharge disabled)

L H L H READ (select column and start READ burst) 9

L H L L WRITE (select column and start new WRITE burst) 9

L L H L PRECHARGE (truncate WRITE burst, start PRECHARGE) 10

L H H L BURST TERMINATE 9, 11

Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 18 (page 37))

and after tXSR has been met (if the previous state was self refresh).

2. This table is bank-specific, except where noted (for example, the current state is for a

specific bank and the commands shown can be issued to that bank when in that state).

Exceptions are covered below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row active: A row in the bank has been activated, and tRCD has been met. No data

bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank.

COMMAND INHIBIT or NOP commands, or supported commands to the other bank

should be issued on any clock edge occurring during these states. Supported commands

to any other bank are determined by the bank’s current state and the conditions descri-

bed in this and the following table.

Precharging: Starts with registration of a PRECHARGE command and ends when tRP is

met. After tRP is met, the bank will be in the idle state.

Row activating: Starts with registration of an ACTIVE command and ends when tRCD is

met. After tRCD is met, the bank will be in the row active state.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Truth Tables

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Read with auto precharge enabled: Starts with registration of a READ command

with auto precharge enabled and ends when tRP has been met. After tRP is met, the

bank will be in the idle state.

Write with auto precharge enabled: Starts with registration of a WRITE command

with auto precharge enabled and ends when tRP has been met. After tRP is met, the

bank will be in the idle state.

5. The following states must not be interrupted by any executable command; COMMAND

INHIBIT or NOP commands must be applied on each positive clock edge during these

states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when

tRFC is met. After tRFC is met, the device will be in the all banks idle state.

Accessing mode register: Starts with registration of a LOAD MODE REGISTER com-

mand and ends when tMRD has been met. After tMRD is met, the device will be in the

all banks idle state.

Precharging all: Starts with registration of a PRECHARGE ALL command and ends

when tRP is met. After tRP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank specific; requires that all banks are idle.

8. Does not affect the state of the bank and acts as a NOP to that bank.

9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

10. May or may not be bank specific; if all banks need to be precharged, each must be in a

valid state for precharging.

11. This command is BURST TERMINATE when CKE is HIGH and DEEP POWER-DOWN when

CKE is LOW.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Truth Tables

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Table 17: Truth Table – Current State Bank n, Command to Bank m

Notes 1–6 apply to all parameters and conditions

Current State CS# RAS# CAS# WE# Command/Action Notes

Any H X X X COMMAND INHIBIT (NOP/continue previous operation)

L H H H NO OPERATION (NOP/continue previous operation)

Idle X X X X Any command otherwise supported for bank m

Row activating, active, or

precharging

L L H H ACTIVE (select and activate row)

L H L H READ (select column and start READ burst) 7

L H L L WRITE (select column and start WRITE burst) 7

L L H L PRECHARGE

Read

(auto precharge disabled)

L L H H ACTIVE (select and activate row)

L H L H READ (select column and start new READ burst) 7, 10

L H L L WRITE (select column and start WRITE burst) 7, 11

L L H L PRECHARGE 9

Write

(auto precharge disabled)

L L H H ACTIVE (select and activate row)

L H L H READ (select column and start READ burst) 7, 12

L H L L WRITE (select column and start new WRITE burst) 7, 13

L L H L PRECHARGE 9

Read

(with auto precharge)

L L H H ACTIVE (select and activate row)

L H L H READ (select column and start new READ burst) 7, 8, 14

L H L L WRITE (select column and start WRITE burst) 7, 8, 15

L L H L PRECHARGE 9

Write

(with auto precharge)

L L H H ACTIVE (select and activate row)

L H L H READ (select column and start READ burst) 7, 8, 16

L H L L WRITE (select column and start new WRITE burst) 7, 8, 17

L L H L PRECHARGE 9

Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (Table 18 (page 37)), and

after tXSR has been met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted; for example, the cur-

rent state is for bank n and the commands shown can be issued to bank m, assuming

that bank m is in such a state that the given command is supported. Exceptions are cov-

ered below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row active: A row in the bank has been activated, and tRCD has been met. No data

bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet

terminated or been terminated.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Truth Tables

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Read with auto precharge enabled: Starts with registration of a READ command

with auto precharge enabled and ends when tRP has been met. After tRP is met, the

bank will be in the idle state.

Write with auto precharge enabled: Starts with registration of a WRITE command

with auto precharge enabled and ends when tRP has been met. After tRP is met, the

bank will be in the idle state.

4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands can only be is-

sued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank

represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command/Action column include READs or

WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disa-

bled.

8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its

burst has been interrupted by bank m burst.

9. The burst in bank n continues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the READ on bank n, CAS latency (CL) later.

11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-

charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM

should be used one clock prior to the WRITE command to prevent bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the WRITE on bank n when registered, with

the data-out appearing CL later. The last valid WRITE to bank n will be data-in regis-

tered one clock prior to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-

charge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The

last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank

14. For a READ with auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the READ on bank n, CL later. The PRE-

CHARGE to bank n will begin when the READ to bank m is registered.

15. For a READ with auto precharge interrupted by a WRITE (with or without auto pre-

charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM

should be used two clocks prior to the WRITE command to prevent bus contention. The

PRECHARGE to bank n will begin when the WRITE to bank m is registered.

16. For a WRITE with auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the WRITE on bank n when registered, with

the data-out appearing CL later. The PRECHARGE to bank n will begin after tWR is met,

where tWR begins when the READ to bank m is registered. The last valid WRITE bank n

will be data-in registered one clock prior to the READ to bank m.

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto pre-

charge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The

PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE

to bank m is registered. The last valid WRITE to bank n will be data registered one clock

to the WRITE to bank m.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Truth Tables

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Table 18: Truth Table – CKE

Notes 1–4 apply to all parameters and conditions

Current State CKEn-1 CKEnCommandnActionnNotes

Power-down L L X Maintain power-down

Self refresh X Maintain self refresh

Clock suspend X Maintain clock suspend

Deep power-down X Maintain deep power-down

Power-down L H COMMAND INHIBIT or NOP Exit power-down 5

Deep power-down X Exit deep power-down

Self refresh COMMAND INHIBIT or NOP Exit self refresh 6

Clock suspend X Exit clock suspend 7

All banks idle H L COMMAND INHIBIT or NOP Power-down entry

All banks idle BURST TERMINATE Deep power-down entry 8

All banks idle AUTO REFRESH Self refresh entry

Reading or writing VALID Clock suspend entry

H H Table 17 (page 35)

Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previ-

ous clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of

COMMANDn.

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time

for clock edge n + 1 (provided that tCKS is met).

6. Exiting self refresh at clock edge n will put the device in the all banks idle state after

tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges

occurring during the tXSR period. A minimum of two NOP commands must be provided

during the tXSR period.

7. After exiting clock suspend at clock edge n, the device will resume operation and recog-

nize the next command at clock edge n + 1.

8. Deep power-down is a power-saving feature of this device. This command is BURST TER-

MINATE when CKE is HIGH and DEEP POWER-DOWN when CKE is LOW.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Truth Tables

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Initialization

Low-power SDRAM devices must be powered up and initialized in a predefined man-

ner. Using initialization procedures other than those specified may result in undefined

operation. After power is simultaneously applied to VDD and VDDQ and the clock is sta-

ble (a stable clock is defined as a signal cycling within timing constraints specified for

the clock ball), the device requires a 100μs delay prior to issuing any command other

than a COMMAND INHIBIT or NOP. Starting at some point during this 100μs period

and continuing at least through the end of this period, COMMAND INHIBIT or NOP

commands should be applied.

After the 100μs delay is satisfied by issuing at least one COMMAND INHIBIT or NOP

command, a PRECHARGE command must be issued. All banks must then be pre-

charged, which places the device in the all banks idle state.

When in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO

REFRESH cycles are complete, the device is ready for mode register programming. Be-

cause the mode register powers up in an unknown state, it should be loaded prior to

issuing any operational command.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Initialization

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Figure 12: Initialize and Load Mode Register

CKE

BA0, BA1

Load extended

mode register

Load mode

tCKS

Power-up:

VDD and

CLK stable

T = 100µs

tCKH

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

DQM

(

)(

)

(

)(

)

High-Z

Address Valid

A10 Valid

CLK

tCK

Command1ARNOP LMRAR LMR Valid

tCMS tCMH

tAS tAH

BA0 = L,

BA1 = L

(

)(

)

(

)(

)

Code Code

tAS tAH

Code Code

(

)(

)

(

)(

)

PRE

All banks

tAH

(

)(

)

(

)(

)

T0 T1

Don’t Care

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

tRP tMRD3

tMRD3

tRFC2tRFC2

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

Valid

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

BA0 = L,

BA1 = L

BA0 = L,

BA1 = H

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

Precharge

all banks

(

)(

)

(

)(

)

Tn + 1 To + 1 Tp + 1 Tq + 1 Tr + 1

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

Notes: 1. PRE = PRECHARGE command, AR = AUTO REFRESH command, LMR = LOAD MODE REG-

ISTER command.

2. NOPs or DESELECTs must only be provided during tRFC time.

3. NOPs or DESELECTs must only be provided during tMRD time.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Initialization

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Mode Register

The mode register defines the specific mode of operation, including burst length (BL),

burst type, CAS latency (CL), operating mode, and write burst mode. The mode register

is programmed via the LOAD MODE REGISTER command and retains the stored infor-

mation until it is programmed again or the device loses power.

Mode register bits M[2:0] specify the BL; M3 specifies the type of burst; M[6:4] specify

the CL; M7 and M8 specify the operating mode; M9 specifies the write burst mode; and

M10–Mn should be set to zero to ensure compatibility with future revisions. Mn + 1 and

Mn + 2 should be set to zero to select the mode register.

The mode registers must be loaded when all banks are idle, and the controller must wait

tMRD before initiating the subsequent operation. Violating either of these requirements

will result in unspecified operation.

Figure 13: Mode Register Definition

*Should be programmed to 0

to ensure compatibility

with future devices.

M3 = 0

Reserved

Continuous

M3 = 1

Reserved

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Mode

Address bus

9 7 6 5 4 38 2 1

Burst lengthCAS latency BTOp mode

Reserved*

WB0

A10

M10

...

10...n

BA0

Mn+1

BA1

Mn+2

n+2 n+1 0

–

Operating Mode

Mode Register Definition

Base mode register

Reserved

Extended mode register

Reserved

Mn+2 Mn+1

Write Burst Mode

Programmed burst length

Single location access

Normal operation

All other states reserved

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Mode Register

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Burst Length

Read and write accesses to the device are burst oriented, and the burst length (BL) is

programmable. The burst length determines the maximum number of column loca-

tions that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2,

4, 8, or continuous locations are available for both the sequential and the interleaved

burst types, and a continuous page burst is available for the sequential type. The con-

tinuous page burst is used in conjunction with the BURST TERMINATE command to

generate arbitrary burst lengths.

Reserved states should not be used, as unknown operation or incompatibility with fu-

ture versions may result.

When a READ or WRITE command is issued, a block of columns equal to the burst

length is effectively selected. All accesses for that burst take place within this block,

meaning that the burst wraps within the block when a boundary is reached. The block

is uniquely selected by A[8:1] when BL = 2, A[8:2] when BL = 4, and A[8:3] when BL = 8.

The remaining (least significant) address bit(s) is (are) used to select the starting loca-

tion within the block. Continuous page bursts wrap within the page when the boundary

is reached.

Burst Type

Accesses within a given burst can be programmed to be either sequential or interleaved;

this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by the burst length, the burst

type, and the starting column address.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Mode Register

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Table 19: Burst Definition Table

Burst Length Starting Column Address

Order of Accesses Within a Burst

Type = Sequential Type = Interleaved

2 A0

0 0-1 0-1

1 1-0 1-0

4 A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

8 A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Continuous

n = A0–An/9/8 (location 0–y) Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1,

Cn...

Not supported

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Mode Register

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CAS Latency

The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ

command and the availability of the output data. The latency can be set to two or three

clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data

will be available by clock edge n + m. The DQ start driving as a result of the clock edge

one cycle earlier (n + m - 1), and provided that the relevant access times are met, the

data is valid by clock edge n + m. For example, assuming that the clock cycle time is

such that all relevant access times are met, if a READ command is registered at T0 and

the latency is programmed to two clocks, the DQ start driving after T1 and the data is

valid by T2.

Reserved states should not be used as unknown operation or incompatibility with fu-

ture versions may result.

Figure 14: CAS Latency

CLK

T2T1 T3T0

CL = 3

tLZ

DOUT

tOH

Command NOPREAD NOP

NOP

Don’t Care Undefined

CLK

T2T1 T3T0

CL = 2

tLZ

DOUT

tOH

Command NOPREAD

tAC

NOP

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combi-

nations of values for M7 and M8 are reserved for future use. Reserved states should not

be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M[2:0] applies to both READ and

WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but

write accesses are single-location (nonburst) accesses.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Mode Register

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Extended Mode Register

The extended mode register (EMR) controls additional functions beyond those control-

led by the mode register. These additional functions include TCSR, PASR, and output

drive strength.

The EMR is programmed via the LMR command (BA1 = 1, BA0 = 0) and retains the stor-

ed information until it is programmed again or the device loses power.

The EMR must be programmed with E[n:7] set to 0. It must be loaded when all banks

are idle and no bursts are in progress, and the controller must wait the specified time

before initiating any subsequent operation. Violating either of these requirements re-

sults in unspecified operation. After the values are entered, the EMR settings are re-

tained even after exiting deep power-down mode.

Figure 15: Extended Mode Register Definition

Extended mode

Address bus

9 7 6 5 4 38 2 1

PASR TCSR1

DSOperation0

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

10...

Partial-Array Self Refresh Coverage

Full array

1/2 array

1/4 array

Reserved

1/8 array

1/16 array

Reserved

BA0

...

BA1

nn + 1n + 2 0

E10

–

...

–

Normal AR operation

All other states reserved

Drive Strength

Full strength

1/2 strength

1/4 strength

3/4 strength

Reserved

E7–E0

Valid

–

En + 2

En + 1

Mode Register Definition

Standard mode register

Status register

Extended mode register

Reserved

Note: 1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no ef-

fect.

Temperature-Compensated Self Refresh

This device includes a temperature sensor that is implemented for automatic control of

the self refresh oscillator. Programming the temperature-compensated self refresh

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Extended Mode Register

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(TCSR) bits has no effect on the device. The self refresh oscillator will continue refresh

at the optimal factory-programmed rate for the device temperature.

Partial-Array Self Refresh

For further power savings during self refresh, the partial-array self refresh (PASR) feature

enables the controller to select the amount of memory to be refreshed during self re-

fresh. The refresh options are:

• Full array: banks 0, 1, 2, and 3

• One-half array: banks 0 and 1

• One-quarter array: bank 0

• One-eighth array: bank 0 with row address most significant bit (MSB) = 0

• One-sixteenth array: bank 0 with row address MSB = 0 and row address MSB - 1 = 0

READ and WRITE commands can still be issued to any bank selected during standard

operation, but only the selected banks or segments of a bank in PASR are refreshed dur-

ing self refresh. It is important to note that data in unused banks or portions of banks is

lost when PASR is used.

Output Drive Strength

Because the device is designed for use in smaller systems that are typically point-to-

point connections, an option to control the drive strength of the output buffers is provi-

ded. Drive strength should be selected based on the expected loading of the memory

bus. There are four supported settings for the output drivers: 25Ω, 37Ω, 55Ω, and 80Ω

internal impedance. These are full, three-quarter, one-half, and one-quarter drive

strengths, respectively.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Extended Mode Register

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Bank/Row Activation

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a

row in that bank must be opened. This is accomplished via the ACTIVE command,

which selects both the bank and the row to be activated.

After a row is opened with the ACTIVE command, a READ or WRITE command can be

issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by

the clock period and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVE command on which a READ or WRITE command can be

entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)

results in 2.5 clocks, rounded to 3. This is reflected in Figure 16 (page 46), which covers

any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other

specification limits from time units to clock cycles.)

A subsequent ACTIVE command to a different row in the same bank can only be issued

after the previous active row has been precharged. The minimum time interval between

successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is

being accessed, which results in a reduction of total row-access overhead. The mini-

mum time interval between successive ACTIVE commands to different banks is defined

by tRRD.

Figure 16: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3

CLK

T2T1 T3T0

Command NOPACTIVE READ or

WRITE

NOP

RCD(MIN)

tCK tCK tCK

Don’t Care

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Bank/Row Activation

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READ Operation

READ bursts are initiated with a READ command, as shown in Figure 9 (page 29). The

starting column and bank addresses are provided with the READ command, and auto

precharge is either enabled or disabled for that burst access. If auto precharge is ena-

bled, the row being accessed is precharged at the completion of the burst. In the follow-

ing figures, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address is

available following the CAS latency after the READ command. Each subsequent data-

out element will be valid by the next positive clock edge. Figure 18 (page 49) shows

general timing for each possible CAS latency setting.

Upon completion of a burst, assuming no other commands have been initiated, the DQ

signals will go to High-Z. A continuous page burst continues until terminated. At the

end of the page, it wraps to column 0 and continues.

Data from any READ burst can be truncated with a subsequent READ command, and

data from a fixed-length READ burst can be followed immediately by data from a READ

command. In either case, a continuous flow of data can be maintained. The first data

element from the new burst either follows the last element of a completed burst or the

last desired data element of a longer burst that is being truncated. The new READ com-

mand should be issued x cycles before the clock edge at which the last desired data ele-

ment is valid, where x = CL - 1. This is shown in Figure 18 (page 49) for CL2 and CL3.

Mobile LPSDR devices use a pipelined architecture and therefore do not require the 2n

rule associated with a prefetch architecture. A READ command can be initiated on any

clock cycle following a READ command. Full-speed random read accesses can be per-

formed to the same bank, or each subsequent READ can be performed to a different

bank.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

READ Operation

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Figure 17: Consecutive READ Bursts

Don’t Care

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

Command

Address

READ NOP NOP NOP NOP

Bank,

Col n

NOP

Bank,

Col b

DOUT

n + 1

DOUT

n + 2

DOUT

n + 3

DOUT

READ

X = 1 cycle

CL = 2

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

Command

Address

READ NOP NOP NOP NOP

Bank,

Col n

NOP

Bank,

Col b

DOUT

n + 1

DOUT

n + 2

DOUT

n + 3

DOUT

READ NOP

CL = 3 Transitioning data

X = 2 cycles

Note: 1. Each READ command can be issued to any bank. DQM is LOW.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

READ Operation

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Figure 18: Random READ Accesses

CLK

T2T1 T4T3 T6T5T0

Command

Address

Don’t Care

DOUT

CLK

DQ DOUT

T2T1 T4T3 T5T0

Command

Address

READ NOP

Bank,

Col n

DOUT

READ READ READ NOP

Bank,

Col a

Bank,

Col x

Bank,

Col m

READ NOP

Bank,

Col n

Bank,

Col a

READ READ READ NOP NOP

Bank,

Col x

Bank,

Col m

CL = 2

CL = 3

Note: 1. Each READ command can be issued to any bank. DQM is LOW.

Data from any READ burst can be truncated with a subsequent WRITE command, and

data from a fixed-length READ burst can be followed immediately by data from a

WRITE command (subject to bus turnaround limitations). The WRITE burst can be ini-

tiated on the clock edge immediately following the last (or last desired) data element

from the READ burst, provided that I/O contention can be avoided. In a given system

design, there is a possibility that the device driving the input data will go Low-Z before

the DQ go High-Z. In this case, at least a single-cycle delay should occur between the

last read data and the WRITE command.

The DQM input is used to avoid I/O contention, as shown in Figure 19 (page 50) and

Figure 20 (page 51). The DQM signal must be asserted (HIGH) at least two clocks prior

to the WRITE command (DQM latency is two clocks for output buffers) to suppress da-

ta-out from the READ. After the WRITE command is registered, the DQ will go to High-Z

(or remain High-Z), regardless of the state of the DQM signal, provided the DQM was

active on the clock just prior to the WRITE command that truncated the READ com-

mand. If not, the second WRITE will be an invalid WRITE. For example, if DQM was

LOW during T4, then the WRITEs at T5 and T7 would be valid, and the WRITE at T6

would be invalid.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

READ Operation

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The DQM signal must be de-asserted prior to the WRITE command (DQM latency is

zero clocks for input buffers) to ensure that the written data is not masked. Figure 19

(page 50) shows where, due to the clock cycle frequency, bus contention is avoided

without having to add a NOP cycle, while Figure 20 (page 51) shows the case where an

additional NOP cycle is required.

A fixed-length READ burst may be followed by or truncated with a PRECHARGE com-

mand to the same bank, provided that auto precharge was not activated. The PRE-

CHARGE command should be issued x cycles before the clock edge at which the last de-

sired data element is valid, where x = CL - 1. This is shown in Figure 21 (page 51) for

each possible CL; data element n + 3 is either the last of a burst of four or the last de-

sired data element of a longer burst. Following the PRECHARGE command, a subse-

quent command to the same bank cannot be issued until tRP is met. Note that part of

the row precharge time is hidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to completion, a PRECHARGE com-

mand issued at the optimum time (as described above) provides the same operation

that would result from the same fixed-length burst with auto precharge. The disadvant-

age of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command. The advantage of the

PRECHARGE command is that it can be used to truncate fixed-length or continuous

page bursts.

Figure 19: READ-to-WRITE

READ NOP NOP WRITE

NOP

CLK

T2T1 T4T3T0

DQM

Command

Address

Bank,

Col b

Bank,

Col n

tHZ

tCK

Don’t Care

Transitioning data

DOUT n DIN b

Note: 1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be

to any bank. If a burst of one is used, DQM is not required.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

READ Operation

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Figure 20: READ-to-WRITE With Extra Clock Cycle

Don’t Care

READ NOP NOPNOP NOP

DQM

CLK

DQ DOUT n

T2T1 T4T3T0

Command

Address Bank,

Col n

WRITE

DIN b

Bank,

Col b

tDS

tHZ

Transitioning data

Note: 1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be

to any bank.

Figure 21: READ-to-PRECHARGE

Don’t Care

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

Command

Address

READ NOP NOP NOP NOPNOP

DOUT

n + 1

DOUT

n + 2

DOUT

n + 3

PRECHARGE ACTIVE

tRP

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

Command

Address

READ NOP NOP NOP NOPNOP

DOUT

n + 1

DOUT

n + 2

DOUT

n + 3

PRECHARGE ACTIVE

tRP

X = 1 cycle

CL = 2

CL = 3

X = 2 cycles

Bank

Col

Bank

Row

Bank

(

or all)

Bank

Col

Bank

Row

Bank

(

or all)

Transitioning data

Note: 1. DQM is LOW.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

READ Operation

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Continuous-page READ bursts can be truncated with a BURST TERMINATE command

and fixed-length READ bursts can be truncated with a BURST TERMINATE command,

provided that auto precharge was not activated. The BURST TERMINATE command

should be issued x cycles before the clock edge at which the last desired data element is

valid, where x = CL - 1. This is shown in Figure 22 (page 52) for each possible CAS la-

tency; data element n + 3 is the last desired data element of a longer burst.

Figure 22: Terminating a READ Burst

CLK

T2T1 T4T3 T6T5T0

Command

Address

NOP NOP NOP NOPNOP BURST

TERMINATE NOP

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

Command

Address

READ NOP NOP NOPNOP

DOUT

n + 1

DOUT

n + 2

DOUT

n + 3

BURST

TERMINATE NOP

X = 1 cycle

CL = 2

CL = 3

X = 2 cycles

Don’t CareTransitioning data

Bank,

Col n

READ

Bank,

Col n

DOUT

n + 1

DOUT

n + 2

DOUT

n + 3

Note: 1. DQM is LOW.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

READ Operation

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Figure 23: Alternating Bank Read Accesses

Don’t Care Undefined

Enable auto precharge

tCH

tCL

tCK

tAC

tLZ

CLK

A10

tOH

DOUT m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

Row

tOH

DOUT

m + 3

tAC

tOH

tAC

tOH

tAC

DOUT

m + 2

DOUT

m + 1

Command

tCMH

tCMS

NOP NOPACTIVE NOP READ NOP ACTIVE

tOH

DOUT b

tAC tAC

READ

Enable auto precharge

Row

ACTIVE

Row

Bank 0 Bank 0 Bank 3 Bank 3 Bank 0

CKE

tCKH

tCKS

Column m Column b1

T0 T1 T2 T4T3 T5 T6 T7 T8

tRP - bank 0

tRAS - bank 0

tRCD - bank 0 tRCD - bank 0

CL - bank 0

tRCD - bank 3 CL - bank 3

tRC - bank 0

tRRD

BA0, BA1

DQM

Address

Note: 1. For this example, BL = 4 and CL = 2.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

READ Operation

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Figure 24: READ Continuous Page Burst

tCH

tCL tCK

tAC

tLZ

tRCD CAS latency

CKE

CLK

A10

tOH

DOUT m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAC

tOH

DOUT

Row

tHZ

tOH

DOUT

m+1

tAC

tOH

DOUT

m+2

tAC

tOH

DOUT

m-1

tAC

tOH

DOUT m

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

Full page completed

All locations within same row

Don’t Care

Undefined

Command

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP

(

)(

)

(

)(

)

NOP

(

)(

)

(

)(

)

tAH

tAS

Bank

(

)(

)

(

)(

)

Bank

tCKH

tCKS

(

)(

)

(

)(

)

(

)(

)

(

)(

)

Column m

T0 T1 T2 T4T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4

BA0, BA1

DQM

Address

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

Note: 1. For this example, CL = 2.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

READ Operation

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Figure 25: READ – DQM Operation

tCH

tCL

tCK

tAC

tLZ

tRCD CL = 2

CKE

CLK

A10

tOH

DOUT m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

Row

Bank

Row

Bank

tHZ

tAC

tLZ

tOH

DOUT m + 2

tOH

DOUT m + 3

tHZ

Command

tCMH

tCMS

NOPNOPNOP NOPACTIVE NOP READ NOP NOP

Disable auto precharge

Enable auto precharge

Don’t Care

Undefined

tCKH

tCKS

Column m

T0 T1 T2 T4T3 T5 T6 T7 T8

BA0, BA1

DQM

Address

Note: 1. For this example, BL = 4 and CL = 2.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

READ Operation

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WRITE Operation

WRITE bursts are initiated with a WRITE command, as shown in Figure 10 (page 30).

The starting column and bank addresses are provided with the WRITE command and

auto precharge is either enabled or disabled for that access. If auto precharge is ena-

bled, the row being accessed is precharged at the completion of the burst. For the ge-

neric WRITE commands used in the following figures, auto precharge is disabled.

During WRITE bursts, the first valid data-in element is registered coincident with the

WRITE command. Subsequent data elements are registered on each successive positive

clock edge. Upon completion of a fixed-length burst, assuming no other commands

have been initiated, the DQ will remain at High-Z and any additional input data will be

ignored (see Figure 26 (page 56)). A continuous page burst continues until terminated;

at the end of the page, it wraps to column 0 and continues.

Data for any WRITE burst can be truncated with a subsequent WRITE command, and

data for a fixed-length WRITE burst can be followed immediately by data for a WRITE

command. The new WRITE command can be issued on any clock following the previ-

ous WRITE command, and the data provided coincident with the new command ap-

plies to the new command (see Figure 27 (page 57)). Data n + 1 is either the last of a

burst of two or the last desired data element of a longer burst.

Mobile LPSDR devices use a pipelined architecture and therefore do not require the 2n

rule associated with a prefetch architecture. A WRITE command can be initiated on any

clock cycle following a previous WRITE command. Full-speed random write accesses

within a page can be performed to the same bank, as shown in Figure 28 (page 58), or

each subsequent WRITE can be performed to a different bank.

Figure 26: WRITE Burst

CLK

DQ DIN

T2T1 T3T0

Command

Address

NOP NOP

Don’t Care

WRITE

DIN

n + 1

NOP

Bank,

Col n

Transitioning data

Note: 1. BL = 2. DQM is LOW.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

WRITE Operation

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Figure 27: WRITE-to-WRITE

CLK

T2T1T0

Command

Address

NOPWRITE WRITE

Bank,

Col n

Bank,

Col b

DIN

n + 1

DIN

Don’t Care

Note: 1. DQM is LOW. Each WRITE command may be issued to any bank.

Data for any WRITE burst can be truncated with a subsequent READ command, and

data for a fixed-length WRITE burst can be followed immediately by a READ command.

After the READ command is registered, data input is ignored and WRITEs will not be

executed (see Figure 29 (page 58)). Data n + 1 is either the last of a burst of two or the

last desired data element of a longer burst.

Data for a fixed-length WRITE burst can be followed by or truncated with a PRE-

CHARGE command to the same bank, provided that auto precharge was not activated.

A continuous-page WRITE burst can be truncated with a PRECHARGE command to the

same bank. The PRECHARGE command should be issued tWR after the clock edge at

which the last desired input data element is registered. The auto precharge mode re-

quires a tWR of at least one clock with time to complete, regardless of frequency.

In addition, when truncating a WRITE burst at high clock frequencies (tCK < 15ns), the

DQM signal must be used to mask input data for the clock edge prior to and the clock

edge coincident with the PRECHARGE command (see Figure 30 (page 59)). Data n + 1

is either the last of a burst of two or the last desired data element of a longer burst. Fol-

lowing the PRECHARGE command, a subsequent command to the same bank cannot

be issued until tRP is met.

In the case of a fixed-length burst being executed to completion, a PRECHARGE com-

mand issued at the optimum time (as described above) provides the same operation

that would result from the same fixed-length burst with auto precharge. The disadvant-

age of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command. The advantage of the

PRECHARGE command is that it can be used to truncate fixed-length bursts or continu-

ous page bursts.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

WRITE Operation

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Figure 28: Random WRITE Cycles

Don’t Care

CLK

DQ DIN

T2T1 T3T0

Command

Address

WRITE

Bank,

Col n

DIN

WRITE WRITE WRITE

Bank,

Col a

Bank,

Col x

Bank,

Col m

Note: 1. Each WRITE command can be issued to any bank. DQM is LOW.

Figure 29: WRITE-to-READ

Don’t Care

CLK

T2T1 T3T0

Command

Address

NOPWRITE

Bank,

Col n

DIN

n + 1

DOUT

READ NOP NOP

Bank,

Col b

NOP

DOUT

b + 1

T4 T5

Note: 1. The WRITE command can be issued to any bank, and the READ command can be to any

bank. DQM is LOW. CL = 2 for illustration.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

WRITE Operation

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Figure 30: WRITE-to-PRECHARGE

Don’t Care

DQM

CLK

T2T1 T4T3T0

Command

Address Bank a,

Col n

NOPWRITE PRECHARGE NOPNOP

DIN

n + 1

ACTIVE

tRP

Bank

(a or all)

tWR

Bank a,

Row

DQM

Command

Address Bank a,

Col n

NOPWRITE PRECHARGE NOPNOP

DIN

n + 1

ACTIVE

tRP

Bank

(a or all)

tWR

Bank a,

Row

NOP

tWR @ tCK < 15ns

tWR @ tCK ≥ 15ns

Note: 1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two.

Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.

When truncating a WRITE burst, the input data applied coincident with the BURST

TERMINATE command is ignored. The last data written (provided that DQM is LOW at

that time) will be the input data applied one clock previous to the BURST TERMINATE

command. This is shown in Figure 31 (page 60), where data n is the last desired data

element of a longer burst.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

WRITE Operation

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Figure 31: Terminating a WRITE Burst

Don’t Care

CLK

T2T1T0

Command

Address Bank,

Col n

WRITE BURST

TERMINATE

COMMAND

DIN

Address

Data

Transitioning data

Note: 1. DQM is LOW.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

WRITE Operation

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Figure 32: Alternating Bank Write Accesses

Don’t Care

Enable auto precharge

tCH

tCL

tCK

CLK

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

Row

Command

tCMH

tCMS

NOP NOPACTIVE NOP WRITE NOPNOP ACTIVEWRITE

Enable auto precharge

Row

ACTIVE

Row

Bank 0 Bank 0 Bank 1 Bank 1 Bank 0

CKE

tCKH

tCKS

Column m Column b

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

tRP - bank 0

tRAS - bank 0

tRCD - bank 0 tRCD - bank 0

tWR - bank 1

tWR - bank 0

tRCD - bank 1

tRC - bank 0

tRRD

BA0, BA1

DQM

Address

DIN m

tDH

tDS

DIN m + 1 DIN m + 2 DIN m + 3

tDH

tDS tDH

tDS

DIN b

tDH

tDS

DIN b + 1

tDH

tDS

DIN b + 2

tDH

tDS

DIN m + 3

tDH

tDS

Note: 1. For this example, BL = 4.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

WRITE Operation

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Figure 33: WRITE – Continuous Page Burst

tCH

tCL tCK

tRCD

CKE

CLK

A10

tCMS

tAH

tAS

tAH

tAS

Row

Full-page burst

does not self-terminate.

Use BURST TERMINATE

command to stop.1, 2

(

)(

)

(

)(

)

(

)(

)

(

)(

)

Full page completed Don’t Care

Command

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP

(

)(

)

(

)(

)

(

)(

)

(

)(

)

DIN

tDH

tDS

DIN

+ 1 DIN

+ 2 DIN

+ 3

tDH

tDS tDH

tDS

DIN

- 1

tDH

tDS

tAH

tAS

Bank

(

)(

)

(

)(

)

Bank

tCMH

tCKH

tCKS

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

All locations within same row

Column

T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3

BA0, BA1

DQM

Address

Notes: 1. tWR must be satisfied prior to issuing a PRECHARGE command.

2. Page left open; no tRP.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

WRITE Operation

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Figure 34: WRITE – DQM Operation

Don’t Care

tCH

tCL

tCK

tRCD

CKE

CLK

A10

tCMS

tAH

tAS

Row

Bank

Row

Bank

Enable auto precharge

DIN m + 3

tDH

tDS

DIN mDIN m + 2

tCMH

Command NOPNOP NOP

ACTIVE NOP WRITE NOPNOP

tCMS tCMH

tDH

tDS

tDH

tDS

tAH

tAS

tAH

tAS

Disable auto precharge

tCKH

tCKS

Column m

T0 T1 T2 T3 T4 T5 T6 T7

BA0, BA1

DQM

Address

Note: 1. For this example, BL = 4.

Burst Read/Single Write

The burst read/single write mode is entered by programming the write burst mode bit

(M9) in the mode register to a 1. In this mode, all WRITE commands result in the access

of a single column location (burst of one), regardless of the programmed burst length.

READ commands access columns according to the programmed burst length and se-

quence, just as in the normal mode of operation (M9 = 0).

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

WRITE Operation

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PRECHARGE Operation

The PRECHARGE command (see Figure 11 (page 31)) is used to deactivate the open row

in a particular bank or the open row in all banks. The bank(s) will be available for a sub-

sequent row access some specified time (tRP) after the PRECHARGE command is is-

sued. Input A10 determines whether one or all banks are to be precharged, and in the

case where only one bank is to be precharged (A10 = LOW), inputs BA0 and BA1 select

the bank. When all banks are to be precharged (A10 = HIGH), inputs BA0 and BA1 are

treated as “Don’t Care.” After a bank has been precharged, it is in the idle state and

must be activated prior to any READ or WRITE commands being issued to that bank.

Auto Precharge

Auto precharge is a feature that performs the same individual-bank PRECHARGE func-

tion described previously, without requiring an explicit command. This is accomplished

by using A10 to enable auto precharge in conjunction with a specific READ or WRITE

command. A precharge of the bank/row that is addressed with the READ or WRITE

command is automatically performed upon completion of the READ or WRITE burst,

except in the continuous page burst mode where auto precharge does not apply. In the

specific case of write burst mode set to single location access with burst length set to

continuous, the burst length setting is the overriding setting and auto precharge does

not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for

each individual READ or WRITE command.

Auto precharge ensures that the precharge is initiated at the earliest valid stage within a

burst. Another command cannot be issued to the same bank until the precharge time

(tRP) is completed. This is determined as if an explicit PRECHARGE command was is-

sued at the earliest possible time, as described for each burst type in the Burst Type

(page 41) section.

This device supports tRAS lock-out. In the case of a single READ with auto precharge, or

a single WRITE with auto precharge, issued at tRCD (MIN), the internal precharge will

be delayed until tRAS (MIN) has been satisfied.

Micron SDRAM supports concurrent auto precharge; cases of concurrent auto pre-

charge for READs and WRITEs are defined below.

READ with auto precharge interrupted by a READ (with or without auto precharge)

A READ to bank m will interrupt a READ on bank n following the programmed CAS la-

tency. The precharge to bank n begins when the READ to bank m is registered (see Fig-

ure 35 (page 65)).

READ with auto precharge interrupted by a WRITE (with or without auto precharge)

A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be

used two clocks prior to the WRITE command to prevent bus contention. The pre-

charge to bank n begins when the WRITE to bank m is registered (see Figure 36

(page 66)).

WRITE with auto precharge interrupted by a READ (with or without auto precharge)

A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out

appearing CL later. The precharge to bank n will begin after tWR is met, where tWR be-

gins when the READ to bank m is registered. The last valid WRITE to bank n will be da-

ta-in registered one clock prior to the READ to bank m (see Figure 41 (page 71)).

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

PRECHARGE Operation

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WRITE with auto precharge interrupted by a WRITE (with or without auto precharge)

A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to

bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is reg-

istered. The last valid data WRITE to bank n will be data registered one clock prior to a

WRITE to bank m (see Figure 42 (page 71)).

Figure 35: READ With Auto Precharge Interrupted by a READ

Don’t Care

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

Command READ - AP

Bank n NOP NOPNOPNOP

DOUT

a + 1

DOUT

d + 1

NOP

Bank n

CL = 3 (bank m)

Bank m

Address

Idle

NOP

Bank n,

Col a

Bank m,

Col d

READ - AP

Bank m

Internal

states

Page active READ with burst of 4 Interrupt burst, precharge

Page active READ with burst of 4 Precharge

RP - bank n tRP - bank m

CL = 3 (bank n)

Note: 1. DQM is LOW.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

PRECHARGE Operation

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Figure 36: READ With Auto Precharge Interrupted by a WRITE

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

Command NOPNOPNOPNOP

DIN

d + 1

DIN

d + 2

DIN

d + 3

NOP

Bank n

Bank m

Address

Idle

NOP

DQM1

Bank n,

Col a

Bank m,

Col d

WRITE - AP

Bank m

Internal

States

Page

active READ with burst of 4 Interrupt burst, precharge

Page active WRITE with burst of 4 Write-back

RP -

bank

tWR - bank m

CL = 3 (bank n)

READ - AP

Bank n

Don’t Care

Note: 1. DQM is HIGH at T2 to prevent DOUTa + 1 from contending with DINd at T4.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

PRECHARGE Operation

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Figure 37: READ With Auto Precharge

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CL = 2

tRC

CKE

CLK

A10

tOH

DOUT m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

Row

Bank Bank

Row

Bank

tHZ

tOH

DOUT

m + 3

tAC

tOH

tAC

tOH

tAC

DOUT

m + 2

DOUT

m + 1

Command

tCMH

tCMS

NOPNOPNOP NOPACTIVE NOP READ NOP ACTIVE

Enable auto precharge

Don’t Care Undefined

tCKH

tCKS

Column m

T0 T1 T2 T4T3 T5 T6 T7 T8

BA0, BA1

DQM

Address

Note: 1. For this example, BL = 4 and CL = 2.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

PRECHARGE Operation

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Figure 38: READ Without Auto Precharge

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CL = 2

tRC

CKE

CLK

A10

tOH

DOUT m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

Row

Bank Bank(s) Bank

Row

Bank

tHZ

tOH

DOUT

m + 3

tAC

tOH

tAC

tOH

tAC

DOUT

m + 2

DOUT

m + 1

Command

tCMH

tCMS

PRECHARGENOPNOP NOPACTIVE NOP READ NOP ACTIVE

Disable auto precharge Single bank

All banks

Don’t Care Undefined

tCKH

tCKS

Column m

T0 T1 T2 T4T3 T5 T6 T7 T8

BA0, BA1

DQM

Address

Note: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRE-

CHARGE.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

PRECHARGE Operation

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Figure 39: Single READ With Auto Precharge

tCH

tCL

tCK

tAC tOH

tLZ

tRP

tRAS

tRCD CL = 2

tRC

CKE

CLK

A10

DOUT m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

Row

Bank Bank

Row

Bank

Command

tCMH

tCMS

NOPNOPNOP NOPACTIVE NOP READ ACTIVE

Enable auto precharge

Don’t Care Undefined

tCKH

tCKS

Column m

T0 T1 T2 T4T3 T5 T6 T7

BA0, BA1

DQM

Address

Note: 1. For this example, BL = 1 and CL = 2.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

PRECHARGE Operation

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Figure 40: Single READ Without Auto Precharge

All banks

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CL = 2

tRC

CKE

CLK

A10

tOH

DOUT m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

Row

Bank Bank(s) Bank

Row

Bank

tHZ

Command

tCMH

tCMS

NOPNOPNOP PRECHARGE

ACTIVE NOP READ ACTIVE NOP

Disable auto precharge Single bank

Don’t Care

Undefined

tCKH

tCKS

Column m

T0 T1 T2 T4T3 T5 T6 T7 T8

BA0, BA1

DQM

Address

Note: 1. For this example, BL = 1, CL = 2, and the READ burst is followed by a manual PRE-

CHARGE.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

PRECHARGE Operation

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Figure 41: WRITE With Auto Precharge Interrupted by a READ

Don’t Care

CLK

T2T1 T4T3 T6T5T0

Command WRITE - AP

Bank n NOPNOPNOPNOP

DIN

a + 1

DIN

NOP NOP

Bank n

Bank m

Address Bank n,

Col a

Bank m,

Col d

READ - AP

Bank m

Internal

States

Page active WRITE with burst of 4 Interrupt burst, write-back Precharge

Page active READ with burst of 4

tRP - bank m

DOUT

d + 1

CL = 3 (bank m)

RP - bank n

WR - bank n

Note: 1. DQM is LOW.

Figure 42: WRITE With Auto Precharge Interrupted by a WRITE

Don’t Care

CLK

T2T1 T4T3 T6T5T0

Command WRITE - AP

Bank n NOPNOPNOPNOP

DIN

d + 1

DIN

a + 1

DIN

a + 2

DIN

d + 2

DIN

d + 3

NOP

Bank n

Bank m

Address

NOP

Bank n,

Col a

Bank m,

Col d

WRITE - AP

Bank m

Internal

States

Page active WRITE with burst of 4 Interrupt burst, write-back Precharge

Page active WRITE with burst of 4 Write-back

WR - bank n tRP - bank n

tWR - bank m

Note: 1. DQM is LOW.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

PRECHARGE Operation

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Figure 43: WRITE With Auto Precharge

Enable auto precharge

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

CKE

CLK

A10

tCMH

tCMS

tAH

tAS

Row

Bank

Row

Bank

tWR

Don’t Care

DIN m

tDH

tDS

DIN m + 1 DIN m + 2 DIN m + 3

Command

CMH

CMS

NOPNOP NOPACTIVE NOP WRITE NOPNOP NOP

Row

Bank

Row

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

tCKH

tCKS

Column m

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

DQM

BA0, BA1

Address

ACTIVE

Note: 1. For this example, BL = 4.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

PRECHARGE Operation

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Figure 44: WRITE Without Auto Precharge

Disable auto precharge

All banks

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

CKE

CLK

A10

tCMH

tCMS

tAH

tAS

Row

Bank Bank

Row

Bank

tWR

Don’t Care

DIN m

tDH

tDS

DIN m + 1 DIN m + 2 DIN m + 3

Command

CMH

CMS

NOPNOP NOPACTIVE NOP WRITE PRECHARGENOP NOP

Row

Bank

Row

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

Single bank

tCKH

tCKS

Column m

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

DQM

BA0, BA1

Address

ACTIVE

Note: 1. For this example, BL = 4 and the WRITE burst is followed by a manual PRECHARGE.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

PRECHARGE Operation

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Figure 45: Single WRITE With Auto Precharge

Enable auto precharge

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

CKE

CLK

A10

tCMH

tCMS

tAH

tAS

Row

Bank

Row

Bank

tWR

Don’t Care

DIN m

tDH

tDS

Command

CMH

CMS

NOPNOP NOPACTIVE NOP WRITE NOP NOP

Row

Bank

Row

tAH

tAS

tAH

tAS

tCKH

tCKS

Column m

T0 T1 T2 T4T3 T5 T6 T7 T8

DQM

BA0, BA1

Address

ACTIVE

Note: 1. For this example, BL = 1.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

PRECHARGE Operation

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Figure 46: Single WRITE Without Auto Precharge

tCH

tCL

tCK

tRP

tRAS

tRCD tWR

tRC

CKE

CLK

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

Row

Bank Bank Bank

Row

Bank

Command

tCMH

tCMS

NOPNOPNOP PRECHARGEACTIVE NOP WRITE ACTIVE NOP

Disable auto precharge

Don’t Care

tCKH

tCKS

Column m

T0 T1 T2 T4T3 T5 T6 T7 T8

BA0, BA1

DQM

Address

DIN m

tDH

tDS

All banks

Single bank

Note: 1. For this example, BL = 1 and the WRITE burst is followed by a manual PRECHARGE.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

PRECHARGE Operation

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AUTO REFRESH Operation

The AUTO REFRESH command is used during normal operation of the device to refresh

the contents of the array. This command is nonpersistent, so it must be issued each

time a refresh is required. All active banks must be precharged prior to issuing an AUTO

REFRESH command. The AUTO REFRESH command should not be issued until the

minimum tRP is met following the PRECHARGE command. Addressing is generated by

the internal refresh controller. This makes the address bits “Don’t Care” during an AU-

TO REFRESH command.

After the AUTO REFRESH command is initiated, it must not be interrupted by any exe-

cutable command until tRFC has been met. During tRFC time, COMMAND INHIBIT or

NOP commands must be issued on each positive edge of the clock. The SDRAM re-

quires that every row be refreshed each tREF period. Providing a distributed AUTO RE-

FRESH command—calculated by dividing the refresh period (tREF) by the number of

rows to be refreshed—meets the timing requirement and ensures that each row is re-

freshed. Alternatively, to satisfy the refresh requirement a burst refresh can be employed

after every tREF period by issuing consecutive AUTO REFRESH commands for the num-

ber of rows to be refreshed at the minimum cycle rate (tRFC).

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

AUTO REFRESH Operation

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Figure 47: Auto Refresh Mode

All banks

Don’t Care

tCH

tCL

tCK

CKE

CLK

tRFC

(

)(

)

(

)(

)

tRP

(

)(

)

(

)(

)

Command

tCMH

tCMS

NOPNOP

(

)(

)

(

)(

)

Bank

ACTIVE

AUTO

REFRESH

(

)(

)

(

)(

)

NOPNOPPRECHARGE

Precharge all

active banks

AUTO

REFRESH

tRFC

High-Z

Bank(s)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

tAH

tAS

tCKH

tCKS

NOP

(

)(

)

(

)(

)

(

)(

)

(

)(

)

Row

(

)(

)

(

)(

)

Single bank

A10

Row

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

T0 T1 T2 Tn + 1 To + 1

BA0, BA1

Address

DQM

(

)(

)

(

)(

)

Note: 1. Back-to-back AUTO REFRESH commands are not required.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

AUTO REFRESH Operation

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SELF REFRESH Operation

The self refresh mode can be used to retain data in the device, even when the rest of the

system is powered down. When in self refresh mode, the device retains data without ex-

ternal clocking. The SELF REFRESH command is initiated like an AUTO REFRESH com-

mand, except CKE is disabled (LOW). After the SELF REFRESH command is registered,

all the inputs to the device become “Don’t Care” with the exception of CKE, which must

remain LOW.

After self refresh mode is engaged, the device provides its own internal clocking, ena-

bling it to perform its own AUTO REFRESH cycles. The device must remain in self re-

fresh mode for a minimum period equal to tRAS and remains in self refresh mode for an

indefinite period beyond that.

The procedure for exiting self refresh requires a sequence of commands. First, CLK

must be stable prior to CKE going back HIGH. (Stable clock is defined as a signal cycling

within timing constraints specified for the clock ball.) After CKE is HIGH, the device

must have NOP commands issued for a minimum of two clocks for tXSR because time is

required for the completion of any internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH commands must be issued accord-

ing to the distributed refresh rate (tREF/refresh row count) as both SELF REFRESH and

AUTO REFRESH utilize the row refresh counter.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

SELF REFRESH Operation

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Figure 48: Self Refresh Mode

All banks

tCH

tCL

tRP

CKE

CLK

Enter self refresh mode

Precharge all

active banks

tXSR

CLK stable prior to exiting

self refresh mode

Exit self refresh mode

(Restart refresh time base)

(

)(

)

(

)(

)

Don’t Care

Command

tCMH

tCMS

AUTO

REFRESH

PRECHARGE NOP NOP

Bank(s)

High-Z

tCKS

tAH

tAS

AUTO

REFRESH

tCKH

tCKS

A10

T0 T1 T2 Tn + 1 To + 1 To + 2

BA0, BA1

DQM

Address

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

(

)(

)

Single bank

Note: 1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are

not required.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

SELF REFRESH Operation

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Power-Down

Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-

HIBIT when no accesses are in progress. If power-down occurs when all banks are idle,

this mode is referred to as precharge power-down; if power-down occurs when there is a

row active in any bank, this mode is referred to as active power-down. Entering power-

down deactivates the input and output buffers, excluding CKE, for maximum power

savings while in standby. The device cannot remain in the power-down state longer

than the refresh period (64ms) because no REFRESH operations are performed in this

mode.

The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE

HIGH at the desired clock edge (meeting tCKS).

Figure 49: Power-Down Mode

All banks

tCH

tCL

tCK

Two clock cycles

CKE

CLK

All banks idle, enter

power-down mode

Precharge all

active banks

Input buffers gated off

while in power-down mode

Exit power-down mode

(

)(

)

Don’t Care

tCKS tCKS

Command

tCMH

tCMS

PRECHARGE NOP NOP ACTIVENOP

(

)(

)

(

)(

)

All banks idle

BA0, BA1 Bank

Bank(s)

(

)(

)

(

)(

)

High-Z

tAH

tAS

tCKH

tCKS

DQM

(

)(

)

(

)(

)

(

)(

)

(

)(

)

Address Row

(

)(

)

(

)(

)

Single bank

A10 Row

(

)(

)

(

)(

)

T0 T1 T2 Tn + 1 Tn + 2

(

)(

)

Note: 1. Violating refresh requirements during power-down may result in a loss of data.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Power-Down

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Deep Power-Down

Deep power-down mode is a maximum power-saving feature achieved by shutting off

the power to the entire device memory array. Data on the memory array will not be re-

tained after deep power-down mode is executed. Deep power-down mode is entered by

having all banks idle, with CS# and WE# held LOW with RAS# and CAS# HIGH at the

rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep power-

down.

To exit deep power-down mode, CKE must be asserted HIGH. Upon exiting deep power-

down mode, a full initialization sequence is required.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Deep Power-Down

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Clock Suspend

The clock suspend mode occurs when a column access/burst is in progress and CKE is

registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing

the synchronous logic.

For each positive clock edge on which CKE is sampled LOW, the next internal positive

clock edge is suspended. Any command or data present on the input balls when an in-

ternal clock edge is suspended will be ignored; any data present on the DQ balls re-

mains driven; and burst counters are not incremented, as long as the clock is suspen-

ded.

Exit clock suspend mode by registering CKE HIGH; the internal clock and related opera-

tion will resume on the subsequent positive clock edge.

Figure 50: Clock Suspend During WRITE Burst

Don’t Care

DIN

Command

Address

WRITE

Bank,

Col n

DIN

NOPNOP

CLK

T2T1 T4T3 T5T0

CKE

Internal

clock

NOP

DIN

n + 1

DIN

n + 2

Note: 1. For this example, BL = 4 or greater, and DQM is LOW.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Clock Suspend

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Figure 51: Clock Suspend During READ Burst

Don’t Care

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

Command

Address

READ NOP NOP NOP

Bank,

Col n

NOP

DOUT

n + 1

DOUT

n + 2

DOUT

n + 3

CKE

Internal

clock

NOP

Note: 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Clock Suspend

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Figure 52: Clock Suspend Mode

tCH

tCL

tCK

tAC

tLZ

DQM

CLK

A10

tOH

DOUT

tAH

tAS

tAH

tAS

tAH

tAS

Bank

tDH

DIN

tAC

tHZ

DOUT

m + 1

Command

tCMH

tCMS

NOPNOP NOP NOPNOPREAD WRITE

Don’t Care Undefined

CKE

tCKS tCKH

Bank

Column m

tDS

DIN

e + 1

NOP

tCKH

tCKS

tCMH

tCMS

Column e

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

BA0, BA1

Address

Note: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Clock Suspend

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Revision History

Rev. J, Production – 09/10

• Select Idd limits were tightened for x16 and x32 configurations

Rev. I, Production – 11/09

• Corrected seating plane value on package dimension drawings from 0.12 to 0.1.

Rev. H, Production – 10/09

• Changed tRFC from 97.5ns to 72ns in the Electrical Specificatins and AC Operating

Conditions table.

Rev. G, Production – 8/09

• Updated format.

Rev. F, Production – 6/09

• DC Electrical Characteristics and Operating Conditions table: Updated IOZ to ±1.5μA.

Rev. E, Production – 4/09

• VFBGA Ball Descriptions table: Removed ball assignments columns.

• AC Functional Characteristics table: Updated note 9.

Rev. D, Production – 1/09

• Replaced the 8mm x 8mm 54-ball package drawing with an 8mm x 9mm package

drawing.

• Updated the 90-ball package drawing.

Rev. C, Production – 12/08

• Changed to Production status.

• IDD7 Specifications and Conditions (x16 and x32) table: Updated IDD7 values for full

array 85°C, 1/8 array 45°C, and 1/16 array 45°C.

Rev. B, Preliminary – 10/08

• Changed to Preliminary status.

• VFBGA Ball Descriptions table: Rearranged table content that was out of order.

Rev. A, Advance – 9/08

• Initial release.

Revision History for Commands, Operations, and Timing Diagrams

Update – 10/08

• Deep Power-Down: Added description for exiting DPD.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Revision History

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Update – 7/08

• Updated address/data range presentation to industry-standard presentation.

• Replaced MODE REGISTER SET with LMR as appropriate.

• Truth Table – Current State Bank n, Command to Bank m, note 13: Added missing

“m.”

• Mode Register: Corrected presentation of mode register bits.

• Partial-Array Self Refresh (PASR): Updated refresh options presentation.

Update – 5/08

• Auto Precharge: Added fourth paragraph regarding tRAS lock-out.

• Single READ With Auto Precharge: Updated figure.

• WRITE Without Auto Precharge: Updated note to BL = 4.

• Single WRITE With Auto Precharge: Updated figure.

• Single WRITE Without Auto Precharge: Updated figure.

Update – 4/08

• Added three-quarter drive strength content.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM

Revision History

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